diff --git a/projects/dl814_dj/dl814_dj_new_48m/.gitignore b/projects/dl814_dj/dl814_dj_new_48m/.gitignore new file mode 100644 index 00000000..d6f41494 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/.gitignore @@ -0,0 +1,131 @@ +################################################################################ +########################### Single Project Specific ############################ +################################################################################ + +# ------------------------------------------------------------------------------ +# ------------------------------ Vivado Specific ------------------------------- +# ------------------------------------------------------------------------------ + +# exclude everything in project directory +project/** + +# include hardware manager projects and sources +# 1. include `.hw` directory +# 2. include everything in `.hw` directory +!project/*.hw/ +!project/*.hw/** + +# include design run results +# 1. include `*.runs` directory +# 2. exclude everything in `.runs` directory +# 3. include `.impl_*` directory +# 4. include `*.bit` file in `.impl_*` directory +# 5. include `*.ltx` file in `.impl_*` directory +!/project/*.runs/ +/project/*.runs/** +!/project/*.runs/impl_*/ +!/project/*.runs/impl_*/*.bit +!/project/*.runs/impl_*/*.ltx + +# ------------------------------------------------------------------------------ +# -------------------------------- SDK Specific -------------------------------- +# ------------------------------------------------------------------------------ + +# include sdk directory and everything in it +!/project/*.sdk/ +!/project/*.sdk/** +/project/*.sdk/**.log + +# exclude some obscure hidden SDK folders +/project/*.sdk/.metadata/ +/project/*.sdk/.sdk/ +/project/*.sdk/RemoteSystemsTempFiles/ +/project/*.sdk/webtalk/ + +# hw_platform: exclude the entire hw_platform folder, as everything can be +# generated from the .hdf file. Make sure to include the bitstream in the .hdf +# file when exporting from Vivado! +/project/*.sdk/*_hw_platform_*/ + +# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and +# Makefile, ps lib files are regenerated automatically +/project/*.sdk/*_bsp/* +!/project/*.sdk/*_bsp/*.cproject +!/project/*.sdk/*_bsp/*.project +!/project/*.sdk/*_bsp/*.sdkproject +!/project/*.sdk/*_bsp/system.mss +!/project/*.sdk/*_bsp/Makefile + +# Application: ignored file patterns, exclude Debug & Release folders +/project/*.sdk/**/*.o +/project/*.sdk/**/*.d +/project/*.sdk/**/*.a +/project/*.sdk/*/Debug/ +/project/*.sdk/*/Release/ + + +################################################################################ +# ############################ Multi Project Specific ############################ +# ################################################################################ + +# # ------------------------------------------------------------------------------ +# # ------------------------------ Vivado Specific ------------------------------- +# # ------------------------------------------------------------------------------ + +# # exclude everything in project directory expect for top level directory +# project/** +# !/project/*/ + +# # include hardware manager projects and sources +# # 1. include `.hw` directory +# # 2. include everything in `.hw` directory +# !project/*/*.hw/ +# !project/*/*.hw/** + +# # include design run results +# # 1. include `*.runs` directory +# # 2. exclude everything in `.runs` directory +# # 3. include `.impl_*` directory +# # 4. include `*.bit` file in `.impl_*` directory +# # 5. include `*.ltx` file in `.impl_*` directory +# !/project/*/*.runs/ +# /project/*/*.runs/** +# !/project/*/*.runs/impl_*/ +# !/project/*/*.runs/impl_*/*.bit +# !/project/*/*.runs/impl_*/*.ltx + +# # ------------------------------------------------------------------------------ +# # -------------------------------- SDK Specific -------------------------------- +# # ------------------------------------------------------------------------------ + +# # include sdk directory and everything in it +# !/project/*/*.sdk/ +# !/project/*/*.sdk/** +# /project/*/*.sdk/**.log + +# # exclude some obscure hidden SDK folders +# /project/*/*.sdk/.metadata/ +# /project/*/*.sdk/.sdk/ +# /project/*/*.sdk/RemoteSystemsTempFiles/ +# /project/*/*.sdk/webtalk/ + +# # hw_platform: exclude the entire hw_platform folder, as everything can be +# # generated from the .hdf file. Make sure to include the bitstream in the .hdf +# # file when exporting from Vivado! +# /project/*/*.sdk/*_hw_platform_*/ + +# # BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and +# # Makefile, ps lib files are regenerated automatically +# /project/*/*.sdk/*_bsp/* +# !/project/*/*.sdk/*_bsp/*.cproject +# !/project/*/*.sdk/*_bsp/*.project +# !/project/*/*.sdk/*_bsp/*.sdkproject +# !/project/*/*.sdk/*_bsp/system.mss +# !/project/*/*.sdk/*_bsp/Makefile + +# # Application: ignored file patterns, exclude Debug & Release folders +# /project/*/*.sdk/**/*.o +# /project/*/*.sdk/**/*.d +# /project/*/*.sdk/**/*.a +# /project/*/*.sdk/*/Debug/ +# /project/*/*.sdk/*/Release/ diff --git a/projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc b/projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc new file mode 100644 index 00000000..7cfc6cf7 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/constraints/z7100_ad9528_ad9371.xdc @@ -0,0 +1,64 @@ +# 2zynq0745_3ad9371 (xc7z100 version) + +## Timing Assertions Section +create_clock -period 8.000 [get_ports refclk_p] +create_clock -period 80.000 [get_ports clk_12M] + +## Physical Constraints Section + +# Clocks and Resets +set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVDS_25 } [get_ports sysclk_p ] ;# FPGA_LOGIC_CLK_IN_1P +set_property -dict {PACKAGE_PIN AD10 } [get_ports refclk_p ] ;# FPGA_JESD204B_CLK_IN_1P +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 } [get_ports sysref_p ] ;# FPGA_SYSREF_IN_1P + +# AD9528 Interface +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS33} [get_ports spi_csn_ad9528 ] ;# SPI_CS_9528 +set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS33} [get_ports spi_clk_ad9528 ] ;# SPI_SCK_9528 +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS33} [get_ports spi_mosi_ad9528 ] ;# SPI_SDI_9528 +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVCMOS33} [get_ports spi_miso_ad9528 ] ;# SPI_SDO_9528 +set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVCMOS33} [get_ports ad9528_reset_b ] ;# AD9528_CLK_RESETB +set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVCMOS33} [get_ports ad9528_sysref_req ] ;# AD9528_CLK_SYSREF_REQUEST + +# AD9371 Interface +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25 } [get_ports rx_sync_p ] ;# AD9371_1_SYNCINB0+ +set_property -dict {PACKAGE_PIN AJ25 IOSTANDARD LVDS_25 } [get_ports tx_sync_p ] ;# AD9371_1_SYNCOUTB0+ +set_property -dict {PACKAGE_PIN AH10 } [get_ports {rx_data_p[0]} ] ;# AD9371_1_SERDOUT0+ +set_property -dict {PACKAGE_PIN AJ8 } [get_ports {rx_data_p[1]} ] ;# AD9371_1_SERDOUT1+ +set_property -dict {PACKAGE_PIN AK10 } [get_ports {tx_data_p[0]} ] ;# AD9371_1_SERDIN0+ +set_property -dict {PACKAGE_PIN AK6 } [get_ports {tx_data_p[1]} ] ;# AD9371_1_SERDIN1+ + +set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports spi_csn_ad9371 ] ;# AD9371_1_SPI_CS +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports spi_clk_ad9371 ] ;# AD9371_1_SPI_CLK +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_mosi_ad9371 ] ;# AD9371_1_SPI_SDIN +set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports spi_miso_ad9371 ] ;# AD9371_1_SPI_SDO + +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports ad9371_test ] ;# AD9371_1_TEST +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports ad9371_reset_b ] ;# AD9371_1_RESETB +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports ad9371_gpint ] ;# AD9371_1_GP_INTERRUPT + +# RF Control +set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[0] } ] +set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[1] } ] +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[2] } ] +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[3] } ] +set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[4] } ] +set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[5] } ] +set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[6] } ] +set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[7] } ] +set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[8] } ] +set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[9] } ] +set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[10]} ] +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports {freq_hop_words[11]} ] + +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS25} [get_ports tx_gain ] +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports rx_gain ] +set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS25} [get_ports clk_12M ] +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports CS_rf ] +set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports tx_gain_on ] +set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports rx_gain_on ] +set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS25} [get_ports hop_words_valid ] +set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS25} [get_ports freq_hop_switch ] + +# Sync Signal +set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS25} [get_ports sync_signal_out ] ;# Bank9, not used before +set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS25} [get_ports sync_gnd ] ;# Bank9, not used before \ No newline at end of file diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/coe/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/coe/freq_word.coe new file mode 100644 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/coe/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/coe/lpf_125k.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/coe/lpf_125k.coe new file mode 100644 index 00000000..91ddd53d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/coe/lpf_125k.coe @@ -0,0 +1,1027 @@ +RADIX = 10; +COEFDATA = +103, +100, +97, +93, +90, +86, +83, +79, +75, +70, +66, +62, +57, +53, +48, +43, +38, +33, +28, +22, +17, +12, +6, +0, +-5, +-11, +-17, +-23, +-29, +-35, +-41, +-47, +-53, +-59, +-65, +-72, +-78, +-84, +-90, +-96, +-103, +-109, +-115, +-121, +-127, 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+564, +556, +546, +536, +525, +514, +502, +489, +476, +463, +449, +434, +419, +404, +389, +373, +357, +341, +325, +309, +292, +275, +259, +242, +225, +209, +192, +176, +159, +143, +127, +111, +95, +80, +64, +49, +35, +20, +6, +-8, +-21, +-34, +-47, +-59, +-71, +-83, +-94, +-104, +-115, +-124, +-134, +-143, +-151, +-159, +-167, +-174, +-180, +-187, +-192, +-198, +-203, +-207, +-211, +-214, +-218, +-220, +-223, +-224, +-226, +-227, +-228, +-228, +-228, +-228, +-227, +-226, +-224, +-223, +-221, +-218, +-216, +-213, +-210, +-206, +-202, +-199, +-195, +-190, +-186, +-181, +-176, +-171, +-166, +-161, +-155, +-150, +-144, +-138, +-133, +-127, +-121, +-115, +-109, +-103, +-96, +-90, +-84, +-78, +-72, +-65, +-59, +-53, +-47, +-41, +-35, +-29, +-23, +-17, +-11, +-5, +0, +6, +12, +17, +22, +28, +33, +38, +43, +48, +53, +57, +62, +66, +70, +75, +79, +83, +86, +90, +93, +97, +100, +103; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/fifo_48m_to_122p88m.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/fifo_48m_to_122p88m.xcix new file mode 100644 index 00000000..fd22dbe5 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/fifo_48m_to_122p88m.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:498cef93c6f3022b571547dec25b0fb035337ad384b5cd31d4bc749d2861584c +size 15316475 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test.xcix new file mode 100644 index 00000000..9a1af0b8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:201d0f64179aee646661c351fafb6cfc75a99fba1d94d3bd0bdf24148f8a1e87 +size 27581687 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/README.txt new file mode 100644 index 00000000..023052ca --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.veo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.veo new file mode 100644 index 00000000..28b5802f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.veo @@ -0,0 +1,75 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fifo_generator:13.2 +// IP Revision: 4 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_48m_to_122p88m your_instance_name ( + .wr_rst_busy(wr_rst_busy), // output wire wr_rst_busy + .rd_rst_busy(rd_rst_busy), // output wire rd_rst_busy + .m_aclk(m_aclk), // input wire m_aclk + .s_aclk(s_aclk), // input wire s_aclk + .s_aresetn(s_aresetn), // input wire s_aresetn + .s_axis_tvalid(s_axis_tvalid), // input wire s_axis_tvalid + .s_axis_tready(s_axis_tready), // output wire s_axis_tready + .s_axis_tdata(s_axis_tdata), // input wire [15 : 0] s_axis_tdata + .m_axis_tvalid(m_axis_tvalid), // output wire m_axis_tvalid + .m_axis_tready(m_axis_tready), // input wire m_axis_tready + .m_axis_tdata(m_axis_tdata) // output wire [15 : 0] m_axis_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_48m_to_122p88m.v when simulating +// the core, fifo_48m_to_122p88m. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.vho b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.vho new file mode 100644 index 00000000..b36d574b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.vho @@ -0,0 +1,95 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fifo_generator:13.2 +-- IP Revision: 4 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT fifo_48m_to_122p88m + PORT ( + wr_rst_busy : OUT STD_LOGIC; + rd_rst_busy : OUT STD_LOGIC; + m_aclk : IN STD_LOGIC; + s_aclk : IN STD_LOGIC; + s_aresetn : IN STD_LOGIC; + s_axis_tvalid : IN STD_LOGIC; + s_axis_tready : OUT STD_LOGIC; + s_axis_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + m_axis_tvalid : OUT STD_LOGIC; + m_axis_tready : IN STD_LOGIC; + m_axis_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fifo_48m_to_122p88m + PORT MAP ( + wr_rst_busy => wr_rst_busy, + rd_rst_busy => rd_rst_busy, + m_aclk => m_aclk, + s_aclk => s_aclk, + s_aresetn => s_aresetn, + s_axis_tvalid => s_axis_tvalid, + s_axis_tready => s_axis_tready, + s_axis_tdata => s_axis_tdata, + m_axis_tvalid => m_axis_tvalid, + m_axis_tready => m_axis_tready, + m_axis_tdata => m_axis_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file fifo_48m_to_122p88m.vhd when simulating +-- the core, fifo_48m_to_122p88m. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_stub.v new file mode 100644 index 00000000..c35402e6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_stub.v @@ -0,0 +1,32 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Tue Mar 21 16:19:06 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top fifo_48m_to_122p88m -prefix +// fifo_48m_to_122p88m_ fifo_48m_to_122p88m_stub.v +// Design : fifo_48m_to_122p88m +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fifo_generator_v13_2_4,Vivado 2019.1.3" *) +module fifo_48m_to_122p88m(wr_rst_busy, rd_rst_busy, m_aclk, s_aclk, + s_aresetn, s_axis_tvalid, s_axis_tready, s_axis_tdata, m_axis_tvalid, m_axis_tready, + m_axis_tdata) +/* synthesis syn_black_box black_box_pad_pin="wr_rst_busy,rd_rst_busy,m_aclk,s_aclk,s_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[15:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[15:0]" */; + output wr_rst_busy; + output rd_rst_busy; + input m_aclk; + input s_aclk; + input s_aresetn; + input s_axis_tvalid; + output s_axis_tready; + input [15:0]s_axis_tdata; + output m_axis_tvalid; + input m_axis_tready; + output [15:0]m_axis_tdata; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_stub.vhdl new file mode 100644 index 00000000..36091bf7 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Tue Mar 21 16:19:06 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top fifo_48m_to_122p88m -prefix +-- fifo_48m_to_122p88m_ fifo_48m_to_122p88m_stub.vhdl +-- Design : fifo_48m_to_122p88m +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity fifo_48m_to_122p88m is + Port ( + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC; + m_aclk : in STD_LOGIC; + s_aclk : in STD_LOGIC; + s_aresetn : in STD_LOGIC; + s_axis_tvalid : in STD_LOGIC; + s_axis_tready : out STD_LOGIC; + s_axis_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axis_tvalid : out STD_LOGIC; + m_axis_tready : in STD_LOGIC; + m_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end fifo_48m_to_122p88m; + +architecture stub of fifo_48m_to_122p88m is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "wr_rst_busy,rd_rst_busy,m_aclk,s_aclk,s_aresetn,s_axis_tvalid,s_axis_tready,s_axis_tdata[15:0],m_axis_tvalid,m_axis_tready,m_axis_tdata[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fifo_generator_v13_2_4,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test.veo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test.veo new file mode 100644 index 00000000..734438ec --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test.veo @@ -0,0 +1,78 @@ +// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + +ila_rf_test your_instance_name ( + .clk(clk), // input wire clk + + + .probe0(probe0), // input wire [11:0] probe0 + .probe1(probe1), // input wire [0:0] probe1 + .probe2(probe2), // input wire [0:0] probe2 + .probe3(probe3), // input wire [0:0] probe3 + .probe4(probe4), // input wire [0:0] probe4 + .probe5(probe5), // input wire [0:0] probe5 + .probe6(probe6), // input wire [0:0] probe6 + .probe7(probe7), // input wire [0:0] probe7 + .probe8(probe8), // input wire [0:0] probe8 + .probe9(probe9) // input wire [11:0] probe9 +); + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file ila_rf_test when simulating +// the core, ila_rf_test. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.v new file mode 100644 index 00000000..cbf75d90 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:19d8ad4109babf969bdfe516c397a62b469ce49220b24c8d85e150a3319d7151 +size 1824426 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.vhdl new file mode 100644 index 00000000..680381a6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:449f65ac341f50fe588c835e11213443114b29b0fa40133ee2f5f46c10dbcd55 +size 3440051 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.v new file mode 100644 index 00000000..be350621 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu May 18 12:55:28 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v +// Design : ila_rf_test +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module ila_rf_test(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]" */; + input clk; + input [11:0]probe0; + input [0:0]probe1; + input [0:0]probe2; + input [0:0]probe3; + input [0:0]probe4; + input [0:0]probe5; + input [0:0]probe6; + input [0:0]probe7; + input [0:0]probe8; + input [11:0]probe9; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.vhdl new file mode 100644 index 00000000..ae79d844 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/ila_rf_test_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu May 18 12:55:28 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl +-- Design : ila_rf_test +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity ila_rf_test is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe3 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe4 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe5 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe6 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe7 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe8 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe9 : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + +end ila_rf_test; + +architecture stub of ila_rf_test is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/sim/ila_rf_test.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/sim/ila_rf_test.v new file mode 100644 index 00000000..76b0a200 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test/sim/ila_rf_test.v @@ -0,0 +1,80 @@ +// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module ila_rf_test ( +clk, + + +probe0, +probe1, +probe2, +probe3, +probe4, +probe5, +probe6, +probe7, +probe8, +probe9 +); + +input clk; + + +input [11 : 0] probe0; +input [0 : 0] probe1; +input [0 : 0] probe2; +input [0 : 0] probe3; +input [0 : 0] probe4; +input [0 : 0] probe5; +input [0 : 0] probe6; +input [0 : 0] probe7; +input [0 : 0] probe8; +input [11 : 0] probe9; + + +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k.veo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k.veo new file mode 100644 index 00000000..8e001935 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:fir_compiler:7.2 +// IP Revision: 12 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +lpf_125k your_instance_name ( + .aclk(aclk), // input wire aclk + .s_axis_data_tvalid(s_axis_data_tvalid), // input wire s_axis_data_tvalid + .s_axis_data_tready(s_axis_data_tready), // output wire s_axis_data_tready + .s_axis_data_tdata(s_axis_data_tdata), // input wire [15 : 0] s_axis_data_tdata + .m_axis_data_tvalid(m_axis_data_tvalid), // output wire m_axis_data_tvalid + .m_axis_data_tdata(m_axis_data_tdata) // output wire [39 : 0] m_axis_data_tdata +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file lpf_125k.v when simulating +// the core, lpf_125k. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k.vho b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k.vho new file mode 100644 index 00000000..688a4f73 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:fir_compiler:7.2 +-- IP Revision: 12 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT lpf_125k + PORT ( + aclk : IN STD_LOGIC; + s_axis_data_tvalid : IN STD_LOGIC; + s_axis_data_tready : OUT STD_LOGIC; + s_axis_data_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + m_axis_data_tvalid : OUT STD_LOGIC; + m_axis_data_tdata : OUT STD_LOGIC_VECTOR(39 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : lpf_125k + PORT MAP ( + aclk => aclk, + s_axis_data_tvalid => s_axis_data_tvalid, + s_axis_data_tready => s_axis_data_tready, + s_axis_data_tdata => s_axis_data_tdata, + m_axis_data_tvalid => m_axis_data_tvalid, + m_axis_data_tdata => m_axis_data_tdata + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file lpf_125k.vhd when simulating +-- the core, lpf_125k. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_stub.v new file mode 100644 index 00000000..aa511f56 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Tue Mar 21 16:04:38 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top lpf_125k -prefix +// lpf_125k_ lpf_125k_stub.v +// Design : lpf_125k +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "fir_compiler_v7_2_12,Vivado 2019.1.3" *) +module lpf_125k(aclk, s_axis_data_tvalid, s_axis_data_tready, + s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata) +/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[39:0]" */; + input aclk; + input s_axis_data_tvalid; + output s_axis_data_tready; + input [15:0]s_axis_data_tdata; + output m_axis_data_tvalid; + output [39:0]m_axis_data_tdata; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_stub.vhdl new file mode 100644 index 00000000..3d86a129 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/lpf_125k/lpf_125k_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Tue Mar 21 16:04:38 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top lpf_125k -prefix +-- lpf_125k_ lpf_125k_stub.vhdl +-- Design : lpf_125k +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity lpf_125k is + Port ( + aclk : in STD_LOGIC; + s_axis_data_tvalid : in STD_LOGIC; + s_axis_data_tready : out STD_LOGIC; + s_axis_data_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); + m_axis_data_tvalid : out STD_LOGIC; + m_axis_data_tdata : out STD_LOGIC_VECTOR ( 39 downto 0 ) + ); + +end lpf_125k; + +architecture stub of lpf_125k is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[39:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "fir_compiler_v7_2_12,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo new file mode 100644 index 00000000..b92dae58 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.veo @@ -0,0 +1,67 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 3 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +rom_freq_word your_instance_name ( + .clka(clka), // input wire clka + .addra(addra), // input wire [6 : 0] addra + .douta(douta) // output wire [10 : 0] douta +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file rom_freq_word.v when simulating +// the core, rom_freq_word. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho new file mode 100644 index 00000000..ab09483f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word.vho @@ -0,0 +1,79 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +-- IP Revision: 3 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT rom_freq_word + PORT ( + clka : IN STD_LOGIC; + addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + douta : OUT STD_LOGIC_VECTOR(10 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : rom_freq_word + PORT MAP ( + clka => clka, + addra => addra, + douta => douta + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file rom_freq_word.vhd when simulating +-- the core, rom_freq_word. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v new file mode 100644 index 00000000..13c0897c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:482fe668adab92087b21160a6d0e10fb3ffa2fc995638d5d08dd4a52b8409893 +size 28455 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl new file mode 100644 index 00000000..7611f3f6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cd58c0a4fa0a7a6a3fcc40039a214c48be722a8e4f124787effaeb782108b146 +size 41688 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v new file mode 100644 index 00000000..7a83bbe0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 18:56:10 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top rom_freq_word -prefix +// rom_freq_word_ rom_freq_word_stub.v +// Design : rom_freq_word +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) +module rom_freq_word(clka, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[10:0]" */; + input clka; + input [6:0]addra; + output [10:0]douta; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl new file mode 100644 index 00000000..c8c7c48b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/rom_freq_word_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 18:56:10 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top rom_freq_word -prefix +-- rom_freq_word_ rom_freq_word_stub.vhdl +-- Design : rom_freq_word +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity rom_freq_word is + Port ( + clka : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + +end rom_freq_word; + +architecture stub of rom_freq_word is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[10:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v new file mode 100644 index 00000000..bca88b77 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/rom_freq_word/sim/rom_freq_word.v @@ -0,0 +1,211 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 +// IP Revision: 3 + +`timescale 1ns/1ps + +(* DowngradeIPIdentifiedWarnings = "yes" *) +module rom_freq_word ( + clka, + addra, + douta +); + +(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) +input wire clka; +(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) +input wire [6 : 0] addra; +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) +(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) +output wire [10 : 0] douta; + + blk_mem_gen_v8_4_3 #( + .C_FAMILY("zynq"), + .C_XDEVICEFAMILY("zynq"), + .C_ELABORATION_DIR("./"), + .C_INTERFACE_TYPE(0), + .C_AXI_TYPE(1), + .C_AXI_SLAVE_TYPE(0), + .C_USE_BRAM_BLOCK(0), + .C_ENABLE_32BIT_ADDRESS(0), + .C_CTRL_ECC_ALGO("NONE"), + .C_HAS_AXI_ID(0), + .C_AXI_ID_WIDTH(4), + .C_MEM_TYPE(3), + .C_BYTE_SIZE(9), + .C_ALGORITHM(1), + .C_PRIM_TYPE(1), + .C_LOAD_INIT_FILE(1), + .C_INIT_FILE_NAME("rom_freq_word.mif"), + .C_INIT_FILE("rom_freq_word.mem"), + .C_USE_DEFAULT_DATA(0), + .C_DEFAULT_DATA("0"), + .C_HAS_RSTA(0), + .C_RST_PRIORITY_A("CE"), + .C_RSTRAM_A(0), + .C_INITA_VAL("0"), + .C_HAS_ENA(0), + .C_HAS_REGCEA(0), + .C_USE_BYTE_WEA(0), + .C_WEA_WIDTH(1), + .C_WRITE_MODE_A("WRITE_FIRST"), + .C_WRITE_WIDTH_A(11), + .C_READ_WIDTH_A(11), + .C_WRITE_DEPTH_A(81), + .C_READ_DEPTH_A(81), + .C_ADDRA_WIDTH(7), + .C_HAS_RSTB(0), + .C_RST_PRIORITY_B("CE"), + .C_RSTRAM_B(0), + .C_INITB_VAL("0"), + .C_HAS_ENB(0), + .C_HAS_REGCEB(0), + .C_USE_BYTE_WEB(0), + .C_WEB_WIDTH(1), + .C_WRITE_MODE_B("WRITE_FIRST"), + .C_WRITE_WIDTH_B(11), + .C_READ_WIDTH_B(11), + .C_WRITE_DEPTH_B(81), + .C_READ_DEPTH_B(81), + .C_ADDRB_WIDTH(7), + .C_HAS_MEM_OUTPUT_REGS_A(1), + .C_HAS_MEM_OUTPUT_REGS_B(0), + .C_HAS_MUX_OUTPUT_REGS_A(0), + .C_HAS_MUX_OUTPUT_REGS_B(0), + .C_MUX_PIPELINE_STAGES(0), + .C_HAS_SOFTECC_INPUT_REGS_A(0), + .C_HAS_SOFTECC_OUTPUT_REGS_B(0), + .C_USE_SOFTECC(0), + .C_USE_ECC(0), + .C_EN_ECC_PIPE(0), + .C_READ_LATENCY_A(1), + .C_READ_LATENCY_B(1), + .C_HAS_INJECTERR(0), + .C_SIM_COLLISION_CHECK("ALL"), + .C_COMMON_CLK(0), + .C_DISABLE_WARN_BHV_COLL(0), + .C_EN_SLEEP_PIN(0), + .C_USE_URAM(0), + .C_EN_RDADDRA_CHG(0), + .C_EN_RDADDRB_CHG(0), + .C_EN_DEEPSLEEP_PIN(0), + .C_EN_SHUTDOWN_PIN(0), + .C_EN_SAFETY_CKT(0), + .C_DISABLE_WARN_BHV_RANGE(0), + .C_COUNT_36K_BRAM("0"), + .C_COUNT_18K_BRAM("1"), + .C_EST_POWER_SUMMARY("Estimated Power for IP : 2.5016 mW") + ) inst ( + .clka(clka), + .rsta(1'D0), + .ena(1'D0), + .regcea(1'D0), + .wea(1'B0), + .addra(addra), + .dina(11'B0), + .douta(douta), + .clkb(1'D0), + .rstb(1'D0), + .enb(1'D0), + .regceb(1'D0), + .web(1'B0), + .addrb(7'B0), + .dinb(11'B0), + .doutb(), + .injectsbiterr(1'D0), + .injectdbiterr(1'D0), + .eccpipece(1'D0), + .sbiterr(), + .dbiterr(), + .rdaddrecc(), + .sleep(1'D0), + .deepsleep(1'D0), + .shutdown(1'D0), + .rsta_busy(), + .rstb_busy(), + .s_aclk(1'H0), + .s_aresetn(1'D0), + .s_axi_awid(4'B0), + .s_axi_awaddr(32'B0), + .s_axi_awlen(8'B0), + .s_axi_awsize(3'B0), + .s_axi_awburst(2'B0), + .s_axi_awvalid(1'D0), + .s_axi_awready(), + .s_axi_wdata(11'B0), + .s_axi_wstrb(1'B0), + .s_axi_wlast(1'D0), + .s_axi_wvalid(1'D0), + .s_axi_wready(), + .s_axi_bid(), + .s_axi_bresp(), + .s_axi_bvalid(), + .s_axi_bready(1'D0), + .s_axi_arid(4'B0), + .s_axi_araddr(32'B0), + .s_axi_arlen(8'B0), + .s_axi_arsize(3'B0), + .s_axi_arburst(2'B0), + .s_axi_arvalid(1'D0), + .s_axi_arready(), + .s_axi_rid(), + .s_axi_rdata(), + .s_axi_rresp(), + .s_axi_rlast(), + .s_axi_rvalid(), + .s_axi_rready(1'D0), + .s_axi_injectsbiterr(1'D0), + .s_axi_injectdbiterr(1'D0), + .s_axi_sbiterr(), + .s_axi_dbiterr(), + .s_axi_rdaddrecc() + ); +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen.veo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen.veo new file mode 100644 index 00000000..a92c53aa --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen.veo @@ -0,0 +1,80 @@ + +// +// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//---------------------------------------------------------------------------- +// User entered comments +//---------------------------------------------------------------------------- +// None +// +//---------------------------------------------------------------------------- +// Output Output Phase Duty Cycle Pk-to-Pk Phase +// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) +//---------------------------------------------------------------------------- +// clk_out1____48.000______0.000______50.0______172.739____111.288 +// +//---------------------------------------------------------------------------- +// Input Clock Freq (MHz) Input Jitter (UI) +//---------------------------------------------------------------------------- +// __primary__________122.88____________0.010 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG + + sig_clk_gen instance_name + ( + // Clock out ports + .clk_out1(clk_out1), // output clk_out1 + // Status and control signals + .reset(reset), // input reset + .locked(locked), // output locked + // Clock in ports + .clk_in1(clk_in1)); // input clk_in1 +// INST_TAG_END ------ End INSTANTIATION Template --------- diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_stub.v new file mode 100644 index 00000000..8a037d17 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +// Date : Tue Mar 21 14:52:21 2023 +// Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +// Command : write_verilog -force -mode synth_stub -rename_top sig_clk_gen -prefix +// sig_clk_gen_ sig_clk_gen_stub.v +// Design : sig_clk_gen +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +module sig_clk_gen(clk_out1, reset, locked, clk_in1) +/* synthesis syn_black_box black_box_pad_pin="clk_out1,reset,locked,clk_in1" */; + output clk_out1; + input reset; + output locked; + input clk_in1; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_stub.vhdl new file mode 100644 index 00000000..cb846cdf --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/sig_clk_gen/sig_clk_gen_stub.vhdl @@ -0,0 +1,31 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (win64) Build 2644227 Wed Sep 4 09:45:24 MDT 2019 +-- Date : Tue Mar 21 14:52:21 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode synth_stub -rename_top sig_clk_gen -prefix +-- sig_clk_gen_ sig_clk_gen_stub.vhdl +-- Design : sig_clk_gen +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity sig_clk_gen is + Port ( + clk_out1 : out STD_LOGIC; + reset : in STD_LOGIC; + locked : out STD_LOGIC; + clk_in1 : in STD_LOGIC + ); + +end sig_clk_gen; + +architecture stub of sig_clk_gen is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk_out1,reset,locked,clk_in1"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v new file mode 100644 index 00000000..56471ab0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/sim/vio_manual_ctrl.v @@ -0,0 +1,68 @@ +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module vio_manual_ctrl ( +clk, + +probe_out0, +probe_out1, +probe_out2, +probe_out3, +probe_out4 +); + +input clk; + +output reg [2 : 0] probe_out0 = 'h4 ; +output reg [0 : 0] probe_out1 = 'h0 ; +output reg [31 : 0] probe_out2 = 'h00000000 ; +output reg [1 : 0] probe_out3 = 'h3 ; +output reg [3 : 0] probe_out4 = 'h0 ; + + +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo new file mode 100644 index 00000000..4832fe5b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.veo @@ -0,0 +1,70 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:vio:3.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +vio_manual_ctrl your_instance_name ( + .clk(clk), // input wire clk + .probe_out0(probe_out0), // output wire [2 : 0] probe_out0 + .probe_out1(probe_out1), // output wire [0 : 0] probe_out1 + .probe_out2(probe_out2), // output wire [31 : 0] probe_out2 + .probe_out3(probe_out3), // output wire [1 : 0] probe_out3 + .probe_out4(probe_out4) // output wire [3 : 0] probe_out4 +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file vio_manual_ctrl.v when simulating +// the core, vio_manual_ctrl. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho new file mode 100644 index 00000000..0775b07e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl.vho @@ -0,0 +1,85 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:vio:3.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT vio_manual_ctrl + PORT ( + clk : IN STD_LOGIC; + probe_out0 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); + probe_out1 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out3 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + probe_out4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : vio_manual_ctrl + PORT MAP ( + clk => clk, + probe_out0 => probe_out0, + probe_out1 => probe_out1, + probe_out2 => probe_out2, + probe_out3 => probe_out3, + probe_out4 => probe_out4 + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file vio_manual_ctrl.vhd when simulating +-- the core, vio_manual_ctrl. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v new file mode 100644 index 00000000..c7abe00f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cb065d0eddb5b655bab77fb0852a87bb5011a810896d8e714356346485691606 +size 353149 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl new file mode 100644 index 00000000..69476f18 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ce8bf1803b3191b816081504adefaa817efc0507189277d23ceb58cfe1deba32 +size 635009 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v new file mode 100644 index 00000000..4ca646b3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 17:56:01 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v +// Design : vio_manual_ctrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; + input clk; + output [2:0]probe_out0; + output [0:0]probe_out1; + output [31:0]probe_out2; + output [1:0]probe_out3; + output [3:0]probe_out4; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl new file mode 100644 index 00000000..7883d1ed --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_manual_ctrl/vio_manual_ctrl_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 17:56:01 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl +-- Design : vio_manual_ctrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_manual_ctrl is + Port ( + clk : in STD_LOGIC; + probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + +end vio_manual_ctrl; + +architecture stub of vio_manual_ctrl is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/sim/vio_rf_control.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/sim/vio_rf_control.v new file mode 100644 index 00000000..0a3ca737 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/sim/vio_rf_control.v @@ -0,0 +1,91 @@ +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module vio_rf_control ( +clk, +probe_in0, +probe_out0, +probe_out1, +probe_out2, +probe_out3, +probe_out4, +probe_out5, +probe_out6, +probe_out7, +probe_out8, +probe_out9, +probe_out10, +probe_out11, +probe_out12, +probe_out13, +probe_out14, +probe_out15 +); + +input clk; +input [10 : 0] probe_in0; + +output reg [0 : 0] probe_out0 = 'h0 ; +output reg [1 : 0] probe_out1 = 'h0 ; +output reg [0 : 0] probe_out2 = 'h0 ; +output reg [5 : 0] probe_out3 = 'h08 ; +output reg [5 : 0] probe_out4 = 'h38 ; +output reg [11 : 0] probe_out5 = 'h3E8 ; +output reg [0 : 0] probe_out6 = 'h0 ; +output reg [0 : 0] probe_out7 = 'h0 ; +output reg [0 : 0] probe_out8 = 'h0 ; +output reg [0 : 0] probe_out9 = 'h0 ; +output reg [0 : 0] probe_out10 = 'h0 ; +output reg [0 : 0] probe_out11 = 'h0 ; +output reg [0 : 0] probe_out12 = 'h0 ; +output reg [31 : 0] probe_out13 = 'h00000000 ; +output reg [0 : 0] probe_out14 = 'h0 ; +output reg [31 : 0] probe_out15 = 'h00000000 ; + + +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.veo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.veo new file mode 100644 index 00000000..2f5a2d03 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.veo @@ -0,0 +1,82 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:vio:3.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +vio_rf_control your_instance_name ( + .clk(clk), // input wire clk + .probe_in0(probe_in0), // input wire [10 : 0] probe_in0 + .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 + .probe_out1(probe_out1), // output wire [1 : 0] probe_out1 + .probe_out2(probe_out2), // output wire [0 : 0] probe_out2 + .probe_out3(probe_out3), // output wire [5 : 0] probe_out3 + .probe_out4(probe_out4), // output wire [5 : 0] probe_out4 + .probe_out5(probe_out5), // output wire [11 : 0] probe_out5 + .probe_out6(probe_out6), // output wire [0 : 0] probe_out6 + .probe_out7(probe_out7), // output wire [0 : 0] probe_out7 + .probe_out8(probe_out8), // output wire [0 : 0] probe_out8 + .probe_out9(probe_out9), // output wire [0 : 0] probe_out9 + .probe_out10(probe_out10), // output wire [0 : 0] probe_out10 + .probe_out11(probe_out11), // output wire [0 : 0] probe_out11 + .probe_out12(probe_out12), // output wire [0 : 0] probe_out12 + .probe_out13(probe_out13), // output wire [31 : 0] probe_out13 + .probe_out14(probe_out14), // output wire [0 : 0] probe_out14 + .probe_out15(probe_out15) // output wire [31 : 0] probe_out15 +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file vio_rf_control.v when simulating +// the core, vio_rf_control. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.vho b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.vho new file mode 100644 index 00000000..9934f43c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control.vho @@ -0,0 +1,109 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:vio:3.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT vio_rf_control + PORT ( + clk : IN STD_LOGIC; + probe_in0 : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out1 : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + probe_out2 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out3 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + probe_out4 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); + probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + probe_out6 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out7 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out8 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out9 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out10 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out12 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out13 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out14 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out15 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : vio_rf_control + PORT MAP ( + clk => clk, + probe_in0 => probe_in0, + probe_out0 => probe_out0, + probe_out1 => probe_out1, + probe_out2 => probe_out2, + probe_out3 => probe_out3, + probe_out4 => probe_out4, + probe_out5 => probe_out5, + probe_out6 => probe_out6, + probe_out7 => probe_out7, + probe_out8 => probe_out8, + probe_out9 => probe_out9, + probe_out10 => probe_out10, + probe_out11 => probe_out11, + probe_out12 => probe_out12, + probe_out13 => probe_out13, + probe_out14 => probe_out14, + probe_out15 => probe_out15 + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file vio_rf_control.vhd when simulating +-- the core, vio_rf_control. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.v new file mode 100644 index 00000000..a82bf59b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:61871bc56b34526261f6ee93952fb8c48de88deae16fa932900a16de7cd4b693 +size 418849 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.vhdl new file mode 100644 index 00000000..285e9cc8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7d4547a5ef5862f5cc376f41a5d671a805063b6777f0f60d9e8d278616fba128 +size 727945 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.v new file mode 100644 index 00000000..e5624f99 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.v @@ -0,0 +1,39 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu May 18 11:36:40 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v +// Design : vio_rf_control +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_rf_control(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */; + input clk; + input [10:0]probe_in0; + output [0:0]probe_out0; + output [1:0]probe_out1; + output [0:0]probe_out2; + output [5:0]probe_out3; + output [5:0]probe_out4; + output [11:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; + output [0:0]probe_out9; + output [0:0]probe_out10; + output [0:0]probe_out11; + output [0:0]probe_out12; + output [31:0]probe_out13; + output [0:0]probe_out14; + output [31:0]probe_out15; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.vhdl new file mode 100644 index 00000000..a80bc92f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control/vio_rf_control_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu May 18 11:36:40 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl +-- Design : vio_rf_control +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_rf_control is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end vio_rf_control; + +architecture stub of vio_rf_control is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/hdl/vio_v3_0_20_vio_include.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/hdl/vio_v3_0_20_vio_include.v new file mode 100644 index 00000000..0673f57f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/hdl/vio_v3_0_20_vio_include.v @@ -0,0 +1,283 @@ +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "XILINX" +`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" +`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`pragma protect key_block +GbQWy7xyRnDVKNEgu/syxcQSo3KIIWjSBPIwi/pSAYCe9sIQf1xA0ykhHf7s3r7GRWRS+sel+0Xx +XWe4lBDDrw== + +`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +rLh670IEMVEjBamdsB+LhhoxrK6I5H9wfmPCOFqaLelJt08QWbH7WNvjIhNNz7hnkT7w+wDWT6AH +9ZJgOGPSJmj9pWoXHAojkkRBTIXpFT11+IDyFQ4FgN2TPXWILoYGY+uZG1GlGN7dsEIm5HUCUy2c +eVhT3XSIJDvufMyiJUc= + +`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +KgKxjU+tI9TXRZLkaaosEf4JcTfzGtF82aOinFlVe78eUyHdMvwHHcKsxUKAjkhYW491bZ0jTKit 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bytes = 256) +`pragma protect key_block +FGUAaXx6dK7W5dgDUXY6j9xLpCHdbPvbaH+O+ozu9kcNjL5BJcGWnTdooAxaZdBsOZBvrVuXUU4v +ev5owQI9+5/+8aoXfeX2zZHp++ESqotCFj5ykw8BPjwCOCZz+tiV1Q8ISqf/NCuDNU2KJyvQUsFX +cOXAwCPvrI5SwQ04u9sVTaHwAuTuRw3j6nkt6BHWrjKpq9pUfNH4L04ag/tUGVpnlcSBGewN0ieC +xkzVV1mPCyCu/thxu0k0yda5pS/u3MFeC1N8rTrSsLEZMUiPYg/BwwWGT7D/s9FCMbbM2kyoUXpa +draqn+K8c06CQxLI+ieilCd38M25buwOc3ANjg== + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +ucIv1ZvudBg6K9ubpyCObknzSo2JKwxETiac5kbTyw0xwj34bo+xJ/DnUCoAdEVHZcAwDc9Fhbhv +j5a7MwnHY+TpzDjhwdN75A97jOZ4V65wcuFErbH19OSacDchGykcwXCiaA5haDJK2hF1qPxu7TtO +R19uHYIhWP+7IpmjTiQ= + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +AI09c0Va0j6swrG6tMKXPaWcjMpXDnvuIze3bAe9Cj0tCXFumugM/pZL81X53kMwmKPvRCpTi8DM +kLLATubglrp6DudyaIY943skTmlH+as6fKaHODrTcy4CDIP4kKrok/7y1rBI6+YAfN3ZIW+45MiV +cHuhXHXxxXblzCT6obAZK5QUCP2qZKgO0jjI1RD7ZEJuS/mX5wkIAvOe8L1HBkyUsRq6Cu30W6u9 +7VI3LOy7TZqb6Nix6Ok85ylO82KP12tdXY2IRivakKu4fdWQ6vc3ARiefSR0+RDmE/eZzhzQbt26 +mf7t4ZoEITJYnmd5zcenAnw+6AO3fUwtTLT81Q== + +`pragma protect data_method = "AES128-CBC" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12464) +`pragma protect data_block +vLDJJUgjrlRfGtI6e1+Byt5lDBB9Oezy8FH9Uy/Lem9icZpnVjts8rEqPHcw31BJ5u3y4ePWkCUm +QQfQ8vh3WaO2dCX+QhbDMTmPaIe/t8nHJKefrbW5OY3eRKkptlVSIFCFITpJlzyfpSe0CsF+dWLc +F4J0aJzlQEKkTcCFk2ey1erWcvHgIf6eCwkGouO/COjRPomcaMzJt3ty3PwhKodmumGUICNXKjG/ +lH5VI4pSkr0hpeNp/WZhHstrrYJB7GSwMCqfL0IH36wCF3R29Yjp7ouoogJ4+imS5vnMJpU2Czmi +PFyY3LiBeZ4VP5b8Iv0AK4XoJtM3XG9iTBAC/oslCJUtBhINFPia8EueAVn178qtq+htmZXlEAbM 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++p+HcJdQfSOpF6AkpWZLChsoTMd2F24Ztmjz3/vNIapPf4rcObfDEJwayu7hSrsslcCIcoXdojo4 +VXLn2QFVUYMgSq3pYGFywvmQTA5x/JAfOcWO8IBKdixvS3F6xSTwH8JaKocC0735inh65PwNjS9F +2KIwvgHQvLpCxNny+0NvSQ7ETTouC6xXj+EUv4bGpml7J3HNjixHtTPfYXf7cl0mqQmUDJu0wLkp +WuvXFDvCxpwSZ5qw+1H5MPeue3MeB1Z6Ibu51Fs1EwnAe/g9C0Mo1XDCD6LfVjvpZYE62HzlzF/K +IJoLfeJT0O0VhjqhC3+M3TGXHNYm6chuUtfNR31cC7WgG/QiHYOVySvp3zljDZWrxsgHO+JwhbQC +n8ALL+g50X6+uS5w/HkFBsxwCIocmViJb0ojg1j2ncsUjwwEqkDBprVPYFh6Zimk5SJ9f3RO6pQj +saDd3hitIgpMf1ha8rpCYBkwqBTogxXfwijLMplBdGWVGSSSnnp6jTnWb0sV2VPA1l2X6Iq+pomM +jilYYfQ2dBuXFEMpQpwDC3/8N4YxpDZWX3gtyK2XV+2BcRONvrl/naflTsXxuXAhSxOBqggJw7pL +HvsOGKk0ng6uKC5yQPc6Q0SbWwwT54D9vLM4U1OiRKPpL9S1YXak+W8ZCXqdHkQNlUlm21ssL4dl +Et7q9IF5Vil/wnUjm0nJxVZ4QJU/uN7icrtnrvAf1gVLwK3fpC0ed6ku9s7Lq1KvNb7NEPDrOu3Q +hg+xhyl9MJTquidnbUsYlHdTvVzxIkI4q/1kx5mkbEjiIWG0R+haIwSqhTCdxpxxTgm+LGAtWJ4W +lEuCQ2VEu3cyamx3PWNKPt+CE1VayIkgGqEBXIaGpwkymL0y6hkgrA+q+2msQq245iR7XC83U26E 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00000000..d9ec5846 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/sim/vio_rf_test.v @@ -0,0 +1,82 @@ +// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. +`timescale 1ns / 1ps +module vio_rf_test ( +clk, + +probe_out0, +probe_out1, +probe_out2, +probe_out3, +probe_out4, +probe_out5, +probe_out6, +probe_out7, +probe_out8, +probe_out9, +probe_out10, +probe_out11 +); + +input clk; + +output reg [0 : 0] probe_out0 = 'h0 ; +output reg [7 : 0] probe_out1 = 'h1f ; +output reg [7 : 0] probe_out2 = 'h1f ; +output reg [31 : 0] probe_out3 = 'h003A9800 ; +output reg [0 : 0] probe_out4 = 'h0 ; +output reg [11 : 0] probe_out5 = 'h3E8 ; +output reg [11 : 0] probe_out6 = 'h5DC ; +output reg [31 : 0] probe_out7 = 'h00004800 ; +output reg [31 : 0] probe_out8 = 'h000000C0 ; +output reg [63 : 0] probe_out9 = 'h0000000000009600 ; +output reg [4 : 0] probe_out10 = 'h10 ; +output reg [0 : 0] probe_out11 = 'h0 ; + + +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.veo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.veo new file mode 100644 index 00000000..76f0f1df --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.veo @@ -0,0 +1,77 @@ +// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + +// IP VLNV: xilinx.com:ip:vio:3.0 +// IP Revision: 20 + +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +vio_rf_test your_instance_name ( + .clk(clk), // input wire clk + .probe_out0(probe_out0), // output wire [0 : 0] probe_out0 + .probe_out1(probe_out1), // output wire [7 : 0] probe_out1 + .probe_out2(probe_out2), // output wire [7 : 0] probe_out2 + .probe_out3(probe_out3), // output wire [31 : 0] probe_out3 + .probe_out4(probe_out4), // output wire [0 : 0] probe_out4 + .probe_out5(probe_out5), // output wire [11 : 0] probe_out5 + .probe_out6(probe_out6), // output wire [11 : 0] probe_out6 + .probe_out7(probe_out7), // output wire [31 : 0] probe_out7 + .probe_out8(probe_out8), // output wire [31 : 0] probe_out8 + .probe_out9(probe_out9), // output wire [63 : 0] probe_out9 + .probe_out10(probe_out10), // output wire [4 : 0] probe_out10 + .probe_out11(probe_out11) // output wire [0 : 0] probe_out11 +); +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file vio_rf_test.v when simulating +// the core, vio_rf_test. When compiling the wrapper file, be sure to +// reference the Verilog simulation library. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.vho b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.vho new file mode 100644 index 00000000..37776596 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test.vho @@ -0,0 +1,99 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:vio:3.0 +-- IP Revision: 20 + +-- The following code must appear in the VHDL architecture header. + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +COMPONENT vio_rf_test + PORT ( + clk : IN STD_LOGIC; + probe_out0 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out1 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + probe_out2 : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + probe_out3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out4 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + probe_out5 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + probe_out6 : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); + probe_out7 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out8 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + probe_out9 : OUT STD_LOGIC_VECTOR(63 DOWNTO 0); + probe_out10 : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); + probe_out11 : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) + ); +END COMPONENT; +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : vio_rf_test + PORT MAP ( + clk => clk, + probe_out0 => probe_out0, + probe_out1 => probe_out1, + probe_out2 => probe_out2, + probe_out3 => probe_out3, + probe_out4 => probe_out4, + probe_out5 => probe_out5, + probe_out6 => probe_out6, + probe_out7 => probe_out7, + probe_out8 => probe_out8, + probe_out9 => probe_out9, + probe_out10 => probe_out10, + probe_out11 => probe_out11 + ); +-- INST_TAG_END ------ End INSTANTIATION Template --------- + +-- You must compile the wrapper file vio_rf_test.vhd when simulating +-- the core, vio_rf_test. When compiling the wrapper file, be sure to +-- reference the VHDL simulation library. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_sim_netlist.v new file mode 100644 index 00000000..b0f9aad4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:5c56114c4d1dbd4de738da259f25557427b35cb18dfeb59dda5bf2598412b05e +size 477028 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_sim_netlist.vhdl new file mode 100644 index 00000000..0ffb41e3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:0d14ce253bc7bd29c3d5ba48eb5bde1db77a4576966d51a7f7133d0cfa5da73e +size 802152 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.v new file mode 100644 index 00000000..374e48d6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.v @@ -0,0 +1,34 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu May 18 12:54:39 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v +// Design : vio_rf_test +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_rf_test(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]" */; + input clk; + output [0:0]probe_out0; + output [7:0]probe_out1; + output [7:0]probe_out2; + output [31:0]probe_out3; + output [0:0]probe_out4; + output [11:0]probe_out5; + output [11:0]probe_out6; + output [31:0]probe_out7; + output [31:0]probe_out8; + output [63:0]probe_out9; + output [4:0]probe_out10; + output [0:0]probe_out11; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.vhdl new file mode 100644 index 00000000..290eaedb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test/vio_rf_test_stub.vhdl @@ -0,0 +1,42 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu May 18 12:54:39 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl +-- Design : vio_rf_test +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_rf_test is + Port ( + clk : in STD_LOGIC; + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 63 downto 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end vio_rf_test; + +architecture stub of vio_rf_test is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff 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+ATFIQi/0T5kkdzeZ0JX4tYMUT5lkBivxYFlxdSQy5Ql35ikZrr9ajK98GUON+eMcoj1kzc+JosYk +dRt+AYJW72mav4u4IRbeRcLWCWSJ8WaNeEyPytuEuYHCLrpQ9Oo/Mfgsuoc3RZSyGgVXvEHpsyvS +TBv+85b9pVNWfOrN+6CpVPjLZLYOJ0PoAzXNrAL8JAqkYUbHwxpiFDcSHvXwJruKZJx4kc8nwniS +5xugBWOBf0UMO2o8F9wEynT2jZtbIhanNq3u7wJ8V+7VVThnp0zLfPoGIQJUprDguIYcdt0mnjrg +yxy0iNJi25SOsBBIIiCcv49E/thornbEpyEEgeOHvAZt2w6TuU/WMv833PCpOw0aECmn8BwYdVoG +4uC0M0kQ9wF3zp5MtMVudBqLFF9e4LbBdD3dtRyZphDjqzzo7bh4RRZtEseZarbATT/YlH3QpTFN +ov2kFVaR0LSU6FplxxhdCQpfZgMFbjb32S8HssvszEUdh/EdqwfIB/P32P8qT9ORgVMh/QCNeFhW +47th8hIfJkZFuVqDQQOgxAQleCfqb5Q8m6ako015USjWWmcmOAAEAX4G8Dfi0WnYvJ6Hb/qJwcTA +jHmoT3O3G8hwCu1/Fz54AzDeO25P6ECOBmIC07SfjVg3S2YUc09lPnNeZzqlSN9O67bmgEecoACT +3PHGAS40pOE+tWlrRmiPbvf0Tb8S3ZZ2HzZwkcoFwo6ef+/SlASPsakva2Z+N2/2ZD9n0BWARjjT +vV1NCyczO7zprZZniQqLcinLVSrnN0H6qnCHw8Ek8bxlIPQ5bBLhnhXBfFImbGg23wd7WbiSN72d +CAH5BQ== +`protect end_protected diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.v new file mode 100644 index 00000000..5ddf59df --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ipstatic/hdl/fifo_generator_v13_2_rfs.v @@ -0,0 +1,7759 @@ +`pragma protect begin_protected +`pragma protect version = 1 +`pragma protect encrypt_agent = "XILINX" +`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" +`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`pragma protect key_block +DjS90P3uFTSw2mNkyo7whVN8nQMcIWM6EHWVElsN47CcN0PotbZr5yaRyuvD56v2YltRSiZwXSQy +t7AcNCbGZQ== + +`pragma protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +hiVCRxNjjt2CnC5oMAP3ypF4T/SDQoivbp3hHV/egYgk2rTt3KW8s20nPTdA7bqwu15MQ4AjN0Ew +gz2/uFDH24mvKdEJjniutuoeoEoaq6PuIRR6tRvoNST0uraQpYDfFhfmYm1yWCMa5EdGH4j2xTuc +Ijhyd8+GE0AaXM0xQIU= + +`pragma protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +e1mRT8ojQhBviZ5mhgrVX6nk2Hin2nFB3sL8+GGF6uHJiaKlQcx1qiiIsa29NwwY+8L0+Sdc7Bwe +mimrmbB5AW3jQqY6SEA/pBsbopf8h5Cs+GFB69BVnMkH76EcmugXQ/U/WMttt/+0U8ebTqOzvVsh +maHchLdTcOMOGk0KOjqA3xeuYmSZ6QeTgx46yhlrFl02l5IxZBDyc3AMp2ewPv16zqkfWaJOnoMI +96IlQUocffCNrvYI9VB7uzEeo3jTE38GXFtw3Q00lt2MHP9hUS/CiFr2UC6MC78dvswwb6bkVW3D +8ky4L9f1zBEmW5MWwTmiVti/DPrF3aEru1ofBA== + +`pragma protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +mUmBQsaNGyqiVGrFwcTlR7MlTbnLOIYvHGlTVF0C1ji5bA0lK7umMKDXoVdfcTdwSKMExNj7Gqox +VFyrxtLrcpmqGiIap2SWS3Pbm874s4Y6boEMWVg7iUp4jnShKY232v9uNA++5R50qMYGP28FrJIe +67CdBh1O5ebOulWQaNirGAhsjQsF7b3Cz6jaLeI1oJdU9hFy1i5CotH3pUIwl75WQTFELhIzGFJw +r+KBwc5Dq/NP/wLmLPF62Bjy5X55LNsAHF1KZHrn/0SAiUai5QTpvrF1bMBhdoOwgj9TdBxp10UR +ydrxJub3MKUcBFv82RIymzgfizOLvI3D5Nbw4g== + +`pragma protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +P6yM9rb+3ZSH3KAr+tYUrDq1Lk26TDI18CdQdkrwI/gFgEiezF7pits6q49vdg27InqmPAeVCPYY +tosVszatEbVDv25/d5bIqaJAFdItcv/k8LBENIcclMqHXboE89+WBj/paWV33wGxzetDbrLUcN8F +CaZYqeKlNRLefNFQj5Dsfj4UTij0sgLfOH1iy26WYH6nIn71GQwdEOL8SXnt5COpc8vW2pK0rfcc +Q44nD+DVeUtyJfi0pNnjRnxB8RG3XpHT+y5InxzplAQwqNX3jEOvGWKeGvFE2URX7ShCbxAO23ZZ +RlGALFYygMBRaRB81iOtWsbirGnPKHdywhWj5g== + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`pragma protect key_block +n4o0T1bNPxuQFkrUx0Ji5GI/A+zutd6cZlB6EJIp/nUQ6V6+8P3wlB0UwPr9oZS0abDQuVXUihUq +uDu7HyKmHJy++CIFFJDIQv4rl9HX54ETfMZCCR0RjpZIYxW63Uvllzoja06zTD3BSPM8PoTAObKo +7XfbQrWoFsgjPX2Ts2Y= + +`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`pragma protect key_block +DPQpIqZ6YzUjSFNpvyY7jAnjsdVo1QBPFA7qtFu6mz76h7KyHee6vS2ejnLNPq3d8NvwNWkXhNH3 +R56P15Df3xRt8kSokTs3j8NQHP7c+hkMmTiaOywTBVnrai2/oFILCt5ujXPbRzSy9jj9uukoddqa +R0OW369sAbUuHvDLDzp81bKH2NDTec7Ck8Zl8yvn3wzENYP/JI/e/FPV8iwcHuOMZIeOxknj4jly +Dp++plsL1cTqYFr3bhNi+pvHFGEtI5hCat9fJgyLsQjsng02YP76lS5wANjNmtc6NawCEIpNflSn +Q9QNQWFy2rnD1nT1TUSPf/hMBMpWP8JW4UkN0A== + +`pragma protect data_method = "AES128-CBC" +`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 438576) +`pragma protect data_block +HX36iU68pDvdSeX+AwGrhWdDMdGxhZr/Tuwx9UlSWc8p3R9ZmajXwkYdJ7rRY5BneNZfpCWnv5GW +sxa8cAU0r1hatJk8YNlsocVmTz7OEH3nIai9l7va98Fh4P1dn3x0oa8IG+sAT0uWK+mOuuQMqPj1 +0JhsZdLZDSrIdmpQYPH3u7GfR0QKfF0h+UX2sMuckAzaMa9GjXTVB2Tke1o9f1qQUWJw7UMtLUac +A9WJXduixx2YWsjpPQ2o5cF93rvp4XFEI941SxWGUQLMJKA9r7c3wAfpjh1kxMmP45JO9kS58kg4 +pEoKtckY70mZqistG8V7/UEIvvPx3rk6flYy2kXCvo/vzsHcJWdd6VrMXemEq6EOPVTQpJ+Ohi0T +PjY9w9QNP49M4N1kXarbQuPcY+0Mk4vcloIkChVDU68PwD7eXV5zASW/l6KxtYeV6Ixs893EJwjM +2sWPNKiFw3oj/tqHZa2LrjjWKYMf9VQx8gC/gfFftrmQA5iGOE/unsvniGAytXTtFcxQSmBENwZe +tbOUmqF42a+hyWVP/YFRI7NMCPPoXNlhBoGUVjZPag8mGPQH4xMzVXdt+Qj5qhkFSaItQassvZ8f +EQUvd0w2YPjO8rCXuXxC8oR9HVwndUmKDn9UQuGontqQGi/YP/Onzk+hI+mYqSaMKDLPYyyf1yn0 +wegO8jHIUBb4GcxPWarr21pmu8/r/+GGv3oVN3t5zsdfQieIYRD2sqCLPxpCAfHtKHK+HOSSTUG3 +r5fHR9N8AAn/h85AaHB2FAwo/Yaj8HBWaZIl2ywy2kxtA6KAlsTVa3MzwJI+D+/oLF9WPpC5Y6jw +Gy4vQeyoMedomKDQepUKkwCUV6die0ue7G4DifkqaAaD1rafRnfXz2AdUTnZcbFZvK2Vs7MSNZFY +8q7OzLZQ+1OgwjKVNyM1ZRJTNsYo39KbD9cqMwCX7ZzSHhBC7Zi5FpJ6Sr8tCx5ahKS56S78eO5v +8w74td+w+yu/pBFG8qtTO0eRgRACsj190ET+GbaB07+7xrwVS/JDHwm36HfyhDcm1BRGDNOdy47f +3Ctew7/lbApv8jCwz2yxsvOz1g3aoOK1uzLHRRpI3+oVkGSiYzjAYQADILeczm6Opw8pyJi3Kv4u +oS9RTXeuvGebYL6YnyIQUdWGTrSMkwb6gV1CI5Ja8jUbqWsM+KBmdKPuHKx+geKlh654JLSOekTL +Zhu/5oMrU0IWZWHthXlxupsvoCnPL0GlHzVSD/0CriVAOVmTx4n5ioPqKUaeIkYBOM/3OqgMB2BG +BaXw5rRA1SFXBZUZqkjh6faXGRH4xMbh6FBNzaq1cGFVJ2syJmO9vGlwwt+0N05ZSwH1xs9Sf41k +IpNvhKt4Sd6+3/RuVpGr6w1ygLnKi09D0OvuwE4rP9qJfNaDPaCtA2xVr9b34HzA//ehbmmso16a +CXvtGBvyH1oLLiOXdQ7+KvVsOb6bWm5xT1yXdUaoidNFMuvi2WUjQ5y/+HA6BTeb3mqZMMvYYFOH +1BtLuQ5EgZH142wYO7q7M999tf0rIh+ohqzsY1a92xKYcVK2bj/MHi+DAKYwUNTFqyzonL87LXgR +4SkOCOzRgnYVvHM+gONJWqQpwQsMWu98zC1fLZnilgKbcxPqiE/lspgq46LpDsUOT0rowgb0lL/E +OB9Wit4oKdQDTcbOcVDAyq3/HzAmx/lKv/k2dkF24x641lcboFkdHI1rRV11qrCgLHSpiNbzYEjT +4s/tZyFptJn/ppksHjLlElXQg6SzPZwIqlThV3xFg6BUccGaVmcvhfiQQqx3n0KsESj1/W9/+K73 +9EyQ59RN/FUTnIfXd1fIsgU8wWFAi/b/4Mjt9XtJV+S7t2bajLwdzi5Fd/TNImYcSeDIbIyau8Zc +//0TLaGoysIFhzVEH8HjXuUZ6lAuugqouq3T+LJC8F+u8kHz1IGVk5RRu2yz5KOb4FNFXM/xT6Y4 +4eR8i7X0H+WIxuY0V408/Famxy1ju9lNZittvEzTSoSgoKn9+Wtwl3V4WZ1iGdSdKMBUsL2CA0JI +aIkfpS14t+MAbpNBKeB8v0fDa+Shw4frx0ZX9XfgyBPn6ohb88iKhpwOfaXK+oBa35/qEV+b3EM3 +MLPZv3NSL2R8EJcLIEUMsIovqaBGcEPKnSsVq4M2DVbu9xjjeUn/32OGAxWTC8Uwdc2hK+sQ1Wl3 +w+t7eRqwTLJhNY9IxL5syWOdaJ5FbXNbG6GGQhT8wKHKONn/bzMGkAhmBzOe+1S/zebqAjyNZcoH +M8TVi7sPuw4GLbveIJkHa/W4rPV0AQakdrtK1vOzLQ/QSQ083/1kEdNGCE+YeLh9whoP9tGWXlRy +ZBG5PrXPBJ17N2rgdJmj9JFecaBkXWEHh59xTJbIWo5mr3C/J+o8t27ahqQWKRvx0+mPxecZcEjC ++KLYG/6tmTqD4RBN2WxVzo3V4pVvvdZuAVb4V+u3jitCFJaSnvnxHDKmuwhH4BuxvRThq8o+cROY +mNQYsC7c6vWbD4qiaOzwAMBySAw55xFJI84lLwA5hsVJtc4ZdR922YuivREcpgerbkuautjkSqN6 +LxSGyUYtSMW+E1PvLG96+Ws59gbd2B5RsxHs/D9eFjNfMq+DXjXDqlduZc07h8YinmKEKdEbQEca ++oouG07tJBhSX139g0YWX0JGk2SEwc4diKLCjMFArfIyXsIUZnU3fXGSvRQBHa5XsuKOTgUk2hy7 +/XULGDiY+LcPTW9ZiGbpF/H2tOkWdVVrqBiPIkCEHIw+ib2jrPQoQTlksuansWtPIbFnpgOOmnZK +oP15c3XFm3JXx2cHxJ8TiK8pCtq3G/pt1K9c6yznXKxNev+Z9TQoSRpk80Vur8f1zLWr0zu9A4yR +m2/lw7DUe6lwrJtDykeFQOJEv/7o4tDDiLBLiSjhRohQvFn1v9o7SlZg/HYoLa4iAh2lLR7z+RiQ +uxgOZO5qvfYWTn4IDlCYSn6mLF8DMCA18oxPg8R7mVr0EqqSte7yU+MFNF9eL5caEPk9ts9Vn7CP +f+YLBXloWHFqYIsDIFPOGGg/KjFW+mgQOXPH1zIMl+3B2ZoOgd/AzStVlWpiliDLUU8I4CPz67nX +piOwqA/IaSM/59Wg7T8KgVmUaJjnj+DzJozgVGd4qjy0o+XGZ2ZjJCTwrYe8gAXRKM1m0FWHZfeT +3jlEQY6yqKb+woS1o+LVKanclepaM4JUZLytm1netEJ5Wmsen2YwsQKhrc2LUkmYI0rmfEW7gcw4 +16Ms4rDtPAgDGmhkihR2uMy0WTqZUEraf4CfS9QdWX3VjPUuRA6ENxgLFjtj3XgcMPBI/NPfjFgw +5ZR5JHIpmKiMhesdXCZpfB+Z22FvljqUgczzrqT9QE5R5PGngcigD4dIiHmmVq6Do7Fi/xKnr3sj +YD/3WjXbXsXUfPmR3qsf2KdajYM89uqrZaZXQaGgxu+KODkbIhJ4t+Wv/oxwjFxVi4CPNFcocWu1 +l8ybUk30Q9IoZxXYTjV34Ks7+zoGwW/tN7sEtzEOESRBtBZ+NDzT8hMfLKlbqLH3XWOb/fQSe4OS +i7MYJhz2C03cNorf7acN9rCw0B4XKq69HCUWQJ3I6Vk67Ei0LniXByoNahGHWPQHHERRbNjInsd/ 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+V2sN9exa/LuXzcbeVcpOxpZc6tzWAwGPfMmjvtjv1Nf1Yj/fq48gtvabqkzsUD0bopkTPP5NDtkl +ihTdCj3S0Q== + +`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +h7ng0L736kJb9TWvsm0D0ZDFqIPvGS8wxd+fOBzJWJdWc5TSyxYiOgf+vn23e8Xg+mx5hjEdVsH+ +QXFbV6XsfUL4WtZvXysWqDjcV6qTWQEyrE8DFhVmz9hVfMUUJ7MBz0OPXVTSNzoDyGrkji8Ze3uG +N9vXCjvjJtNsOeZ+1N0= + +`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +rF1s29ceyNBGDssRabPL/UtCTca0rA/dplPVmdyPEmUhwYfsDggcbEhdlEHOrHEAug/eLNyc2vOb +MTEOC0QmlcSu8L7ZAT+KPP/TeM56QFlWS6AiCdxgezKzEI2SqLzIxp5t9tsYnLWEIrHJAxqD+fE+ +vcrpS3Ub5KbBmaHzEz41LNnl7EMOtSMy5fuFgoWVvqhYypouQArv/p3vakIidVNrF02vNSHud8xo +VjXQlbfiLs8m2t3qQGQgCsSOde72tO++445FMm7Oy0juKmEqZzO42Foux8QYfQMGOJjr0w/Z95E0 +AonluWLez3Z3a4NGGJA19XUv0sb/4ijZbDJ8CQ== + +`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +n8hn6RWmPq/J0Rqx2sGnIG0LSqUf8PkRtLB726c65BS6sGNAgzDVAtP++DrLKZLkl45qsKkQC9YF +kn8Dj1+HMZtp+WDzRX3eQctaAEtZXFu+fO4VPqOom1ElpZvHVJow8QftAm9YmTN6tBjkunFjU+Ps +S+AZrvcB4Pccu9kBRolL+2MO5bB4Ncvvp6CM+hg693sPSWXdusIx9WPWQXlEJgFrAznTyQrpL9qI +yeR1yBJlIjueFEayWBprLJvKMcceIPRgWhKZseDVUj/tPvRmZe1yqNdi/2nCHkmXmUDL0MZ0SRb5 +8wu1ZPY4CGlUDSjkC/IPXwhab6kDriR77+6ylw== + +`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +cWtffUmo3Aa2CU8y/9bRBbfbn+5QjemnWBAtSYDYzke7H+C7Wcnm4jtWqsPDty1bhS8bJNU4J5RI +zXSpO96ITImT0MJB6u37hnuw98u2paJkQPttMoQ2rCd2JOrxWPpauRilz8s5mSpXDPJkYd7+9CaT +TT0AFjPsjD9iO3VM8at915gmQFx4V4Wl5W3/f0cJlytrny2ope1/AIEUsvRdTD5piF1sTDBTYvyF +CEQHonvsTJtnvWrGhjy6CzWFtDRsxQFznWRYEz8OT+fzyMppOgHLBCPhpTqsEA77o5Hh9R7dgCHp +bJaTS9Lb3qCGKFK4lS42qGlIgFzwXOE4wKv7+Q== + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +ERh+6MeszTrqJ3nKdkTGhpC1G14E9qvR1265MEtmcBFoMy4FC8tefkRbx/tt2sBVI+8y8jvIneiT +LVxUeKXl+K3jaqaRX0zMC4Fop1uCJv/vU2G7rcqtHFNSLENbKFTkmvlkjk9PA2UKknlM0TjSOBqS +B11TyJDp/lYe5fNw6W8= + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +EFc/Zj3G+eZ8YI+uowpq4sfQKeeVeJ8b0LtOOnxGqsJQJfwab2p8jkAR59Ptx048P1NXrMNlKFy/ +wBEoURarBZ4hXNnLW3ai850YZfX6TxyVvCO3nGQw115QGzRnHHxRIcjZY1HCPwf8iz/y0Ic8xZ/o +oFJW+LXFXDtDjHS8eFlL+RqHdg9Tw2fL0L6EIAxJpRob0/jGv3RvouDJRf1D6fqLqT4xi1k+VBrj +Y9jjNBJoBZrUtbfQGB/+eYufqWwXjJ8BE0jo+4UDhtFqzpO2xaTsrKx6OnQ17YAFWSDalA2oyzTg +6q4RLJDRBub/VmmDlGF5kbiGqtUX0joCTdoIbQ== + +`protect data_method = "AES128-CBC" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 1068304) +`protect data_block +Nzo9zCHrPiSqQ/RBXmcnbVqmAPcXUT/f3SmIAoETTHRhCD9IHXyA5GdYEMaQCgjsDC84MUtuRA2H +l3sFeqLNBs2gtQIQ+FqanUBFVzBugZezS1CdBYo5u6xfP+dWRP2co1kApzAKF95PXChJIcTPYpgT +1wAROfwQt/XD584Lrzw/7sMtTwgD8ixvH1I8zP0ivHHBIOHDUgQTiR+fkcT9PDDYSMoVDnod3yrz +KbFoyMOOu9c/dT7q80AVTDStN7a8v+zasKeQkYLI8ZxMFV9Eaohs0+grS4e5SbZTH1n7DPHMbMZJ +GKIg7i20PiGOnnwGvZIIfK92r+DqtafpJ6gXi1zwLA7QZDP4ViYtvCYOz/K1fpkMCfKU/1ww9xqY +W45eOckVLMIjd1bY+b2plpN41dWK59/jKQXetE89yVptCoqpmISmcLJdtODeNduwqRDFv7C7JiyX +BSJS9iNLi/5twq11+CPlUiHIGqrSQhCan7D01UX4Canv4bZjSardymFToWA1QTQPXy2imRDkNx0S +PBuJlOAt5kIb15jOkK6Hc7AjGjZcMoWgK5XqzqLp7Flv4mX0SJZNOP00jfz0kc7Nlqk+gFg/cPGO +gPBGQKE2P/fSdk+nPvC+kpC3Azfj4bxvKv1k+cakol0tzxxX/We3/PlKonSTBqZ3fJpn1I3bZ08T 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"SNPS-VCS-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +WMu7kFTLnidedbfVrZuh/7ca7CUttjqfOqFAqALtw+gkp4fPh7ZCC2c3FriF2MGJNdt0inCBZQ1w +ERGO+2E2lzKAF62aWczdna33VjhJbQEhVD66TE3XkcNa3kH5qqUhb+EgT0e6ErzcmqjyjnkFxoKK +XKvbLV/yC8Myvjbgd1A= + +`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +xD5n0VbWIE6P1VxF0RmDDu2TYD4jh2LNu0PcTQhqBRKitH0v3xG4GrD/vuHfz6qhNoYV25YBOEWi +7kVjcZSXNFtC5ITuwneS2ZMRryiXpM8fFiU2j9L4eELr2/mHrJrVvacPISdaWzzVZMaXZGjjLF31 +zK98DBrt3GchBNvrcOgQmuPVAvjrSEZ+P+LhtLFVfq/zmFgYzV3AELJD6jr7elUkLyTjsJWEFYcf +b43n7Hb0i+cIbRt6Dd+v0kyLoVGDXUE7IXud31zG1Rotvh/eF07hFqqllLHHu2UWUNW8RAWEy1Fo +3/0kdpsYoC+scwVlEiw6L4xm3ZvOMO3xLhlx9Q== + +`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +fQrDOnMjpZojQhY1c1rw1hwuEu2Y2M8ofkmIyKutN5o3WWgs402wk38nunx4Rn3nJ4alOoXDi3N8 +wCK4FFFUnB/83xpx5yiE801fH9CrSpiGk2CFUTGUPQ2AKib6X7q/ypXzIE3Xi/Fp8v68pOYfzYgB +DWCJiGAer9WgqVkNoAOLB2B99+hjhpjUr+bqeFKCONh+smCJvnzi5NuFbGTw6NRi9XF/fOBJpA7N +7mSHNKQA9TZaG877TLVUYWhpu8Tllt4YOnNvOy5csoZO6jBxXCjuxWmM9dl9WSOXp2HX/onR6rpz +sNUbO2lQftIr2WNh0Jv073YUwDxDBpl586IEWg== + +`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +Yt/xtD+YwHpwIG7cpV+YFKRLELTuOpDyL++EbS2PSHkTTnkY+SDEglVSGBUkgEMCy4FK2fL2wt2N +qjVnO38YwcIpkFA3hdVylOufwvfkyXzLnO4I/oXAmiPI3b+yEyPArGvVOGpDgyd07VUs/V9x8yNF +fJU+AQwpZcLwvczmvjIU4/eR8fdXCMBV/C6JW2N+CHrwTU69ne3XstJaVfOIPupKIpZjLVLIrAYs +UQMdOWUz5FDENYd645Oho01vEbgtbLb+GrcpRedjCAIY2LgO42kQ9rDb7oVFFsUuoIPnWF4fLEjb +Pq5mb00fUdX1TzSueiRRmMIn69wkk/QkSb8jag== + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +S5Ng9U2ICFR2ATladKVkI9g1B4mI1wuXRMAnMNgbxvoijFO8db10A3+6fvjuey2Yzxp1Hf4dZcYN +c/lBn1GB/WXkp/IAC1a0hNWcvyknzHaPnT0XXAr2t5Xncs67wJ8pN5Gp2D1qrZQQzDnNoYG2S/bd +YiWvkcmY78GRhm+UXVk= + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +HAhvjf08asX78hSz5fysjZpqt6weT/hM0aPw+9OZ6ZFgT2U7lNg0+xRLXb9nzh4EewIjMgSyWdbq +Irle9J+zY0NjMxQhF0AU4uZR3mjfrD6Ci+uFgn2FssxWd9BHXv/cqiRhCZU2ybiUWpzjYSU0dR0h +2hg5PlS+G3dlVbHVWfTO0k/13GXvSnwpugvkHI9jnHi2x1XT0gcm6G9Zhe1EI5PttaiCD/hIEpFy +dE9D4GBdwkisk7PYdWIuZlsBFWDWcbGou0FPnNgoQxkmsqJf2be0EcDmDksiH0SWYeS3S/ePy+eL +24oKZ31y2jK7rq17ZMr87dpRzRIdMsvbgjgGWg== + +`protect data_method = "AES128-CBC" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 3185184) +`protect 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b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd @@ -0,0 +1,2392 @@ +`protect begin_protected +`protect version = 1 +`protect encrypt_agent = "XILINX" +`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1" +`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) +`protect key_block +AxZSYlrqWjjbM/ghGgP335GwqxDgV3HmMQL/p5ebckAQyJ+kqJFTPj58BKjOX4mpdCMv1bT58Fu1 +qGdZGqaeUw== + +`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +EIaioRFBcSeMA6Aux6hZm/WyyYgPDWVHaRtKbzIwL1QTiiAUZlNppzkL3bbmZ6KUvAn+f3bbBLZv +nI1at70553BjJ/f7JWSLFqvUyJvDaz1fb/ElTqdB3VheCofSfItuLq6wNAf1eaXg4UAiQMs6nSeP +bYv5xrpdIQrLt1D9QHA= + +`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +mb9yHUsW7uBsE4c/OKrF7NiKsfxXH5+bboQS2NnscX6YeRYxm+eBZvwT3PSD9ibYiQFnSx/solW3 +OQO086UdWxyqMUFLcczGEx5Tqo5CpVbQ3CRAT7KgWnfq3Sw5pAuNsxwfXjN6luLSyUceI44YWnvZ +jNzoi8aSibopmfyW1ySUElOtnOzAOOsZpW6FBPVqwSIV18HJmOORpq6HJ1huXP6kFt/P0LgI4KNJ +0SeFy/2RlRADetCrV8umpxarjaDfW3dkNCeZIu0mWy7n8bNc/glh/qa2/i5v89Lt3neYjpa7cMXy +ICB4vX0zyiAb1G7xomAPECN8BfyzZeKkXU3L9A== + +`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +gBaQZNFSH7Q+cY8yvr3uGZIme+w3oCQPu8RtICVgaZhAcjEo9yTTeID+H4cca0yFpRdgM0pcus5J +5FJKmqOUXCBailX6awFdkRbi8P+qzd5LZWhXxCEFoQCAWDXZdantxf1Npl2sva9dLV8+XevpyvWw +na2fAJSEp/lWg0rNz+EcKnd11hmCw3Uq5A17kwqrW2kIl8yBpmqhRpwTKUaeyi1PlK2yMzLkDSj3 +g3L9JraXIHucFD5JDVMs31PKB0bLhp9xva2XeqGFDomux1ArgEU2GMtksKuFBZYWi7EM3MnZ/210 +ICkCIfO7B1+tuTs/vDrpmr16T/pcZfWjHD8i4g== + +`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2019_02", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +X/0WESaoHNKE+VQh6wiFQZUGC/wvvLyzJWa7+XHLf9u2HGK/wbJysf+svmnB6pdyOjRcvCdqkITz +XwegHvpEnCL5eBSM7wrkLdsUEF3XcNtNuFXLtFkrk/zKPfCV+Cj5+TdjprdgEEGSQyiJEbOirUGo +QfOyWo4Cn++z8sGq6DZemWplV82dIQad0OMeak7WWmG7Pwef65b49WpZp4VtkmzU6zP3Hq2RKuc2 +JfAEvP+4m1AKa1AIvFYtKkIno5azYqCR8icyJj/aAeFkwKgmw475EaivMmiwXI0CEGgGhUaSatGn +t78rUSYMEB8FycWJ+tnZkr2fLD603a+4Ea82kA== + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) +`protect key_block +Y2sBFuuYPz+gbw4FP5O5GG+zlVJ0DyXBElOfyt3NhcumgiOFXrUdbEKBNszNLNHqdAfX83DQlvFe +dmRFhUTrp1zAwODtXOHbgp7OcQKFuaGIo+poJ6g+migbsS0N35Sw+qK4xtbAtXQz3HjATWd+gz+S +zCFMgvYoG1+WYEUj2X0= + +`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) +`protect key_block +sOc8FhbMR64uyLpKFyrXkbouaX3PkKiNHTHeAKNeDiWbDAV3jythTS34N4HWRYzf/duBai4EaRTQ +3byQC47/ahfN7MGuftFmc033WhoNzsfTJkqu5w+sXclPKETCwWwBGCfd6WDcYwA1EaV24NgJqZLO +VytDboZOGxpfIwB2yEEPyqHZQZtat4wiSyi5mDJ0GF7oPhDS3s+HLx50a1i46WdrdohQl2WaD1sL +bzITraqPIVbRdj8G/0aABIIWM19aF6l4O+1DKGIRw/F86DxkXKS+zA6V3SGO7M3LwyGSWxhDz0AL +KBu6Yul8QRtuswKo8lHHQeNt5xF8Z6yRrWyGDg== + +`protect data_method = "AES128-CBC" +`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 132688) +`protect data_block +5Q6eby1O70wRs7hZksMgwYcm4BYNMASyQwUcj9ZBTRJeWYtXGNx8hEXhIoKCUWN8uVTOyFsOI9Qo +JWICHdVIHACuxge7bNqX02EfSli9NZj+/lkKAPusLL0xrJ9v1MLOQABzACIrsSTzNvxPELtguR9s +IHO9woqF8SDng+FEhAQH21fpEvPeuYoDoHRh9JLw9y2LDqk62Gce0cACeAFu4ztjKPRkcQNL8PKD +28EyfqtWUtKcoFFAQoz8/x4FNdWwtlQwmnDb3zhvLTT0VHYFRnCGPervV+N5mJ8dgQs5ohX9TRf+ +WsjcVJywOaSZXTadWIY37Ri4DtKuREffFf7fFHgHUydazWng98jX0lUzmZA68rJW5zzvnsQcF2xC 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+/****************************************************************************** +-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + ***************************************************************************** + * + * Filename: blk_mem_gen_v8_4_3.v + * + * Description: + * This file is the Verilog behvarial model for the + * Block Memory Generator Core. + * + ***************************************************************************** + * Author: Xilinx + * + * History: Jan 11, 2006 Initial revision + * Jun 11, 2007 Added independent register stages for + * Port A and Port B (IP1_Jm/v2.5) + * Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6) + * Mar 13, 2008 Behavioral model optimizations + * April 07, 2009 : Added support for Spartan-6 and Virtex-6 + * features, including the following: + * (i) error injection, detection and/or correction + * (ii) reset priority + * (iii) special reset behavior + * + *****************************************************************************/ +`timescale 1ps/1ps + +module STATE_LOGIC_v8_4 (O, I0, I1, I2, I3, I4, I5); + + parameter INIT = 64'h0000000000000000; + + input I0, I1, I2, I3, I4, I5; + + output O; + + reg O; + reg tmp; + + always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin + + tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5; + + if ( tmp == 0 || tmp == 1) + + O = INIT[{I5, I4, I3, I2, I1, I0}]; + + end +endmodule + +module beh_vlog_muxf7_v8_4 (O, I0, I1, S); + + output O; + reg O; + + input I0, I1, S; + + always @(I0 or I1 or S) + if (S) + O = I1; + else + O = I0; +endmodule + +module beh_vlog_ff_clr_v8_4 (Q, C, CLR, D); + parameter INIT = 0; +localparam FLOP_DELAY = 100; + output Q; + + input C, CLR, D; + + reg Q; + + initial Q= 1'b0; + + always @(posedge C ) + if (CLR) + Q<= 1'b0; + else + Q<= #FLOP_DELAY D; + + +endmodule + +module beh_vlog_ff_pre_v8_4 (Q, C, D, PRE); + + parameter INIT = 0; +localparam FLOP_DELAY = 100; + output Q; + input C, D, PRE; + + reg Q; + + initial Q= 1'b0; + + always @(posedge C ) + if (PRE) + Q <= 1'b1; + else + Q <= #FLOP_DELAY D; + +endmodule + +module beh_vlog_ff_ce_clr_v8_4 (Q, C, CE, CLR, D); + + parameter INIT = 0; +localparam FLOP_DELAY = 100; + output Q; + input C, CE, CLR, D; + + reg Q; + + initial Q= 1'b0; + always @(posedge C ) + if (CLR) + Q <= 1'b0; + else if (CE) + Q <= #FLOP_DELAY D; + +endmodule + +module write_netlist_v8_4 +#( + parameter C_AXI_TYPE = 0 + ) + ( + S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY, + w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID, + S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c + ); + + input S_ACLK; + input S_ARESETN; + input S_AXI_AWVALID; + input S_AXI_WVALID; + input S_AXI_BREADY; + input w_last_c; + input bready_timeout_c; + output aw_ready_r; + output S_AXI_WREADY; + output S_AXI_BVALID; + output S_AXI_WR_EN; + output addr_en_c; + output incr_addr_c; + output bvalid_c; + //------------------------------------------------------------------------- + //AXI LITE + //------------------------------------------------------------------------- +generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm + wire w_ready_r_7; + wire w_ready_c; + wire aw_ready_c; + wire NlwRenamedSignal_bvalid_c; + wire NlwRenamedSignal_incr_addr_c; + wire present_state_FSM_FFd3_13; + wire present_state_FSM_FFd2_14; + wire present_state_FSM_FFd1_15; + wire present_state_FSM_FFd4_16; + wire present_state_FSM_FFd4_In; + wire present_state_FSM_FFd3_In; + wire present_state_FSM_FFd2_In; + wire present_state_FSM_FFd1_In; + wire present_state_FSM_FFd4_In1_21; + wire [0:0] Mmux_aw_ready_c ; +begin + assign + S_AXI_WREADY = w_ready_r_7, + S_AXI_BVALID = NlwRenamedSignal_incr_addr_c, + S_AXI_WR_EN = NlwRenamedSignal_bvalid_c, + incr_addr_c = NlwRenamedSignal_incr_addr_c, + bvalid_c = NlwRenamedSignal_bvalid_c; + + assign NlwRenamedSignal_incr_addr_c = 1'b0; + + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + aw_ready_r_2 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( aw_ready_c), + .Q ( aw_ready_r) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + w_ready_r ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( w_ready_c), + .Q ( w_ready_r_7) + ); + beh_vlog_ff_pre_v8_4 #( + .INIT (1'b1)) + present_state_FSM_FFd4 ( + .C ( S_ACLK), + .D ( present_state_FSM_FFd4_In), + .PRE ( S_ARESETN), + .Q ( present_state_FSM_FFd4_16) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd3 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd3_In), + .Q ( present_state_FSM_FFd3_13) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd2 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd2_In), + .Q ( present_state_FSM_FFd2_14) + ); +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd1 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd1_In), + .Q ( present_state_FSM_FFd1_15) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h0000000055554440)) + present_state_FSM_FFd3_In1 ( + .I0 ( S_AXI_WVALID), + .I1 ( S_AXI_AWVALID), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( present_state_FSM_FFd4_16), + .I4 ( present_state_FSM_FFd3_13), + .I5 (1'b0), + .O ( present_state_FSM_FFd3_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h0000000088880800)) + present_state_FSM_FFd2_In1 ( + .I0 ( S_AXI_AWVALID), + .I1 ( S_AXI_WVALID), + .I2 ( bready_timeout_c), + .I3 ( present_state_FSM_FFd2_14), + .I4 ( present_state_FSM_FFd4_16), + .I5 (1'b0), + .O ( present_state_FSM_FFd2_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h00000000AAAA2000)) + Mmux_addr_en_c_0_1 ( + .I0 ( S_AXI_AWVALID), + .I1 ( bready_timeout_c), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( S_AXI_WVALID), + .I4 ( present_state_FSM_FFd4_16), + .I5 (1'b0), + .O ( addr_en_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hF5F07570F5F05500)) + Mmux_w_ready_c_0_1 ( + .I0 ( S_AXI_WVALID), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd3_13), + .I4 ( present_state_FSM_FFd4_16), + .I5 ( present_state_FSM_FFd2_14), + .O ( w_ready_c) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h88808880FFFF8880)) + present_state_FSM_FFd1_In1 ( + .I0 ( S_AXI_WVALID), + .I1 ( bready_timeout_c), + .I2 ( present_state_FSM_FFd3_13), + .I3 ( present_state_FSM_FFd2_14), + .I4 ( present_state_FSM_FFd1_15), + .I5 ( S_AXI_BREADY), + .O ( present_state_FSM_FFd1_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000A8)) + Mmux_S_AXI_WR_EN_0_1 ( + .I0 ( S_AXI_WVALID), + .I1 ( present_state_FSM_FFd2_14), + .I2 ( present_state_FSM_FFd3_13), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( NlwRenamedSignal_bvalid_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h2F0F27072F0F2200)) + present_state_FSM_FFd4_In1 ( + .I0 ( S_AXI_WVALID), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd3_13), + .I4 ( present_state_FSM_FFd4_16), + .I5 ( present_state_FSM_FFd2_14), + .O ( present_state_FSM_FFd4_In1_21) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000F8)) + present_state_FSM_FFd4_In2 ( + .I0 ( present_state_FSM_FFd1_15), + .I1 ( S_AXI_BREADY), + .I2 ( present_state_FSM_FFd4_In1_21), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( present_state_FSM_FFd4_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h7535753575305500)) + Mmux_aw_ready_c_0_1 ( + .I0 ( S_AXI_AWVALID), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_WVALID), + .I3 ( present_state_FSM_FFd4_16), + .I4 ( present_state_FSM_FFd3_13), + .I5 ( present_state_FSM_FFd2_14), + .O ( Mmux_aw_ready_c[0]) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000F8)) + Mmux_aw_ready_c_0_2 ( + .I0 ( present_state_FSM_FFd1_15), + .I1 ( S_AXI_BREADY), + .I2 ( Mmux_aw_ready_c[0]), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( aw_ready_c) + ); +end +end +endgenerate + + //--------------------------------------------------------------------- + // AXI FULL + //--------------------------------------------------------------------- +generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm + wire w_ready_r_8; + wire w_ready_c; + wire aw_ready_c; + wire NlwRenamedSig_OI_bvalid_c; + wire present_state_FSM_FFd1_16; + wire present_state_FSM_FFd4_17; + wire present_state_FSM_FFd3_18; + wire present_state_FSM_FFd2_19; + wire present_state_FSM_FFd4_In; + wire present_state_FSM_FFd3_In; + wire present_state_FSM_FFd2_In; + wire present_state_FSM_FFd1_In; + wire present_state_FSM_FFd2_In1_24; + wire present_state_FSM_FFd4_In1_25; + wire N2; + wire N4; +begin +assign + S_AXI_WREADY = w_ready_r_8, + bvalid_c = NlwRenamedSig_OI_bvalid_c, + S_AXI_BVALID = 1'b0; + +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + aw_ready_r_2 + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( aw_ready_c), + .Q ( aw_ready_r) + ); +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + w_ready_r + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( w_ready_c), + .Q ( w_ready_r_8) + ); + beh_vlog_ff_pre_v8_4 #( + .INIT (1'b1)) + present_state_FSM_FFd4 + ( + .C ( S_ACLK), + .D ( present_state_FSM_FFd4_In), + .PRE ( S_ARESETN), + .Q ( present_state_FSM_FFd4_17) + ); +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd3 + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd3_In), + .Q ( present_state_FSM_FFd3_18) + ); +beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd2 + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd2_In), + .Q ( present_state_FSM_FFd2_19) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd1 + ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd1_In), + .Q ( present_state_FSM_FFd1_16) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000005540)) + present_state_FSM_FFd3_In1 + ( + .I0 ( S_AXI_WVALID), + .I1 ( present_state_FSM_FFd4_17), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd3_18), + .I4 (1'b0), + .I5 (1'b0), + .O ( present_state_FSM_FFd3_In) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'hBF3FBB33AF0FAA00)) + Mmux_aw_ready_c_0_2 + ( + .I0 ( S_AXI_BREADY), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd1_16), + .I4 ( present_state_FSM_FFd4_17), + .I5 ( NlwRenamedSig_OI_bvalid_c), + .O ( aw_ready_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hAAAAAAAA20000000)) + Mmux_addr_en_c_0_1 + ( + .I0 ( S_AXI_AWVALID), + .I1 ( bready_timeout_c), + .I2 ( present_state_FSM_FFd2_19), + .I3 ( S_AXI_WVALID), + .I4 ( w_last_c), + .I5 ( present_state_FSM_FFd4_17), + .O ( addr_en_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000A8)) + Mmux_S_AXI_WR_EN_0_1 + ( + .I0 ( S_AXI_WVALID), + .I1 ( present_state_FSM_FFd2_19), + .I2 ( present_state_FSM_FFd3_18), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( S_AXI_WR_EN) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000002220)) + Mmux_incr_addr_c_0_1 + ( + .I0 ( S_AXI_WVALID), + .I1 ( w_last_c), + .I2 ( present_state_FSM_FFd2_19), + .I3 ( present_state_FSM_FFd3_18), + .I4 (1'b0), + .I5 (1'b0), + .O ( incr_addr_c) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000008880)) + Mmux_aw_ready_c_0_11 + ( + .I0 ( S_AXI_WVALID), + .I1 ( w_last_c), + .I2 ( present_state_FSM_FFd2_19), + .I3 ( present_state_FSM_FFd3_18), + .I4 (1'b0), + .I5 (1'b0), + .O ( NlwRenamedSig_OI_bvalid_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h000000000000D5C0)) + present_state_FSM_FFd2_In1 + ( + .I0 ( w_last_c), + .I1 ( S_AXI_AWVALID), + .I2 ( present_state_FSM_FFd4_17), + .I3 ( present_state_FSM_FFd3_18), + .I4 (1'b0), + .I5 (1'b0), + .O ( present_state_FSM_FFd2_In1_24) + ); +STATE_LOGIC_v8_4 #( + .INIT (64'hFFFFAAAA08AAAAAA)) + present_state_FSM_FFd2_In2 + ( + .I0 ( present_state_FSM_FFd2_19), + .I1 ( S_AXI_AWVALID), + .I2 ( bready_timeout_c), + .I3 ( w_last_c), + .I4 ( S_AXI_WVALID), + .I5 ( present_state_FSM_FFd2_In1_24), + .O ( present_state_FSM_FFd2_In) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00C0004000C00000)) + present_state_FSM_FFd4_In1 + ( + .I0 ( S_AXI_AWVALID), + .I1 ( w_last_c), + .I2 ( S_AXI_WVALID), + .I3 ( bready_timeout_c), + .I4 ( present_state_FSM_FFd3_18), + .I5 ( present_state_FSM_FFd2_19), + .O ( present_state_FSM_FFd4_In1_25) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000FFFF88F8)) + present_state_FSM_FFd4_In2 + ( + .I0 ( present_state_FSM_FFd1_16), + .I1 ( S_AXI_BREADY), + .I2 ( present_state_FSM_FFd4_17), + .I3 ( S_AXI_AWVALID), + .I4 ( present_state_FSM_FFd4_In1_25), + .I5 (1'b0), + .O ( present_state_FSM_FFd4_In) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000007)) + Mmux_w_ready_c_0_SW0 + ( + .I0 ( w_last_c), + .I1 ( S_AXI_WVALID), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( N2) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hFABAFABAFAAAF000)) + Mmux_w_ready_c_0_Q + ( + .I0 ( N2), + .I1 ( bready_timeout_c), + .I2 ( S_AXI_AWVALID), + .I3 ( present_state_FSM_FFd4_17), + .I4 ( present_state_FSM_FFd3_18), + .I5 ( present_state_FSM_FFd2_19), + .O ( w_ready_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000008)) + Mmux_aw_ready_c_0_11_SW0 + ( + .I0 ( bready_timeout_c), + .I1 ( S_AXI_WVALID), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O ( N4) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h88808880FFFF8880)) + present_state_FSM_FFd1_In1 + ( + .I0 ( w_last_c), + .I1 ( N4), + .I2 ( present_state_FSM_FFd2_19), + .I3 ( present_state_FSM_FFd3_18), + .I4 ( present_state_FSM_FFd1_16), + .I5 ( S_AXI_BREADY), + .O ( present_state_FSM_FFd1_In) + ); +end +end +endgenerate +endmodule + + +module read_netlist_v8_4 #( + parameter C_AXI_TYPE = 1, + parameter C_ADDRB_WIDTH = 12 + ) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID, + S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN, + S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY, + S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN); + + input S_AXI_R_LAST_INT; + input S_ACLK; + input S_ARESETN; + input S_AXI_ARVALID; + input S_AXI_RREADY; + output S_AXI_INCR_ADDR; + output S_AXI_ADDR_EN; + output S_AXI_SINGLE_TRANS; + output S_AXI_MUX_SEL; + output S_AXI_R_LAST; + output S_AXI_ARREADY; + output S_AXI_RLAST; + output S_AXI_RVALID; + output S_AXI_RD_EN; + input [7:0] S_AXI_ARLEN; + + wire present_state_FSM_FFd1_13 ; + wire present_state_FSM_FFd2_14 ; + wire gaxi_full_sm_outstanding_read_r_15 ; + wire gaxi_full_sm_ar_ready_r_16 ; + wire gaxi_full_sm_r_last_r_17 ; + wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ; + wire gaxi_full_sm_r_valid_c ; + wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ; + wire gaxi_full_sm_ar_ready_c ; + wire gaxi_full_sm_outstanding_read_c ; + wire NlwRenamedSig_OI_S_AXI_R_LAST ; + wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ; + wire present_state_FSM_FFd2_In ; + wire present_state_FSM_FFd1_In ; + wire Mmux_S_AXI_R_LAST13 ; + wire N01 ; + wire N2 ; + wire Mmux_gaxi_full_sm_ar_ready_c11 ; + wire N4 ; + wire N8 ; + wire N9 ; + wire N10 ; + wire N11 ; + wire N12 ; + wire N13 ; + assign + S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST, + S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16, + S_AXI_RLAST = gaxi_full_sm_r_last_r_17, + S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r; + + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + gaxi_full_sm_outstanding_read_r ( + .C (S_ACLK), + .CLR(S_ARESETN), + .D(gaxi_full_sm_outstanding_read_c), + .Q(gaxi_full_sm_outstanding_read_r_15) + ); + beh_vlog_ff_ce_clr_v8_4 #( + .INIT (1'b0)) + gaxi_full_sm_r_valid_r ( + .C (S_ACLK), + .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), + .CLR (S_ARESETN), + .D (gaxi_full_sm_r_valid_c), + .Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + gaxi_full_sm_ar_ready_r ( + .C (S_ACLK), + .CLR (S_ARESETN), + .D (gaxi_full_sm_ar_ready_c), + .Q (gaxi_full_sm_ar_ready_r_16) + ); + beh_vlog_ff_ce_clr_v8_4 #( + .INIT(1'b0)) + gaxi_full_sm_r_last_r ( + .C (S_ACLK), + .CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), + .CLR (S_ARESETN), + .D (NlwRenamedSig_OI_S_AXI_R_LAST), + .Q (gaxi_full_sm_r_last_r_17) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd2 ( + .C ( S_ACLK), + .CLR ( S_ARESETN), + .D ( present_state_FSM_FFd2_In), + .Q ( present_state_FSM_FFd2_14) + ); + beh_vlog_ff_clr_v8_4 #( + .INIT (1'b0)) + present_state_FSM_FFd1 ( + .C (S_ACLK), + .CLR (S_ARESETN), + .D (present_state_FSM_FFd1_In), + .Q (present_state_FSM_FFd1_13) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h000000000000000B)) + S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 ( + .I0 ( S_AXI_RREADY), + .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000008)) + Mmux_S_AXI_SINGLE_TRANS11 ( + .I0 (S_AXI_ARVALID), + .I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O (S_AXI_SINGLE_TRANS) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000004)) + Mmux_S_AXI_ADDR_EN11 ( + .I0 (present_state_FSM_FFd1_13), + .I1 (S_AXI_ARVALID), + .I2 (1'b0), + .I3 (1'b0), + .I4 (1'b0), + .I5 (1'b0), + .O (S_AXI_ADDR_EN) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hECEE2022EEEE2022)) + present_state_FSM_FFd2_In1 ( + .I0 ( S_AXI_ARVALID), + .I1 ( present_state_FSM_FFd1_13), + .I2 ( S_AXI_RREADY), + .I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I4 ( present_state_FSM_FFd2_14), + .I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .O ( present_state_FSM_FFd2_In) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000044440444)) + Mmux_S_AXI_R_LAST131 ( + .I0 ( present_state_FSM_FFd1_13), + .I1 ( S_AXI_ARVALID), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I4 ( S_AXI_RREADY), + .I5 (1'b0), + .O ( Mmux_S_AXI_R_LAST13) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h4000FFFF40004000)) + Mmux_S_AXI_INCR_ADDR11 ( + .I0 ( S_AXI_R_LAST_INT), + .I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( present_state_FSM_FFd1_13), + .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I5 ( Mmux_S_AXI_R_LAST13), + .O ( S_AXI_INCR_ADDR) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000FE)) + S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 ( + .I0 ( S_AXI_ARLEN[2]), + .I1 ( S_AXI_ARLEN[1]), + .I2 ( S_AXI_ARLEN[0]), + .I3 ( 1'b0), + .I4 ( 1'b0), + .I5 ( 1'b0), + .O ( N01) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000001)) + S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q ( + .I0 ( S_AXI_ARLEN[7]), + .I1 ( S_AXI_ARLEN[6]), + .I2 ( S_AXI_ARLEN[5]), + .I3 ( S_AXI_ARLEN[4]), + .I4 ( S_AXI_ARLEN[3]), + .I5 ( N01), + .O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000000007)) + Mmux_gaxi_full_sm_outstanding_read_c1_SW0 ( + .I0 ( S_AXI_ARVALID), + .I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I2 ( 1'b0), + .I3 ( 1'b0), + .I4 ( 1'b0), + .I5 ( 1'b0), + .O ( N2) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0020000002200200)) + Mmux_gaxi_full_sm_outstanding_read_c1 ( + .I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I1 ( S_AXI_RREADY), + .I2 ( present_state_FSM_FFd1_13), + .I3 ( present_state_FSM_FFd2_14), + .I4 ( gaxi_full_sm_outstanding_read_r_15), + .I5 ( N2), + .O ( gaxi_full_sm_outstanding_read_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000000004555)) + Mmux_gaxi_full_sm_ar_ready_c12 ( + .I0 ( S_AXI_ARVALID), + .I1 ( S_AXI_RREADY), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I4 ( 1'b0), + .I5 ( 1'b0), + .O ( Mmux_gaxi_full_sm_ar_ready_c11) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000000000EF)) + Mmux_S_AXI_R_LAST11_SW0 ( + .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I1 ( S_AXI_RREADY), + .I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I3 ( 1'b0), + .I4 ( 1'b0), + .I5 ( 1'b0), + .O ( N4) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hFCAAFC0A00AA000A)) + Mmux_S_AXI_R_LAST11 ( + .I0 ( S_AXI_ARVALID), + .I1 ( gaxi_full_sm_outstanding_read_r_15), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( present_state_FSM_FFd1_13), + .I4 ( N4), + .I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o), + .O ( gaxi_full_sm_r_valid_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000AAAAAA08)) + S_AXI_MUX_SEL1 ( + .I0 (present_state_FSM_FFd1_13), + .I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I2 (S_AXI_RREADY), + .I3 (present_state_FSM_FFd2_14), + .I4 (gaxi_full_sm_outstanding_read_r_15), + .I5 (1'b0), + .O (S_AXI_MUX_SEL) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'hF3F3F755A2A2A200)) + Mmux_S_AXI_RD_EN11 ( + .I0 ( present_state_FSM_FFd1_13), + .I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I2 ( S_AXI_RREADY), + .I3 ( gaxi_full_sm_outstanding_read_r_15), + .I4 ( present_state_FSM_FFd2_14), + .I5 ( S_AXI_ARVALID), + .O ( S_AXI_RD_EN) + ); + beh_vlog_muxf7_v8_4 present_state_FSM_FFd1_In3 ( + .I0 ( N8), + .I1 ( N9), + .S ( present_state_FSM_FFd1_13), + .O ( present_state_FSM_FFd1_In) + ); + + STATE_LOGIC_v8_4 #( + .INIT (64'h000000005410F4F0)) + present_state_FSM_FFd1_In3_F ( + .I0 ( S_AXI_RREADY), + .I1 ( present_state_FSM_FFd2_14), + .I2 ( S_AXI_ARVALID), + .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I5 ( 1'b0), + .O ( N8) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000072FF7272)) + present_state_FSM_FFd1_In3_G ( + .I0 ( present_state_FSM_FFd2_14), + .I1 ( S_AXI_R_LAST_INT), + .I2 ( gaxi_full_sm_outstanding_read_r_15), + .I3 ( S_AXI_RREADY), + .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I5 ( 1'b0), + .O ( N9) + ); + beh_vlog_muxf7_v8_4 Mmux_gaxi_full_sm_ar_ready_c14 ( + .I0 ( N10), + .I1 ( N11), + .S ( present_state_FSM_FFd1_13), + .O ( gaxi_full_sm_ar_ready_c) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000FFFF88A8)) + Mmux_gaxi_full_sm_ar_ready_c14_F ( + .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I1 ( S_AXI_RREADY), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I4 ( Mmux_gaxi_full_sm_ar_ready_c11), + .I5 ( 1'b0), + .O ( N10) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h000000008D008D8D)) + Mmux_gaxi_full_sm_ar_ready_c14_G ( + .I0 ( present_state_FSM_FFd2_14), + .I1 ( S_AXI_R_LAST_INT), + .I2 ( gaxi_full_sm_outstanding_read_r_15), + .I3 ( S_AXI_RREADY), + .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I5 ( 1'b0), + .O ( N11) + ); + beh_vlog_muxf7_v8_4 Mmux_S_AXI_R_LAST1 ( + .I0 ( N12), + .I1 ( N13), + .S ( present_state_FSM_FFd1_13), + .O ( NlwRenamedSig_OI_S_AXI_R_LAST) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h0000000088088888)) + Mmux_S_AXI_R_LAST1_F ( + .I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o), + .I1 ( S_AXI_ARVALID), + .I2 ( present_state_FSM_FFd2_14), + .I3 ( S_AXI_RREADY), + .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I5 ( 1'b0), + .O ( N12) + ); + STATE_LOGIC_v8_4 #( + .INIT (64'h00000000E400E4E4)) + Mmux_S_AXI_R_LAST1_G ( + .I0 ( present_state_FSM_FFd2_14), + .I1 ( gaxi_full_sm_outstanding_read_r_15), + .I2 ( S_AXI_R_LAST_INT), + .I3 ( S_AXI_RREADY), + .I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r), + .I5 ( 1'b0), + .O ( N13) + ); + +endmodule + + +module blk_mem_axi_write_wrapper_beh_v8_4 + # ( + // AXI Interface related parameters start here + parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface + parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full; + parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE; + parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM; + parameter C_WRITE_DEPTH_A = 0, + parameter C_AXI_AWADDR_WIDTH = 32, + parameter C_ADDRA_WIDTH = 12, + parameter C_AXI_WDATA_WIDTH = 32, + parameter C_HAS_AXI_ID = 0, + parameter C_AXI_ID_WIDTH = 4, + // AXI OUTSTANDING WRITES + parameter C_AXI_OS_WR = 2 + ) + ( + // AXI Global Signals + input S_ACLK, + input S_ARESETN, + // AXI Full/Lite Slave Write Channel (write side) + input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID, + input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR, + input [8-1:0] S_AXI_AWLEN, + input [2:0] S_AXI_AWSIZE, + input [1:0] S_AXI_AWBURST, + input S_AXI_AWVALID, + output S_AXI_AWREADY, + input S_AXI_WVALID, + output S_AXI_WREADY, + output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0, + output S_AXI_BVALID, + input S_AXI_BREADY, + // Signals for BMG interface + output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT, + output S_AXI_WR_EN + ); + + localparam FLOP_DELAY = 100; // 100 ps + + localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0: + ((C_AXI_WDATA_WIDTH==16)?1: + ((C_AXI_WDATA_WIDTH==32)?2: + ((C_AXI_WDATA_WIDTH==64)?3: + ((C_AXI_WDATA_WIDTH==128)?4: + ((C_AXI_WDATA_WIDTH==256)?5:0)))))); + + + + + wire bvalid_c ; + reg bready_timeout_c = 0; + wire [1:0] bvalid_rd_cnt_c; + reg bvalid_r = 0; + reg [2:0] bvalid_count_r = 0; + reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? + C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0; + reg [1:0] bvalid_wr_cnt_r = 0; + reg [1:0] bvalid_rd_cnt_r = 0; + wire w_last_c ; + wire addr_en_c ; + wire incr_addr_c ; + wire aw_ready_r ; + wire dec_alen_c ; + reg bvalid_d1_c = 0; + reg [7:0] awlen_cntr_r = 0; + reg [7:0] awlen_int = 0; + reg [1:0] awburst_int = 0; + + integer total_bytes = 0; + integer wrap_boundary = 0; + integer wrap_base_addr = 0; + integer num_of_bytes_c = 0; + integer num_of_bytes_r = 0; + // Array to store BIDs + reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ; + wire S_AXI_BVALID_axi_wr_fsm; + + //------------------------------------- + //AXI WRITE FSM COMPONENT INSTANTIATION + //------------------------------------- + write_netlist_v8_4 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm + ( + .S_ACLK(S_ACLK), + .S_ARESETN(S_ARESETN), + .S_AXI_AWVALID(S_AXI_AWVALID), + .aw_ready_r(aw_ready_r), + .S_AXI_WVALID(S_AXI_WVALID), + .S_AXI_WREADY(S_AXI_WREADY), + .S_AXI_BREADY(S_AXI_BREADY), + .S_AXI_WR_EN(S_AXI_WR_EN), + .w_last_c(w_last_c), + .bready_timeout_c(bready_timeout_c), + .addr_en_c(addr_en_c), + .incr_addr_c(incr_addr_c), + .bvalid_c(bvalid_c), + .S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm) + ); + + + //Wrap Address boundary calculation + always@(*) begin + num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0); + total_bytes = (num_of_bytes_r)*(awlen_int+1); + wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes); + wrap_boundary = wrap_base_addr+total_bytes; + end + + //------------------------------------------------------------------------- + // BMG address generation + //------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + awaddr_reg <= 0; + num_of_bytes_r <= 0; + awburst_int <= 0; + end else begin + if (addr_en_c == 1'b1) begin + awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ; + num_of_bytes_r <= num_of_bytes_c; + awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01); + end else if (incr_addr_c == 1'b1) begin + if (awburst_int == 2'b10) begin + if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin + awaddr_reg <= wrap_base_addr; + end else begin + awaddr_reg <= awaddr_reg + num_of_bytes_r; + end + end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin + awaddr_reg <= awaddr_reg + num_of_bytes_r; + end + end + end + end + + + assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? + awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg); + + //------------------------------------------------------------------------- + // AXI wlast generation + //------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + awlen_cntr_r <= 0; + awlen_int <= 0; + end else begin + if (addr_en_c == 1'b1) begin + awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; + awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ; + end else if (dec_alen_c == 1'b1) begin + awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ; + end + end + end + + assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0; + + assign dec_alen_c = (incr_addr_c | w_last_c); + + //------------------------------------------------------------------------- + // Generation of bvalid counter for outstanding transactions + //------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + bvalid_count_r <= 0; + end else begin + // bvalid_count_r generation + if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin + bvalid_count_r <= #FLOP_DELAY bvalid_count_r ; + end else if (bvalid_c == 1'b1) begin + bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ; + end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin + bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ; + end + end + end + + //------------------------------------------------------------------------- + // Generation of bvalid when BID is used + //------------------------------------------------------------------------- + generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + bvalid_r <= 0; + bvalid_d1_c <= 0; + end else begin + // Delay the generation o bvalid_r for generation for BID + bvalid_d1_c <= bvalid_c; + + //external bvalid signal generation + if (bvalid_d1_c == 1'b1) begin + bvalid_r <= #FLOP_DELAY 1'b1 ; + end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin + bvalid_r <= #FLOP_DELAY 0 ; + end + end + end + end + endgenerate + + //------------------------------------------------------------------------- + // Generation of bvalid when BID is not used + //------------------------------------------------------------------------- + generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + bvalid_r <= 0; + end else begin + //external bvalid signal generation + if (bvalid_c == 1'b1) begin + bvalid_r <= #FLOP_DELAY 1'b1 ; + end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin + bvalid_r <= #FLOP_DELAY 0 ; + end + end + end + end + endgenerate + + //------------------------------------------------------------------------- + // Generation of Bready timeout + //------------------------------------------------------------------------- + always @(bvalid_count_r) begin + // bready_timeout_c generation + if(bvalid_count_r == C_AXI_OS_WR-1) begin + bready_timeout_c <= 1'b1; + end else begin + bready_timeout_c <= 1'b0; + end + end + + //------------------------------------------------------------------------- + // Generation of BID + //------------------------------------------------------------------------- + generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen + + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + bvalid_wr_cnt_r <= 0; + bvalid_rd_cnt_r <= 0; + end else begin + // STORE AWID IN AN ARRAY + if(bvalid_c == 1'b1) begin + bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1; + end + // generate BID FROM AWID ARRAY + bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ; + S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c]; + end + end + + assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r; + + //------------------------------------------------------------------------- + // Storing AWID for generation of BID + //------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if(S_ARESETN == 1'b1) begin + axi_bid_array[0] = 0; + axi_bid_array[1] = 0; + axi_bid_array[2] = 0; + axi_bid_array[3] = 0; + end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin + axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID; + end + end + + end + endgenerate + + assign S_AXI_BVALID = bvalid_r; + assign S_AXI_AWREADY = aw_ready_r; + + endmodule + +module blk_mem_axi_read_wrapper_beh_v8_4 +# ( + //// AXI Interface related parameters start here + parameter C_INTERFACE_TYPE = 0, + parameter C_AXI_TYPE = 0, + parameter C_AXI_SLAVE_TYPE = 0, + parameter C_MEMORY_TYPE = 0, + parameter C_WRITE_WIDTH_A = 4, + parameter C_WRITE_DEPTH_A = 32, + parameter C_ADDRA_WIDTH = 12, + parameter C_AXI_PIPELINE_STAGES = 0, + parameter C_AXI_ARADDR_WIDTH = 12, + parameter C_HAS_AXI_ID = 0, + parameter C_AXI_ID_WIDTH = 4, + parameter C_ADDRB_WIDTH = 12 + ) + ( + + //// AXI Global Signals + input S_ACLK, + input S_ARESETN, + //// AXI Full/Lite Slave Read (Read side) + input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR, + input [7:0] S_AXI_ARLEN, + input [2:0] S_AXI_ARSIZE, + input [1:0] S_AXI_ARBURST, + input S_AXI_ARVALID, + output S_AXI_ARREADY, + output S_AXI_RLAST, + output S_AXI_RVALID, + input S_AXI_RREADY, + input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID, + output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0, + //// AXI Full/Lite Read Address Signals to BRAM + output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT, + output S_AXI_RD_EN + ); + + localparam FLOP_DELAY = 100; // 100 ps + localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0: + ((C_WRITE_WIDTH_A==16)?1: + ((C_WRITE_WIDTH_A==32)?2: + ((C_WRITE_WIDTH_A==64)?3: + ((C_WRITE_WIDTH_A==128)?4: + ((C_WRITE_WIDTH_A==256)?5:0)))))); + + + + reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0; + wire addr_en_c; + wire rd_en_c; + wire incr_addr_c; + wire single_trans_c; + wire dec_alen_c; + wire mux_sel_c; + wire r_last_c; + wire r_last_int_c; + wire [C_ADDRB_WIDTH-1 : 0] araddr_out; + + reg [7:0] arlen_int_r=0; + reg [7:0] arlen_cntr=8'h01; + reg [1:0] arburst_int_c=0; + reg [1:0] arburst_int_r=0; + reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)? + C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0; + integer num_of_bytes_c = 0; + integer total_bytes = 0; + integer num_of_bytes_r = 0; + integer wrap_base_addr_r = 0; + integer wrap_boundary_r = 0; + + reg [7:0] arlen_int_c=0; + integer total_bytes_c = 0; + integer wrap_base_addr_c = 0; + integer wrap_boundary_c = 0; + + assign dec_alen_c = incr_addr_c | r_last_int_c; + + + read_netlist_v8_4 + #(.C_AXI_TYPE (1), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) + axi_read_fsm ( + .S_AXI_INCR_ADDR(incr_addr_c), + .S_AXI_ADDR_EN(addr_en_c), + .S_AXI_SINGLE_TRANS(single_trans_c), + .S_AXI_MUX_SEL(mux_sel_c), + .S_AXI_R_LAST(r_last_c), + .S_AXI_R_LAST_INT(r_last_int_c), + + //// AXI Global Signals + .S_ACLK(S_ACLK), + .S_ARESETN(S_ARESETN), + //// AXI Full/Lite Slave Read (Read side) + .S_AXI_ARLEN(S_AXI_ARLEN), + .S_AXI_ARVALID(S_AXI_ARVALID), + .S_AXI_ARREADY(S_AXI_ARREADY), + .S_AXI_RLAST(S_AXI_RLAST), + .S_AXI_RVALID(S_AXI_RVALID), + .S_AXI_RREADY(S_AXI_RREADY), + //// AXI Full/Lite Read Address Signals to BRAM + .S_AXI_RD_EN(rd_en_c) + ); + + always@(*) begin + num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0); + total_bytes = (num_of_bytes_r)*(arlen_int_r+1); + wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes); + wrap_boundary_r = wrap_base_addr_r+total_bytes; + + //////// combinatorial from interface + arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN); + total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1); + wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c); + wrap_boundary_c = wrap_base_addr_c+total_bytes_c; + + arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1); + end + + ////------------------------------------------------------------------------- + //// BMG address generation + ////------------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + araddr_reg <= 0; + arburst_int_r <= 0; + num_of_bytes_r <= 0; + end else begin + if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin + arburst_int_r <= arburst_int_c; + num_of_bytes_r <= num_of_bytes_c; + if (arburst_int_c == 2'b10) begin + if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin + araddr_reg <= wrap_base_addr_c; + end else begin + araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; + end + end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin + araddr_reg <= S_AXI_ARADDR + num_of_bytes_c; + end + + end else if (addr_en_c == 1'b1) begin + araddr_reg <= S_AXI_ARADDR; + num_of_bytes_r <= num_of_bytes_c; + arburst_int_r <= arburst_int_c; + end else if (incr_addr_c == 1'b1) begin + if (arburst_int_r == 2'b10) begin + if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin + araddr_reg <= wrap_base_addr_r; + end else begin + araddr_reg <= araddr_reg + num_of_bytes_r; + end + end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin + araddr_reg <= araddr_reg + num_of_bytes_r; + end + end + end + end + +assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg); + + + ////----------------------------------------------------------------------- + //// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM + ////----------------------------------------------------------------------- + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + arlen_cntr <= 8'h01; + arlen_int_r <= 0; + end else begin + if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin + arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; + arlen_cntr <= S_AXI_ARLEN - 1'b1; + end else if (addr_en_c == 1'b1) begin + arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; + arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ; + end else if (dec_alen_c == 1'b1) begin + arlen_cntr <= arlen_cntr - 1'b1 ; + end + else begin + arlen_cntr <= arlen_cntr; + end + end + end + + assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0; + + + ////------------------------------------------------------------------------ + //// AXI FULL FSM + //// Mux Selection of ARADDR + //// ARADDR is driven out from the read fsm based on the mux_sel_c + //// Based on mux_sel either ARADDR is given out or the latched ARADDR is + //// given out to BRAM + ////------------------------------------------------------------------------ + assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out; + + ////------------------------------------------------------------------------ + //// Assign output signals - AXI FULL FSM + ////------------------------------------------------------------------------ + assign S_AXI_RD_EN = rd_en_c; + + generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r + always @(posedge S_ACLK or S_ARESETN) begin + if (S_ARESETN == 1'b1) begin + S_AXI_RID <= 0; + ar_id_r <= 0; + end else begin + if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin + S_AXI_RID <= S_AXI_ARID; + ar_id_r <= S_AXI_ARID; + end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin + ar_id_r <= S_AXI_ARID; + end else if (rd_en_c == 1'b1) begin + S_AXI_RID <= ar_id_r; + end + end + end + end + endgenerate + +endmodule + +module blk_mem_axi_regs_fwd_v8_4 + #(parameter C_DATA_WIDTH = 8 + )( + input ACLK, + input ARESET, + input S_VALID, + output S_READY, + input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, + output M_VALID, + input M_READY, + output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA + ); + + reg [C_DATA_WIDTH-1:0] STORAGE_DATA; + wire S_READY_I; + reg M_VALID_I; + reg [1:0] ARESET_D; + + //assign local signal to its output signal + assign S_READY = S_READY_I; + assign M_VALID = M_VALID_I; + + always @(posedge ACLK) begin + ARESET_D <= {ARESET_D[0], ARESET}; + end + + //Save payload data whenever we have a transaction on the slave side + always @(posedge ACLK or ARESET) begin + if (ARESET == 1'b1) begin + STORAGE_DATA <= 0; + end else begin + if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin + STORAGE_DATA <= S_PAYLOAD_DATA; + end + end + end + + always @(posedge ACLK) begin + M_PAYLOAD_DATA = STORAGE_DATA; + end + + //M_Valid set to high when we have a completed transfer on slave side + //Is removed on a M_READY except if we have a new transfer on the slave side + + always @(posedge ACLK or ARESET_D) begin + if (ARESET_D != 2'b00) begin + M_VALID_I <= 1'b0; + end else begin + if (S_VALID == 1'b1) begin + //Always set M_VALID_I when slave side is valid + M_VALID_I <= 1'b1; + end else if (M_READY == 1'b1 ) begin + //Clear (or keep) when no slave side is valid but master side is ready + M_VALID_I <= 1'b0; + end + end + end + + //Slave Ready is either when Master side drives M_READY or we have space in our storage data + assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D)); + + endmodule + +//***************************************************************************** +// Output Register Stage module +// +// This module builds the output register stages of the memory. This module is +// instantiated in the main memory module (blk_mem_gen_v8_4_3) which is +// declared/implemented further down in this file. +//***************************************************************************** +module blk_mem_gen_v8_4_3_output_stage + #(parameter C_FAMILY = "virtex7", + parameter C_XDEVICEFAMILY = "virtex7", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RST = 0, + parameter C_RSTRAM = 0, + parameter C_RST_PRIORITY = "CE", + parameter C_INIT_VAL = "0", + parameter C_HAS_EN = 0, + parameter C_HAS_REGCE = 0, + parameter C_DATA_WIDTH = 32, + parameter C_ADDRB_WIDTH = 10, + parameter C_HAS_MEM_OUTPUT_REGS = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter NUM_STAGES = 1, + parameter C_EN_ECC_PIPE = 0, + parameter FLOP_DELAY = 100 + ) + ( + input CLK, + input RST, + input EN, + input REGCE, + input [C_DATA_WIDTH-1:0] DIN_I, + output reg [C_DATA_WIDTH-1:0] DOUT, + input SBITERR_IN_I, + input DBITERR_IN_I, + output reg SBITERR, + output reg DBITERR, + input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I, + input ECCPIPECE, + output reg [C_ADDRB_WIDTH-1:0] RDADDRECC +); + +//****************************** +// Port and Generic Definitions +//****************************** + ////////////////////////////////////////////////////////////////////////// + // Generic Definitions + ////////////////////////////////////////////////////////////////////////// + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RST : Determines the presence of the RST port + // C_RSTRAM : Determines if special reset behavior is used + // C_RST_PRIORITY : Determines the priority between CE and SR + // C_INIT_VAL : Initialization value + // C_HAS_EN : Determines the presence of the EN port + // C_HAS_REGCE : Determines the presence of the REGCE port + // C_DATA_WIDTH : Memory write/read width + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output + // of the RAM primitive + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // NUM_STAGES : Determines the number of output stages + // FLOP_DELAY : Constant delay for register assignments + ////////////////////////////////////////////////////////////////////////// + // Port Definitions + ////////////////////////////////////////////////////////////////////////// + // CLK : Clock to synchronize all read and write operations + // RST : Reset input to reset memory outputs to a user-defined + // reset state + // EN : Enable all read and write operations + // REGCE : Register Clock Enable to control each pipeline output + // register stages + // DIN : Data input to the Output stage. + // DOUT : Final Data output + // SBITERR_IN : SBITERR input signal to the Output stage. + // SBITERR : Final SBITERR Output signal. + // DBITERR_IN : DBITERR input signal to the Output stage. + // DBITERR : Final DBITERR Output signal. + // RDADDRECC_IN : RDADDRECC input signal to the Output stage. + // RDADDRECC : Final RDADDRECC Output signal. + ////////////////////////////////////////////////////////////////////////// + +// Fix for CR-509792 + + localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1; + + // Declare the pipeline registers + // (includes mem output reg, mux pipeline stages, and mux output reg) + reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs; + reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs; + reg [REG_STAGES-1:0] sbiterr_regs; + reg [REG_STAGES-1:0] dbiterr_regs; + + reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL; + reg [C_DATA_WIDTH-1:0] init_val ; + + //********************************************* + // Wire off optional inputs based on parameters + //********************************************* + wire en_i; + wire regce_i; + wire rst_i; + + // Internal signals + reg [C_DATA_WIDTH-1:0] DIN; + reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN; + reg SBITERR_IN; + reg DBITERR_IN; + + + // Internal enable for output registers is tied to user EN or '1' depending + // on parameters + assign en_i = (C_HAS_EN==0 || EN); + + // Internal register enable for output registers is tied to user REGCE, EN or + // '1' depending on parameters + // For V4 ECC, REGCE is always 1 + // Virtex-4 ECC Not Yet Supported + assign regce_i = ((C_HAS_REGCE==1) && REGCE) || + ((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN)); + + //Internal SRR is tied to user RST or '0' depending on parameters + assign rst_i = (C_HAS_RST==1) && RST; + + //**************************************************** + // Power on: load up the output registers and latches + //**************************************************** + initial begin + if (!($sscanf(init_str, "%h", init_val))) begin + init_val = 0; + end + DOUT = init_val; + RDADDRECC = 0; + SBITERR = 1'b0; + DBITERR = 1'b0; + DIN = {(C_DATA_WIDTH){1'b0}}; + RDADDRECC_IN = 0; + SBITERR_IN = 0; + DBITERR_IN = 0; + // This will be one wider than need, but 0 is an error + out_regs = {(REG_STAGES+1){init_val}}; + rdaddrecc_regs = 0; + sbiterr_regs = {(REG_STAGES+1){1'b0}}; + dbiterr_regs = {(REG_STAGES+1){1'b0}}; + end + + //*********************************************** + // NUM_STAGES = 0 (No output registers. RAM only) + //*********************************************** + generate if (NUM_STAGES == 0) begin : zero_stages + always @* begin + DOUT = DIN; + RDADDRECC = RDADDRECC_IN; + SBITERR = SBITERR_IN; + DBITERR = DBITERR_IN; + end + end + endgenerate + + generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg + always @* begin + DIN = DIN_I; + SBITERR_IN = SBITERR_IN_I; + DBITERR_IN = DBITERR_IN_I; + RDADDRECC_IN = RDADDRECC_IN_I; + end + end + endgenerate + + generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg + always @(posedge CLK) begin + if(ECCPIPECE == 1) begin + DIN <= #FLOP_DELAY DIN_I; + SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I; + DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I; + RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I; + end + end + end + endgenerate + + + //*********************************************** + // NUM_STAGES = 1 + // (Mem Output Reg only or Mux Output Reg only) + //*********************************************** + + // Possible valid combinations: + // Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1) + // +-----------------------------------------+ + // | C_RSTRAM_* | Reset Behavior | + // +----------------+------------------------+ + // | 0 | Normal Behavior | + // +----------------+------------------------+ + // | 1 | Special Behavior | + // +----------------+------------------------+ + // + // Normal = REGCE gates reset, as in the case of all families except S3ADSP. + // Special = EN gates reset, as in the case of S3ADSP. + + generate if (NUM_STAGES == 1 && + (C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) || + C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0)) + begin : one_stages_norm + + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY DIN; + RDADDRECC <= #FLOP_DELAY RDADDRECC_IN; + SBITERR <= #FLOP_DELAY SBITERR_IN; + DBITERR <= #FLOP_DELAY DBITERR_IN; + end //Output signal assignments + end //end Priority conditions + end //end RST Type conditions + end //end one_stages_norm generate statement + endgenerate + + // Special Reset Behavior for S3ADSP + generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp")) + begin : one_stage_splbhv + always @(posedge CLK) begin + if (en_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + end else if (regce_i && !rst_i) begin + DOUT <= #FLOP_DELAY DIN; + end //Output signal assignments + end //end CLK + end //end one_stage_splbhv generate statement + endgenerate + + //************************************************************ + // NUM_STAGES > 1 + // Mem Output Reg + Mux Output Reg + // or + // Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg + // or + // Mux Pipeline Stages (>0) + Mux Output Reg + //************************************************************* + generate if (NUM_STAGES > 1) begin : multi_stage + //Asynchronous Reset + always @(posedge CLK) begin + if (C_RST_PRIORITY == "CE") begin //REGCE has priority + if (regce_i && rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end else begin //RST has priority + if (rst_i) begin + DOUT <= #FLOP_DELAY init_val; + RDADDRECC <= #FLOP_DELAY 0; + SBITERR <= #FLOP_DELAY 1'b0; + DBITERR <= #FLOP_DELAY 1'b0; + end else if (regce_i) begin + DOUT <= #FLOP_DELAY + out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH]; + RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH]; + SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2]; + DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2]; + end //Output signal assignments + end //end Priority conditions + // Shift the data through the output stages + if (en_i) begin + out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN; + rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN; + sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN; + dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN; + end + end //end CLK + end //end multi_stage generate statement + endgenerate +endmodule + +module blk_mem_gen_v8_4_3_softecc_output_reg_stage + #(parameter C_DATA_WIDTH = 32, + parameter C_ADDRB_WIDTH = 10, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_USE_SOFTECC = 0, + parameter FLOP_DELAY = 100 + ) + ( + input CLK, + input [C_DATA_WIDTH-1:0] DIN, + output reg [C_DATA_WIDTH-1:0] DOUT, + input SBITERR_IN, + input DBITERR_IN, + output reg SBITERR, + output reg DBITERR, + input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN, + output reg [C_ADDRB_WIDTH-1:0] RDADDRECC +); + +//****************************** +// Port and Generic Definitions +//****************************** + ////////////////////////////////////////////////////////////////////////// + // Generic Definitions + ////////////////////////////////////////////////////////////////////////// + // C_DATA_WIDTH : Memory write/read width + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // FLOP_DELAY : Constant delay for register assignments + ////////////////////////////////////////////////////////////////////////// + // Port Definitions + ////////////////////////////////////////////////////////////////////////// + // CLK : Clock to synchronize all read and write operations + // DIN : Data input to the Output stage. + // DOUT : Final Data output + // SBITERR_IN : SBITERR input signal to the Output stage. + // SBITERR : Final SBITERR Output signal. + // DBITERR_IN : DBITERR input signal to the Output stage. + // DBITERR : Final DBITERR Output signal. + // RDADDRECC_IN : RDADDRECC input signal to the Output stage. + // RDADDRECC : Final RDADDRECC Output signal. + ////////////////////////////////////////////////////////////////////////// + + reg [C_DATA_WIDTH-1:0] dout_i = 0; + reg sbiterr_i = 0; + reg dbiterr_i = 0; + reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0; + + //*********************************************** + // NO OUTPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage + always @* begin + DOUT = DIN; + RDADDRECC = RDADDRECC_IN; + SBITERR = SBITERR_IN; + DBITERR = DBITERR_IN; + end + end + endgenerate + + //*********************************************** + // WITH OUTPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage + always @(posedge CLK) begin + dout_i <= #FLOP_DELAY DIN; + rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN; + sbiterr_i <= #FLOP_DELAY SBITERR_IN; + dbiterr_i <= #FLOP_DELAY DBITERR_IN; + end + + always @* begin + DOUT = dout_i; + RDADDRECC = rdaddrecc_i; + SBITERR = sbiterr_i; + DBITERR = dbiterr_i; + end //end always + end //end in_or_out_stage generate statement + endgenerate + +endmodule + + +//***************************************************************************** +// Main Memory module +// +// This module is the top-level behavioral model and this implements the RAM +//***************************************************************************** +module blk_mem_gen_v8_4_3_mem_module + #(parameter C_CORENAME = "blk_mem_gen_v8_4_3", + parameter C_FAMILY = "virtex7", + parameter C_XDEVICEFAMILY = "virtex7", + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_USE_BRAM_BLOCK = 0, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_INIT_FILE = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_SOFTECC = 0, + parameter C_USE_ECC = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter FLOP_DELAY = 100, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_EN_ECC_PIPE = 0, + parameter C_DISABLE_WARN_BHV_RANGE = 0 + ) + (input CLKA, + input RSTA, + input ENA, + input REGCEA, + input [C_WEA_WIDTH-1:0] WEA, + input [C_ADDRA_WIDTH-1:0] ADDRA, + input [C_WRITE_WIDTH_A-1:0] DINA, + output [C_READ_WIDTH_A-1:0] DOUTA, + input CLKB, + input RSTB, + input ENB, + input REGCEB, + input [C_WEB_WIDTH-1:0] WEB, + input [C_ADDRB_WIDTH-1:0] ADDRB, + input [C_WRITE_WIDTH_B-1:0] DINB, + output [C_READ_WIDTH_B-1:0] DOUTB, + input INJECTSBITERR, + input INJECTDBITERR, + input ECCPIPECE, + input SLEEP, + output SBITERR, + output DBITERR, + output [C_ADDRB_WIDTH-1:0] RDADDRECC + ); +//****************************** +// Port and Generic Definitions +//****************************** + ////////////////////////////////////////////////////////////////////////// + // Generic Definitions + ////////////////////////////////////////////////////////////////////////// + // C_CORENAME : Instance name of the Block Memory Generator core + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_MEM_TYPE : Designates memory type. + // It can be + // 0 - Single Port Memory + // 1 - Simple Dual Port Memory + // 2 - True Dual Port Memory + // 3 - Single Port Read Only Memory + // 4 - Dual Port Read Only Memory + // C_BYTE_SIZE : Size of a byte (8 or 9 bits) + // C_ALGORITHM : Designates the algorithm method used + // for constructing the memory. + // It can be Fixed_Primitives, Minimum_Area or + // Low_Power + // C_PRIM_TYPE : Designates the user selected primitive used to + // construct the memory. + // + // C_LOAD_INIT_FILE : Designates the use of an initialization file to + // initialize memory contents. + // C_INIT_FILE_NAME : Memory initialization file name. + // C_USE_DEFAULT_DATA : Designates whether to fill remaining + // initialization space with default data + // C_DEFAULT_DATA : Default value of all memory locations + // not initialized by the memory + // initialization file. + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RSTA : Determines the presence of the RSTA port + // C_RST_PRIORITY_A : Determines the priority between CE and SR for + // Port A. + // C_RSTRAM_A : Determines if special reset behavior is used for + // Port A + // C_INITA_VAL : The initialization value for Port A + // C_HAS_ENA : Determines the presence of the ENA port + // C_HAS_REGCEA : Determines the presence of the REGCEA port + // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. + // C_WEA_WIDTH : The width of the WEA port + // C_WRITE_MODE_A : Configurable write mode for Port A. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_A : Memory write width for Port A. + // C_READ_WIDTH_A : Memory read width for Port A. + // C_WRITE_DEPTH_A : Memory write depth for Port A. + // C_READ_DEPTH_A : Memory read depth for Port A. + // C_ADDRA_WIDTH : Width of the ADDRA input port + // C_HAS_RSTB : Determines the presence of the RSTB port + // C_RST_PRIORITY_B : Determines the priority between CE and SR for + // Port B. + // C_RSTRAM_B : Determines if special reset behavior is used for + // Port B + // C_INITB_VAL : The initialization value for Port B + // C_HAS_ENB : Determines the presence of the ENB port + // C_HAS_REGCEB : Determines the presence of the REGCEB port + // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. + // C_WEB_WIDTH : The width of the WEB port + // C_WRITE_MODE_B : Configurable write mode for Port B. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_B : Memory write width for Port B. + // C_READ_WIDTH_B : Memory read width for Port B. + // C_WRITE_DEPTH_B : Memory write depth for Port B. + // C_READ_DEPTH_B : Memory read depth for Port B. + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output + // of the RAM primitive for Port A. + // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive for Port B. + // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output + // of the MUX for Port A. + // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output + // of the MUX for Port B. + // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in + // between the muxes. + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // C_HAS_INJECTERR : Determines if the error injection pins + // are present or not. If the ECC feature + // is not used, this value is defaulted to + // 0, else the following are the allowed + // values: + // 0 : No INJECTSBITERR or INJECTDBITERR pins + // 1 : Only INJECTSBITERR pin exists + // 2 : Only INJECTDBITERR pin exists + // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist + // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision + // warnings. It can be "ALL", "NONE", + // "Warnings_Only" or "Generate_X_Only". + // C_COMMON_CLK : Determins if the core has a single CLK input. + // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings + // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range + // warnings + ////////////////////////////////////////////////////////////////////////// + // Port Definitions + ////////////////////////////////////////////////////////////////////////// + // CLKA : Clock to synchronize all read and write operations of Port A. + // RSTA : Reset input to reset memory outputs to a user-defined + // reset state for Port A. + // ENA : Enable all read and write operations of Port A. + // REGCEA : Register Clock Enable to control each pipeline output + // register stages for Port A. + // WEA : Write Enable to enable all write operations of Port A. + // ADDRA : Address of Port A. + // DINA : Data input of Port A. + // DOUTA : Data output of Port A. + // CLKB : Clock to synchronize all read and write operations of Port B. + // RSTB : Reset input to reset memory outputs to a user-defined + // reset state for Port B. + // ENB : Enable all read and write operations of Port B. + // REGCEB : Register Clock Enable to control each pipeline output + // register stages for Port B. + // WEB : Write Enable to enable all write operations of Port B. + // ADDRB : Address of Port B. + // DINB : Data input of Port B. + // DOUTB : Data output of Port B. + // INJECTSBITERR : Single Bit ECC Error Injection Pin. + // INJECTDBITERR : Double Bit ECC Error Injection Pin. + // SBITERR : Output signal indicating that a Single Bit ECC Error has been + // detected and corrected. + // DBITERR : Output signal indicating that a Double Bit ECC Error has been + // detected. + // RDADDRECC : Read Address Output signal indicating address at which an + // ECC error has occurred. + ////////////////////////////////////////////////////////////////////////// + + +// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_4_3" and it is +// only used by this module to print warning messages. It is neither passed +// down from blk_mem_gen_v8_4_3_xst.v nor present in the instantiation template +// coregen generates + + //*************************************************************************** + // constants for the core behavior + //*************************************************************************** + // file handles for logging + //-------------------------------------------------- + localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range + localparam COLLFILE = 32'h8000_0001; //stdout for coll detection + localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors + + // other constants + //-------------------------------------------------- + localparam COLL_DELAY = 100; // 100 ps + + // locally derived parameters to determine memory shape + //----------------------------------------------------- + + localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0))))); + + localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ? + C_WRITE_WIDTH_A : C_READ_WIDTH_A; + localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ? + C_WRITE_WIDTH_B : C_READ_WIDTH_B; + localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ? + MIN_WIDTH_A : MIN_WIDTH_B; + + localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ? + C_WRITE_DEPTH_A : C_READ_DEPTH_A; + localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ? + C_WRITE_DEPTH_B : C_READ_DEPTH_B; + localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ? + MAX_DEPTH_A : MAX_DEPTH_B; + + + // locally derived parameters to assist memory access + //---------------------------------------------------- + // Calculate the width ratios of each port with respect to the narrowest + // port + localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH; + localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH; + localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH; + localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH; + + // To modify the LSBs of the 'wider' data to the actual + // address value + //---------------------------------------------------- + localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A; + localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A; + localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B; + localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B; + + // If byte writes aren't being used, make sure BYTE_SIZE is not + // wider than the memory elements to avoid compilation warnings + localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH; + + // The memory + reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1]; + reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1]; + reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3; + // ECC error arrays + reg sbiterr_arr [0:MAX_DEPTH-1]; + reg dbiterr_arr [0:MAX_DEPTH-1]; + + reg softecc_sbiterr_arr [0:MAX_DEPTH-1]; + reg softecc_dbiterr_arr [0:MAX_DEPTH-1]; + // Memory output 'latches' + reg [C_READ_WIDTH_A-1:0] memory_out_a; + reg [C_READ_WIDTH_B-1:0] memory_out_b; + + // ECC error inputs and outputs from output_stage module: + reg sbiterr_in; + wire sbiterr_sdp; + reg dbiterr_in; + wire dbiterr_sdp; + + wire [C_READ_WIDTH_B-1:0] dout_i; + wire dbiterr_i; + wire sbiterr_i; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i; + + reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in; + wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp; + + // Reset values + reg [C_READ_WIDTH_A-1:0] inita_val; + reg [C_READ_WIDTH_B-1:0] initb_val; + + // Collision detect + reg is_collision; + reg is_collision_a, is_collision_delay_a; + reg is_collision_b, is_collision_delay_b; + + // Temporary variables for initialization + //--------------------------------------- + integer status; + integer initfile; + integer meminitfile; + // data input buffer + reg [C_WRITE_WIDTH_A-1:0] mif_data; + reg [C_WRITE_WIDTH_A-1:0] mem_data; + // string values in hex + reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL; + reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL; + reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA; + // initialization filename + reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME; + reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE; + + + //Constants used to calculate the effective address widths for each of the + //four ports. + integer cnt = 1; + integer write_addr_a_width, read_addr_a_width; + integer write_addr_b_width, read_addr_b_width; + + localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtexuplushbm"?"virtex7":(C_FAMILY=="zynquplusrfsoc"?"virtex7":(C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))))))))); + + // Internal configuration parameters + //--------------------------------------------- + localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3); + localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4); + localparam HAS_A_WRITE = (!IS_ROM); + localparam HAS_B_WRITE = (C_MEM_TYPE==2); + localparam HAS_A_READ = (C_MEM_TYPE!=1); + localparam HAS_B_READ = (!SINGLE_PORT); + localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE); + + // Calculate the mux pipeline register stages for Port A and Port B + //------------------------------------------------------------------ + localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ? + C_MUX_PIPELINE_STAGES : 0; + localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ? + C_MUX_PIPELINE_STAGES : 0; + + // Calculate total number of register stages in the core + // ----------------------------------------------------- + localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A); + + localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B); + + wire ena_i; + wire enb_i; + wire reseta_i; + wire resetb_i; + wire [C_WEA_WIDTH-1:0] wea_i; + wire [C_WEB_WIDTH-1:0] web_i; + wire rea_i; + wire reb_i; + wire rsta_outp_stage; + wire rstb_outp_stage; + // ECC SBITERR/DBITERR Outputs + // The ECC Behavior is modeled by the behavioral models only for Virtex-6. + // For Virtex-5, these outputs will be tied to 0. + assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0; + assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0; + assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0; + + + // This effectively wires off optional inputs + assign ena_i = (C_HAS_ENA==0) || ENA; + assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT; + // To match RTL : In RTL, write enable of the primitive is tied to all 1's and + // the enable of the primitive is ANDing of wea(0) and ena. so eventually, the + // write operation depends on both enable and write enable. So, the below code + // which is actually doing the write operation only on enable ignoring the wea + // is removed to be in consistent with RTL. + // To Fix CR855535 (The fix to this CR is reverted to match RTL) + //assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0; + assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0; + assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0; + assign rea_i = (HAS_A_READ) ? ena_i : 'b0; + assign reb_i = (HAS_B_READ) ? enb_i : 'b0; + + // These signals reset the memory latches + + assign reseta_i = + ((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) || + (C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1)); + + assign resetb_i = + ((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) || + (C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1)); + + // Tasks to access the memory + //--------------------------- + //************** + // write_a + //************** + task write_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg [C_WEA_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_A-1:0] data, + input inj_sbiterr, + input inj_dbiterr); + reg [C_WRITE_WIDTH_A-1:0] current_contents; + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_A_DIV); + if (address >= C_WRITE_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEA) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_A + i]; + end + end + + // Apply incoming bytes + if (C_WEA_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Insert double bit errors: + if (C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin +// Modified for Implementing CR_859399 + current_contents[0] = !(current_contents[30]); + current_contents[1] = !(current_contents[62]); + + /*current_contents[0] = !(current_contents[0]); + current_contents[1] = !(current_contents[1]);*/ + end + end + + // Insert softecc double bit errors: + if (C_USE_SOFTECC == 1) begin + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0]; + doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1]; + doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2]; + current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0]; + end + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_A == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_A] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_A + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + + // Store the address at which error is injected: + if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin + if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || + (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) + begin + sbiterr_arr[addr] = 1; + end else begin + sbiterr_arr[addr] = 0; + end + + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + dbiterr_arr[addr] = 1; + end else begin + dbiterr_arr[addr] = 0; + end + end + + // Store the address at which softecc error is injected: + if (C_USE_SOFTECC == 1) begin + if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) || + (C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1)) + begin + softecc_sbiterr_arr[addr] = 1; + end else begin + softecc_sbiterr_arr[addr] = 0; + end + + if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin + softecc_dbiterr_arr[addr] = 1; + end else begin + softecc_dbiterr_arr[addr] = 0; + end + end + + end + end + endtask + + //************** + // write_b + //************** + task write_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg [C_WEB_WIDTH-1:0] byte_en, + input reg [C_WRITE_WIDTH_B-1:0] data); + reg [C_WRITE_WIDTH_B-1:0] current_contents; + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + // Shift the address by the ratio + address = (addr/WRITE_ADDR_B_DIV); + if (address >= C_WRITE_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Write", + C_CORENAME, addr); + end + + // valid address + end else begin + + // Combine w/ byte writes + if (C_USE_BYTE_WEB) begin + + // Get the current memory contents + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + current_contents = memory[address]; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + current_contents[MIN_WIDTH*i+:MIN_WIDTH] + = memory[address*WRITE_WIDTH_RATIO_B + i]; + end + end + + // Apply incoming bytes + if (C_WEB_WIDTH == 1) begin + // Workaround for IUS 5.5 part-select issue + if (byte_en[0]) begin + current_contents = data; + end + end else begin + for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin + if (byte_en[i]) begin + current_contents[BYTE_SIZE*i+:BYTE_SIZE] + = data[BYTE_SIZE*i+:BYTE_SIZE]; + end + end + end + + // No byte-writes, overwrite the whole word + end else begin + current_contents = data; + end + + // Write data to memory + if (WRITE_WIDTH_RATIO_B == 1) begin + // Workaround for IUS 5.5 part-select issue + memory[address*WRITE_WIDTH_RATIO_B] = current_contents; + end else begin + for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin + memory[address*WRITE_WIDTH_RATIO_B + i] + = current_contents[MIN_WIDTH*i+:MIN_WIDTH]; + end + end + end + end + endtask + + //************** + // read_a + //************** + task read_a + (input reg [C_ADDRA_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRA_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_a <= #FLOP_DELAY inita_val; + end else begin + // Shift the address by the ratio + address = (addr/READ_ADDR_A_DIV); + if (address >= C_READ_DEPTH_A) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for A Read", + C_CORENAME, addr); + end + memory_out_a <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_A==1) begin + memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin + memory_out_a[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i]; + end + end //end READ_WIDTH_RATIO_A==1 loop + + end //end valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // read_b + //************** + task read_b + (input reg [C_ADDRB_WIDTH-1:0] addr, + input reg reset); + reg [C_ADDRB_WIDTH-1:0] address; + integer i; + begin + + if (reset) begin + memory_out_b <= #FLOP_DELAY initb_val; + sbiterr_in <= #FLOP_DELAY 1'b0; + dbiterr_in <= #FLOP_DELAY 1'b0; + rdaddrecc_in <= #FLOP_DELAY 0; + end else begin + // Shift the address + address = (addr/READ_ADDR_B_DIV); + if (address >= C_READ_DEPTH_B) begin + if (!C_DISABLE_WARN_BHV_RANGE) begin + $fdisplay(ADDRFILE, + "%0s WARNING: Address %0h is outside range for B Read", + C_CORENAME, addr); + end + memory_out_b <= #FLOP_DELAY 'bX; + sbiterr_in <= #FLOP_DELAY 1'bX; + dbiterr_in <= #FLOP_DELAY 1'bX; + rdaddrecc_in <= #FLOP_DELAY 'bX; + // valid address + end else begin + if (READ_WIDTH_RATIO_B==1) begin + memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B]; + end else begin + // Increment through the 'partial' words in the memory + for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin + memory_out_b[MIN_WIDTH*i+:MIN_WIDTH] + <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i]; + end + end + + if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin + rdaddrecc_in <= #FLOP_DELAY addr; + if (sbiterr_arr[addr] == 1) begin + sbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + sbiterr_in <= #FLOP_DELAY 1'b0; + end + + if (dbiterr_arr[addr] == 1) begin + dbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + dbiterr_in <= #FLOP_DELAY 1'b0; + end + + end else if (C_USE_SOFTECC == 1) begin + rdaddrecc_in <= #FLOP_DELAY addr; + if (softecc_sbiterr_arr[addr] == 1) begin + sbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + sbiterr_in <= #FLOP_DELAY 1'b0; + end + + if (softecc_dbiterr_arr[addr] == 1) begin + dbiterr_in <= #FLOP_DELAY 1'b1; + end else begin + dbiterr_in <= #FLOP_DELAY 1'b0; + end + end else begin + rdaddrecc_in <= #FLOP_DELAY 0; + dbiterr_in <= #FLOP_DELAY 1'b0; + sbiterr_in <= #FLOP_DELAY 1'b0; + end //end SOFTECC Loop + end //end Valid address loop + end //end reset-data assignment loops + end + endtask + + //************** + // reset_a + //************** + task reset_a (input reg reset); + begin + if (reset) memory_out_a <= #FLOP_DELAY inita_val; + end + endtask + + //************** + // reset_b + //************** + task reset_b (input reg reset); + begin + if (reset) memory_out_b <= #FLOP_DELAY initb_val; + end + endtask + + //************** + // init_memory + //************** + task init_memory; + integer i, j, addr_step; + integer status; + reg [C_WRITE_WIDTH_A-1:0] default_data; + begin + default_data = 0; + + //Display output message indicating that the behavioral model is being + //initialized + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data..."); + + // Convert the default to hex + if (C_USE_DEFAULT_DATA) begin + if (default_data_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME); + $finish; + end else begin + status = $sscanf(default_data_str, "%h", default_data); + if (status == 0) begin + $fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read", + "from C_DEFAULT_DATA: %0s"}, + C_CORENAME, C_DEFAULT_DATA); + $finish; + end + end + end + + // Step by WRITE_ADDR_A_DIV through the memory via the + // Port A write interface to hit every location once + addr_step = WRITE_ADDR_A_DIV; + + // 'write' to every location with default (or 0) + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0); + end + + // Get specialized data from the MIF file + if (C_LOAD_INIT_FILE) begin + if (init_file_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!", + C_CORENAME); + $finish; + end else begin + initfile = $fopen(init_file_str, "r"); + if (initfile == 0) begin + $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", + "C_INIT_FILE_NAME: %0s!"}, + C_CORENAME, init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin + status = $fscanf(initfile, "%b", mif_data); + if (status > 0) begin + write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0); + end + end + $fclose(initfile); + end //initfile + end //init_file_str + end //C_LOAD_INIT_FILE + + + if (C_USE_BRAM_BLOCK) begin + // Get specialized data from the MIF file + if (C_INIT_FILE != "NONE") begin + if (mem_init_file_str == "") begin + $fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!", + C_CORENAME); + $finish; + end else begin + meminitfile = $fopen(mem_init_file_str, "r"); + if (meminitfile == 0) begin + $fdisplay(ERRFILE, {"%0s, ERROR: Problem opening", + "C_INIT_FILE: %0s!"}, + C_CORENAME, mem_init_file_str); + $finish; + end else begin + // loop through the mif file, loading in the data + $readmemh(mem_init_file_str, memory ); + for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin + end + $fclose(meminitfile); + end //meminitfile + end //mem_init_file_str + end //C_INIT_FILE + end //C_USE_BRAM_BLOCK + + //Display output message indicating that the behavioral model is done + //initializing + if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) + $display(" Block Memory Generator data initialization complete."); + end + endtask + + //************** + // log2roundup + //************** + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + + //******************* + // collision_check + //******************* + function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a, + input integer iswrite_a, + input reg [C_ADDRB_WIDTH-1:0] addr_b, + input integer iswrite_b); + reg c_aw_bw, c_aw_br, c_ar_bw; + integer scaled_addra_to_waddrb_width; + integer scaled_addrb_to_waddrb_width; + integer scaled_addra_to_waddra_width; + integer scaled_addrb_to_waddra_width; + integer scaled_addra_to_raddrb_width; + integer scaled_addrb_to_raddrb_width; + integer scaled_addra_to_raddra_width; + integer scaled_addrb_to_raddra_width; + + + + begin + + c_aw_bw = 0; + c_aw_br = 0; + c_ar_bw = 0; + + //If write_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_b_width. Once both are scaled to + //write_addr_b_width, compare. + scaled_addra_to_waddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_b_width)); + scaled_addrb_to_waddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_b_width)); + + //If write_addr_a_width is smaller, scale both addresses to that width for + //comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to write_addr_a_width. Once both are scaled to + //write_addr_a_width, compare. + scaled_addra_to_waddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-write_addr_a_width)); + scaled_addrb_to_waddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-write_addr_a_width)); + + //If read_addr_b_width is smaller, scale both addresses to that width for + //comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_b_width. Once both are scaled to + //read_addr_b_width, compare. + scaled_addra_to_raddrb_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_b_width)); + scaled_addrb_to_raddrb_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_b_width)); + + //If read_addr_a_width is smaller, scale both addresses to that width for + //comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH, + //scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH, + //scale it down to read_addr_a_width. Once both are scaled to + //read_addr_a_width, compare. + scaled_addra_to_raddra_width = ((addr_a)/ + 2**(C_ADDRA_WIDTH-read_addr_a_width)); + scaled_addrb_to_raddra_width = ((addr_b)/ + 2**(C_ADDRB_WIDTH-read_addr_a_width)); + + //Look for a write-write collision. In order for a write-write + //collision to exist, both ports must have a write transaction. + if (iswrite_a && iswrite_b) begin + if (write_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_bw = 1; + end else begin + c_aw_bw = 0; + end + end //width + end //iswrite_a and iswrite_b + + //If the B port is reading (which means it is enabled - so could be + //a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + //to asymmetric write/read ports. + if (iswrite_a) begin + if (write_addr_a_width > read_addr_b_width) begin + if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end else begin + if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin + c_aw_br = 1; + end else begin + c_aw_br = 0; + end + end //width + end //iswrite_a + + //If the A port is reading (which means it is enabled - so could be + // a TX_WRITE or TX_READ), then check for a write-read collision). + //This could happen whether or not a write-write collision exists due + // to asymmetric write/read ports. + if (iswrite_b) begin + if (read_addr_a_width > write_addr_b_width) begin + if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end else begin + if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin + c_ar_bw = 1; + end else begin + c_ar_bw = 0; + end + end //width + end //iswrite_b + + + + collision_check = c_aw_bw | c_aw_br | c_ar_bw; + + end + endfunction + + //******************************* + // power on values + //******************************* + initial begin + // Load up the memory + init_memory; + // Load up the output registers and latches + if ($sscanf(inita_str, "%h", inita_val)) begin + memory_out_a = inita_val; + end else begin + memory_out_a = 0; + end + if ($sscanf(initb_str, "%h", initb_val)) begin + memory_out_b = initb_val; + end else begin + memory_out_b = 0; + end + + sbiterr_in = 1'b0; + dbiterr_in = 1'b0; + rdaddrecc_in = 0; + + // Determine the effective address widths for each of the 4 ports + write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV); + read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV); + write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV); + read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV); + + $display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior."); + + end + + //*************************************************************************** + // These are the main blocks which schedule read and write operations + // Note that the reset priority feature at the latch stage is only supported + // for Spartan-6. For other families, the default priority at the latch stage + // is "CE" + //*************************************************************************** + // Synchronous clocks: schedule port operations with respect to + // both write operating modes + generate + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_wf_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + + if (rea_i) read_a(ADDRA, reseta_i); + + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_rf_wf + always @(posedge CLKA) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_wf_rf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else + if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_rf_rf + always @(posedge CLKA) begin + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_wf_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_rf_nc + always @(posedge CLKA) begin + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "WRITE_FIRST")) begin : com_clk_sched_nc_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "READ_FIRST")) begin : com_clk_sched_nc_rf + always @(posedge CLKA) begin + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Read A + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B == + "NO_CHANGE")) begin : com_clk_sched_nc_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + //Read B + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + else if(C_COMMON_CLK) begin: com_clk_sched_default + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + end + end + endgenerate + + // Asynchronous clocks: port operation is independent + generate + if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf + always @(posedge CLKA) begin + //Read A + if (rea_i) read_a(ADDRA, reseta_i); + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + end + end + else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc + always @(posedge CLKA) begin + //Write A + if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR); + //Read A + if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i); + end + end + endgenerate + + generate + if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf + always @(posedge CLKB) begin + //Read B + if (reb_i) read_b(ADDRB, resetb_i); + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + end + end + else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc + always @(posedge CLKB) begin + //Write B + if (web_i) write_b(ADDRB, web_i, DINB); + //Read B + if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i); + end + end + endgenerate + + + //*************************************************************** + // Instantiate the variable depth output register stage module + //*************************************************************** + // Port A + + assign rsta_outp_stage = RSTA & (~SLEEP); + + blk_mem_gen_v8_4_3_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE ("SYNC"), + .C_HAS_RST (C_HAS_RSTA), + .C_RSTRAM (C_RSTRAM_A), + .C_RST_PRIORITY (C_RST_PRIORITY_A), + .C_INIT_VAL (C_INITA_VAL), + .C_HAS_EN (C_HAS_ENA), + .C_HAS_REGCE (C_HAS_REGCEA), + .C_DATA_WIDTH (C_READ_WIDTH_A), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_A), + .C_EN_ECC_PIPE (0), + .FLOP_DELAY (FLOP_DELAY)) + reg_a + (.CLK (CLKA), + .RST (rsta_outp_stage),//(RSTA), + .EN (ENA), + .REGCE (REGCEA), + .DIN_I (memory_out_a), + .DOUT (DOUTA), + .SBITERR_IN_I (1'b0), + .DBITERR_IN_I (1'b0), + .SBITERR (), + .DBITERR (), + .RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}), + .ECCPIPECE (1'b0), + .RDADDRECC () + ); + + assign rstb_outp_stage = RSTB & (~SLEEP); + + // Port B + blk_mem_gen_v8_4_3_output_stage + #(.C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_RST_TYPE ("SYNC"), + .C_HAS_RST (C_HAS_RSTB), + .C_RSTRAM (C_RSTRAM_B), + .C_RST_PRIORITY (C_RST_PRIORITY_B), + .C_INIT_VAL (C_INITB_VAL), + .C_HAS_EN (C_HAS_ENB), + .C_HAS_REGCE (C_HAS_REGCEB), + .C_DATA_WIDTH (C_READ_WIDTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .NUM_STAGES (NUM_OUTPUT_STAGES_B), + .C_EN_ECC_PIPE (C_EN_ECC_PIPE), + .FLOP_DELAY (FLOP_DELAY)) + reg_b + (.CLK (CLKB), + .RST (rstb_outp_stage),//(RSTB), + .EN (ENB), + .REGCE (REGCEB), + .DIN_I (memory_out_b), + .DOUT (dout_i), + .SBITERR_IN_I (sbiterr_in), + .DBITERR_IN_I (dbiterr_in), + .SBITERR (sbiterr_i), + .DBITERR (dbiterr_i), + .RDADDRECC_IN_I (rdaddrecc_in), + .ECCPIPECE (ECCPIPECE), + .RDADDRECC (rdaddrecc_i) + ); + + //*************************************************************** + // Instantiate the Input and Output register stages + //*************************************************************** +blk_mem_gen_v8_4_3_softecc_output_reg_stage + #(.C_DATA_WIDTH (C_READ_WIDTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_USE_SOFTECC (C_USE_SOFTECC), + .FLOP_DELAY (FLOP_DELAY)) + has_softecc_output_reg_stage + (.CLK (CLKB), + .DIN (dout_i), + .DOUT (DOUTB), + .SBITERR_IN (sbiterr_i), + .DBITERR_IN (dbiterr_i), + .SBITERR (sbiterr_sdp), + .DBITERR (dbiterr_sdp), + .RDADDRECC_IN (rdaddrecc_i), + .RDADDRECC (rdaddrecc_sdp) +); + + //**************************************************** + // Synchronous collision checks + //**************************************************** +// CR 780544 : To make verilog model's collison warnings in consistant with +// vhdl model, the non-blocking assignments are replaced with blocking +// assignments. + generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision = 0; + end + end else begin + is_collision = 0; + end + + // If the write port is in READ_FIRST mode, there is no collision + if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin + is_collision = 0; + end + if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin + is_collision = 0; + end + + // Only flag if one of the accesses is a write + if (is_collision && (wea_i || web_i)) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A %0s address: %0h, B %0s address: %0h\n", + wea_i ? "write" : "read", ADDRA, + web_i ? "write" : "read", ADDRB); + end + end + + //**************************************************** + // Asynchronous collision checks + //**************************************************** + end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll + + // Delay A and B addresses in order to mimic setup/hold times + wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA; + wire [0:0] #COLL_DELAY wea_delay = wea_i; + wire #COLL_DELAY ena_delay = ena_i; + wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB; + wire [0:0] #COLL_DELAY web_delay = web_i; + wire #COLL_DELAY enb_delay = enb_i; + + // Do the checks w/rt A + always @(posedge CLKA) begin + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_a = 0; + end + end else begin + is_collision_a = 0; + end + + if (ena_i && enb_delay) begin + if(wea_i || web_delay) begin + is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay, + web_delay); + end else begin + is_collision_delay_a = 0; + end + end else begin + is_collision_delay_a = 0; + end + + // Only flag if B access is a write + if (is_collision_a && web_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, ADDRB); + + end else if (is_collision_delay_a && web_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A %0s address: %0h, B write address: %0h\n", + wea_i ? "write" : "read", ADDRA, addrb_delay); + end + + end + + // Do the checks w/rt B + always @(posedge CLKB) begin + + // Possible collision if both are enabled and the addresses match + if (ena_i && enb_i) begin + if (wea_i || web_i) begin + is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i); + end else begin + is_collision_b = 0; + end + end else begin + is_collision_b = 0; + end + + if (ena_delay && enb_i) begin + if (wea_delay || web_i) begin + is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB, + web_i); + end else begin + is_collision_delay_b = 0; + end + end else begin + is_collision_delay_b = 0; + end + + + // Only flag if A access is a write + if (is_collision_b && wea_i) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A write address: %0h, B %s address: %0h\n", + ADDRA, web_i ? "write" : "read", ADDRB); + + end else if (is_collision_delay_b && wea_delay) begin + $fwrite(COLLFILE, "%0s collision detected at time: %0d, ", + C_CORENAME, $time); + $fwrite(COLLFILE, "Instance: %m, A write address: %0h, B %s address: %0h\n", + addra_delay, web_i ? "write" : "read", ADDRB); + end + + end + end + endgenerate + +endmodule +//***************************************************************************** +// Top module wraps Input register and Memory module +// +// This module is the top-level behavioral model and this implements the memory +// module and the input registers +//***************************************************************************** +module blk_mem_gen_v8_4_3 + #(parameter C_CORENAME = "blk_mem_gen_v8_4_3", + parameter C_FAMILY = "virtex7", + parameter C_XDEVICEFAMILY = "virtex7", + parameter C_ELABORATION_DIR = "", + parameter C_INTERFACE_TYPE = 0, + parameter C_USE_BRAM_BLOCK = 0, + parameter C_CTRL_ECC_ALGO = "NONE", + parameter C_ENABLE_32BIT_ADDRESS = 0, + parameter C_AXI_TYPE = 0, + parameter C_AXI_SLAVE_TYPE = 0, + parameter C_HAS_AXI_ID = 0, + parameter C_AXI_ID_WIDTH = 4, + parameter C_MEM_TYPE = 2, + parameter C_BYTE_SIZE = 9, + parameter C_ALGORITHM = 1, + parameter C_PRIM_TYPE = 3, + parameter C_LOAD_INIT_FILE = 0, + parameter C_INIT_FILE_NAME = "", + parameter C_INIT_FILE = "", + parameter C_USE_DEFAULT_DATA = 0, + parameter C_DEFAULT_DATA = "0", + //parameter C_RST_TYPE = "SYNC", + parameter C_HAS_RSTA = 0, + parameter C_RST_PRIORITY_A = "CE", + parameter C_RSTRAM_A = 0, + parameter C_INITA_VAL = "0", + parameter C_HAS_ENA = 1, + parameter C_HAS_REGCEA = 0, + parameter C_USE_BYTE_WEA = 0, + parameter C_WEA_WIDTH = 1, + parameter C_WRITE_MODE_A = "WRITE_FIRST", + parameter C_WRITE_WIDTH_A = 32, + parameter C_READ_WIDTH_A = 32, + parameter C_WRITE_DEPTH_A = 64, + parameter C_READ_DEPTH_A = 64, + parameter C_ADDRA_WIDTH = 5, + parameter C_HAS_RSTB = 0, + parameter C_RST_PRIORITY_B = "CE", + parameter C_RSTRAM_B = 0, + parameter C_INITB_VAL = "", + parameter C_HAS_ENB = 1, + parameter C_HAS_REGCEB = 0, + parameter C_USE_BYTE_WEB = 0, + parameter C_WEB_WIDTH = 1, + parameter C_WRITE_MODE_B = "WRITE_FIRST", + parameter C_WRITE_WIDTH_B = 32, + parameter C_READ_WIDTH_B = 32, + parameter C_WRITE_DEPTH_B = 64, + parameter C_READ_DEPTH_B = 64, + parameter C_ADDRB_WIDTH = 5, + parameter C_HAS_MEM_OUTPUT_REGS_A = 0, + parameter C_HAS_MEM_OUTPUT_REGS_B = 0, + parameter C_HAS_MUX_OUTPUT_REGS_A = 0, + parameter C_HAS_MUX_OUTPUT_REGS_B = 0, + parameter C_HAS_SOFTECC_INPUT_REGS_A = 0, + parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0, + parameter C_MUX_PIPELINE_STAGES = 0, + parameter C_USE_SOFTECC = 0, + parameter C_READ_LATENCY_A = 1, + parameter C_READ_LATENCY_B = 1, + parameter C_USE_ECC = 0, + parameter C_EN_ECC_PIPE = 0, + parameter C_HAS_INJECTERR = 0, + parameter C_SIM_COLLISION_CHECK = "NONE", + parameter C_COMMON_CLK = 1, + parameter C_DISABLE_WARN_BHV_COLL = 0, + parameter C_EN_SLEEP_PIN = 0, + parameter C_USE_URAM = 0, + parameter C_EN_RDADDRA_CHG = 0, + parameter C_EN_RDADDRB_CHG = 0, + parameter C_EN_DEEPSLEEP_PIN = 0, + parameter C_EN_SHUTDOWN_PIN = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_COUNT_36K_BRAM = "", + parameter C_COUNT_18K_BRAM = "", + parameter C_EST_POWER_SUMMARY = "", + parameter C_DISABLE_WARN_BHV_RANGE = 0 + + ) + (input clka, + input rsta, + input ena, + input regcea, + input [C_WEA_WIDTH-1:0] wea, + input [C_ADDRA_WIDTH-1:0] addra, + input [C_WRITE_WIDTH_A-1:0] dina, + output [C_READ_WIDTH_A-1:0] douta, + input clkb, + input rstb, + input enb, + input regceb, + input [C_WEB_WIDTH-1:0] web, + input [C_ADDRB_WIDTH-1:0] addrb, + input [C_WRITE_WIDTH_B-1:0] dinb, + output [C_READ_WIDTH_B-1:0] doutb, + input injectsbiterr, + input injectdbiterr, + output sbiterr, + output dbiterr, + output [C_ADDRB_WIDTH-1:0] rdaddrecc, + input eccpipece, + input sleep, + input deepsleep, + input shutdown, + output rsta_busy, + output rstb_busy, + //AXI BMG Input and Output Port Declarations + + //AXI Global Signals + input s_aclk, + input s_aresetn, + + //AXI Full/lite slave write (write side) + input [C_AXI_ID_WIDTH-1:0] s_axi_awid, + input [31:0] s_axi_awaddr, + input [7:0] s_axi_awlen, + input [2:0] s_axi_awsize, + input [1:0] s_axi_awburst, + input s_axi_awvalid, + output s_axi_awready, + input [C_WRITE_WIDTH_A-1:0] s_axi_wdata, + input [C_WEA_WIDTH-1:0] s_axi_wstrb, + input s_axi_wlast, + input s_axi_wvalid, + output s_axi_wready, + output [C_AXI_ID_WIDTH-1:0] s_axi_bid, + output [1:0] s_axi_bresp, + output s_axi_bvalid, + input s_axi_bready, + + //AXI Full/lite slave read (write side) + input [C_AXI_ID_WIDTH-1:0] s_axi_arid, + input [31:0] s_axi_araddr, + input [7:0] s_axi_arlen, + input [2:0] s_axi_arsize, + input [1:0] s_axi_arburst, + input s_axi_arvalid, + output s_axi_arready, + output [C_AXI_ID_WIDTH-1:0] s_axi_rid, + output [C_WRITE_WIDTH_B-1:0] s_axi_rdata, + output [1:0] s_axi_rresp, + output s_axi_rlast, + output s_axi_rvalid, + input s_axi_rready, + + //AXI Full/lite sideband signals + input s_axi_injectsbiterr, + input s_axi_injectdbiterr, + output s_axi_sbiterr, + output s_axi_dbiterr, + output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc + + ); +//****************************** +// Port and Generic Definitions +//****************************** + ////////////////////////////////////////////////////////////////////////// + // Generic Definitions + ////////////////////////////////////////////////////////////////////////// + // C_CORENAME : Instance name of the Block Memory Generator core + // C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following + // options are available - "spartan3", "spartan6", + // "virtex4", "virtex5", "virtex6" and "virtex6l". + // C_MEM_TYPE : Designates memory type. + // It can be + // 0 - Single Port Memory + // 1 - Simple Dual Port Memory + // 2 - True Dual Port Memory + // 3 - Single Port Read Only Memory + // 4 - Dual Port Read Only Memory + // C_BYTE_SIZE : Size of a byte (8 or 9 bits) + // C_ALGORITHM : Designates the algorithm method used + // for constructing the memory. + // It can be Fixed_Primitives, Minimum_Area or + // Low_Power + // C_PRIM_TYPE : Designates the user selected primitive used to + // construct the memory. + // + // C_LOAD_INIT_FILE : Designates the use of an initialization file to + // initialize memory contents. + // C_INIT_FILE_NAME : Memory initialization file name. + // C_USE_DEFAULT_DATA : Designates whether to fill remaining + // initialization space with default data + // C_DEFAULT_DATA : Default value of all memory locations + // not initialized by the memory + // initialization file. + // C_RST_TYPE : Type of reset - Synchronous or Asynchronous + // C_HAS_RSTA : Determines the presence of the RSTA port + // C_RST_PRIORITY_A : Determines the priority between CE and SR for + // Port A. + // C_RSTRAM_A : Determines if special reset behavior is used for + // Port A + // C_INITA_VAL : The initialization value for Port A + // C_HAS_ENA : Determines the presence of the ENA port + // C_HAS_REGCEA : Determines the presence of the REGCEA port + // C_USE_BYTE_WEA : Determines if the Byte Write is used or not. + // C_WEA_WIDTH : The width of the WEA port + // C_WRITE_MODE_A : Configurable write mode for Port A. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_A : Memory write width for Port A. + // C_READ_WIDTH_A : Memory read width for Port A. + // C_WRITE_DEPTH_A : Memory write depth for Port A. + // C_READ_DEPTH_A : Memory read depth for Port A. + // C_ADDRA_WIDTH : Width of the ADDRA input port + // C_HAS_RSTB : Determines the presence of the RSTB port + // C_RST_PRIORITY_B : Determines the priority between CE and SR for + // Port B. + // C_RSTRAM_B : Determines if special reset behavior is used for + // Port B + // C_INITB_VAL : The initialization value for Port B + // C_HAS_ENB : Determines the presence of the ENB port + // C_HAS_REGCEB : Determines the presence of the REGCEB port + // C_USE_BYTE_WEB : Determines if the Byte Write is used or not. + // C_WEB_WIDTH : The width of the WEB port + // C_WRITE_MODE_B : Configurable write mode for Port B. It can be + // WRITE_FIRST, READ_FIRST or NO_CHANGE. + // C_WRITE_WIDTH_B : Memory write width for Port B. + // C_READ_WIDTH_B : Memory read width for Port B. + // C_WRITE_DEPTH_B : Memory write depth for Port B. + // C_READ_DEPTH_B : Memory read depth for Port B. + // C_ADDRB_WIDTH : Width of the ADDRB input port + // C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output + // of the RAM primitive for Port A. + // C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output + // of the RAM primitive for Port B. + // C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output + // of the MUX for Port A. + // C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output + // of the MUX for Port B. + // C_HAS_SOFTECC_INPUT_REGS_A : + // C_HAS_SOFTECC_OUTPUT_REGS_B : + // C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in + // between the muxes. + // C_USE_SOFTECC : Determines if the Soft ECC feature is used or + // not. Only applicable Spartan-6 + // C_USE_ECC : Determines if the ECC feature is used or + // not. Only applicable for V5 and V6 + // C_HAS_INJECTERR : Determines if the error injection pins + // are present or not. If the ECC feature + // is not used, this value is defaulted to + // 0, else the following are the allowed + // values: + // 0 : No INJECTSBITERR or INJECTDBITERR pins + // 1 : Only INJECTSBITERR pin exists + // 2 : Only INJECTDBITERR pin exists + // 3 : Both INJECTSBITERR and INJECTDBITERR pins exist + // C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision + // warnings. It can be "ALL", "NONE", + // "Warnings_Only" or "Generate_X_Only". + // C_COMMON_CLK : Determins if the core has a single CLK input. + // C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings + // C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range + // warnings + ////////////////////////////////////////////////////////////////////////// + // Port Definitions + ////////////////////////////////////////////////////////////////////////// + // CLKA : Clock to synchronize all read and write operations of Port A. + // RSTA : Reset input to reset memory outputs to a user-defined + // reset state for Port A. + // ENA : Enable all read and write operations of Port A. + // REGCEA : Register Clock Enable to control each pipeline output + // register stages for Port A. + // WEA : Write Enable to enable all write operations of Port A. + // ADDRA : Address of Port A. + // DINA : Data input of Port A. + // DOUTA : Data output of Port A. + // CLKB : Clock to synchronize all read and write operations of Port B. + // RSTB : Reset input to reset memory outputs to a user-defined + // reset state for Port B. + // ENB : Enable all read and write operations of Port B. + // REGCEB : Register Clock Enable to control each pipeline output + // register stages for Port B. + // WEB : Write Enable to enable all write operations of Port B. + // ADDRB : Address of Port B. + // DINB : Data input of Port B. + // DOUTB : Data output of Port B. + // INJECTSBITERR : Single Bit ECC Error Injection Pin. + // INJECTDBITERR : Double Bit ECC Error Injection Pin. + // SBITERR : Output signal indicating that a Single Bit ECC Error has been + // detected and corrected. + // DBITERR : Output signal indicating that a Double Bit ECC Error has been + // detected. + // RDADDRECC : Read Address Output signal indicating address at which an + // ECC error has occurred. + ////////////////////////////////////////////////////////////////////////// + + wire SBITERR; + wire DBITERR; + wire S_AXI_AWREADY; + wire S_AXI_WREADY; + wire S_AXI_BVALID; + wire S_AXI_ARREADY; + wire S_AXI_RLAST; + wire S_AXI_RVALID; + wire S_AXI_SBITERR; + wire S_AXI_DBITERR; + + wire [C_WEA_WIDTH-1:0] WEA = wea; + wire [C_ADDRA_WIDTH-1:0] ADDRA = addra; + wire [C_WRITE_WIDTH_A-1:0] DINA = dina; + wire [C_READ_WIDTH_A-1:0] DOUTA; + wire [C_WEB_WIDTH-1:0] WEB = web; + wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb; + wire [C_WRITE_WIDTH_B-1:0] DINB = dinb; + wire [C_READ_WIDTH_B-1:0] DOUTB; + wire [C_ADDRB_WIDTH-1:0] RDADDRECC; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid; + wire [31:0] S_AXI_AWADDR = s_axi_awaddr; + wire [7:0] S_AXI_AWLEN = s_axi_awlen; + wire [2:0] S_AXI_AWSIZE = s_axi_awsize; + wire [1:0] S_AXI_AWBURST = s_axi_awburst; + wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata; + wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID; + wire [1:0] S_AXI_BRESP; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid; + wire [31:0] S_AXI_ARADDR = s_axi_araddr; + wire [7:0] S_AXI_ARLEN = s_axi_arlen; + wire [2:0] S_AXI_ARSIZE = s_axi_arsize; + wire [1:0] S_AXI_ARBURST = s_axi_arburst; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; + wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA; + wire [1:0] S_AXI_RRESP; + wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC; + // Added to fix the simulation warning #CR731605 + wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0; + wire ECCPIPECE; + wire SLEEP; + reg RSTA_BUSY = 0; + reg RSTB_BUSY = 0; + // Declaration of internal signals to avoid warnings #927399 + wire CLKA; + wire RSTA; + wire ENA; + wire REGCEA; + wire CLKB; + wire RSTB; + wire ENB; + wire REGCEB; + wire INJECTSBITERR; + wire INJECTDBITERR; + wire S_ACLK; + wire S_ARESETN; + wire S_AXI_AWVALID; + wire S_AXI_WLAST; + wire S_AXI_WVALID; + wire S_AXI_BREADY; + wire S_AXI_ARVALID; + wire S_AXI_RREADY; + wire S_AXI_INJECTSBITERR; + wire S_AXI_INJECTDBITERR; + + assign CLKA = clka; + assign RSTA = rsta; + assign ENA = ena; + assign REGCEA = regcea; + assign CLKB = clkb; + assign RSTB = rstb; + assign ENB = enb; + assign REGCEB = regceb; + assign INJECTSBITERR = injectsbiterr; + assign INJECTDBITERR = injectdbiterr; + assign ECCPIPECE = eccpipece; + assign SLEEP = sleep; + assign sbiterr = SBITERR; + assign dbiterr = DBITERR; + assign S_ACLK = s_aclk; + assign S_ARESETN = s_aresetn; + assign S_AXI_AWVALID = s_axi_awvalid; + assign s_axi_awready = S_AXI_AWREADY; + assign S_AXI_WLAST = s_axi_wlast; + assign S_AXI_WVALID = s_axi_wvalid; + assign s_axi_wready = S_AXI_WREADY; + assign s_axi_bvalid = S_AXI_BVALID; + assign S_AXI_BREADY = s_axi_bready; + assign S_AXI_ARVALID = s_axi_arvalid; + assign s_axi_arready = S_AXI_ARREADY; + assign s_axi_rlast = S_AXI_RLAST; + assign s_axi_rvalid = S_AXI_RVALID; + assign S_AXI_RREADY = s_axi_rready; + assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr; + assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr; + assign s_axi_sbiterr = S_AXI_SBITERR; + assign s_axi_dbiterr = S_AXI_DBITERR; + + assign rsta_busy = RSTA_BUSY; + assign rstb_busy = RSTB_BUSY; + + assign doutb = DOUTB; + assign douta = DOUTA; + assign rdaddrecc = RDADDRECC; + assign s_axi_bid = S_AXI_BID; + assign s_axi_bresp = S_AXI_BRESP; + assign s_axi_rid = S_AXI_RID; + assign s_axi_rdata = S_AXI_RDATA; + assign s_axi_rresp = S_AXI_RRESP; + assign s_axi_rdaddrecc = S_AXI_RDADDRECC; + + localparam FLOP_DELAY = 100; // 100 ps + + reg injectsbiterr_in; + reg injectdbiterr_in; + reg rsta_in; + reg ena_in; + reg regcea_in; + reg [C_WEA_WIDTH-1:0] wea_in; + reg [C_ADDRA_WIDTH-1:0] addra_in; + reg [C_WRITE_WIDTH_A-1:0] dina_in; + + wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c; + wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c; + wire s_axi_wr_en_c; + wire s_axi_rd_en_c; + wire s_aresetn_a_c; + wire [7:0] s_axi_arlen_c ; + + + wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c; + wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c; + wire [1:0] s_axi_rresp_c; + wire s_axi_rlast_c; + wire s_axi_rvalid_c; + wire s_axi_rready_c; + wire regceb_c; + + localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3; + wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c; + wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c; + +// Safety logic related signals + + reg [4:0] RSTA_SHFT_REG = 0; + reg POR_A = 0; + reg [4:0] RSTB_SHFT_REG = 0; + reg POR_B = 0; + + reg ENA_dly = 0; + reg ENA_dly_D = 0; + + reg ENB_dly = 0; + reg ENB_dly_D = 0; + + wire RSTA_I_SAFE; + wire RSTB_I_SAFE; + + wire ENA_I_SAFE; + wire ENB_I_SAFE; + + reg ram_rstram_a_busy = 0; + reg ram_rstreg_a_busy = 0; + reg ram_rstram_b_busy = 0; + reg ram_rstreg_b_busy = 0; + + reg ENA_dly_reg = 0; + reg ENB_dly_reg = 0; + + reg ENA_dly_reg_D = 0; + reg ENB_dly_reg_D = 0; + + //************** + // log2roundup + //************** + function integer log2roundup (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + + if (data_value > 1) begin + for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin + width = width + 1; + end //loop + end //if + + log2roundup = width; + + end //log2roundup + endfunction + + //************** + // log2int + //************** + function integer log2int (input integer data_value); + integer width; + integer cnt; + begin + width = 0; + cnt= data_value; + + for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin + width = width + 1; + end //loop + + log2int = width; + + end //log2int + endfunction + + //************************************************************************** + // FUNCTION : divroundup + // Returns the ceiling value of the division + // Data_value - the quantity to be divided, dividend + // Divisor - the value to divide the data_value by + //************************************************************************** + function integer divroundup (input integer data_value,input integer divisor); + integer div; + begin + div = data_value/divisor; + if ((data_value % divisor) != 0) begin + div = div+1; + end //if + divroundup = div; + end //if + endfunction + + localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0); + localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8); + localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB; + + //Data Width Number of LSB address bits to be discarded + //1 to 16 1 + //17 to 32 2 + //33 to 64 3 + //65 to 128 4 + //129 to 256 5 + //257 to 512 6 + //513 to 1024 7 + // The following two constants determine this. + + localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8))); + localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL); + localparam C_AXI_OS_WR = 2; + + //*********************************************** + // INPUT REGISTERS. + //*********************************************** + generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage + always @* begin + injectsbiterr_in = INJECTSBITERR; + injectdbiterr_in = INJECTDBITERR; + rsta_in = RSTA; + ena_in = ENA; + regcea_in = REGCEA; + wea_in = WEA; + addra_in = ADDRA; + dina_in = DINA; + end //end always + end //end no_softecc_input_reg_stage + endgenerate + + generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage + always @(posedge CLKA) begin + injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR; + injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR; + rsta_in <= #FLOP_DELAY RSTA; + ena_in <= #FLOP_DELAY ENA; + regcea_in <= #FLOP_DELAY REGCEA; + wea_in <= #FLOP_DELAY WEA; + addra_in <= #FLOP_DELAY ADDRA; + dina_in <= #FLOP_DELAY DINA; + end //end always + end //end input_reg_stages generate statement + endgenerate + + //************************************************************************** + // NO SAFETY LOGIC + //************************************************************************** + + generate + if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN + assign ENA_I_SAFE = ena_in; + assign ENB_I_SAFE = ENB; + assign RSTA_I_SAFE = rsta_in; + assign RSTB_I_SAFE = RSTB; + end + endgenerate + + //*************************************************************************** + // SAFETY LOGIC + // Power-ON Reset Generation + //*************************************************************************** + generate + if (C_EN_SAFETY_CKT == 1) begin + always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ; + always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0]; + always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ; + always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0]; + + assign RSTA_I_SAFE = rsta_in | POR_A; + assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B); + end + endgenerate + + //----------------------------------------------------------------------------- + // -- RSTA/B_BUSY Generation + //----------------------------------------------------------------------------- + + generate + if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG + always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D; + always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy; + end + endgenerate + + generate + if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG + always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D; + always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy; + end + endgenerate + + generate + if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY + always @(*) RSTB_BUSY = 1'b0; + end + endgenerate + + generate + if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG + always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D; + always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy; + end + endgenerate + + generate + if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG + always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D; + always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy; + end + endgenerate + + //----------------------------------------------------------------------------- + // -- ENA/ENB Generation + //----------------------------------------------------------------------------- + + generate + if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG + always @(posedge clka) begin + ENA_dly <= #FLOP_DELAY RSTA_I_SAFE; + ENA_dly_D <= #FLOP_DELAY ENA_dly; + end + assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in); + end + endgenerate + + generate + if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG + always @(posedge clka) begin + ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE; + ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg; + end + assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in); + end + endgenerate + + generate + if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB + assign ENB_I_SAFE = 1'b0; + end + endgenerate + + generate + if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG + always @(posedge clkb) begin : PROC_ENB_GEN + ENB_dly <= #FLOP_DELAY RSTB_I_SAFE; + ENB_dly_D <= #FLOP_DELAY ENB_dly; + end + assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB); + end + endgenerate + + generate + if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG + always @(posedge clkb) begin : PROC_ENB_GEN + ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE; + ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg; + end + assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB); + end + endgenerate + + generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module +blk_mem_gen_v8_4_3_mem_module + #(.C_CORENAME (C_CORENAME), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_ALGORITHM (C_ALGORITHM), + .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_INIT_FILE (C_INIT_FILE), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE ("SYNC"), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .FLOP_DELAY (FLOP_DELAY), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_EN_ECC_PIPE (C_EN_ECC_PIPE), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) + blk_mem_gen_v8_4_3_inst + (.CLKA (CLKA), + .RSTA (RSTA_I_SAFE),//(rsta_in), + .ENA (ENA_I_SAFE),//(ena_in), + .REGCEA (regcea_in), + .WEA (wea_in), + .ADDRA (addra_in), + .DINA (dina_in), + .DOUTA (DOUTA), + .CLKB (CLKB), + .RSTB (RSTB_I_SAFE),//(RSTB), + .ENB (ENB_I_SAFE),//(ENB), + .REGCEB (REGCEB), + .WEB (WEB), + .ADDRB (ADDRB), + .DINB (DINB), + .DOUTB (DOUTB), + .INJECTSBITERR (injectsbiterr_in), + .INJECTDBITERR (injectdbiterr_in), + .ECCPIPECE (ECCPIPECE), + .SLEEP (SLEEP), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .RDADDRECC (RDADDRECC) + ); + end + endgenerate + + generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module + + localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A); + localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B); + + localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8); + localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8); + // localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8); + // localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8); + localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB; + localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB; + + // Data Width Number of LSB address bits to be discarded + // 1 to 16 1 + // 17 to 32 2 + // 33 to 64 3 + // 65 to 128 4 + // 129 to 256 5 + // 257 to 512 6 + // 513 to 1024 7 + // The following two constants determine this. + + localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8))); + localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_B,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_B,8))); + localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A; + localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B; + + wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i; + wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i; + wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i; + + assign msb_zero_i = 0; + assign lsb_zero_i = 0; + assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i}; + +blk_mem_gen_v8_4_3_mem_module + #(.C_CORENAME (C_CORENAME), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_INIT_FILE (C_INIT_FILE), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE ("SYNC"), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (C_HAS_ENA), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (C_USE_BYTE_WEA), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (C_HAS_ENB), + .C_HAS_REGCEB (C_HAS_REGCEB), + .C_USE_BYTE_WEB (C_USE_BYTE_WEB), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL), + .C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A), + .C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B), + .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .FLOP_DELAY (FLOP_DELAY), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_EN_ECC_PIPE (C_EN_ECC_PIPE), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) + blk_mem_gen_v8_4_3_inst + (.CLKA (CLKA), + .RSTA (RSTA_I_SAFE),//(rsta_in), + .ENA (ENA_I_SAFE),//(ena_in), + .REGCEA (regcea_in), + .WEA (wea_in), + .ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]), + .DINA (dina_in), + .DOUTA (DOUTA), + .CLKB (CLKB), + .RSTB (RSTB_I_SAFE),//(RSTB), + .ENB (ENB_I_SAFE),//(ENB), + .REGCEB (REGCEB), + .WEB (WEB), + .ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]), + .DINB (DINB), + .DOUTB (DOUTB), + .INJECTSBITERR (injectsbiterr_in), + .INJECTDBITERR (injectdbiterr_in), + .ECCPIPECE (ECCPIPECE), + .SLEEP (SLEEP), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .RDADDRECC (rdaddrecc_i) + ); + end + endgenerate + + generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs + assign S_AXI_RDATA = s_axi_rdata_c; + assign S_AXI_RLAST = s_axi_rlast_c; + assign S_AXI_RVALID = s_axi_rvalid_c; + assign S_AXI_RID = s_axi_rid_c; + assign S_AXI_RRESP = s_axi_rresp_c; + assign s_axi_rready_c = S_AXI_RREADY; + end + endgenerate + + generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb + assign regceb_c = s_axi_rvalid_c && s_axi_rready_c; + end + endgenerate + + generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb + assign regceb_c = REGCEB; + end + endgenerate + + generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs + assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c}; + assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; + assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B]; + assign S_AXI_RRESP = m_axi_payload_c[2:1]; + assign S_AXI_RLAST = m_axi_payload_c[0]; + end + endgenerate + + generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs + assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c}; + assign S_AXI_RDATA = s_axi_rdata_c; + assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH]; + assign S_AXI_RRESP = m_axi_payload_c[2:1]; + assign S_AXI_RLAST = m_axi_payload_c[0]; + end + endgenerate + + generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd + + blk_mem_axi_regs_fwd_v8_4 + #(.C_DATA_WIDTH (C_AXI_PAYLOAD)) + axi_regs_inst ( + .ACLK (S_ACLK), + .ARESET (s_aresetn_a_c), + .S_VALID (s_axi_rvalid_c), + .S_READY (s_axi_rready_c), + .S_PAYLOAD_DATA (s_axi_payload_c), + .M_VALID (S_AXI_RVALID), + .M_READY (S_AXI_RREADY), + .M_PAYLOAD_DATA (m_axi_payload_c) + ); + end + endgenerate + + generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module + +assign s_aresetn_a_c = !S_ARESETN; +assign S_AXI_BRESP = 2'b00; +assign s_axi_rresp_c = 2'b00; +assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0; + + blk_mem_axi_write_wrapper_beh_v8_4 + #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_AXI_TYPE (C_AXI_TYPE), + .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), + .C_MEMORY_TYPE (C_MEM_TYPE), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), + .C_HAS_AXI_ID (C_HAS_AXI_ID), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A), + .C_AXI_OS_WR (C_AXI_OS_WR)) + axi_wr_fsm ( + // AXI Global Signals + .S_ACLK (S_ACLK), + .S_ARESETN (s_aresetn_a_c), + // AXI Full/Lite Slave Write interface + .S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), + .S_AXI_AWLEN (S_AXI_AWLEN), + .S_AXI_AWID (S_AXI_AWID), + .S_AXI_AWSIZE (S_AXI_AWSIZE), + .S_AXI_AWBURST (S_AXI_AWBURST), + .S_AXI_AWVALID (S_AXI_AWVALID), + .S_AXI_AWREADY (S_AXI_AWREADY), + .S_AXI_WVALID (S_AXI_WVALID), + .S_AXI_WREADY (S_AXI_WREADY), + .S_AXI_BVALID (S_AXI_BVALID), + .S_AXI_BREADY (S_AXI_BREADY), + .S_AXI_BID (S_AXI_BID), + // Signals for BRAM interfac( + .S_AXI_AWADDR_OUT (s_axi_awaddr_out_c), + .S_AXI_WR_EN (s_axi_wr_en_c) + ); + + blk_mem_axi_read_wrapper_beh_v8_4 + #(.C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_AXI_TYPE (C_AXI_TYPE), + .C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE), + .C_MEMORY_TYPE (C_MEM_TYPE), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_AXI_PIPELINE_STAGES (1), + .C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB), + .C_HAS_AXI_ID (C_HAS_AXI_ID), + .C_AXI_ID_WIDTH (C_AXI_ID_WIDTH), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH)) + axi_rd_sm( + //AXI Global Signals + .S_ACLK (S_ACLK), + .S_ARESETN (s_aresetn_a_c), + //AXI Full/Lite Read Side + .S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]), + .S_AXI_ARLEN (s_axi_arlen_c), + .S_AXI_ARSIZE (S_AXI_ARSIZE), + .S_AXI_ARBURST (S_AXI_ARBURST), + .S_AXI_ARVALID (S_AXI_ARVALID), + .S_AXI_ARREADY (S_AXI_ARREADY), + .S_AXI_RLAST (s_axi_rlast_c), + .S_AXI_RVALID (s_axi_rvalid_c), + .S_AXI_RREADY (s_axi_rready_c), + .S_AXI_ARID (S_AXI_ARID), + .S_AXI_RID (s_axi_rid_c), + //AXI Full/Lite Read FSM Outputs + .S_AXI_ARADDR_OUT (s_axi_araddr_out_c), + .S_AXI_RD_EN (s_axi_rd_en_c) + ); + +blk_mem_gen_v8_4_3_mem_module + #(.C_CORENAME (C_CORENAME), + .C_FAMILY (C_FAMILY), + .C_XDEVICEFAMILY (C_XDEVICEFAMILY), + .C_MEM_TYPE (C_MEM_TYPE), + .C_BYTE_SIZE (C_BYTE_SIZE), + .C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK), + .C_ALGORITHM (C_ALGORITHM), + .C_PRIM_TYPE (C_PRIM_TYPE), + .C_LOAD_INIT_FILE (C_LOAD_INIT_FILE), + .C_INIT_FILE_NAME (C_INIT_FILE_NAME), + .C_INIT_FILE (C_INIT_FILE), + .C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA), + .C_DEFAULT_DATA (C_DEFAULT_DATA), + .C_RST_TYPE ("SYNC"), + .C_HAS_RSTA (C_HAS_RSTA), + .C_RST_PRIORITY_A (C_RST_PRIORITY_A), + .C_RSTRAM_A (C_RSTRAM_A), + .C_INITA_VAL (C_INITA_VAL), + .C_HAS_ENA (1), + .C_HAS_REGCEA (C_HAS_REGCEA), + .C_USE_BYTE_WEA (1), + .C_WEA_WIDTH (C_WEA_WIDTH), + .C_WRITE_MODE_A (C_WRITE_MODE_A), + .C_WRITE_WIDTH_A (C_WRITE_WIDTH_A), + .C_READ_WIDTH_A (C_READ_WIDTH_A), + .C_WRITE_DEPTH_A (C_WRITE_DEPTH_A), + .C_READ_DEPTH_A (C_READ_DEPTH_A), + .C_ADDRA_WIDTH (C_ADDRA_WIDTH), + .C_HAS_RSTB (C_HAS_RSTB), + .C_RST_PRIORITY_B (C_RST_PRIORITY_B), + .C_RSTRAM_B (C_RSTRAM_B), + .C_INITB_VAL (C_INITB_VAL), + .C_HAS_ENB (1), + .C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B), + .C_USE_BYTE_WEB (1), + .C_WEB_WIDTH (C_WEB_WIDTH), + .C_WRITE_MODE_B (C_WRITE_MODE_B), + .C_WRITE_WIDTH_B (C_WRITE_WIDTH_B), + .C_READ_WIDTH_B (C_READ_WIDTH_B), + .C_WRITE_DEPTH_B (C_WRITE_DEPTH_B), + .C_READ_DEPTH_B (C_READ_DEPTH_B), + .C_ADDRB_WIDTH (C_ADDRB_WIDTH), + .C_HAS_MEM_OUTPUT_REGS_A (0), + .C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B), + .C_HAS_MUX_OUTPUT_REGS_A (0), + .C_HAS_MUX_OUTPUT_REGS_B (0), + .C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A), + .C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B), + .C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES), + .C_USE_SOFTECC (C_USE_SOFTECC), + .C_USE_ECC (C_USE_ECC), + .C_HAS_INJECTERR (C_HAS_INJECTERR), + .C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK), + .C_COMMON_CLK (C_COMMON_CLK), + .FLOP_DELAY (FLOP_DELAY), + .C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL), + .C_EN_ECC_PIPE (0), + .C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE)) + blk_mem_gen_v8_4_3_inst + (.CLKA (S_ACLK), + .RSTA (s_aresetn_a_c), + .ENA (s_axi_wr_en_c), + .REGCEA (regcea_in), + .WEA (S_AXI_WSTRB), + .ADDRA (s_axi_awaddr_out_c), + .DINA (S_AXI_WDATA), + .DOUTA (DOUTA), + .CLKB (S_ACLK), + .RSTB (s_aresetn_a_c), + .ENB (s_axi_rd_en_c), + .REGCEB (regceb_c), + .WEB (WEB_parameterized), + .ADDRB (s_axi_araddr_out_c), + .DINB (DINB), + .DOUTB (s_axi_rdata_c), + .INJECTSBITERR (injectsbiterr_in), + .INJECTDBITERR (injectdbiterr_in), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .ECCPIPECE (1'b0), + .SLEEP (1'b0), + .RDADDRECC (RDADDRECC) + ); + end + endgenerate +endmodule + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ipstatic/simulation/fifo_generator_vlog_beh.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ipstatic/simulation/fifo_generator_vlog_beh.v new file mode 100644 index 00000000..54ebbe2f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ipstatic/simulation/fifo_generator_vlog_beh.v @@ -0,0 +1,10519 @@ +/* + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: fifo_generator_vlog_beh.v + * + * Author : Xilinx + * + ******************************************************************************* + * Structure: + * + * fifo_generator_vlog_beh.v + * | + * +-fifo_generator_v13_2_4_bhv_ver_as + * | + * +-fifo_generator_v13_2_4_bhv_ver_ss + * | + * +-fifo_generator_v13_2_4_bhv_ver_preload0 + * + ******************************************************************************* + * Description: + * + * The Verilog behavioral model for the FIFO Generator. + * + * The behavioral model has three parts: + * - The behavioral model for independent clocks FIFOs (_as) + * - The behavioral model for common clock FIFOs (_ss) + * - The "preload logic" block which implements First-word Fall-through + * + ******************************************************************************* + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_vlog_beh + #( + //----------------------------------------------------------------------- + // Generic Declarations + //----------------------------------------------------------------------- + parameter C_COMMON_CLOCK = 0, + parameter C_COUNT_TYPE = 0, + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DEFAULT_VALUE = "", + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_ENABLE_RLOCS = 0, + parameter C_FAMILY = "", + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_BACKUP = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_INT_CLK = 0, + parameter C_HAS_MEMINIT_FILE = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RD_RST = 0, + parameter C_HAS_RST = 1, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_HAS_WR_RST = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_INIT_WR_PNTR_VAL = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_MIF_FILE_NAME = "", + parameter C_OPTIMIZATION_MODE = 0, + parameter C_OVERFLOW_LOW = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PRIM_FIFO_TYPE = "4kx4", + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_FREQ = 1, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_ECC = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_PIPELINE_REG = 0, + parameter C_POWER_SAVING_MODE = 0, + parameter C_USE_FIFO16_FLAGS = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_FREQ = 1, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_WR_RESPONSE_LATENCY = 1, + parameter C_MSGON_VAL = 1, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0, + parameter C_SYNCHRONIZER_STAGE = 2, + + // AXI Interface related parameters start here + parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3 + parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3 + parameter C_HAS_AXI_WR_CHANNEL = 0, + parameter C_HAS_AXI_RD_CHANNEL = 0, + parameter C_HAS_SLAVE_CE = 0, + parameter C_HAS_MASTER_CE = 0, + parameter C_ADD_NGC_CONSTRAINT = 0, + parameter C_USE_COMMON_UNDERFLOW = 0, + parameter C_USE_COMMON_OVERFLOW = 0, + parameter C_USE_DEFAULT_SETTINGS = 0, + + // AXI Full/Lite + parameter C_AXI_ID_WIDTH = 0, + parameter C_AXI_ADDR_WIDTH = 0, + parameter C_AXI_DATA_WIDTH = 0, + parameter C_AXI_LEN_WIDTH = 8, + parameter C_AXI_LOCK_WIDTH = 2, + parameter C_HAS_AXI_ID = 0, + parameter C_HAS_AXI_AWUSER = 0, + parameter C_HAS_AXI_WUSER = 0, + parameter C_HAS_AXI_BUSER = 0, + parameter C_HAS_AXI_ARUSER = 0, + parameter C_HAS_AXI_RUSER = 0, + parameter C_AXI_ARUSER_WIDTH = 0, + parameter C_AXI_AWUSER_WIDTH = 0, + parameter C_AXI_WUSER_WIDTH = 0, + parameter C_AXI_BUSER_WIDTH = 0, + parameter C_AXI_RUSER_WIDTH = 0, + + // AXI Streaming + parameter C_HAS_AXIS_TDATA = 0, + parameter C_HAS_AXIS_TID = 0, + parameter C_HAS_AXIS_TDEST = 0, + parameter C_HAS_AXIS_TUSER = 0, + parameter C_HAS_AXIS_TREADY = 0, + parameter C_HAS_AXIS_TLAST = 0, + parameter C_HAS_AXIS_TSTRB = 0, + parameter C_HAS_AXIS_TKEEP = 0, + parameter C_AXIS_TDATA_WIDTH = 1, + parameter C_AXIS_TID_WIDTH = 1, + parameter C_AXIS_TDEST_WIDTH = 1, + parameter C_AXIS_TUSER_WIDTH = 1, + parameter C_AXIS_TSTRB_WIDTH = 1, + parameter C_AXIS_TKEEP_WIDTH = 1, + + // AXI Channel Type + // WACH --> Write Address Channel + // WDCH --> Write Data Channel + // WRCH --> Write Response Channel + // RACH --> Read Address Channel + // RDCH --> Read Data Channel + // AXIS --> AXI Streaming + parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic + parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie + + // AXI Implementation Type + // 1 = Common Clock Block RAM FIFO + // 2 = Common Clock Distributed RAM FIFO + // 11 = Independent Clock Block RAM FIFO + // 12 = Independent Clock Distributed RAM FIFO + parameter C_IMPLEMENTATION_TYPE_WACH = 0, + parameter C_IMPLEMENTATION_TYPE_WDCH = 0, + parameter C_IMPLEMENTATION_TYPE_WRCH = 0, + parameter C_IMPLEMENTATION_TYPE_RACH = 0, + parameter C_IMPLEMENTATION_TYPE_RDCH = 0, + parameter C_IMPLEMENTATION_TYPE_AXIS = 0, + + // AXI FIFO Type + // 0 = Data FIFO + // 1 = Packet FIFO + // 2 = Low Latency Sync FIFO + // 3 = Low Latency Async FIFO + parameter C_APPLICATION_TYPE_WACH = 0, + parameter C_APPLICATION_TYPE_WDCH = 0, + parameter C_APPLICATION_TYPE_WRCH = 0, + parameter C_APPLICATION_TYPE_RACH = 0, + parameter C_APPLICATION_TYPE_RDCH = 0, + parameter C_APPLICATION_TYPE_AXIS = 0, + + // AXI Built-in FIFO Primitive Type + // 512x36, 1kx18, 2kx9, 4kx4, etc + parameter C_PRIM_FIFO_TYPE_WACH = "512x36", + parameter C_PRIM_FIFO_TYPE_WDCH = "512x36", + parameter C_PRIM_FIFO_TYPE_WRCH = "512x36", + parameter C_PRIM_FIFO_TYPE_RACH = "512x36", + parameter C_PRIM_FIFO_TYPE_RDCH = "512x36", + parameter C_PRIM_FIFO_TYPE_AXIS = "512x36", + + // Enable ECC + // 0 = ECC disabled + // 1 = ECC enabled + parameter C_USE_ECC_WACH = 0, + parameter C_USE_ECC_WDCH = 0, + parameter C_USE_ECC_WRCH = 0, + parameter C_USE_ECC_RACH = 0, + parameter C_USE_ECC_RDCH = 0, + parameter C_USE_ECC_AXIS = 0, + + // ECC Error Injection Type + // 0 = No Error Injection + // 1 = Single Bit Error Injection + // 2 = Double Bit Error Injection + // 3 = Single Bit and Double Bit Error Injection + parameter C_ERROR_INJECTION_TYPE_WACH = 0, + parameter C_ERROR_INJECTION_TYPE_WDCH = 0, + parameter C_ERROR_INJECTION_TYPE_WRCH = 0, + parameter C_ERROR_INJECTION_TYPE_RACH = 0, + parameter C_ERROR_INJECTION_TYPE_RDCH = 0, + parameter C_ERROR_INJECTION_TYPE_AXIS = 0, + + // Input Data Width + // Accumulation of all AXI input signal's width + parameter C_DIN_WIDTH_WACH = 1, + parameter C_DIN_WIDTH_WDCH = 1, + parameter C_DIN_WIDTH_WRCH = 1, + parameter C_DIN_WIDTH_RACH = 1, + parameter C_DIN_WIDTH_RDCH = 1, + parameter C_DIN_WIDTH_AXIS = 1, + + parameter C_WR_DEPTH_WACH = 16, + parameter C_WR_DEPTH_WDCH = 16, + parameter C_WR_DEPTH_WRCH = 16, + parameter C_WR_DEPTH_RACH = 16, + parameter C_WR_DEPTH_RDCH = 16, + parameter C_WR_DEPTH_AXIS = 16, + + parameter C_WR_PNTR_WIDTH_WACH = 4, + parameter C_WR_PNTR_WIDTH_WDCH = 4, + parameter C_WR_PNTR_WIDTH_WRCH = 4, + parameter C_WR_PNTR_WIDTH_RACH = 4, + parameter C_WR_PNTR_WIDTH_RDCH = 4, + parameter C_WR_PNTR_WIDTH_AXIS = 4, + + parameter C_HAS_DATA_COUNTS_WACH = 0, + parameter C_HAS_DATA_COUNTS_WDCH = 0, + parameter C_HAS_DATA_COUNTS_WRCH = 0, + parameter C_HAS_DATA_COUNTS_RACH = 0, + parameter C_HAS_DATA_COUNTS_RDCH = 0, + parameter C_HAS_DATA_COUNTS_AXIS = 0, + + parameter C_HAS_PROG_FLAGS_WACH = 0, + parameter C_HAS_PROG_FLAGS_WDCH = 0, + parameter C_HAS_PROG_FLAGS_WRCH = 0, + parameter C_HAS_PROG_FLAGS_RACH = 0, + parameter C_HAS_PROG_FLAGS_RDCH = 0, + parameter C_HAS_PROG_FLAGS_AXIS = 0, + + parameter C_PROG_FULL_TYPE_WACH = 0, + parameter C_PROG_FULL_TYPE_WDCH = 0, + parameter C_PROG_FULL_TYPE_WRCH = 0, + parameter C_PROG_FULL_TYPE_RACH = 0, + parameter C_PROG_FULL_TYPE_RDCH = 0, + parameter C_PROG_FULL_TYPE_AXIS = 0, + + parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0, + + parameter C_PROG_EMPTY_TYPE_WACH = 0, + parameter C_PROG_EMPTY_TYPE_WDCH = 0, + parameter C_PROG_EMPTY_TYPE_WRCH = 0, + parameter C_PROG_EMPTY_TYPE_RACH = 0, + parameter C_PROG_EMPTY_TYPE_RDCH = 0, + parameter C_PROG_EMPTY_TYPE_AXIS = 0, + + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0, + + parameter C_REG_SLICE_MODE_WACH = 0, + parameter C_REG_SLICE_MODE_WDCH = 0, + parameter C_REG_SLICE_MODE_WRCH = 0, + parameter C_REG_SLICE_MODE_RACH = 0, + parameter C_REG_SLICE_MODE_RDCH = 0, + parameter C_REG_SLICE_MODE_AXIS = 0 + + ) + + ( + //------------------------------------------------------------------------------ + // Input and Output Declarations + //------------------------------------------------------------------------------ + + // Conventional FIFO Interface Signals + input backup, + input backup_marker, + input clk, + input rst, + input srst, + input wr_clk, + input wr_rst, + input rd_clk, + input rd_rst, + input [C_DIN_WIDTH-1:0] din, + input wr_en, + input rd_en, + // Optional inputs + input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh, + input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert, + input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate, + input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh, + input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert, + input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate, + input int_clk, + input injectdbiterr, + input injectsbiterr, + input sleep, + + output [C_DOUT_WIDTH-1:0] dout, + output full, + output almost_full, + output wr_ack, + output overflow, + output empty, + output almost_empty, + output valid, + output underflow, + output [C_DATA_COUNT_WIDTH-1:0] data_count, + output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count, + output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count, + output prog_full, + output prog_empty, + output sbiterr, + output dbiterr, + output wr_rst_busy, + output rd_rst_busy, + + + // AXI Global Signal + input m_aclk, + input s_aclk, + input s_aresetn, + input s_aclk_en, + input m_aclk_en, + + // AXI Full/Lite Slave Write Channel (write side) + input [C_AXI_ID_WIDTH-1:0] s_axi_awid, + input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr, + input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen, + input [3-1:0] s_axi_awsize, + input [2-1:0] s_axi_awburst, + input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock, + input [4-1:0] s_axi_awcache, + input [3-1:0] s_axi_awprot, + input [4-1:0] s_axi_awqos, + input [4-1:0] s_axi_awregion, + input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser, + input s_axi_awvalid, + output s_axi_awready, + input [C_AXI_ID_WIDTH-1:0] s_axi_wid, + input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata, + input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb, + input s_axi_wlast, + input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser, + input s_axi_wvalid, + output s_axi_wready, + output [C_AXI_ID_WIDTH-1:0] s_axi_bid, + output [2-1:0] s_axi_bresp, + output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser, + output s_axi_bvalid, + input s_axi_bready, + + // AXI Full/Lite Master Write Channel (read side) + output [C_AXI_ID_WIDTH-1:0] m_axi_awid, + output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen, + output [3-1:0] m_axi_awsize, + output [2-1:0] m_axi_awburst, + output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock, + output [4-1:0] m_axi_awcache, + output [3-1:0] m_axi_awprot, + output [4-1:0] m_axi_awqos, + output [4-1:0] m_axi_awregion, + output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + output m_axi_awvalid, + input m_axi_awready, + output [C_AXI_ID_WIDTH-1:0] m_axi_wid, + output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata, + output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, + output m_axi_wlast, + output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser, + output m_axi_wvalid, + input m_axi_wready, + input [C_AXI_ID_WIDTH-1:0] m_axi_bid, + input [2-1:0] m_axi_bresp, + input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser, + input m_axi_bvalid, + output m_axi_bready, + + + // AXI Full/Lite Slave Read Channel (write side) + input [C_AXI_ID_WIDTH-1:0] s_axi_arid, + input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr, + input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen, + input [3-1:0] s_axi_arsize, + input [2-1:0] s_axi_arburst, + input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock, + input [4-1:0] s_axi_arcache, + input [3-1:0] s_axi_arprot, + input [4-1:0] s_axi_arqos, + input [4-1:0] s_axi_arregion, + input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser, + input s_axi_arvalid, + output s_axi_arready, + output [C_AXI_ID_WIDTH-1:0] s_axi_rid, + output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata, + output [2-1:0] s_axi_rresp, + output s_axi_rlast, + output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser, + output s_axi_rvalid, + input s_axi_rready, + + + + // AXI Full/Lite Master Read Channel (read side) + output [C_AXI_ID_WIDTH-1:0] m_axi_arid, + output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen, + output [3-1:0] m_axi_arsize, + output [2-1:0] m_axi_arburst, + output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock, + output [4-1:0] m_axi_arcache, + output [3-1:0] m_axi_arprot, + output [4-1:0] m_axi_arqos, + output [4-1:0] m_axi_arregion, + output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + output m_axi_arvalid, + input m_axi_arready, + input [C_AXI_ID_WIDTH-1:0] m_axi_rid, + input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata, + input [2-1:0] m_axi_rresp, + input m_axi_rlast, + input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser, + input m_axi_rvalid, + output m_axi_rready, + + + // AXI Streaming Slave Signals (Write side) + input s_axis_tvalid, + output s_axis_tready, + input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata, + input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb, + input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep, + input s_axis_tlast, + input [C_AXIS_TID_WIDTH-1:0] s_axis_tid, + input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest, + input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser, + + // AXI Streaming Master Signals (Read side) + output m_axis_tvalid, + input m_axis_tready, + output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata, + output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb, + output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep, + output m_axis_tlast, + output [C_AXIS_TID_WIDTH-1:0] m_axis_tid, + output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest, + output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser, + + + + + // AXI Full/Lite Write Address Channel signals + input axi_aw_injectsbiterr, + input axi_aw_injectdbiterr, + input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh, + input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count, + output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count, + output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count, + output axi_aw_sbiterr, + output axi_aw_dbiterr, + output axi_aw_overflow, + output axi_aw_underflow, + output axi_aw_prog_full, + output axi_aw_prog_empty, + + + // AXI Full/Lite Write Data Channel signals + input axi_w_injectsbiterr, + input axi_w_injectdbiterr, + input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh, + input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count, + output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count, + output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count, + output axi_w_sbiterr, + output axi_w_dbiterr, + output axi_w_overflow, + output axi_w_underflow, + output axi_w_prog_full, + output axi_w_prog_empty, + + + // AXI Full/Lite Write Response Channel signals + input axi_b_injectsbiterr, + input axi_b_injectdbiterr, + input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh, + input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count, + output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count, + output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count, + output axi_b_sbiterr, + output axi_b_dbiterr, + output axi_b_overflow, + output axi_b_underflow, + output axi_b_prog_full, + output axi_b_prog_empty, + + + + // AXI Full/Lite Read Address Channel signals + input axi_ar_injectsbiterr, + input axi_ar_injectdbiterr, + input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh, + input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count, + output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count, + output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count, + output axi_ar_sbiterr, + output axi_ar_dbiterr, + output axi_ar_overflow, + output axi_ar_underflow, + output axi_ar_prog_full, + output axi_ar_prog_empty, + + + // AXI Full/Lite Read Data Channel Signals + input axi_r_injectsbiterr, + input axi_r_injectdbiterr, + input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh, + input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count, + output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count, + output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count, + output axi_r_sbiterr, + output axi_r_dbiterr, + output axi_r_overflow, + output axi_r_underflow, + output axi_r_prog_full, + output axi_r_prog_empty, + + + // AXI Streaming FIFO Related Signals + input axis_injectsbiterr, + input axis_injectdbiterr, + input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh, + input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh, + output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count, + output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count, + output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count, + output axis_sbiterr, + output axis_dbiterr, + output axis_overflow, + output axis_underflow, + output axis_prog_full, + output axis_prog_empty + + ); + + wire BACKUP; + wire BACKUP_MARKER; + wire CLK; + wire RST; + wire SRST; + wire WR_CLK; + wire WR_RST; + wire RD_CLK; + wire RD_RST; + wire [C_DIN_WIDTH-1:0] DIN; + wire WR_EN; + wire RD_EN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire INT_CLK; + wire INJECTDBITERR; + wire INJECTSBITERR; + wire SLEEP; + wire [C_DOUT_WIDTH-1:0] DOUT; + wire FULL; + wire ALMOST_FULL; + wire WR_ACK; + wire OVERFLOW; + wire EMPTY; + wire ALMOST_EMPTY; + wire VALID; + wire UNDERFLOW; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT; + wire PROG_FULL; + wire PROG_EMPTY; + wire SBITERR; + wire DBITERR; + wire WR_RST_BUSY; + wire RD_RST_BUSY; + wire M_ACLK; + wire S_ACLK; + wire S_ARESETN; + wire S_ACLK_EN; + wire M_ACLK_EN; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID; + wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR; + wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN; + wire [3-1:0] S_AXI_AWSIZE; + wire [2-1:0] S_AXI_AWBURST; + wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK; + wire [4-1:0] S_AXI_AWCACHE; + wire [3-1:0] S_AXI_AWPROT; + wire [4-1:0] S_AXI_AWQOS; + wire [4-1:0] S_AXI_AWREGION; + wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER; + wire S_AXI_AWVALID; + wire S_AXI_AWREADY; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID; + wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA; + wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB; + wire S_AXI_WLAST; + wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER; + wire S_AXI_WVALID; + wire S_AXI_WREADY; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID; + wire [2-1:0] S_AXI_BRESP; + wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER; + wire S_AXI_BVALID; + wire S_AXI_BREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID; + wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR; + wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN; + wire [3-1:0] M_AXI_AWSIZE; + wire [2-1:0] M_AXI_AWBURST; + wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK; + wire [4-1:0] M_AXI_AWCACHE; + wire [3-1:0] M_AXI_AWPROT; + wire [4-1:0] M_AXI_AWQOS; + wire [4-1:0] M_AXI_AWREGION; + wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER; + wire M_AXI_AWVALID; + wire M_AXI_AWREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID; + wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA; + wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB; + wire M_AXI_WLAST; + wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER; + wire M_AXI_WVALID; + wire M_AXI_WREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID; + wire [2-1:0] M_AXI_BRESP; + wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER; + wire M_AXI_BVALID; + wire M_AXI_BREADY; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID; + wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR; + wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN; + wire [3-1:0] S_AXI_ARSIZE; + wire [2-1:0] S_AXI_ARBURST; + wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK; + wire [4-1:0] S_AXI_ARCACHE; + wire [3-1:0] S_AXI_ARPROT; + wire [4-1:0] S_AXI_ARQOS; + wire [4-1:0] S_AXI_ARREGION; + wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER; + wire S_AXI_ARVALID; + wire S_AXI_ARREADY; + wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID; + wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA; + wire [2-1:0] S_AXI_RRESP; + wire S_AXI_RLAST; + wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER; + wire S_AXI_RVALID; + wire S_AXI_RREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID; + wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR; + wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN; + wire [3-1:0] M_AXI_ARSIZE; + wire [2-1:0] M_AXI_ARBURST; + wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK; + wire [4-1:0] M_AXI_ARCACHE; + wire [3-1:0] M_AXI_ARPROT; + wire [4-1:0] M_AXI_ARQOS; + wire [4-1:0] M_AXI_ARREGION; + wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER; + wire M_AXI_ARVALID; + wire M_AXI_ARREADY; + wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID; + wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA; + wire [2-1:0] M_AXI_RRESP; + wire M_AXI_RLAST; + wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER; + wire M_AXI_RVALID; + wire M_AXI_RREADY; + wire S_AXIS_TVALID; + wire S_AXIS_TREADY; + wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA; + wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB; + wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP; + wire S_AXIS_TLAST; + wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID; + wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST; + wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER; + wire M_AXIS_TVALID; + wire M_AXIS_TREADY; + wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA; + wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB; + wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP; + wire M_AXIS_TLAST; + wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID; + wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST; + wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER; + wire AXI_AW_INJECTSBITERR; + wire AXI_AW_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT; + wire AXI_AW_SBITERR; + wire AXI_AW_DBITERR; + wire AXI_AW_OVERFLOW; + wire AXI_AW_UNDERFLOW; + wire AXI_AW_PROG_FULL; + wire AXI_AW_PROG_EMPTY; + wire AXI_W_INJECTSBITERR; + wire AXI_W_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT; + wire AXI_W_SBITERR; + wire AXI_W_DBITERR; + wire AXI_W_OVERFLOW; + wire AXI_W_UNDERFLOW; + wire AXI_W_PROG_FULL; + wire AXI_W_PROG_EMPTY; + wire AXI_B_INJECTSBITERR; + wire AXI_B_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT; + wire AXI_B_SBITERR; + wire AXI_B_DBITERR; + wire AXI_B_OVERFLOW; + wire AXI_B_UNDERFLOW; + wire AXI_B_PROG_FULL; + wire AXI_B_PROG_EMPTY; + wire AXI_AR_INJECTSBITERR; + wire AXI_AR_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT; + wire AXI_AR_SBITERR; + wire AXI_AR_DBITERR; + wire AXI_AR_OVERFLOW; + wire AXI_AR_UNDERFLOW; + wire AXI_AR_PROG_FULL; + wire AXI_AR_PROG_EMPTY; + wire AXI_R_INJECTSBITERR; + wire AXI_R_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT; + wire AXI_R_SBITERR; + wire AXI_R_DBITERR; + wire AXI_R_OVERFLOW; + wire AXI_R_UNDERFLOW; + wire AXI_R_PROG_FULL; + wire AXI_R_PROG_EMPTY; + wire AXIS_INJECTSBITERR; + wire AXIS_INJECTDBITERR; + wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH; + wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT; + wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT; + wire AXIS_SBITERR; + wire AXIS_DBITERR; + wire AXIS_OVERFLOW; + wire AXIS_UNDERFLOW; + wire AXIS_PROG_FULL; + wire AXIS_PROG_EMPTY; + wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in; + wire wr_rst_int; + wire rd_rst_int; + wire wr_rst_busy_o; + wire wr_rst_busy_ntve; + wire wr_rst_busy_axis; + wire wr_rst_busy_wach; + wire wr_rst_busy_wdch; + wire wr_rst_busy_wrch; + wire wr_rst_busy_rach; + wire wr_rst_busy_rdch; + + + + function integer find_log2; + input integer int_val; + integer i,j; + begin + i = 1; + j = 0; + for (i = 1; i < int_val; i = i*2) begin + j = j + 1; + end + find_log2 = j; + end + endfunction + + + + + // Conventional FIFO Interface Signals + assign BACKUP = backup; + assign BACKUP_MARKER = backup_marker; + assign CLK = clk; + assign RST = rst; + assign SRST = srst; + assign WR_CLK = wr_clk; + assign WR_RST = wr_rst; + assign RD_CLK = rd_clk; + assign RD_RST = rd_rst; + assign WR_EN = wr_en; + assign RD_EN = rd_en; + assign INT_CLK = int_clk; + assign INJECTDBITERR = injectdbiterr; + assign INJECTSBITERR = injectsbiterr; + assign SLEEP = sleep; + assign full = FULL; + assign almost_full = ALMOST_FULL; + assign wr_ack = WR_ACK; + assign overflow = OVERFLOW; + assign empty = EMPTY; + assign almost_empty = ALMOST_EMPTY; + assign valid = VALID; + assign underflow = UNDERFLOW; + assign prog_full = PROG_FULL; + assign prog_empty = PROG_EMPTY; + assign sbiterr = SBITERR; + assign dbiterr = DBITERR; +// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o; + assign wr_rst_busy = wr_rst_busy_o; + assign rd_rst_busy = RD_RST_BUSY; + assign M_ACLK = m_aclk; + assign S_ACLK = s_aclk; + assign S_ARESETN = s_aresetn; + assign S_ACLK_EN = s_aclk_en; + assign M_ACLK_EN = m_aclk_en; + assign S_AXI_AWVALID = s_axi_awvalid; + assign s_axi_awready = S_AXI_AWREADY; + assign S_AXI_WLAST = s_axi_wlast; + assign S_AXI_WVALID = s_axi_wvalid; + assign s_axi_wready = S_AXI_WREADY; + assign s_axi_bvalid = S_AXI_BVALID; + assign S_AXI_BREADY = s_axi_bready; + assign m_axi_awvalid = M_AXI_AWVALID; + assign M_AXI_AWREADY = m_axi_awready; + assign m_axi_wlast = M_AXI_WLAST; + assign m_axi_wvalid = M_AXI_WVALID; + assign M_AXI_WREADY = m_axi_wready; + assign M_AXI_BVALID = m_axi_bvalid; + assign m_axi_bready = M_AXI_BREADY; + assign S_AXI_ARVALID = s_axi_arvalid; + assign s_axi_arready = S_AXI_ARREADY; + assign s_axi_rlast = S_AXI_RLAST; + assign s_axi_rvalid = S_AXI_RVALID; + assign S_AXI_RREADY = s_axi_rready; + assign m_axi_arvalid = M_AXI_ARVALID; + assign M_AXI_ARREADY = m_axi_arready; + assign M_AXI_RLAST = m_axi_rlast; + assign M_AXI_RVALID = m_axi_rvalid; + assign m_axi_rready = M_AXI_RREADY; + assign S_AXIS_TVALID = s_axis_tvalid; + assign s_axis_tready = S_AXIS_TREADY; + assign S_AXIS_TLAST = s_axis_tlast; + assign m_axis_tvalid = M_AXIS_TVALID; + assign M_AXIS_TREADY = m_axis_tready; + assign m_axis_tlast = M_AXIS_TLAST; + assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr; + assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr; + assign axi_aw_sbiterr = AXI_AW_SBITERR; + assign axi_aw_dbiterr = AXI_AW_DBITERR; + assign axi_aw_overflow = AXI_AW_OVERFLOW; + assign axi_aw_underflow = AXI_AW_UNDERFLOW; + assign axi_aw_prog_full = AXI_AW_PROG_FULL; + assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY; + assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr; + assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr; + assign axi_w_sbiterr = AXI_W_SBITERR; + assign axi_w_dbiterr = AXI_W_DBITERR; + assign axi_w_overflow = AXI_W_OVERFLOW; + assign axi_w_underflow = AXI_W_UNDERFLOW; + assign axi_w_prog_full = AXI_W_PROG_FULL; + assign axi_w_prog_empty = AXI_W_PROG_EMPTY; + assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr; + assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr; + assign axi_b_sbiterr = AXI_B_SBITERR; + assign axi_b_dbiterr = AXI_B_DBITERR; + assign axi_b_overflow = AXI_B_OVERFLOW; + assign axi_b_underflow = AXI_B_UNDERFLOW; + assign axi_b_prog_full = AXI_B_PROG_FULL; + assign axi_b_prog_empty = AXI_B_PROG_EMPTY; + assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr; + assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr; + assign axi_ar_sbiterr = AXI_AR_SBITERR; + assign axi_ar_dbiterr = AXI_AR_DBITERR; + assign axi_ar_overflow = AXI_AR_OVERFLOW; + assign axi_ar_underflow = AXI_AR_UNDERFLOW; + assign axi_ar_prog_full = AXI_AR_PROG_FULL; + assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY; + assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr; + assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr; + assign axi_r_sbiterr = AXI_R_SBITERR; + assign axi_r_dbiterr = AXI_R_DBITERR; + assign axi_r_overflow = AXI_R_OVERFLOW; + assign axi_r_underflow = AXI_R_UNDERFLOW; + assign axi_r_prog_full = AXI_R_PROG_FULL; + assign axi_r_prog_empty = AXI_R_PROG_EMPTY; + assign AXIS_INJECTSBITERR = axis_injectsbiterr; + assign AXIS_INJECTDBITERR = axis_injectdbiterr; + assign axis_sbiterr = AXIS_SBITERR; + assign axis_dbiterr = AXIS_DBITERR; + assign axis_overflow = AXIS_OVERFLOW; + assign axis_underflow = AXIS_UNDERFLOW; + assign axis_prog_full = AXIS_PROG_FULL; + assign axis_prog_empty = AXIS_PROG_EMPTY; + + + assign DIN = din; + assign PROG_EMPTY_THRESH = prog_empty_thresh; + assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert; + assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate; + assign PROG_FULL_THRESH = prog_full_thresh; + assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert; + assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate; + assign dout = DOUT; + assign data_count = DATA_COUNT; + assign rd_data_count = RD_DATA_COUNT; + assign wr_data_count = WR_DATA_COUNT; + assign S_AXI_AWID = s_axi_awid; + assign S_AXI_AWADDR = s_axi_awaddr; + assign S_AXI_AWLEN = s_axi_awlen; + assign S_AXI_AWSIZE = s_axi_awsize; + assign S_AXI_AWBURST = s_axi_awburst; + assign S_AXI_AWLOCK = s_axi_awlock; + assign S_AXI_AWCACHE = s_axi_awcache; + assign S_AXI_AWPROT = s_axi_awprot; + assign S_AXI_AWQOS = s_axi_awqos; + assign S_AXI_AWREGION = s_axi_awregion; + assign S_AXI_AWUSER = s_axi_awuser; + assign S_AXI_WID = s_axi_wid; + assign S_AXI_WDATA = s_axi_wdata; + assign S_AXI_WSTRB = s_axi_wstrb; + assign S_AXI_WUSER = s_axi_wuser; + assign s_axi_bid = S_AXI_BID; + assign s_axi_bresp = S_AXI_BRESP; + assign s_axi_buser = S_AXI_BUSER; + assign m_axi_awid = M_AXI_AWID; + assign m_axi_awaddr = M_AXI_AWADDR; + assign m_axi_awlen = M_AXI_AWLEN; + assign m_axi_awsize = M_AXI_AWSIZE; + assign m_axi_awburst = M_AXI_AWBURST; + assign m_axi_awlock = M_AXI_AWLOCK; + assign m_axi_awcache = M_AXI_AWCACHE; + assign m_axi_awprot = M_AXI_AWPROT; + assign m_axi_awqos = M_AXI_AWQOS; + assign m_axi_awregion = M_AXI_AWREGION; + assign m_axi_awuser = M_AXI_AWUSER; + assign m_axi_wid = M_AXI_WID; + assign m_axi_wdata = M_AXI_WDATA; + assign m_axi_wstrb = M_AXI_WSTRB; + assign m_axi_wuser = M_AXI_WUSER; + assign M_AXI_BID = m_axi_bid; + assign M_AXI_BRESP = m_axi_bresp; + assign M_AXI_BUSER = m_axi_buser; + assign S_AXI_ARID = s_axi_arid; + assign S_AXI_ARADDR = s_axi_araddr; + assign S_AXI_ARLEN = s_axi_arlen; + assign S_AXI_ARSIZE = s_axi_arsize; + assign S_AXI_ARBURST = s_axi_arburst; + assign S_AXI_ARLOCK = s_axi_arlock; + assign S_AXI_ARCACHE = s_axi_arcache; + assign S_AXI_ARPROT = s_axi_arprot; + assign S_AXI_ARQOS = s_axi_arqos; + assign S_AXI_ARREGION = s_axi_arregion; + assign S_AXI_ARUSER = s_axi_aruser; + assign s_axi_rid = S_AXI_RID; + assign s_axi_rdata = S_AXI_RDATA; + assign s_axi_rresp = S_AXI_RRESP; + assign s_axi_ruser = S_AXI_RUSER; + assign m_axi_arid = M_AXI_ARID; + assign m_axi_araddr = M_AXI_ARADDR; + assign m_axi_arlen = M_AXI_ARLEN; + assign m_axi_arsize = M_AXI_ARSIZE; + assign m_axi_arburst = M_AXI_ARBURST; + assign m_axi_arlock = M_AXI_ARLOCK; + assign m_axi_arcache = M_AXI_ARCACHE; + assign m_axi_arprot = M_AXI_ARPROT; + assign m_axi_arqos = M_AXI_ARQOS; + assign m_axi_arregion = M_AXI_ARREGION; + assign m_axi_aruser = M_AXI_ARUSER; + assign M_AXI_RID = m_axi_rid; + assign M_AXI_RDATA = m_axi_rdata; + assign M_AXI_RRESP = m_axi_rresp; + assign M_AXI_RUSER = m_axi_ruser; + assign S_AXIS_TDATA = s_axis_tdata; + assign S_AXIS_TSTRB = s_axis_tstrb; + assign S_AXIS_TKEEP = s_axis_tkeep; + assign S_AXIS_TID = s_axis_tid; + assign S_AXIS_TDEST = s_axis_tdest; + assign S_AXIS_TUSER = s_axis_tuser; + assign m_axis_tdata = M_AXIS_TDATA; + assign m_axis_tstrb = M_AXIS_TSTRB; + assign m_axis_tkeep = M_AXIS_TKEEP; + assign m_axis_tid = M_AXIS_TID; + assign m_axis_tdest = M_AXIS_TDEST; + assign m_axis_tuser = M_AXIS_TUSER; + assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh; + assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh; + assign axi_aw_data_count = AXI_AW_DATA_COUNT; + assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT; + assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT; + assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh; + assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh; + assign axi_w_data_count = AXI_W_DATA_COUNT; + assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT; + assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT; + assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh; + assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh; + assign axi_b_data_count = AXI_B_DATA_COUNT; + assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT; + assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT; + assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh; + assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh; + assign axi_ar_data_count = AXI_AR_DATA_COUNT; + assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT; + assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT; + assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh; + assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh; + assign axi_r_data_count = AXI_R_DATA_COUNT; + assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT; + assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT; + assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh; + assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh; + assign axis_data_count = AXIS_DATA_COUNT; + assign axis_wr_data_count = AXIS_WR_DATA_COUNT; + assign axis_rd_data_count = AXIS_RD_DATA_COUNT; + + + generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo + + fifo_generator_v13_2_4_CONV_VER + #( + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_FAMILY (C_FAMILY), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RD_RST (C_HAS_RD_RST), + .C_HAS_RST (C_HAS_RST), + .C_HAS_SRST (C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_HAS_WR_RST (C_HAS_WR_RST), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_FREQ (C_RD_FREQ), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_ECC (C_USE_ECC), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE), + .C_AXI_TYPE (C_AXI_TYPE), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE) + ) + fifo_generator_v13_2_4_conv_dut + ( + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .CLK (CLK), + .RST (RST), + .SRST (SRST), + .WR_CLK (WR_CLK), + .WR_RST (WR_RST), + .RD_CLK (RD_CLK), + .RD_RST (RD_RST), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INT_CLK (INT_CLK), + .INJECTDBITERR (INJECTDBITERR), + .INJECTSBITERR (INJECTSBITERR), + + .DOUT (DOUT), + .FULL (FULL), + .ALMOST_FULL (ALMOST_FULL), + .WR_ACK (WR_ACK), + .OVERFLOW (OVERFLOW), + .EMPTY (EMPTY), + .ALMOST_EMPTY (ALMOST_EMPTY), + .VALID (VALID), + .UNDERFLOW (UNDERFLOW), + .DATA_COUNT (DATA_COUNT), + .RD_DATA_COUNT (RD_DATA_COUNT), + .WR_DATA_COUNT (wr_data_count_in), + .PROG_FULL (PROG_FULL), + .PROG_EMPTY (PROG_EMPTY), + .SBITERR (SBITERR), + .DBITERR (DBITERR), + .wr_rst_busy_o (wr_rst_busy_o), + .wr_rst_busy (wr_rst_busy_i), + .rd_rst_busy (rd_rst_busy), + .wr_rst_i_out (wr_rst_int), + .rd_rst_i_out (rd_rst_int) + ); + end endgenerate + + + + localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0; + localparam C_AXI_SIZE_WIDTH = 3; + localparam C_AXI_BURST_WIDTH = 2; + localparam C_AXI_CACHE_WIDTH = 4; + localparam C_AXI_PROT_WIDTH = 3; + localparam C_AXI_QOS_WIDTH = 4; + localparam C_AXI_REGION_WIDTH = 4; + localparam C_AXI_BRESP_WIDTH = 2; + localparam C_AXI_RRESP_WIDTH = 2; + + localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0; + localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS; + localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET; + localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET; + localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET; + localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET; + localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET; + localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS); + localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH); + + + function [LOG_DEPTH_AXIS-1:0] bin2gray; + input [LOG_DEPTH_AXIS-1:0] x; + begin + bin2gray = x ^ (x>>1); + end + endfunction + + function [LOG_DEPTH_AXIS-1:0] gray2bin; + input [LOG_DEPTH_AXIS-1:0] x; + integer i; + begin + gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1]; + for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin + gray2bin[i] = gray2bin[i+1] ^ x[i]; + end + end + endfunction + +wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last; +wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ; +wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ; +reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0; +reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0; +reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0; +reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0; +wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad; +wire [LOG_WR_DEPTH : 0] r_inv_pad; +wire [LOG_WR_DEPTH-1 : 0] d_cnt; +reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0; +reg adj_w_cnt_rd_pad_0 = 0; +reg r_inv_pad_0 = 0; + + + genvar l; + + generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage + fifo_generator_v13_2_4_sync_stage + #( + .C_WIDTH (LOG_WR_DEPTH) + ) + rd_stg_inst + ( + .RST (rd_rst_int), + .CLK (RD_CLK), + .DIN (w_q[l-1]), + .DOUT (w_q[l]) + ); + end endgenerate // gpkt_cnt_sync_stage + + + + generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter + assign wr_eop_ad = WR_EN & !(FULL); + assign rd_eop_ad = RD_EN & !(EMPTY); + + + always @ (posedge wr_rst_int or posedge WR_CLK) + begin + if (wr_rst_int) + w_cnt <= 1'b0; + else if (wr_eop_ad) + w_cnt <= w_cnt + 1; + end + + always @ (posedge wr_rst_int or posedge WR_CLK) + begin + if (wr_rst_int) + w_cnt_gc <= 1'b0; + else + w_cnt_gc <= bin2gray(w_cnt); + end + + + assign w_q[0] = w_cnt_gc; + assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE]; + + + + always @ (posedge rd_rst_int or posedge RD_CLK) + begin + if (rd_rst_int) + w_cnt_rd <= 1'b0; + else + w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last); + end + + always @ (posedge rd_rst_int or posedge RD_CLK) + begin + if (rd_rst_int) + r_cnt <= 1'b0; + else if (rd_eop_ad) + r_cnt <= r_cnt + 1; + end + + + // Take the difference of write and read packet count + // Logic is similar to rd_pe_as + assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd; + assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt; + assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0; + assign r_inv_pad[0] = r_inv_pad_0; + + + always @ ( rd_eop_ad ) + begin + if (!rd_eop_ad) begin + adj_w_cnt_rd_pad_0 <= 1'b1; + r_inv_pad_0 <= 1'b1; + end else begin + adj_w_cnt_rd_pad_0 <= 1'b0; + r_inv_pad_0 <= 1'b0; + end + end + + always @ (posedge rd_rst_int or posedge RD_CLK) + begin + if (rd_rst_int) + d_cnt_pad <= 1'b0; + else + d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ; + end + + assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ; + assign WR_DATA_COUNT = d_cnt; + + end endgenerate // fifo_ic_adapter + + generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter + assign WR_DATA_COUNT = wr_data_count_in; + + end endgenerate // fifo_icn_adapter + + + + wire inverted_reset = ~S_ARESETN; + wire axi_rs_rst; + wire [C_DIN_WIDTH_AXIS-1:0] axis_din ; + wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ; + wire axis_full ; + wire axis_almost_full ; + wire axis_empty ; + wire axis_s_axis_tready; + wire axis_m_axis_tvalid; + wire axis_wr_en ; + wire axis_rd_en ; + wire axis_we ; + wire axis_re ; + wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc; + reg axis_pkt_read = 1'b0; + wire axis_rd_rst; + wire axis_wr_rst; + + generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 || + C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst + reg rst_d1 = 0 ; + reg rst_d2 = 0 ; + reg [3:0] axi_rst = 4'h0 ; + always @ (posedge inverted_reset or posedge S_ACLK) begin + if (inverted_reset) begin + rst_d1 <= 1'b1; + rst_d2 <= 1'b1; + axi_rst <= 4'hf; + end else begin + rst_d1 <= #`TCQ 1'b0; + rst_d2 <= #`TCQ rst_d1; + axi_rst <= #`TCQ {axi_rst[2:0],1'b0}; + end + end + + assign axi_rs_rst = axi_rst[3];//rst_d2; + end endgenerate // gaxi_rs_rst + + generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming + + // Write protection when almost full or prog_full is high + assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID : + (C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID; + + // Read protection when almost empty or prog_empty is high + assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY : + (C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY; + assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we; + assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re; + + fifo_generator_v13_2_4_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_AXIS), + .C_WR_DEPTH (C_WR_DEPTH_AXIS), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS), + .C_DOUT_WIDTH (C_DIN_WIDTH_AXIS), + .C_RD_DEPTH (C_WR_DEPTH_AXIS), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS), + .C_USE_ECC (C_USE_ECC_AXIS), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_4_axis_dut + ( + .CLK (S_ACLK), + .WR_CLK (S_ACLK), + .RD_CLK (M_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (axis_wr_en), + .RD_EN (axis_rd_en), + .PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), + .PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}), + .INJECTDBITERR (AXIS_INJECTDBITERR), + .INJECTSBITERR (AXIS_INJECTSBITERR), + + .DIN (axis_din), + .DOUT (axis_dout), + .FULL (axis_full), + .EMPTY (axis_empty), + .ALMOST_FULL (axis_almost_full), + .PROG_FULL (AXIS_PROG_FULL), + .ALMOST_EMPTY (), + .PROG_EMPTY (AXIS_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (AXIS_OVERFLOW), + .VALID (), + .UNDERFLOW (AXIS_UNDERFLOW), + .DATA_COUNT (axis_dc), + .RD_DATA_COUNT (AXIS_RD_DATA_COUNT), + .WR_DATA_COUNT (AXIS_WR_DATA_COUNT), + .SBITERR (AXIS_SBITERR), + .DBITERR (AXIS_DBITERR), + .wr_rst_busy (wr_rst_busy_axis), + .rd_rst_busy (rd_rst_busy_axis), + .wr_rst_i_out (axis_wr_rst), + .rd_rst_i_out (axis_rd_rst), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full; + assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read; + assign S_AXIS_TREADY = axis_s_axis_tready; + assign M_AXIS_TVALID = axis_m_axis_tvalid; + + end endgenerate // axi_streaming + + wire axis_wr_eop; + reg axis_wr_eop_d1 = 1'b0; + wire axis_rd_eop; + integer axis_pkt_cnt; + + generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc + assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST; + assign axis_rd_eop = axis_rd_en & axis_dout[0]; + + always @ (posedge inverted_reset or posedge S_ACLK) + begin + if (inverted_reset) + axis_pkt_read <= 1'b0; + else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1) + axis_pkt_read <= 1'b0; + else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty)) + axis_pkt_read <= 1'b1; + end + + always @ (posedge inverted_reset or posedge S_ACLK) + begin + if (inverted_reset) + axis_wr_eop_d1 <= 1'b0; + else + axis_wr_eop_d1 <= axis_wr_eop; + end + + always @ (posedge inverted_reset or posedge S_ACLK) + begin + if (inverted_reset) + axis_pkt_cnt <= 0; + else if (axis_wr_eop_d1 && ~axis_rd_eop) + axis_pkt_cnt <= axis_pkt_cnt + 1; + else if (axis_rd_eop && ~axis_wr_eop_d1) + axis_pkt_cnt <= axis_pkt_cnt - 1; + end + end endgenerate // gaxis_pkt_fifo_cc + + +reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0; +wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last; +wire axis_rd_has_rst; +wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ; +wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ; +wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0; +wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ; +reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0; +reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0; +reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0; +wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad; +wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad; +wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt; +reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0; +reg adj_axis_wpkt_cnt_rd_pad_0 = 0; +reg rpkt_inv_pad_0 = 0; +wire axis_af_rd ; + +generate if (C_HAS_RST == 1) begin : rst_blk_has + assign axis_rd_has_rst = axis_rd_rst; +end endgenerate //rst_blk_has + +generate if (C_HAS_RST == 0) begin :rst_blk_no + assign axis_rd_has_rst = 1'b0; +end endgenerate //rst_blk_no + + genvar i; + + generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage + fifo_generator_v13_2_4_sync_stage + #( + .C_WIDTH (LOG_DEPTH_AXIS) + ) + rd_stg_inst + ( + .RST (axis_rd_has_rst), + .CLK (M_ACLK), + .DIN (wpkt_q[i-1]), + .DOUT (wpkt_q[i]) + ); + + fifo_generator_v13_2_4_sync_stage + #( + .C_WIDTH (1) + ) + wr_stg_inst + ( + .RST (axis_rd_has_rst), + .CLK (M_ACLK), + .DIN (axis_af_q[i-1]), + .DOUT (axis_af_q[i]) + ); + end endgenerate // gpkt_cnt_sync_stage + + + generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic + assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST; + assign axis_rd_eop = axis_rd_en & axis_dout[0]; + + always @ (posedge axis_rd_has_rst or posedge M_ACLK) + begin + if (axis_rd_has_rst) + axis_pkt_read <= 1'b0; + else if (axis_rd_eop && (diff_pkt_cnt == 1)) + axis_pkt_read <= 1'b0; + else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty)) + axis_pkt_read <= 1'b1; + end + + always @ (posedge axis_wr_rst or posedge S_ACLK) + begin + if (axis_wr_rst) + axis_wpkt_cnt <= 1'b0; + else if (axis_wr_eop) + axis_wpkt_cnt <= axis_wpkt_cnt + 1; + end + + always @ (posedge axis_wr_rst or posedge S_ACLK) + begin + if (axis_wr_rst) + axis_wpkt_cnt_gc <= 1'b0; + else + axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt); + end + + + assign wpkt_q[0] = axis_wpkt_cnt_gc; + assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE]; + assign axis_af_q[0] = axis_almost_full; + //assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE]; + assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE]; + + + + always @ (posedge axis_rd_has_rst or posedge M_ACLK) + begin + if (axis_rd_has_rst) + axis_wpkt_cnt_rd <= 1'b0; + else + axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last); + end + + always @ (posedge axis_rd_rst or posedge M_ACLK) + begin + if (axis_rd_has_rst) + axis_rpkt_cnt <= 1'b0; + else if (axis_rd_eop) + axis_rpkt_cnt <= axis_rpkt_cnt + 1; + end + + + // Take the difference of write and read packet count + // Logic is similar to rd_pe_as + assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd; + assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt; + assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0; + assign rpkt_inv_pad[0] = rpkt_inv_pad_0; + + + always @ ( axis_rd_eop ) + begin + if (!axis_rd_eop) begin + adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1; + rpkt_inv_pad_0 <= 1'b1; + end else begin + adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0; + rpkt_inv_pad_0 <= 1'b0; + end + end + + always @ (posedge axis_rd_rst or posedge M_ACLK) + begin + if (axis_rd_has_rst) + diff_pkt_cnt_pad <= 1'b0; + else + diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ; + end + + assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ; + + + + + + end endgenerate // gaxis_pkt_fifo_ic + + + + + // Generate the accurate data count for axi stream packet fifo configuration + reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0; + generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt + always @ (posedge inverted_reset or posedge S_ACLK) + begin + if (inverted_reset) + axis_dc_pkt_fifo <= 0; + else if (axis_wr_en && (~axis_rd_en)) + axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1; + else if (~axis_wr_en && axis_rd_en) + axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1; + end + assign AXIS_DATA_COUNT = axis_dc_pkt_fifo; + end endgenerate // gdc_pkt + + generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt + assign AXIS_DATA_COUNT = 0; + end endgenerate // gndc_pkt + + generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc + assign AXIS_DATA_COUNT = axis_dc; + end endgenerate // gdc + + // Register Slice for Write Address Channel + generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice + assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID; + assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY; + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_AXIS), + .C_REG_CONFIG (C_REG_SLICE_MODE_AXIS) + ) + axis_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (axis_din), + .S_VALID (axis_wr_en), + .S_READY (S_AXIS_TREADY), + + // Master side + .M_PAYLOAD_DATA (axis_dout), + .M_VALID (M_AXIS_TVALID), + .M_READY (axis_rd_en) + ); + end endgenerate // gaxis_reg_slice + + + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata + assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA; + assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb + assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB; + assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep + assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP; + assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid + assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID; + assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest + assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST; + assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser + assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER; + assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET]; + end endgenerate + + generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast + assign axis_din[0] = S_AXIS_TLAST; + assign M_AXIS_TLAST = axis_dout[0]; + end endgenerate + + //########################################################################### + // AXI FULL Write Channel (axi_write_channel) + //########################################################################### + + localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0; + localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0; + + localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; + + localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; + localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0; + + localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0; + localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0; + localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0; + localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0; + localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0; + + localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH; + localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH; + localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET; + localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET; + localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET; + localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET; + localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET; + localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH; + localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH; + localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET; + localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET; + + localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH; + localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH; + localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8; + localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET; + + localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH; + localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH; + localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET; + + + wire [C_DIN_WIDTH_WACH-1:0] wach_din ; + wire [C_DIN_WIDTH_WACH-1:0] wach_dout ; + wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ; + wire wach_full ; + wire wach_almost_full ; + wire wach_prog_full ; + wire wach_empty ; + wire wach_almost_empty ; + wire wach_prog_empty ; + wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ; + wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ; + wire wdch_full ; + wire wdch_almost_full ; + wire wdch_prog_full ; + wire wdch_empty ; + wire wdch_almost_empty ; + wire wdch_prog_empty ; + wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ; + wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ; + wire wrch_full ; + wire wrch_almost_full ; + wire wrch_prog_full ; + wire wrch_empty ; + wire wrch_almost_empty ; + wire wrch_prog_empty ; + wire axi_aw_underflow_i; + wire axi_w_underflow_i ; + wire axi_b_underflow_i ; + wire axi_aw_overflow_i ; + wire axi_w_overflow_i ; + wire axi_b_overflow_i ; + wire axi_wr_underflow_i; + wire axi_wr_overflow_i ; + wire wach_s_axi_awready; + wire wach_m_axi_awvalid; + wire wach_wr_en ; + wire wach_rd_en ; + wire wdch_s_axi_wready ; + wire wdch_m_axi_wvalid ; + wire wdch_wr_en ; + wire wdch_rd_en ; + wire wrch_s_axi_bvalid ; + wire wrch_m_axi_bready ; + wire wrch_wr_en ; + wire wrch_rd_en ; + wire txn_count_up ; + wire txn_count_down ; + wire awvalid_en ; + wire awvalid_pkt ; + wire awready_pkt ; + integer wr_pkt_count ; + wire wach_we ; + wire wach_re ; + wire wdch_we ; + wire wdch_re ; + wire wrch_we ; + wire wrch_re ; + + generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel + // Write protection when almost full or prog_full is high + assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID; + + // Read protection when almost empty or prog_empty is high + assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ? + wach_m_axi_awvalid & awready_pkt & awvalid_en : + (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ? + M_AXI_AWREADY && wach_m_axi_awvalid : + (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ? + awready_pkt & awvalid_en : + (C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ? + M_AXI_AWREADY : 1'b0; + assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we; + assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re; + + fifo_generator_v13_2_4_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_WACH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_WR_DEPTH (C_WR_DEPTH_WACH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH), + .C_DOUT_WIDTH (C_DIN_WIDTH_WACH), + .C_RD_DEPTH (C_WR_DEPTH_WACH), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH), + .C_USE_ECC (C_USE_ECC_WACH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0), + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_4_wach_dut + ( + .CLK (S_ACLK), + .WR_CLK (S_ACLK), + .RD_CLK (M_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (wach_wr_en), + .RD_EN (wach_rd_en), + .PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}), + .INJECTDBITERR (AXI_AW_INJECTDBITERR), + .INJECTSBITERR (AXI_AW_INJECTSBITERR), + + .DIN (wach_din), + .DOUT (wach_dout_pkt), + .FULL (wach_full), + .EMPTY (wach_empty), + .ALMOST_FULL (), + .PROG_FULL (AXI_AW_PROG_FULL), + .ALMOST_EMPTY (), + .PROG_EMPTY (AXI_AW_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_aw_overflow_i), + .VALID (), + .UNDERFLOW (axi_aw_underflow_i), + .DATA_COUNT (AXI_AW_DATA_COUNT), + .RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT), + .SBITERR (AXI_AW_SBITERR), + .DBITERR (AXI_AW_DBITERR), + .wr_rst_busy (wr_rst_busy_wach), + .rd_rst_busy (rd_rst_busy_wach), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full; + assign wach_m_axi_awvalid = ~wach_empty; + assign S_AXI_AWREADY = wach_s_axi_awready; + + assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0; + assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0; + + end endgenerate // axi_write_address_channel + + // Register Slice for Write Address Channel + generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_WACH), + .C_REG_CONFIG (C_REG_SLICE_MODE_WACH) + ) + wach_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (wach_din), + .S_VALID (S_AXI_AWVALID), + .S_READY (S_AXI_AWREADY), + + // Master side + .M_PAYLOAD_DATA (wach_dout), + .M_VALID (M_AXI_AWVALID), + .M_READY (M_AXI_AWREADY) + ); + end endgenerate // gwach_reg_slice + + generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_WACH), + .C_REG_CONFIG (1) + ) + wach_pkt_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (wach_dout_pkt), + .S_VALID (awvalid_pkt), + .S_READY (awready_pkt), + + // Master side + .M_PAYLOAD_DATA (wach_dout), + .M_VALID (M_AXI_AWVALID), + .M_READY (M_AXI_AWREADY) + ); + + assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en; + + assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0]; + assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en; + + always@(posedge S_ACLK or posedge inverted_reset) begin + if(inverted_reset == 1) begin + wr_pkt_count <= 0; + end else begin + if(txn_count_up == 1 && txn_count_down == 0) begin + wr_pkt_count <= wr_pkt_count + 1; + end else if(txn_count_up == 0 && txn_count_down == 1) begin + wr_pkt_count <= wr_pkt_count - 1; + end + end + end //Always end + assign awvalid_en = (wr_pkt_count > 0)?1:0; + end endgenerate + + generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr + assign awvalid_en = 1; + assign wach_dout = wach_dout_pkt; + assign M_AXI_AWVALID = wach_m_axi_awvalid; + end + endgenerate + + + + generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel + // Write protection when almost full or prog_full is high + assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID; + + // Read protection when almost empty or prog_empty is high + assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY; + assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we; + assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re; + + + fifo_generator_v13_2_4_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_WDCH), + .C_WR_DEPTH (C_WR_DEPTH_WDCH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH), + .C_DOUT_WIDTH (C_DIN_WIDTH_WDCH), + .C_RD_DEPTH (C_WR_DEPTH_WDCH), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH), + .C_USE_ECC (C_USE_ECC_WDCH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_4_wdch_dut + ( + .CLK (S_ACLK), + .WR_CLK (S_ACLK), + .RD_CLK (M_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (wdch_wr_en), + .RD_EN (wdch_rd_en), + .PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}), + .INJECTDBITERR (AXI_W_INJECTDBITERR), + .INJECTSBITERR (AXI_W_INJECTSBITERR), + + .DIN (wdch_din), + .DOUT (wdch_dout), + .FULL (wdch_full), + .EMPTY (wdch_empty), + .ALMOST_FULL (), + .PROG_FULL (AXI_W_PROG_FULL), + .ALMOST_EMPTY (), + .PROG_EMPTY (AXI_W_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_w_overflow_i), + .VALID (), + .UNDERFLOW (axi_w_underflow_i), + .DATA_COUNT (AXI_W_DATA_COUNT), + .RD_DATA_COUNT (AXI_W_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_W_WR_DATA_COUNT), + .SBITERR (AXI_W_SBITERR), + .DBITERR (AXI_W_DBITERR), + .wr_rst_busy (wr_rst_busy_wdch), + .rd_rst_busy (rd_rst_busy_wdch), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full; + assign wdch_m_axi_wvalid = ~wdch_empty; + assign S_AXI_WREADY = wdch_s_axi_wready; + assign M_AXI_WVALID = wdch_m_axi_wvalid; + + assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0; + assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0; + + end endgenerate // axi_write_data_channel + + // Register Slice for Write Data Channel + generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_WDCH), + .C_REG_CONFIG (C_REG_SLICE_MODE_WDCH) + ) + wdch_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (wdch_din), + .S_VALID (S_AXI_WVALID), + .S_READY (S_AXI_WREADY), + + // Master side + .M_PAYLOAD_DATA (wdch_dout), + .M_VALID (M_AXI_WVALID), + .M_READY (M_AXI_WREADY) + ); + end endgenerate // gwdch_reg_slice + + generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel + // Write protection when almost full or prog_full is high + assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID; + + // Read protection when almost empty or prog_empty is high + assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY; + assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we; + assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re; + + fifo_generator_v13_2_4_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_WRCH), + .C_WR_DEPTH (C_WR_DEPTH_WRCH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH), + .C_DOUT_WIDTH (C_DIN_WIDTH_WRCH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_RD_DEPTH (C_WR_DEPTH_WRCH), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH), + .C_USE_ECC (C_USE_ECC_WRCH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_4_wrch_dut + ( + .CLK (S_ACLK), + .WR_CLK (M_ACLK), + .RD_CLK (S_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (wrch_wr_en), + .RD_EN (wrch_rd_en), + .PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}), + .INJECTDBITERR (AXI_B_INJECTDBITERR), + .INJECTSBITERR (AXI_B_INJECTSBITERR), + + .DIN (wrch_din), + .DOUT (wrch_dout), + .FULL (wrch_full), + .EMPTY (wrch_empty), + .ALMOST_FULL (), + .ALMOST_EMPTY (), + .PROG_FULL (AXI_B_PROG_FULL), + .PROG_EMPTY (AXI_B_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_b_overflow_i), + .VALID (), + .UNDERFLOW (axi_b_underflow_i), + .DATA_COUNT (AXI_B_DATA_COUNT), + .RD_DATA_COUNT (AXI_B_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_B_WR_DATA_COUNT), + .SBITERR (AXI_B_SBITERR), + .DBITERR (AXI_B_DBITERR), + .wr_rst_busy (wr_rst_busy_wrch), + .rd_rst_busy (rd_rst_busy_wrch), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign wrch_s_axi_bvalid = ~wrch_empty; + assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full; + assign S_AXI_BVALID = wrch_s_axi_bvalid; + assign M_AXI_BREADY = wrch_m_axi_bready; + + assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0; + assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0; + end endgenerate // axi_write_resp_channel + + // Register Slice for Write Response Channel + generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_WRCH), + .C_REG_CONFIG (C_REG_SLICE_MODE_WRCH) + ) + wrch_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (wrch_din), + .S_VALID (M_AXI_BVALID), + .S_READY (M_AXI_BREADY), + + // Master side + .M_PAYLOAD_DATA (wrch_dout), + .M_VALID (S_AXI_BVALID), + .M_READY (S_AXI_BREADY) + ); + end endgenerate // gwrch_reg_slice + + + assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0; + assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0; + + generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output + assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET]; + assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET]; + assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET]; + assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET]; + assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET]; + assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET]; + assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET]; + assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET]; + assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR; + assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN; + assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE; + assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST; + assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK; + assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE; + assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT; + assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS; + end endgenerate // axi_wach_output + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion + assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET]; + end endgenerate // axi_awregion + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion + assign M_AXI_AWREGION = 0; + end endgenerate // naxi_awregion + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser + assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET]; + end endgenerate // axi_awuser + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser + assign M_AXI_AWUSER = 0; + end endgenerate // naxi_awuser + + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid + assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET]; + end endgenerate //axi_awid + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid + assign M_AXI_AWID = 0; + end endgenerate //naxi_awid + + generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output + assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET]; + assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET]; + assign M_AXI_WLAST = wdch_dout[0]; + assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA; + assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB; + assign wdch_din[0] = S_AXI_WLAST; + end endgenerate // axi_wdch_output + + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin + assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET]; + end endgenerate + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin + assign M_AXI_WID = 0; + end endgenerate + + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin + assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET]; + end endgenerate + generate if (C_HAS_AXI_WUSER == 0) begin + assign M_AXI_WUSER = 0; + end endgenerate + + generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output + assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET]; + assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP; + end endgenerate // axi_wrch_output + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser + assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET]; + end endgenerate // axi_buser + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser + assign S_AXI_BUSER = 0; + end endgenerate // naxi_buser + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid + assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET]; + end endgenerate // axi_bid + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid + assign S_AXI_BID = 0 ; + end endgenerate // naxi_bid + + + generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1 + assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT}; + assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET]; + assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET]; + end endgenerate // axi_wach_output1 + + generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1 + assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB}; + assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET]; + assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET]; + end endgenerate // axi_wdch_output1 + + generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1 + assign wrch_din = M_AXI_BRESP; + assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET]; + end endgenerate // axi_wrch_output1 + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1 + assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER; + end endgenerate // gwach_din1 + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2 + assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID; + end endgenerate // gwach_din2 + + generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3 + assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION; + end endgenerate // gwach_din3 + + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1 + assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER; + end endgenerate // gwdch_din1 + + generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2 + assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID; + end endgenerate // gwdch_din2 + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1 + assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER; + end endgenerate // gwrch_din1 + + generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2 + assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID; + end endgenerate // gwrch_din2 + + //end of axi_write_channel + + //########################################################################### + // AXI FULL Read Channel (axi_read_channel) + //########################################################################### + wire [C_DIN_WIDTH_RACH-1:0] rach_din ; + wire [C_DIN_WIDTH_RACH-1:0] rach_dout ; + wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ; + wire rach_full ; + wire rach_almost_full ; + wire rach_prog_full ; + wire rach_empty ; + wire rach_almost_empty ; + wire rach_prog_empty ; + wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ; + wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ; + wire rdch_full ; + wire rdch_almost_full ; + wire rdch_prog_full ; + wire rdch_empty ; + wire rdch_almost_empty ; + wire rdch_prog_empty ; + wire axi_ar_underflow_i ; + wire axi_r_underflow_i ; + wire axi_ar_overflow_i ; + wire axi_r_overflow_i ; + wire axi_rd_underflow_i ; + wire axi_rd_overflow_i ; + wire rach_s_axi_arready ; + wire rach_m_axi_arvalid ; + wire rach_wr_en ; + wire rach_rd_en ; + wire rdch_m_axi_rready ; + wire rdch_s_axi_rvalid ; + wire rdch_wr_en ; + wire rdch_rd_en ; + wire arvalid_pkt ; + wire arready_pkt ; + wire arvalid_en ; + wire rdch_rd_ok ; + wire accept_next_pkt ; + integer rdch_free_space ; + integer rdch_commited_space ; + wire rach_we ; + wire rach_re ; + wire rdch_we ; + wire rdch_re ; + + localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH; + localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH; + localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET; + localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET; + localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET; + localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET; + localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET; + localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH; + localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH; + localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET; + localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET; + + localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH; + localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH; + localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH; + localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET; + + + generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel + + // Write protection when almost full or prog_full is high + assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID; + + // Read protection when almost empty or prog_empty is high +// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en; + assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ? + rach_m_axi_arvalid & arready_pkt & arvalid_en : + (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ? + M_AXI_ARREADY && rach_m_axi_arvalid : + (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ? + arready_pkt & arvalid_en : + (C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ? + M_AXI_ARREADY : 1'b0; + assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we; + assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re; + + + fifo_generator_v13_2_4_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_RACH), + .C_WR_DEPTH (C_WR_DEPTH_RACH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_DOUT_WIDTH (C_DIN_WIDTH_RACH), + .C_RD_DEPTH (C_WR_DEPTH_RACH), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH), + .C_USE_ECC (C_USE_ECC_RACH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_4_rach_dut + ( + .CLK (S_ACLK), + .WR_CLK (S_ACLK), + .RD_CLK (M_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (rach_wr_en), + .RD_EN (rach_rd_en), + .PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}), + .INJECTDBITERR (AXI_AR_INJECTDBITERR), + .INJECTSBITERR (AXI_AR_INJECTSBITERR), + + .DIN (rach_din), + .DOUT (rach_dout_pkt), + .FULL (rach_full), + .EMPTY (rach_empty), + .ALMOST_FULL (), + .ALMOST_EMPTY (), + .PROG_FULL (AXI_AR_PROG_FULL), + .PROG_EMPTY (AXI_AR_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_ar_overflow_i), + .VALID (), + .UNDERFLOW (axi_ar_underflow_i), + .DATA_COUNT (AXI_AR_DATA_COUNT), + .RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT), + .SBITERR (AXI_AR_SBITERR), + .DBITERR (AXI_AR_DBITERR), + .wr_rst_busy (wr_rst_busy_rach), + .rd_rst_busy (rd_rst_busy_rach), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full; + assign rach_m_axi_arvalid = ~rach_empty; + assign S_AXI_ARREADY = rach_s_axi_arready; + + assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0; + assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0; + + end endgenerate // axi_read_addr_channel + + // Register Slice for Read Address Channel + generate if (C_RACH_TYPE == 1) begin : grach_reg_slice + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_RACH), + .C_REG_CONFIG (C_REG_SLICE_MODE_RACH) + ) + rach_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (rach_din), + .S_VALID (S_AXI_ARVALID), + .S_READY (S_AXI_ARREADY), + + // Master side + .M_PAYLOAD_DATA (rach_dout), + .M_VALID (M_AXI_ARVALID), + .M_READY (M_AXI_ARREADY) + ); + end endgenerate // grach_reg_slice + + // Register Slice for Read Address Channel for MM Packet FIFO + generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_RACH), + .C_REG_CONFIG (1) + ) + reg_slice_mm_pkt_fifo_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (rach_dout_pkt), + .S_VALID (arvalid_pkt), + .S_READY (arready_pkt), + + // Master side + .M_PAYLOAD_DATA (rach_dout), + .M_VALID (M_AXI_ARVALID), + .M_READY (M_AXI_ARREADY) + ); + end endgenerate // grach_reg_slice_mm_pkt_fifo + + + generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid + assign M_AXI_ARVALID = rach_m_axi_arvalid; + assign rach_dout = rach_dout_pkt; + end endgenerate // grach_m_axi_arvalid + + + generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd + assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en; + assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en; + assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en; + + always@(posedge S_ACLK or posedge inverted_reset) begin + if(inverted_reset) begin + rdch_commited_space <= 0; + end else begin + if(rdch_rd_ok && !accept_next_pkt) begin + rdch_commited_space <= rdch_commited_space-1; + end else if(!rdch_rd_ok && accept_next_pkt) begin + rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1); + end else if(rdch_rd_ok && accept_next_pkt) begin + rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]); + end + end + end //Always end + + always@(*) begin + rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1)); + end + + assign arvalid_en = (rdch_free_space >= 0)?1:0; + end + endgenerate + + generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd + assign arvalid_en = 1; + end + endgenerate + + generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel + + // Write protection when almost full or prog_full is high + assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID; + + // Read protection when almost empty or prog_empty is high + assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY; + assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we; + assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re; + + fifo_generator_v13_2_4_CONV_VER + #( + .C_FAMILY (C_FAMILY), + .C_COMMON_CLOCK (C_COMMON_CLOCK), + .C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : + (C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4), + .C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 : + (C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6), + .C_PRELOAD_REGS (1), // always FWFT for AXI + .C_PRELOAD_LATENCY (0), // always FWFT for AXI + .C_DIN_WIDTH (C_DIN_WIDTH_RDCH), + .C_WR_DEPTH (C_WR_DEPTH_RDCH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH), + .C_DOUT_WIDTH (C_DIN_WIDTH_RDCH), + .C_RD_DEPTH (C_WR_DEPTH_RDCH), + .C_INTERFACE_TYPE (C_INTERFACE_TYPE), + .C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH), + .C_USE_ECC (C_USE_ECC_RDCH), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH), + .C_HAS_ALMOST_EMPTY (0), + .C_HAS_ALMOST_FULL (0), + .C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE), + + .C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + + .C_HAS_WR_RST (0), + .C_HAS_RD_RST (0), + .C_HAS_RST (1), + .C_HAS_SRST (0), + .C_DOUT_RST_VAL (0), + + .C_HAS_VALID (0), + .C_VALID_LOW (C_VALID_LOW), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_HAS_WR_ACK (0), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + + .C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), + .C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), + .C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), + .C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), + .C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true + .C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0), + .C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1), + .C_FULL_FLAGS_RST_VAL (1), + .C_USE_EMBEDDED_REG (0), + .C_USE_DOUT_RST (0), + .C_MSGON_VAL (C_MSGON_VAL), + .C_ENABLE_RST_SYNC (1), + .C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0), + .C_COUNT_TYPE (C_COUNT_TYPE), + .C_DEFAULT_VALUE (C_DEFAULT_VALUE), + .C_ENABLE_RLOCS (C_ENABLE_RLOCS), + .C_HAS_BACKUP (C_HAS_BACKUP), + .C_HAS_INT_CLK (C_HAS_INT_CLK), + .C_MIF_FILE_NAME (C_MIF_FILE_NAME), + .C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE), + .C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL), + .C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE), + .C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE), + .C_RD_FREQ (C_RD_FREQ), + .C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS), + .C_WR_FREQ (C_WR_FREQ), + .C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY) + ) + fifo_generator_v13_2_4_rdch_dut + ( + .CLK (S_ACLK), + .WR_CLK (M_ACLK), + .RD_CLK (S_ACLK), + .RST (inverted_reset), + .SRST (1'b0), + .WR_RST (inverted_reset), + .RD_RST (inverted_reset), + .WR_EN (rdch_wr_en), + .RD_EN (rdch_rd_en), + .PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), + .PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), + .PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), + .PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}), + .INJECTDBITERR (AXI_R_INJECTDBITERR), + .INJECTSBITERR (AXI_R_INJECTSBITERR), + + .DIN (rdch_din), + .DOUT (rdch_dout), + .FULL (rdch_full), + .EMPTY (rdch_empty), + .ALMOST_FULL (), + .ALMOST_EMPTY (), + .PROG_FULL (AXI_R_PROG_FULL), + .PROG_EMPTY (AXI_R_PROG_EMPTY), + + .WR_ACK (), + .OVERFLOW (axi_r_overflow_i), + .VALID (), + .UNDERFLOW (axi_r_underflow_i), + .DATA_COUNT (AXI_R_DATA_COUNT), + .RD_DATA_COUNT (AXI_R_RD_DATA_COUNT), + .WR_DATA_COUNT (AXI_R_WR_DATA_COUNT), + .SBITERR (AXI_R_SBITERR), + .DBITERR (AXI_R_DBITERR), + .wr_rst_busy (wr_rst_busy_rdch), + .rd_rst_busy (rd_rst_busy_rdch), + .wr_rst_i_out (), + .rd_rst_i_out (), + + .BACKUP (BACKUP), + .BACKUP_MARKER (BACKUP_MARKER), + .INT_CLK (INT_CLK) + ); + + assign rdch_s_axi_rvalid = ~rdch_empty; + assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full; + assign S_AXI_RVALID = rdch_s_axi_rvalid; + assign M_AXI_RREADY = rdch_m_axi_rready; + + assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0; + assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0; + + end endgenerate //axi_read_data_channel + + // Register Slice for read Data Channel + generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice + + fifo_generator_v13_2_4_axic_reg_slice + #( + .C_FAMILY (C_FAMILY), + .C_DATA_WIDTH (C_DIN_WIDTH_RDCH), + .C_REG_CONFIG (C_REG_SLICE_MODE_RDCH) + ) + rdch_reg_slice_inst + ( + // System Signals + .ACLK (S_ACLK), + .ARESET (inverted_reset), + + // Slave side + .S_PAYLOAD_DATA (rdch_din), + .S_VALID (M_AXI_RVALID), + .S_READY (M_AXI_RREADY), + + // Master side + .M_PAYLOAD_DATA (rdch_dout), + .M_VALID (S_AXI_RVALID), + .M_READY (S_AXI_RREADY) + ); + end endgenerate // grdch_reg_slice + + + assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0; + assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0; + + + generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output + assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET]; + assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET]; + assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET]; + assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET]; + assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET]; + assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET]; + assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET]; + assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET]; + assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR; + assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN; + assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE; + assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST; + assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK; + assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE; + assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT; + assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS; + end endgenerate // axi_full_rach_output + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion + assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET]; + end endgenerate // axi_arregion + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion + assign M_AXI_ARREGION = 0; + end endgenerate // naxi_arregion + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser + assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET]; + end endgenerate // axi_aruser + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser + assign M_AXI_ARUSER = 0; + end endgenerate // naxi_aruser + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid + assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET]; + end endgenerate // axi_arid + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid + assign M_AXI_ARID = 0; + end endgenerate // naxi_arid + + generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output + assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET]; + assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET]; + assign S_AXI_RLAST = rdch_dout[0]; + assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA; + assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP; + assign rdch_din[0] = M_AXI_RLAST; + end endgenerate // axi_full_rdch_output + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output + assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET]; + end endgenerate // axi_full_ruser_output + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output + assign S_AXI_RUSER = 0; + end endgenerate // axi_full_nruser_output + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid + assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET]; + end endgenerate // axi_rid + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid + assign S_AXI_RID = 0; + end endgenerate // naxi_rid + + generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1 + assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT}; + assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET]; + assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET]; + end endgenerate // axi_lite_rach_output + + generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1 + assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP}; + assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET]; + assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET]; + end endgenerate // axi_lite_rdch_output + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1 + assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER; + end endgenerate // grach_din1 + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2 + assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID; + end endgenerate // grach_din2 + + generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin + assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION; + end endgenerate + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1 + assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER; + end endgenerate // grdch_din1 + + generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2 + assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID; + end endgenerate // grdch_din2 + + //end of axi_read_channel + + generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf + assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) : + (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i : + (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0; + end endgenerate // gaxi_comm_uf + + generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of + assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) : + (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i : + (C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0; + end endgenerate // gaxi_comm_of + + //------------------------------------------------------------------------- + //------------------------------------------------------------------------- + //------------------------------------------------------------------------- + // Pass Through Logic or Wiring Logic + //------------------------------------------------------------------------- + //------------------------------------------------------------------------- + //------------------------------------------------------------------------- + + //------------------------------------------------------------------------- + // Pass Through Logic for Read Channel + //------------------------------------------------------------------------- + + // Wiring logic for Write Address Channel + generate if (C_WACH_TYPE == 2) begin : gwach_pass_through + assign M_AXI_AWID = S_AXI_AWID; + assign M_AXI_AWADDR = S_AXI_AWADDR; + assign M_AXI_AWLEN = S_AXI_AWLEN; + assign M_AXI_AWSIZE = S_AXI_AWSIZE; + assign M_AXI_AWBURST = S_AXI_AWBURST; + assign M_AXI_AWLOCK = S_AXI_AWLOCK; + assign M_AXI_AWCACHE = S_AXI_AWCACHE; + assign M_AXI_AWPROT = S_AXI_AWPROT; + assign M_AXI_AWQOS = S_AXI_AWQOS; + assign M_AXI_AWREGION = S_AXI_AWREGION; + assign M_AXI_AWUSER = S_AXI_AWUSER; + assign S_AXI_AWREADY = M_AXI_AWREADY; + assign M_AXI_AWVALID = S_AXI_AWVALID; + end endgenerate // gwach_pass_through; + + // Wiring logic for Write Data Channel + generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through + assign M_AXI_WID = S_AXI_WID; + assign M_AXI_WDATA = S_AXI_WDATA; + assign M_AXI_WSTRB = S_AXI_WSTRB; + assign M_AXI_WLAST = S_AXI_WLAST; + assign M_AXI_WUSER = S_AXI_WUSER; + assign S_AXI_WREADY = M_AXI_WREADY; + assign M_AXI_WVALID = S_AXI_WVALID; + end endgenerate // gwdch_pass_through; + + // Wiring logic for Write Response Channel + generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through + assign S_AXI_BID = M_AXI_BID; + assign S_AXI_BRESP = M_AXI_BRESP; + assign S_AXI_BUSER = M_AXI_BUSER; + assign M_AXI_BREADY = S_AXI_BREADY; + assign S_AXI_BVALID = M_AXI_BVALID; + end endgenerate // gwrch_pass_through; + + //------------------------------------------------------------------------- + // Pass Through Logic for Read Channel + //------------------------------------------------------------------------- + + // Wiring logic for Read Address Channel + generate if (C_RACH_TYPE == 2) begin : grach_pass_through + assign M_AXI_ARID = S_AXI_ARID; + assign M_AXI_ARADDR = S_AXI_ARADDR; + assign M_AXI_ARLEN = S_AXI_ARLEN; + assign M_AXI_ARSIZE = S_AXI_ARSIZE; + assign M_AXI_ARBURST = S_AXI_ARBURST; + assign M_AXI_ARLOCK = S_AXI_ARLOCK; + assign M_AXI_ARCACHE = S_AXI_ARCACHE; + assign M_AXI_ARPROT = S_AXI_ARPROT; + assign M_AXI_ARQOS = S_AXI_ARQOS; + assign M_AXI_ARREGION = S_AXI_ARREGION; + assign M_AXI_ARUSER = S_AXI_ARUSER; + assign S_AXI_ARREADY = M_AXI_ARREADY; + assign M_AXI_ARVALID = S_AXI_ARVALID; + end endgenerate // grach_pass_through; + + // Wiring logic for Read Data Channel + generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through + assign S_AXI_RID = M_AXI_RID; + assign S_AXI_RLAST = M_AXI_RLAST; + assign S_AXI_RUSER = M_AXI_RUSER; + assign S_AXI_RDATA = M_AXI_RDATA; + assign S_AXI_RRESP = M_AXI_RRESP; + assign S_AXI_RVALID = M_AXI_RVALID; + assign M_AXI_RREADY = S_AXI_RREADY; + end endgenerate // grdch_pass_through; + + // Wiring logic for AXI Streaming + generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through + assign M_AXIS_TDATA = S_AXIS_TDATA; + assign M_AXIS_TSTRB = S_AXIS_TSTRB; + assign M_AXIS_TKEEP = S_AXIS_TKEEP; + assign M_AXIS_TID = S_AXIS_TID; + assign M_AXIS_TDEST = S_AXIS_TDEST; + assign M_AXIS_TUSER = S_AXIS_TUSER; + assign M_AXIS_TLAST = S_AXIS_TLAST; + assign S_AXIS_TREADY = M_AXIS_TREADY; + assign M_AXIS_TVALID = S_AXIS_TVALID; + end endgenerate // gaxis_pass_through; + + +endmodule //fifo_generator_v13_2_4 + + + +/******************************************************************************* + * Declaration of top-level module for Conventional FIFO + ******************************************************************************/ +module fifo_generator_v13_2_4_CONV_VER + #( + parameter C_COMMON_CLOCK = 0, + parameter C_INTERFACE_TYPE = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_COUNT_TYPE = 0, + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DEFAULT_VALUE = "", + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_ENABLE_RLOCS = 0, + parameter C_FAMILY = "virtex7", //Not allowed in Verilog model + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_BACKUP = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_INT_CLK = 0, + parameter C_HAS_MEMINIT_FILE = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RD_RST = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_HAS_WR_RST = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_INIT_WR_PNTR_VAL = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_MIF_FILE_NAME = "", + parameter C_OPTIMIZATION_MODE = 0, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PRIM_FIFO_TYPE = "", + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_FREQ = 1, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_ECC = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FIFO16_FLAGS = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_FREQ = 1, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_WR_RESPONSE_LATENCY = 1, + parameter C_MSGON_VAL = 1, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0, + parameter C_FIFO_TYPE = 0, + parameter C_SYNCHRONIZER_STAGE = 2, + parameter C_AXI_TYPE = 0 + ) + + ( + input BACKUP, + input BACKUP_MARKER, + input CLK, + input RST, + input SRST, + input WR_CLK, + input WR_RST, + input RD_CLK, + input RD_RST, + input [C_DIN_WIDTH-1:0] DIN, + input WR_EN, + input RD_EN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input INT_CLK, + input INJECTDBITERR, + input INJECTSBITERR, + + output [C_DOUT_WIDTH-1:0] DOUT, + output FULL, + output ALMOST_FULL, + output WR_ACK, + output OVERFLOW, + output EMPTY, + output ALMOST_EMPTY, + output VALID, + output UNDERFLOW, + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output PROG_FULL, + output PROG_EMPTY, + output SBITERR, + output DBITERR, + output wr_rst_busy_o, + output wr_rst_busy, + output rd_rst_busy, + output wr_rst_i_out, + output rd_rst_i_out + ); + +/* + ****************************************************************************** + * Definition of Parameters + ****************************************************************************** + * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) + * C_COUNT_TYPE : *not used + * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus + * C_DEFAULT_VALUE : *not used + * C_DIN_WIDTH : Width of DIN bus + * C_DOUT_RST_VAL : Reset value of DOUT + * C_DOUT_WIDTH : Width of DOUT bus + * C_ENABLE_RLOCS : *not used + * C_FAMILY : not used in bhv model + * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) + * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag + * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag + * C_HAS_BACKUP : *not used + * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus + * C_HAS_INT_CLK : not used in bhv model + * C_HAS_MEMINIT_FILE : *not used + * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag + * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus + * C_HAS_RD_RST : *not used + * C_HAS_RST : 1=Core has Async Rst + * C_HAS_SRST : 1=Core has Sync Rst + * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag + * C_HAS_VALID : 1=Core has VALID flag + * C_HAS_WR_ACK : 1=Core has WR_ACK flag + * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus + * C_HAS_WR_RST : *not used + * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram + * 1=Common-Clock ShiftRam + * 2=Indep. Clocks Bram/Dram + * 3=Virtex-4 Built-in + * 4=Virtex-5 Built-in + * C_INIT_WR_PNTR_VAL : *not used + * C_MEMORY_TYPE : 1=Block RAM + * 2=Distributed RAM + * 3=Shift RAM + * 4=Built-in FIFO + * C_MIF_FILE_NAME : *not used + * C_OPTIMIZATION_MODE : *not used + * C_OVERFLOW_LOW : 1=OVERFLOW active low + * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 + * C_PRELOAD_REGS : 1=Use output registers + * C_PRIM_FIFO_TYPE : not used in bhv model + * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold + * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold + * C_PROG_EMPTY_TYPE : 0=No programmable empty + * 1=Single prog empty thresh constant + * 2=Multiple prog empty thresh constants + * 3=Single prog empty thresh input + * 4=Multiple prog empty thresh inputs + * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold + * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold + * C_PROG_FULL_TYPE : 0=No prog full + * 1=Single prog full thresh constant + * 2=Multiple prog full thresh constants + * 3=Single prog full thresh input + * 4=Multiple prog full thresh inputs + * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus + * C_RD_DEPTH : Depth of read interface (2^N) + * C_RD_FREQ : not used in bhv model + * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) + * C_UNDERFLOW_LOW : 1=UNDERFLOW active low + * C_USE_DOUT_RST : 1=Resets DOUT on RST + * C_USE_ECC : Used for error injection purpose + * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register + * C_USE_FIFO16_FLAGS : not used in bhv model + * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count + * C_VALID_LOW : 1=VALID active low + * C_WR_ACK_LOW : 1=WR_ACK active low + * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus + * C_WR_DEPTH : Depth of write interface (2^N) + * C_WR_FREQ : not used in bhv model + * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) + * C_WR_RESPONSE_LATENCY : *not used + * C_MSGON_VAL : *not used by bhv model + * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST + * 1 = Use RST + * C_ERROR_INJECTION_TYPE : 0 = No error injection + * 1 = Single bit error injection only + * 2 = Double bit error injection only + * 3 = Single and double bit error injection + ****************************************************************************** + * Definition of Ports + ****************************************************************************** + * BACKUP : Not used + * BACKUP_MARKER: Not used + * CLK : Clock + * DIN : Input data bus + * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag + * PROG_FULL_THRESH : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag + * RD_CLK : Read Domain Clock + * RD_EN : Read enable + * RD_RST : Read Reset + * RST : Asynchronous Reset + * SRST : Synchronous Reset + * WR_CLK : Write Domain Clock + * WR_EN : Write enable + * WR_RST : Write Reset + * INT_CLK : Internal Clock + * INJECTSBITERR: Inject Signle bit error + * INJECTDBITERR: Inject Double bit error + * ALMOST_EMPTY : One word remaining in FIFO + * ALMOST_FULL : One empty space remaining in FIFO + * DATA_COUNT : Number of data words in fifo( synchronous to CLK) + * DOUT : Output data bus + * EMPTY : Empty flag + * FULL : Full flag + * OVERFLOW : Last write rejected + * PROG_EMPTY : Programmable Empty Flag + * PROG_FULL : Programmable Full Flag + * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) + * UNDERFLOW : Last read rejected + * VALID : Last read acknowledged, DOUT bus VALID + * WR_ACK : Last write acknowledged + * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) + * SBITERR : Single Bit ECC Error Detected + * DBITERR : Double Bit ECC Error Detected + ****************************************************************************** + */ + + //---------------------------------------------------------------------------- + //- Internal Signals for delayed input signals + //- All the input signals except Clock are delayed by 100 ps and then given to + //- the models. + //---------------------------------------------------------------------------- + + reg rst_delayed ; + reg empty_fb ; + reg srst_delayed ; + reg wr_rst_delayed ; + reg rd_rst_delayed ; + reg wr_en_delayed ; + reg rd_en_delayed ; + reg [C_DIN_WIDTH-1:0] din_delayed ; + reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ; + reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ; + reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ; + reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ; + reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ; + reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ; + reg injectdbiterr_delayed ; + reg injectsbiterr_delayed ; + wire empty_p0_out; + + always @* rst_delayed <= #`TCQ RST ; + always @* empty_fb <= #`TCQ empty_p0_out ; + always @* srst_delayed <= #`TCQ SRST ; + always @* wr_rst_delayed <= #`TCQ WR_RST ; + always @* rd_rst_delayed <= #`TCQ RD_RST ; + always @* din_delayed <= #`TCQ DIN ; + always @* wr_en_delayed <= #`TCQ WR_EN ; + always @* rd_en_delayed <= #`TCQ RD_EN ; + always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ; + always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ; + always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ; + always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ; + always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ; + always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ; + always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ; + always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ; + + /***************************************************************************** + * Derived parameters + ****************************************************************************/ + //There are 2 Verilog behavioral models + // 0 = Common-Clock FIFO/ShiftRam FIFO + // 1 = Independent Clocks FIFO + // 2 = Low Latency Synchronous FIFO + // 3 = Low Latency Asynchronous FIFO + localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 : + (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0; + localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0; + + //Internal reset signals + reg rd_rst_asreg = 1'b0; + reg rd_rst_asreg_d1 = 1'b0; + reg rd_rst_asreg_d2 = 1'b0; + reg rd_rst_asreg_d3 = 1'b0; + reg rd_rst_reg = 1'b0; + reg rd_rst_comb = 1'b1; + reg rd_rst_comb_d1 = 1'b0; + reg wr_rst_d0 = 1'b0; + reg wr_rst_d1 = 1'b0; + reg wr_rst_d2 = 1'b0; + reg rd_rst_d0 = 1'b0; + reg rd_rst_d1 = 1'b0; + reg rd_rst_d2 = 1'b0; + reg rd_rst_d3 = 1'b0; + reg wrrst_done = 1'b0; + reg rdrst_done = 1'b0; + reg wr_rst_asreg = 1'b0; + reg wr_rst_asreg_d1 = 1'b0; + reg wr_rst_asreg_d2 = 1'b0; + reg wr_rst_asreg_d3 = 1'b0; + reg rd_rst_wr_d0 = 1'b0; + reg rd_rst_wr_d1 = 1'b0; + reg rd_rst_wr_d2 = 1'b0; + reg wr_rst_reg = 1'b0; + reg rst_active_i = 1'b1; + reg rst_delayed_d1 = 1'b1; + reg rst_delayed_d2 = 1'b1; + reg wr_rst_comb = 1'b1; + reg wr_rst_comb_d1 = 1'b0; + wire wr_rst_i; + wire rd_rst_i; + wire rst_i; + + //Internal reset signals + reg rst_asreg = 1'b0; + reg srst_asreg = 1'b0; + reg rst_asreg_d1 = 1'b0; + reg rst_asreg_d2 = 1'b0; + reg srst_asreg_d1 = 1'b0; + reg srst_asreg_d2 = 1'b0; + reg rst_reg = 1'b0; + reg srst_reg = 1'b0; + reg rst_comb = 1'b1; + reg rst_comb_d1 = 1'b0; + wire srst_comb; + reg rst_full_gen_i = 0; + reg rst_full_ff_i = 0; + reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}}; + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire fifo_empty_fb; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + reg [31:0] DATA_COUNT_FWFT; + reg SS_FWFT_WR ; + reg SS_FWFT_RD ; + + wire sbiterr_fifo_out; + wire dbiterr_fifo_out; + wire inject_sbit_err; + wire inject_dbit_err; + wire sckt_wr_rst_i; + wire sckt_rd_rst_i; + reg sckt_wr_rst_i_q = 1'b0; + + wire w_fab_read_data_valid_i; + wire w_read_data_valid_i; + wire w_ram_valid_i; + // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR. + assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ? + injectsbiterr_delayed : 0; + assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ? + injectdbiterr_delayed : 0; + + assign wr_rst_i_out = wr_rst_i; + assign rd_rst_i_out = rd_rst_i; + assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2]; + generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o + wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK; + always @ (posedge clk_i) + sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy}; + end endgenerate +// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL +// parameter (1=Independent Clocks, 0=Common Clock) + + localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL; +generate +case (C_VERILOG_IMPL) +0 : begin : block1_ss + //Common Clock Behavioral Model + fifo_generator_v13_2_4_bhv_ver_ss + #( + .C_FAMILY (C_FAMILY), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RST (C_EN_SAFETY_CKT?0:C_HAS_RST), + .C_HAS_SRST (C_EN_SAFETY_CKT?1:C_HAS_SRST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_USE_ECC (C_USE_ECC), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE), + .C_FIFO_TYPE (C_FIFO_TYPE) + ) + gen_ss + ( + .SAFETY_CKT_WR_RST (sckt_wr_rst_i), + .CLK (CLK), + .RST (C_EN_SAFETY_CKT?1'b0:rst_i), + .SRST (C_EN_SAFETY_CKT?sckt_wr_rst_i:srst_delayed), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .DIN (din_delayed), + .WR_EN (wr_en_delayed), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (rd_en_delayed), + .USER_EMPTY_FB (empty_fb), + .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), + .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), + .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), + .PROG_FULL_THRESH (prog_full_thresh_delayed), + .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), + .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .EMPTY_FB (fifo_empty_fb), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .WR_RST_BUSY (wr_rst_busy), + .RD_RST_BUSY (rd_rst_busy), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end +1 : begin : block1_as + //Independent Clocks Behavioral Model + fifo_generator_v13_2_4_bhv_ver_as + #( + .C_FAMILY (C_FAMILY), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RST (C_EN_SAFETY_CKT?0:C_HAS_RST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_USE_ECC (C_USE_ECC), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) + ) + gen_as + ( + .SAFETY_CKT_WR_RST (sckt_wr_rst_i), + .SAFETY_CKT_RD_RST (sckt_rd_rst_i), + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (din_delayed), + .WR_EN (wr_en_delayed), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (rd_en_delayed), + .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), + .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), + .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), + .PROG_FULL_THRESH (prog_full_thresh_delayed), + .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), + .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .EMPTY_FB (fifo_empty_fb), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .fab_read_data_valid_i (w_fab_read_data_valid_i), + .read_data_valid_i (w_read_data_valid_i), + .ram_valid_i (w_ram_valid_i), + .DBITERR (dbiterr_fifo_out) + ); +end + +2 : begin : ll_afifo_inst + fifo_generator_v13_2_4_beh_ver_ll_afifo + #( + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_FIFO_TYPE (C_FIFO_TYPE) + ) + gen_ll_afifo + ( + .DIN (din_delayed), + .RD_CLK (RD_CLK), + .RD_EN (rd_en_delayed), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .WR_CLK (WR_CLK), + .WR_EN (wr_en_delayed), + .DOUT (DOUT), + .EMPTY (EMPTY), + .FULL (FULL) + ); +end +default : begin : block1_as + //Independent Clocks Behavioral Model + fifo_generator_v13_2_4_bhv_ver_as + #( + .C_FAMILY (C_FAMILY), + .C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH), + .C_DIN_WIDTH (C_DIN_WIDTH), + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL), + .C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY), + .C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL), + .C_HAS_DATA_COUNT (C_HAS_DATA_COUNT), + .C_HAS_OVERFLOW (C_HAS_OVERFLOW), + .C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT), + .C_HAS_RST (C_EN_SAFETY_CKT?0:C_HAS_RST), + .C_HAS_UNDERFLOW (C_HAS_UNDERFLOW), + .C_HAS_VALID (C_HAS_VALID), + .C_HAS_WR_ACK (C_HAS_WR_ACK), + .C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT), + .C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_OVERFLOW_LOW (C_OVERFLOW_LOW), + .C_PRELOAD_LATENCY (C_PRELOAD_LATENCY), + .C_PRELOAD_REGS (C_PRELOAD_REGS), + .C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL), + .C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL), + .C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE), + .C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL), + .C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL), + .C_PROG_FULL_TYPE (C_PROG_FULL_TYPE), + .C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH), + .C_RD_DEPTH (C_RD_DEPTH), + .C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH), + .C_UNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT), + .C_VALID_LOW (C_VALID_LOW), + .C_WR_ACK_LOW (C_WR_ACK_LOW), + .C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH), + .C_WR_DEPTH (C_WR_DEPTH), + .C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH), + .C_USE_ECC (C_USE_ECC), + .C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE) + ) + gen_as + ( + .SAFETY_CKT_WR_RST (sckt_wr_rst_i), + .SAFETY_CKT_RD_RST (sckt_rd_rst_i), + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (din_delayed), + .WR_EN (wr_en_delayed), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (rd_en_delayed), + .PROG_EMPTY_THRESH (prog_empty_thresh_delayed), + .PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed), + .PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed), + .PROG_FULL_THRESH (prog_full_thresh_delayed), + .PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed), + .PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .EMPTY_FB (fifo_empty_fb), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +endcase +endgenerate + + + //************************************************************************** + // Connect Internal Signals + // (Signals labeled internal_*) + // In the normal case, these signals tie directly to the FIFO's inputs and + // outputs. + // In the case of Preload Latency 0 or 1, there are intermediate + // signals between the internal FIFO and the preload logic. + //************************************************************************** + + + //*********************************************** + // If First-Word Fall-Through, instantiate + // the preload0 (FWFT) module + //*********************************************** + wire rd_en_to_fwft_fifo; + wire sbiterr_fwft; + wire dbiterr_fwft; + wire [C_DOUT_WIDTH-1:0] dout_fwft; + wire empty_fwft; + wire rd_en_fifo_in; + wire stage2_reg_en_i; + wire [1:0] valid_stages_i; + wire rst_fwft; + //wire empty_p0_out; + reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1; + + localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0; + localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0; + localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0; + assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0; + + generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2_fwft + + + fifo_generator_v13_2_4_bhv_ver_preload0 + #( + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_HAS_RST (C_HAS_RST), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_HAS_SRST (C_HAS_SRST), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG), + .C_USE_ECC (C_USE_ECC), + .C_USERVALID_LOW (C_VALID_LOW), + .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_FIFO_TYPE (C_FIFO_TYPE) + ) + fgpl0 + ( + .SAFETY_CKT_RD_RST(safety_ckt_rd_rst), + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .SRST (srst_delayed), + .WR_RST_BUSY (wr_rst_busy), + .RD_RST_BUSY (rd_rst_busy), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .FIFOSBITERR (sbiterr_fifo_out), + .FIFODBITERR (dbiterr_fifo_out), + // Output + .USERDATA (dout_fwft), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (empty_fwft), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (), + .FIFORDEN (rd_en_fifo_in), + .USERSBITERR (sbiterr_fwft), + .USERDBITERR (dbiterr_fwft), + .STAGE2_REG_EN (stage2_reg_en_i), + .fab_read_data_valid_i_o (w_fab_read_data_valid_i), + .read_data_valid_i_o (w_read_data_valid_i), + .ram_valid_i_o (w_ram_valid_i), + .VALID_STAGES (valid_stages_i) + ); + + + //*********************************************** + // Connect inputs to preload (FWFT) module + //*********************************************** + //Connect the RD_CLK of the Preload (FWFT) module to CLK if we + // have a common-clock FIFO, or RD_CLK if we have an + // independent clock FIFO + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0; + assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo; + assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + + //*********************************************** + // Connect outputs from preload (FWFT) module + //*********************************************** + assign VALID = VALID_P0_OUT ; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + assign RD_EN_FIFO_IN = rd_en_fifo_in; + + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: + (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + EMPTY_P0_OUT_Q <= 1; + ALMOSTEMPTY_P0_OUT_Q <= 1; + end else begin + EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out; +// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; + end + end //always + + + //*********************************************** + // logic for common-clock data count when FWFT is selected + //*********************************************** + initial begin + SS_FWFT_RD = 1'b0; + DATA_COUNT_FWFT = 0 ; + SS_FWFT_WR = 1'b0 ; + end //initial + + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter. SS_FWFT_WR and SS_FWFT_RD + // are the up/down enables for the counter. + //*********************************************** + always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin + if (C_VALID_LOW == 1) begin + SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ; + end else begin + SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ; + end + SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; + end + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter for FWFT. This always block + // calculates the counter. + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + DATA_COUNT_FWFT <= 0; + end else begin + //if (srst_delayed && (C_HAS_SRST == 1) ) begin + if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + case ( {SS_FWFT_WR, SS_FWFT_RD}) + 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; + 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; + 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + endcase + end //if SRST + end //IF RST + end //always + + end endgenerate // : block2 + + // AXI Streaming Packet FIFO + reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0; + reg partial_packet = 0; + reg stage1_eop_d1 = 0; + reg rd_en_fifo_in_d1 = 0; + reg eop_at_stage2 = 0; + reg ram_pkt_empty = 0; + reg ram_pkt_empty_d1 = 0; + + wire [C_DOUT_WIDTH-1:0] dout_p0_out; + wire packet_empty_wr; + wire wr_rst_fwft_pkt_fifo; + wire dummy_wr_eop; + wire ram_wr_en_pkt_fifo; + wire wr_eop; + wire ram_rd_en_compare; + wire stage1_eop; + wire pkt_ready_to_read; + wire rd_en_2_stage2; + + // Generate Dummy WR_EOP for partial packet (Only for AXI Streaming) + // When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP + // When dummy WR_EOP is high, mask the actual EOP to avoid double increment of + // write packet count + generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop + always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin + if (wr_rst_fwft_pkt_fifo) + partial_packet <= 1'b0; + else begin + if (srst_delayed | wr_rst_busy | rd_rst_busy) + partial_packet <= #`TCQ 1'b0; + else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0])) + partial_packet <= #`TCQ 1'b1; + else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo) + partial_packet <= #`TCQ 1'b0; + end + end + end endgenerate // gdummy_wr_eop + + generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin : gpkt_fifo_fwft + assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0; + assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet); + assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1]; + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) begin + stage1_eop_d1 <= 1'b0; + rd_en_fifo_in_d1 <= 1'b0; + end else begin + if (srst_delayed | wr_rst_busy | rd_rst_busy) begin + stage1_eop_d1 <= #`TCQ 1'b0; + rd_en_fifo_in_d1 <= #`TCQ 1'b0; + end else begin + stage1_eop_d1 <= #`TCQ stage1_eop; + rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in; + end + end + end + assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1; + assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT); + assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop); + assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop; + + + fifo_generator_v13_2_4_bhv_ver_preload0 + #( + .C_DOUT_RST_VAL (C_DOUT_RST_VAL), + .C_DOUT_WIDTH (C_DOUT_WIDTH), + .C_HAS_RST (C_HAS_RST), + .C_HAS_SRST (C_HAS_SRST), + .C_USE_DOUT_RST (C_USE_DOUT_RST), + .C_USE_ECC (C_USE_ECC), + .C_USERVALID_LOW (C_VALID_LOW), + .C_EN_SAFETY_CKT (C_EN_SAFETY_CKT), + .C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW), + .C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC), + .C_MEMORY_TYPE (C_MEMORY_TYPE), + .C_FIFO_TYPE (2) // Enable low latency fwft logic + ) + pkt_fifo_fwft + ( + .SAFETY_CKT_RD_RST(safety_ckt_rd_rst), + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (rst_fwft), + .SRST (srst_delayed), + .WR_RST_BUSY (wr_rst_busy), + .RD_RST_BUSY (rd_rst_busy), + .RD_EN (rd_en_delayed), + .FIFOEMPTY (pkt_ready_to_read), + .FIFODATA (dout_fwft), + .FIFOSBITERR (sbiterr_fwft), + .FIFODBITERR (dbiterr_fwft), + // Output + .USERDATA (dout_p0_out), + .USERVALID (), + .USEREMPTY (empty_p0_out), + .USERALMOSTEMPTY (), + .USERUNDERFLOW (), + .RAMVALID (), + .FIFORDEN (rd_en_2_stage2), + .USERSBITERR (SBITERR), + .USERDBITERR (DBITERR), + .STAGE2_REG_EN (), + .VALID_STAGES () + ); + + assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2)); + assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2; + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) + eop_at_stage2 <= 1'b0; + else if (stage2_reg_en_i) + eop_at_stage2 <= #`TCQ stage1_eop; + end + + //--------------------------------------------------------------------------- + // Write and Read Packet Count + //--------------------------------------------------------------------------- + always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin + if (wr_rst_fwft_pkt_fifo) + wr_pkt_count <= 0; + else if (srst_delayed | wr_rst_busy | rd_rst_busy) + wr_pkt_count <= #`TCQ 0; + else if (wr_eop) + wr_pkt_count <= #`TCQ wr_pkt_count + 1; + end + + end endgenerate //: gpkt_fifo_fwft + + assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out; + assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out; + + generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) begin + rd_pkt_count <= 0; + rd_pkt_count_plus1 <= 1; + end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin + rd_pkt_count <= #`TCQ 0; + rd_pkt_count_plus1 <= #`TCQ 1; + end else if (stage2_reg_en_i && stage1_eop) begin + rd_pkt_count <= #`TCQ rd_pkt_count + 1; + rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1; + end + end + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) begin + ram_pkt_empty <= 1'b1; + ram_pkt_empty_d1 <= 1'b1; + end else if (SRST | wr_rst_busy | rd_rst_busy) begin + ram_pkt_empty <= #`TCQ 1'b1; + ram_pkt_empty_d1 <= #`TCQ 1'b1; + end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin + ram_pkt_empty <= #`TCQ 1'b0; + ram_pkt_empty_d1 <= #`TCQ 1'b0; + end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin + ram_pkt_empty <= #`TCQ 1'b1; + end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin + ram_pkt_empty_d1 <= #`TCQ 1'b1; + end + end + end endgenerate //grss_pkt_cnt + + localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH; + reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0; + wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd; + generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt + // Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay + always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin + if (wr_rst_fwft_pkt_fifo) + wr_pkt_count_b2g <= 0; + else + wr_pkt_count_b2g <= #`TCQ wr_pkt_count; + end + + // Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) + wr_pkt_count_q <= 0; + else + wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g}; + end + + always @* begin + if (stage1_eop) + rd_pkt_count <= rd_pkt_count_reg + 1; + else + rd_pkt_count <= rd_pkt_count_reg; + end + + assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH]; + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) + rd_pkt_count_reg <= 0; + else if (rd_en_fifo_in) + rd_pkt_count_reg <= #`TCQ rd_pkt_count; + end + + always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin + if (rst_fwft) begin + ram_pkt_empty <= 1'b1; + ram_pkt_empty_d1 <= 1'b1; + end else if (rd_pkt_count != wr_pkt_count_rd) begin + ram_pkt_empty <= #`TCQ 1'b0; + ram_pkt_empty_d1 <= #`TCQ 1'b0; + end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin + ram_pkt_empty <= #`TCQ 1'b1; + end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin + ram_pkt_empty_d1 <= #`TCQ 1'b1; + end + end + + // Synchronize the empty in write domain + always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin + if (wr_rst_fwft_pkt_fifo) + pkt_empty_sync <= 'b1; + else + pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out}; + end + + end endgenerate //gras_pkt_cnt + + generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO + + //*********************************************** + // If NOT First-Word Fall-Through, wire the outputs + // of the internal _ss or _as FIFO directly to the + // output, and do not instantiate the preload0 + // module. + //*********************************************** + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = rd_en_delayed; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + assign SBITERR = sbiterr_fifo_out; + assign DBITERR = dbiterr_fifo_out; + + end endgenerate // STD_FIFO + + generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO + assign empty_p0_out = empty_fwft; + assign SBITERR = sbiterr_fwft; + assign DBITERR = dbiterr_fwft; + assign DOUT = dout_fwft; + assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo; + + end endgenerate // NO_PKT_FIFO + + //*********************************************** + // Connect user flags to internal signals + //*********************************************** + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3 + if (C_COMMON_CLOCK == 0) begin : block_ic + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); + end //block_ic + else begin + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + end //block3 + endgenerate + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30 + if (C_COMMON_CLOCK == 0) begin : block_ic + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); + end + else begin + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + end //block30 + endgenerate + + + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both + if (C_COMMON_CLOCK == 0) begin : block_ic_both + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT)); + end + else begin + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + end //block30_both + endgenerate + + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both + if (C_COMMON_CLOCK == 0) begin : block_ic_both + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT)); + end //block_ic_both + else begin + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + end //block3_both + endgenerate + + + //If we are not using extra logic for the FWFT data count, + //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the + //internal FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + endgenerate + + //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal + //FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + endgenerate + + + //Connect other flags to the internal FIFO instance + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + + + /************************************************************************** + * find_log2 + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function integer find_log2; + input integer int_val; + integer i,j; + begin + i = 1; + j = 0; + for (i = 1; i < int_val; i = i*2) begin + j = j + 1; + end + find_log2 = j; + end + endfunction + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + if (C_IMPLEMENTATION_TYPE == 2) begin + $display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information."); + end else if (C_MEMORY_TYPE == 4) begin + $display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado."); + $finish; + end + + if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin + $display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH."); + $finish; + end + + if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin + $display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH."); + $finish; + end + + if (C_USE_ECC == 1) begin + if (C_DIN_WIDTH != C_DOUT_WIDTH) begin + $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration."); + $finish; + end + if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin + $display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection."); + $finish; + end + end + + end //initial + + /************************************************************************** + * Internal reset logic + **************************************************************************/ + assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg|sckt_wr_rst_i : 0; + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg|sckt_rd_rst_i : 0; + assign rst_i = C_HAS_RST ? rst_reg|sckt_wr_rst_i : 0; + + wire rst_2_sync; + wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK; + + localparam RST_SYNC_STAGES = C_EN_SAFETY_CKT == 0 ? C_COMMON_CLOCK ? C_SYNCHRONIZER_STAGE : C_SYNCHRONIZER_STAGE+2 : 5; + localparam RST_BUSY_LEN = 4; + reg wr_rst_busy_i = 0; + reg rd_rst_busy_i = 0; + generate + if (C_ENABLE_RST_SYNC == 0 || (C_HAS_RST == 0 && C_HAS_SRST == 0)) begin : gnrst_sync + always @* begin + wr_rst_reg <= wr_rst_delayed; + rd_rst_reg <= rd_rst_delayed; + rst_reg <= 1'b0; + srst_reg <= 1'b0; + end + assign rst_2_sync = wr_rst_delayed; + assign wr_rst_busy = 1'b0; + assign wr_rst_busy_o = 1'b0; + assign rd_rst_busy = 1'b0; + assign sckt_wr_rst_i = 1'b0; + assign sckt_rd_rst_i = 1'b0; + end // gnrst_sync + else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 0) begin : g7s_ic_rst_nsckt + reg [1:0] arst_sync_wr = 2'b11; + reg [1:0] arst_sync_rd = 2'b11; + reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0; + reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0; + reg [3:0] rd_rst_wr_ext = 0; + reg [1:0] wr_rst_rd_ext = 0; + reg sckt_wr_rst_ic = 0; + reg sckt_rd_rst_ic = 0; + + assign rst_2_sync = arst_sync_wr[1]; + + always @(posedge WR_CLK or posedge rst_delayed) begin + if (rst_delayed == 1'b1) + arst_sync_wr <= #`TCQ 2'b11; + else + arst_sync_wr <= #`TCQ {arst_sync_wr[0], rst_delayed}; + end + + always @(posedge RD_CLK or posedge rst_delayed) begin + if (rst_delayed == 1'b1) + arst_sync_rd <= #`TCQ 2'b11; + else + arst_sync_rd <= #`TCQ {arst_sync_rd[0], rst_delayed}; + end + always @(posedge WR_CLK) begin + sckt_rd_rst_wr <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic}; + end + always @(posedge WR_CLK or posedge arst_sync_wr[1]) begin + if (arst_sync_wr[1]) begin + sckt_wr_rst_ic <= #`TCQ 1'b1; + wr_rst_busy_i <= #`TCQ 1'b1; + rd_rst_wr_ext <= #`TCQ {RST_SYNC_STAGES{1'b0}}; + end else begin + rd_rst_wr_ext <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]}; + if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0]) + sckt_wr_rst_ic <= #`TCQ 1'b0; + else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2]) + wr_rst_busy_i <= #`TCQ 1'b0; + end + end + always @(posedge RD_CLK) begin + sckt_wr_rst_rd <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], sckt_wr_rst_ic}; + end + always @(posedge RD_CLK or posedge arst_sync_rd[1]) begin + if (arst_sync_rd[1]) begin + sckt_rd_rst_ic <= #`TCQ 1'b1; + rd_rst_busy_i <= #`TCQ 1'b1; + wr_rst_rd_ext <= #`TCQ {RST_SYNC_STAGES{1'b0}}; + end else begin + wr_rst_rd_ext <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]}; + if (wr_rst_rd_ext[1]) begin + sckt_rd_rst_ic <= #`TCQ 1'b0; + rd_rst_busy_i <= #`TCQ 1'b0; + end + end + end + + assign rd_rst_busy = rd_rst_busy_i; + assign wr_rst_busy = wr_rst_busy_i; + assign wr_rst_busy_o = wr_rst_busy_i; + assign sckt_wr_rst_i = sckt_wr_rst_ic|arst_sync_wr[1]; + assign sckt_rd_rst_i = sckt_rd_rst_ic|arst_sync_rd[1]; + end // g7s_ic_rst_nsckt + else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 0 && C_EN_SAFETY_CKT == 1) begin : g7s_ic_rst_sckt + reg [RST_SYNC_STAGES-1:0] arst_sync_wr = {RST_SYNC_STAGES{1'b1}}; + reg [RST_SYNC_STAGES-1:0] arst_sync_rd = {RST_SYNC_STAGES{1'b1}}; + reg [RST_SYNC_STAGES-1:0] sckt_wr_rst_rd = 0; + reg [RST_SYNC_STAGES-1:0] sckt_rd_rst_wr = 0; + reg [3:0] rd_rst_wr_ext = 0; + reg [1:0] wr_rst_rd_ext = 0; + reg sckt_wr_rst_ic = 0; + reg sckt_rd_rst_ic = 0; + + always @(posedge WR_CLK) begin + arst_sync_wr <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed}; + sckt_rd_rst_wr <= #`TCQ {sckt_rd_rst_wr[RST_SYNC_STAGES-2:0], sckt_rd_rst_ic}; + rd_rst_wr_ext <= #`TCQ {rd_rst_wr_ext[2:0], sckt_rd_rst_wr[RST_SYNC_STAGES-1]}; + if (arst_sync_wr[RST_SYNC_STAGES-1]) begin + sckt_wr_rst_ic <= #`TCQ 1'b1; + wr_rst_busy_i <= #`TCQ 1'b1; + end else if (rd_rst_wr_ext[1] && ~rd_rst_wr_ext[0]) + sckt_wr_rst_ic <= #`TCQ 1'b0; + else if (rd_rst_wr_ext[3] && ~rd_rst_wr_ext[2]) + wr_rst_busy_i <= #`TCQ 1'b0; + end + always @(posedge RD_CLK) begin + arst_sync_rd <= #`TCQ {arst_sync_rd[RST_SYNC_STAGES-2:0], rst_delayed}; + sckt_wr_rst_rd <= #`TCQ {sckt_wr_rst_rd[RST_SYNC_STAGES-2:0], arst_sync_wr[RST_SYNC_STAGES-1]}; + wr_rst_rd_ext <= #`TCQ {wr_rst_rd_ext[0], sckt_wr_rst_rd[RST_SYNC_STAGES-1]}; + if (arst_sync_rd[RST_SYNC_STAGES-1]) begin + sckt_rd_rst_ic <= #`TCQ 1'b1; + rd_rst_busy_i <= #`TCQ 1'b1; + end else if (wr_rst_rd_ext[1]) begin + sckt_rd_rst_ic <= #`TCQ 1'b0; + rd_rst_busy_i <= #`TCQ 1'b0; + end + end + + assign rd_rst_busy = rd_rst_busy_i; + assign wr_rst_busy = wr_rst_busy_i; + assign wr_rst_busy_o = wr_rst_busy_i; + assign sckt_wr_rst_i = sckt_wr_rst_ic; + assign sckt_rd_rst_i = sckt_rd_rst_ic; + end // g7s_ic_rst_sckt + else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 0) begin : g7s_cc_rst_nsckt + reg [1:0] arst_sync_wr = 0; + reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0; + assign rst_2_sync = arst_sync_wr[1]; + + always @(posedge CLK or posedge rst_delayed) begin + if (rst_delayed == 1'b1) + arst_sync_wr <= #`TCQ 2'b11; + else + arst_sync_wr <= #`TCQ {arst_sync_wr[0], rst_delayed}; + end + + always @(posedge CLK) begin + sckt_wr_rst_cc <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]}; + end + + assign sckt_wr_rst_i = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0] | arst_sync_wr[1]; + assign sckt_rd_rst_i = sckt_wr_rst_i; + assign wr_rst_busy = |sckt_wr_rst_cc | arst_sync_wr[1]; + assign rd_rst_busy = |sckt_wr_rst_cc; + assign wr_rst_busy_o = |sckt_wr_rst_cc; + end // g7s_cc_rst_nsckt + else if (C_ENABLE_RST_SYNC == 1 && C_HAS_RST == 1 && C_COMMON_CLOCK == 1 && C_EN_SAFETY_CKT == 1) begin : g7s_cc_rst_sckt + reg [RST_SYNC_STAGES-1:0] arst_sync_wr = 0; + reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0; + + always @(posedge CLK) begin + arst_sync_wr <= #`TCQ {arst_sync_wr[RST_SYNC_STAGES-2:0], rst_delayed}; + sckt_wr_rst_cc <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[RST_SYNC_STAGES-1]}; + end + + assign sckt_wr_rst_i = |sckt_wr_rst_cc[RST_BUSY_LEN-3:0]; + assign sckt_rd_rst_i = sckt_wr_rst_i; + assign wr_rst_busy = |sckt_wr_rst_cc; + assign rd_rst_busy = |sckt_wr_rst_cc; + assign wr_rst_busy_o = |sckt_wr_rst_cc; + end // g7s_cc_rst_sckt + else if (C_ENABLE_RST_SYNC == 1 && IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst + assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i; + assign rd_rst_busy = rst_reg; + assign rst_2_sync = srst_delayed; + assign sckt_wr_rst_i = rst_reg; + always @* rst_full_ff_i <= 1'b0; + always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0; + + always @(posedge CLK) begin + rst_delayed_d1 <= #`TCQ srst_delayed; + rst_delayed_d2 <= #`TCQ rst_delayed_d1; + if (rst_reg || rst_delayed_d2) begin + rst_active_i <= #`TCQ 1'b1; + end else begin + rst_active_i <= #`TCQ rst_reg; + end + end + always @(posedge CLK) begin + if (~rst_reg && srst_delayed) begin + rst_reg <= #`TCQ 1'b1; + end else if (rst_reg) begin + rst_reg <= #`TCQ 1'b0; + end else begin + rst_reg <= #`TCQ rst_reg; + end + end + end // g8s_cc_rst + else if (IS_8SERIES != 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_srst + assign wr_rst_busy = srst_delayed; + assign rd_rst_busy = srst_delayed; + assign rst_2_sync = srst_delayed; + assign sckt_wr_rst_i = srst_delayed; + always @* rst_full_ff_i <= 1'b0; + end // g7s_cc_srst + endgenerate + + reg rst_d1 = 1'b0; + reg rst_d2 = 1'b0; + reg rst_d3 = 1'b0; + reg rst_d4 = 1'b0; + generate + if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1 + // RST_FULL_GEN replaces the reset falling edge detection used to de-assert + // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. + + // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & + // PROG_FULL + + always @ (posedge rst_2_sync or posedge clk_2_sync) begin + if (rst_2_sync && C_EN_SAFETY_CKT == 0) begin + rst_d1 <= 1'b1; + rst_d2 <= 1'b1; + rst_d3 <= 1'b1; + rst_d4 <= 1'b0; + end else begin + if (srst_delayed) begin + rst_d1 <= #`TCQ 1'b1; + rst_d2 <= #`TCQ 1'b1; + rst_d3 <= #`TCQ 1'b1; + rst_d4 <= #`TCQ 1'b0; + end else begin + rst_d1 <= #`TCQ wr_rst_busy;//1'b0; + rst_d2 <= #`TCQ rst_d1; + rst_d3 <= #`TCQ rst_d2 | sckt_wr_rst_i; + rst_d4 <= #`TCQ rst_d3; + end + end + end + + always @* rst_full_ff_i <= C_HAS_SRST ? 1'b0 : rst_d2 | sckt_wr_rst_i; + always @* rst_full_gen_i <= C_HAS_SRST ? rst_d4 : rst_d3; + + end else if (C_EN_SAFETY_CKT == 1 && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full_sckt + always @* rst_full_ff_i <= C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; + always @* rst_full_gen_i <= 1'b0; + end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full + always @* rst_full_ff_i <= C_HAS_SRST ? 1'b0 : (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; + always @* rst_full_gen_i <= 1'b0; + end + endgenerate // grstd1 + +endmodule //fifo_generator_v13_2_4_CONV_VER + + +module fifo_generator_v13_2_4_sync_stage + #( + parameter C_WIDTH = 10 + ) + ( + input RST, + input CLK, + input [C_WIDTH-1:0] DIN, + output reg [C_WIDTH-1:0] DOUT = 0 + ); + always @ (posedge RST or posedge CLK) begin + if (RST) + DOUT <= 0; + else + DOUT <= #`TCQ DIN; + end +endmodule // fifo_generator_v13_2_4_sync_stage + +/******************************************************************************* + * Declaration of Independent-Clocks FIFO Module + ******************************************************************************/ +module fifo_generator_v13_2_4_bhv_ver_as + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + #( + parameter C_FAMILY = "virtex7", + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0, + parameter C_SYNCHRONIZER_STAGE = 2 + ) + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + ( + input SAFETY_CKT_WR_RST, + input SAFETY_CKT_RD_RST, + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_CLK, + input RD_EN, + input RD_EN_USER, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input WR_RST, + input RD_RST, + input WR_CLK, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + input USER_EMPTY_FB, + input fab_read_data_valid_i, + input read_data_valid_i, + input ram_valid_i, + output reg ALMOST_EMPTY = 1'b1, + output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL, + output [C_DOUT_WIDTH-1:0] DOUT, + output reg EMPTY = 1'b1, + output reg EMPTY_FB = 1'b1, + output reg FULL = C_FULL_FLAGS_RST_VAL, + output OVERFLOW, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output UNDERFLOW, + output WR_ACK, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output SBITERR, + output DBITERR + ); + + + reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0; + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + localparam C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + localparam C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 2 + // 1 | 4 | C_RD_PNTR_WIDTH | 2 + // 1 | 2 | C_RD_PNTR_WIDTH | 2 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + + localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + localparam [31:0] log2_reads_per_write = log2_val(reads_per_write); + + localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + localparam [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK + // domain. + //num_wr_bits is calculated by considering the total words in the FIFO, + // and the state of the read pointer (which may not have yet crossed clock + // domains.) + //num_rd_bits is calculated by considering the total words in the FIFO, + // and the state of the write pointer (which may not have yet crossed clock + // domains.) + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; + wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; + wire wr_rst_i = WR_RST; + reg wr_rst_d1 =0; + + //The read pointer - tracks read operations + // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; + wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; + wire rd_rst_i = RD_RST; + wire ram_rd_en; + wire empty_int; + wire almost_empty_int; + wire ram_wr_en; + wire full_int; + wire almost_full_int; + reg ram_rd_en_d1 = 1'b0; + reg fab_rd_en_d1 = 1'b0; + + + + // Delayed ram_rd_en is needed only for STD Embedded register option + generate + if (C_PRELOAD_LATENCY == 2) begin : grd_d + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + ram_rd_en_d1 <= 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + end + end + endgenerate + + generate + if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1 + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + ram_rd_en_d1 <= 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; + end + end + endgenerate + + + + // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; + end else begin : rdl // Read depth lesser than or equal to write depth + assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + endgenerate + + // Generate Empty and Almost Empty + // ram_rd_en used to determine EMPTY should depend on the EMPTY. + assign ram_rd_en = RD_EN & !EMPTY; + assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); + assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); + + // Register Empty and Almost Empty + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin + EMPTY <= 1'b1; + ALMOST_EMPTY <= 1'b1; + rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}}; + end else if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) begin + EMPTY <= 1'b1; + ALMOST_EMPTY <= 1'b1; + rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}}; + end else begin + rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; + + if (empty_int) + EMPTY <= #`TCQ 1'b1; + else + EMPTY <= #`TCQ 1'b0; + + if (!EMPTY) begin + if (almost_empty_int) + ALMOST_EMPTY <= #`TCQ 1'b1; + else + ALMOST_EMPTY <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin + EMPTY_FB <= 1'b1; + end else begin + if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT) + EMPTY_FB <= #`TCQ 1'b1; + else if (empty_int) + EMPTY_FB <= #`TCQ 1'b1; + else + EMPTY_FB <= #`TCQ 1'b0; + end // rd_rst_i + end // always + + // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; + end else begin : wdl // Write depth lesser than or equal to read depth + assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end + endgenerate + + // Generate FULL and ALMOST_FULL + // ram_wr_en used to determine FULL should depend on the FULL. + assign ram_wr_en = WR_EN & !FULL; + assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); + assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); + + // Register FULL and ALMOST_FULL Empty + always @ (posedge WR_CLK or posedge RST_FULL_FF) + begin + if (RST_FULL_FF & C_HAS_RST) begin + FULL <= C_FULL_FLAGS_RST_VAL; + ALMOST_FULL <= C_FULL_FLAGS_RST_VAL; + end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin + FULL <= C_FULL_FLAGS_RST_VAL; + ALMOST_FULL <= C_FULL_FLAGS_RST_VAL; + end else begin + if (full_int) begin + FULL <= #`TCQ 1'b1; + end else begin + FULL <= #`TCQ 1'b0; + end + + if (RST_FULL_GEN) begin + ALMOST_FULL <= #`TCQ 1'b0; + end else if (!FULL) begin + if (almost_full_int) + ALMOST_FULL <= #`TCQ 1'b1; + else + ALMOST_FULL <= #`TCQ 1'b0; + end + end // wr_rst_i + end // always + always @ (posedge WR_CLK or posedge wr_rst_i) + begin + if (wr_rst_i) begin + wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}}; + end else begin + wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; + end // wr_rst_i + end // always + + // Determine which stage in FWFT registers are valid + reg stage1_valid = 0; + reg stage2_valid = 0; + generate + if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + stage1_valid <= 0; + stage2_valid <= 0; + end else begin + + if (!stage1_valid && !stage2_valid) begin + if (!EMPTY) + stage1_valid <= #`TCQ 1'b1; + else + stage1_valid <= #`TCQ 1'b0; + end else if (stage1_valid && !stage2_valid) begin + if (EMPTY) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else if (!stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && !RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end + end else if (stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + end + endgenerate + + //Pointers passed into opposite clock domain + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_EMPTY. + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_FULL. + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + + /************************** + * Read Data Count + *************************/ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************** + * Write Data Count + *************************/ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + /*************************************************************************** + * Internal registers and wires + **************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire valid_i; + wire valid_out1; + wire valid_out2; + wire valid_out; + wire underflow_i; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [1:0] err_type_both = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = C_OVERFLOW_LOW; + reg ideal_underflow = C_UNDERFLOW_LOW; + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; + + //Assorted reg values for delayed versions of signals + reg valid_d1 = 0; + reg valid_d2 = 0; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + wr_pntr <= #`TCQ wr_pntr + 1; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + reg [1:0] tmp_ecc_err; + begin + rd_pntr <= #`TCQ rd_pntr + 1; + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) begin + $display("FAILURE : Data width must be >= 2 for double bit error injection."); + $finish; + end else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /*********************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + wr_pntr = 0; + rd_pntr = 0; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + err_type_d1 = 0; + err_type_both = 0; + ideal_dout_d1 = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + valid_d2 = 1'b0; + ideal_overflow = C_OVERFLOW_LOW; + ideal_underflow = C_UNDERFLOW_LOW; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + */ + + //*************************************************************************** + // Dout may change behavior based on latency + //*************************************************************************** + assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )? + ideal_dout_d1: ideal_dout; + assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; + + //*************************************************************************** + // Assign SBITERR and DBITERR based on latency + //*************************************************************************** + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY == 2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + //*************************************************************************** + // Safety-ckt logic with embedded reg/fabric reg + //*************************************************************************** + generate + if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin + + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + // if (C_HAS_VALID == 1) begin + // assign valid_out = valid_d1; + // end + + always@(posedge RD_CLK) + begin + rst_delayed_sft1 <= #`TCQ rd_rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) + begin + if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) + ram_rd_en_d1 <= #`TCQ 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + end + + always@(posedge rst_delayed_sft2 or posedge RD_CLK) + begin + if (rst_delayed_sft2 == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge RD_CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + else begin + if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1[0] <= #`TCQ err_type[0]; + err_type_d1[1] <= #`TCQ err_type[1]; + end + end + end + end + endgenerate + +//*************************************************************************** + // Safety-ckt logic with embedded reg + fabric reg + //*************************************************************************** + generate + if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin + + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge RD_CLK) begin + rst_delayed_sft1 <= #`TCQ rd_rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin + if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1) + ram_rd_en_d1 <= #`TCQ 1'b0; + else begin + ram_rd_en_d1 <= #`TCQ ram_rd_en; + fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; + end + end + + always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin + if (rst_delayed_sft2 == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge RD_CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + end + end else begin + if (ram_rd_en_d1) begin + ideal_dout_both <= #`TCQ ideal_dout; + err_type_both[0] <= #`TCQ err_type[0]; + err_type_both[1] <= #`TCQ err_type[1]; + end + + if (fab_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout_both; + err_type_d1[0] <= #`TCQ err_type_both[0]; + err_type_d1[1] <= #`TCQ err_type_both[1]; + end + end + end + end + endgenerate + + //*************************************************************************** + // Overflow may be active-low + //*************************************************************************** + generate + if (C_HAS_OVERFLOW==1) begin : blockOF1 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //*************************************************************************** + // Valid may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_VALID==1) begin : blockVL1 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out1 = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)? + valid_d1: valid_i; + assign valid_out2 = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)? + valid_d2: valid_i; + assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + + //*************************************************************************** + // Underflow may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF1 + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + //*************************************************************************** + // Write acknowledge may be active low + //*************************************************************************** + generate + if (C_HAS_WR_ACK==1) begin : blockWK1 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext + + reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; + reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; + wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; + wire [C_PNTR_WIDTH:0] diff_wr_rd; + reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; + always @* begin + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = 0; + adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin + adjusted_rd_pntr = rd_pntr_wr; + adjusted_wr_pntr = 0; + adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; + end else begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = rd_pntr_wr; + end + end // always @* + + assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; + assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; + + always @ (posedge wr_rst_i or posedge WR_CLK) + begin + if (wr_rst_i) + wr_data_count_i <= 0; + else + wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; + end // always @ (posedge WR_CLK or posedge WR_CLK) + + always @* begin + if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; + else + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end // always @* + end // wdc_fwft_ext + endgenerate + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; + + generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext + reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; + always @* begin + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin + adjusted_wr_pntr_rd = 0; + adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + end else begin + adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + end // always @* + + assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; + assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; + + + always @ (posedge rd_rst_i or posedge RD_CLK) + begin + if (rd_rst_i) begin + rdc_fwft_ext_as <= 0; + end else begin + if (!stage2_valid) + rdc_fwft_ext_as <= #`TCQ 0; + else if (!stage1_valid && stage2_valid) + rdc_fwft_ext_as <= #`TCQ 1; + else + rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; + end + end // always @ (posedge WR_CLK or posedge WR_CLK) + end // rdc_fwft_ext + end + endgenerate + + + generate if (C_USE_EMBEDDED_REG == 3) begin + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext + reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; + always @* begin + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin + adjusted_wr_pntr_rd = 0; + adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + end else begin + adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + end // always @* + + assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; + assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1; + // assign diff_rd_wr_1 = diff_rd_wr +2'h2; + + always @ (posedge rd_rst_i or posedge RD_CLK) + begin + if (rd_rst_i) begin + rdc_fwft_ext_as <= #`TCQ 0; + end else begin + //if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1))) + // rdc_fwft_ext_as <= 1'b0; + //else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1))) + // rdc_fwft_ext_as <= 1'b1; + //else + rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ; + end + + + +end +end +end +endgenerate + + + //*************************************************************************** + // Assign the read data count value only if it is selected, + // otherwise output zeros. + //*************************************************************************** + generate + if (C_HAS_RD_DATA_COUNT == 1) begin : grdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? + rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : + rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}}; + end + endgenerate + + //*************************************************************************** + // Assign the write data count value only if it is selected, + // otherwise output zeros + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? + wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : + wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}}; + end + endgenerate + + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL2 + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= 1'b0; + valid_d2 <= 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + valid_d2 <= #`TCQ valid_d1; + end +// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin + // valid_d2 <= #`TCQ valid_d1; + // end + end + end + endgenerate + + //Capture delayed version of dout + /************************************************************************** + *embedded/fabric reg with no safety ckt + **************************************************************************/ + generate + if (C_USE_EMBEDDED_REG < 3) begin + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge RD_CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout <= #`TCQ dout_reset_val; + end + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + +end +endgenerate +/************************************************************************** + *embedded + fabric reg with no safety ckt + **************************************************************************/ + +generate + if (C_USE_EMBEDDED_REG == 3) begin + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge RD_CLK) + ideal_dout <= #`TCQ dout_reset_val; + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + end + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + end else begin + if (ram_rd_en_d1) begin + ideal_dout_both <= #`TCQ ideal_dout; + err_type_both <= #`TCQ err_type; + end + if (fab_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout_both; + err_type_d1 <= #`TCQ err_type_both; + end + end + end + end +endgenerate + + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw + always @(posedge WR_CLK) begin + ideal_overflow <= #`TCQ WR_EN & FULL; + end + end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw + always @(posedge WR_CLK) begin + //ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i); + ideal_overflow <= #`TCQ WR_EN & (FULL ); + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw + always @(posedge RD_CLK) begin + ideal_underflow <= #`TCQ EMPTY & RD_EN; + end + end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw + always @(posedge RD_CLK) begin + ideal_underflow <= #`TCQ (EMPTY) & RD_EN; + //ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN; + end + end + endgenerate + + /************************************************************************** + * Write/Read Pointer Synchronization + **************************************************************************/ + localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1; + wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B]; + wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B]; + genvar gss; + + generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst + fifo_generator_v13_2_4_sync_stage + #( + .C_WIDTH (C_WR_PNTR_WIDTH) + ) + rd_stg_inst + ( + .RST (rd_rst_i), + .CLK (RD_CLK), + .DIN (wr_pntr_sync_stgs[gss-1]), + .DOUT (wr_pntr_sync_stgs[gss]) + ); + + fifo_generator_v13_2_4_sync_stage + #( + .C_WIDTH (C_RD_PNTR_WIDTH) + ) + wr_stg_inst + ( + .RST (wr_rst_i), + .CLK (WR_CLK), + .DIN (rd_pntr_sync_stgs[gss-1]), + .DOUT (rd_pntr_sync_stgs[gss]) + ); + end endgenerate // Sync_stage_inst + + assign wr_pntr_sync_stgs[0] = wr_pntr_rd1; + assign rd_pntr_sync_stgs[0] = rd_pntr_wr1; + always@* begin + wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B]; + rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B]; + end + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp + if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0) + wr_pntr <= 0; + else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1) + wr_pntr <= #`TCQ 0; + end + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= 0; + next_num_wr_bits = 0; + wr_ptr <= C_WR_DEPTH - 1; + rd_ptr_wrclk <= C_RD_DEPTH - 1; + ideal_wr_ack <= 0; + ideal_wr_count <= 0; + tmp_wr_listsize = 0; + rd_ptr_wrclk_next <= 0; + wr_pntr_rd1 <= 0; + + end else begin //wr_rst_i==0 + + wr_pntr_rd1 <= #`TCQ wr_pntr; + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (FULL == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //With DEPTH-1 words in the FIFO, it is almost_full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //FIFO is really not close to full, so change flag status. + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //This write is CAUSING the FIFO to go full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is 2 from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Still 2 from full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is not close to being full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Not even close to full. + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end + num_wr_bits <= #`TCQ next_num_wr_bits; + rd_ptr_wrclk <= #`TCQ rd_ptr; + + end //wr_rst_i==0 + end // gen_fifo_w + + + /*************************************************************************** + * Programmable FULL flags + ***************************************************************************/ + + wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val; + wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val; + + generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT + assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC; + assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC; + end else begin // STD + assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL; + assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL; + end endgenerate + + always @(posedge WR_CLK or posedge wr_rst_i) begin + + if (wr_rst_i == 1'b1) begin + diff_pntr <= 0; + end else begin + if (ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1); + else if (!ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr); + end + end + + + always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf + + if (RST_FULL_FF & C_HAS_RST) begin + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + end else if (SAFETY_CKT_WR_RST & C_EN_SAFETY_CKT) begin + ideal_prog_full <= C_FULL_FLAGS_RST_VAL; + end else begin + + if (RST_FULL_GEN) + ideal_prog_full <= #`TCQ 0; + //Single Programmable Full Constant Threshold + else if (C_PROG_FULL_TYPE == 1) begin + if (FULL == 0) begin + if (diff_pntr >= pf_thr_assert_val) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if (FULL == 0) begin + if (diff_pntr >= pf_thr_assert_val) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < pf_thr_negate_val) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE == 3) begin + if (FULL == 0) begin + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC)) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else begin // STD + if (diff_pntr >= PROG_FULL_THRESH) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE == 4) begin + if (FULL == 0) begin + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC)) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC)) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else begin // STD + if (diff_pntr >= PROG_FULL_THRESH_ASSERT) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < PROG_FULL_THRESH_NEGATE) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + end // C_PROG_FULL_TYPE + + end //wr_rst_i==0 + end // + + + /************************************************************************** + * Read Domain Logic + **************************************************************************/ + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + + wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val; + wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val; + reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0; + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe + + if (rd_rst_i & C_HAS_RST) begin + diff_pntr_rd <= 0; + ideal_prog_empty <= 1'b1; + end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin + diff_pntr_rd <= 0; + ideal_prog_empty <= 1'b1; + end else begin + if (ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1; + else if (!ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr); + else + diff_pntr_rd <= #`TCQ diff_pntr_rd; + + if (C_PROG_EMPTY_TYPE == 1) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 2) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 3) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 4) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end //C_PROG_EMPTY_TYPE + end + end // gen_pe + + generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input + assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH; + end endgenerate // single_pe_thr_input + + generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input + assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT; + assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE; + end endgenerate // multiple_pe_thr_input + + generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const + assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL; + assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? + C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL; + end endgenerate // single_multiple_pe_thr_const + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp + if (rd_rst_i && C_EN_SAFETY_CKT == 0) + rd_pntr <= 0; + else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1) + rd_pntr <= #`TCQ 0; + end + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i & C_HAS_RST) begin + num_rd_bits <= 0; + next_num_rd_bits = 0; + rd_ptr <= C_RD_DEPTH -1; + rd_pntr_wr1 <= 0; + wr_ptr_rdclk <= C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) + ideal_dout <= dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type <= 0; + err_type_d1 <= 0; + err_type_both <= 0; + end + ideal_valid <= 1'b0; + ideal_rd_count <= 0; + + end else if (SAFETY_CKT_RD_RST & C_EN_SAFETY_CKT) begin + num_rd_bits <= 0; + next_num_rd_bits = 0; + rd_ptr <= C_RD_DEPTH -1; + rd_pntr_wr1 <= 0; + wr_ptr_rdclk <= C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) + ideal_dout <= dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type <= 0; + err_type_d1 <= 0; + err_type_both <= 0; + end + ideal_valid <= 1'b0; + ideal_rd_count <= 0; + end else begin //rd_rst_i==0 + + rd_pntr_wr1 <= #`TCQ rd_pntr; + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + ideal_valid <= #`TCQ 1'b0; + + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + ideal_valid <= #`TCQ 1'b0; + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + num_rd_bits <= #`TCQ next_num_rd_bits; + wr_ptr_rdclk <= #`TCQ wr_ptr; + end //rd_rst_i==0 + end //always gen_fifo_r_as + +endmodule // fifo_generator_v13_2_4_bhv_ver_as + + +/******************************************************************************* + * Declaration of Low Latency Asynchronous FIFO + ******************************************************************************/ +module fifo_generator_v13_2_4_beh_ver_ll_afifo + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + #( + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_USE_DOUT_RST = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_FIFO_TYPE = 0 + ) + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + ( + input [C_DIN_WIDTH-1:0] DIN, + input RD_CLK, + input RD_EN, + input WR_RST, + input RD_RST, + input WR_CLK, + input WR_EN, + output reg [C_DOUT_WIDTH-1:0] DOUT = 0, + output reg EMPTY = 1'b1, + output reg FULL = C_FULL_FLAGS_RST_VAL + ); + + //----------------------------------------------------------------------------- + // Low Latency Asynchronous FIFO + //----------------------------------------------------------------------------- + + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + integer i; + initial begin + for (i = 0; i < C_WR_DEPTH; i = i + 1) + memory[i] = 0; + end + + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0; + wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0; + reg ll_afifo_full = 1'b0; + reg ll_afifo_empty = 1'b1; + wire write_allow; + wire read_allow; + + assign write_allow = WR_EN & ~ll_afifo_full; + assign read_allow = RD_EN & ~ll_afifo_empty; + + //----------------------------------------------------------------------------- + // Write Pointer Generation + //----------------------------------------------------------------------------- + always @(posedge WR_CLK or posedge WR_RST) begin + if (WR_RST) + wr_pntr_ll_afifo <= 0; + else if (write_allow) + wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1; + end + + //----------------------------------------------------------------------------- + // Read Pointer Generation + //----------------------------------------------------------------------------- + always @(posedge RD_CLK or posedge RD_RST) begin + if (RD_RST) + rd_pntr_ll_afifo_q <= 0; + else + rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo; + end + assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q; + + //----------------------------------------------------------------------------- + // Fill the Memory + //----------------------------------------------------------------------------- + always @(posedge WR_CLK) begin + if (write_allow) + memory[wr_pntr_ll_afifo] <= #`TCQ DIN; + end + + //----------------------------------------------------------------------------- + // Generate DOUT + //----------------------------------------------------------------------------- + always @(posedge RD_CLK) begin + DOUT <= #`TCQ memory[rd_pntr_ll_afifo]; + end + + //----------------------------------------------------------------------------- + // Generate EMPTY + //----------------------------------------------------------------------------- + always @(posedge RD_CLK or posedge RD_RST) begin + if (RD_RST) + ll_afifo_empty <= 1'b1; + else + ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) | + (read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1)))); + end + + //----------------------------------------------------------------------------- + // Generate FULL + //----------------------------------------------------------------------------- + always @(posedge WR_CLK or posedge WR_RST) begin + if (WR_RST) + ll_afifo_full <= 1'b1; + else + ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) | + (write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2)))); + end + + always @* begin + FULL <= ll_afifo_full; + EMPTY <= ll_afifo_empty; + end + +endmodule // fifo_generator_v13_2_4_beh_ver_ll_afifo + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v13_2_4_bhv_ver_ss + + /************************************************************************** + * Declare user parameters and their defaults + *************************************************************************/ + #( + parameter C_FAMILY = "virtex7", + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0, + parameter C_FIFO_TYPE = 0 + ) + + /************************************************************************** + * Declare Input and Output Ports + *************************************************************************/ + ( + //Inputs + input SAFETY_CKT_WR_RST, + input CLK, + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_EN, + input RD_EN_USER, + input USER_EMPTY_FB, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input SRST, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + input WR_RST_BUSY, + input RD_RST_BUSY, + + //Outputs + output ALMOST_EMPTY, + output ALMOST_FULL, + output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0, + output [C_DOUT_WIDTH-1:0] DOUT, + output EMPTY, + output reg EMPTY_FB = 1'b1, + output FULL, + output OVERFLOW, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output UNDERFLOW, + output WR_ACK, + output SBITERR, + output DBITERR + ); + + + reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; + wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss; + wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss; + reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus" || C_FAMILY == "virtexuplushbm") ? 1 : 0; + localparam C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + localparam C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + //localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + //localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ; + + + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 2 + // 1 | 4 | C_RD_PNTR_WIDTH | 2 + // 1 | 2 | C_RD_PNTR_WIDTH | 2 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + + localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + //wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR); + localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + //localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR); + + localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + localparam [31:0] log2_reads_per_write = log2_val(reads_per_write); + + localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + localparam [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + localparam C_HAS_FAST_FIFO = 0; + localparam C_FIFO_WR_DEPTH = C_WR_DEPTH; + localparam C_FIFO_RD_DEPTH = C_RD_DEPTH; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH; + localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1; + localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}}; + localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}}; + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + + /************************************************************************** + * Internal Registers and wires + *************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire underflow_i; + wire valid_i; + wire valid_out; + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; + reg wr_rst_d1 =0; + + //The read pointer - tracks read operations + // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; + + wire ram_rd_en; + wire empty_int; + wire almost_empty_int; + wire ram_wr_en; + wire full_int; + wire almost_full_int; + reg ram_rd_en_reg = 1'b0; + reg ram_rd_en_d1 = 1'b0; + reg fab_rd_en_d1 = 1'b0; + wire srst_rrst_busy; + + + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [1:0] err_type_both = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire fwft_enabled; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = C_OVERFLOW_LOW; + reg ideal_underflow = C_UNDERFLOW_LOW; + + reg full_i = C_FULL_FLAGS_RST_VAL; + reg full_i_temp = 0; + reg empty_i = 1; + reg almost_full_i = 0; + reg almost_empty_i = 1; + reg prog_full_i = 0; + reg prog_empty_i = 1; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; + wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; + wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; + reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0; + + reg write_allow_q = 0; + reg read_allow_q = 0; + reg valid_d1 = 0; + reg valid_both = 0; + reg valid_d2 = 0; + wire rst_i; + wire srst_i; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin + case (def_data[7:0]) + 8'b00000000 : begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) begin + if ((index*4)+j < C_DOUT_WIDTH) begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; + + //Assorted reg values for delayed versions of signals + //reg valid_d1 = 0; + + + //user specified value for reseting the size of the fifo + //reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + wr_pntr <= #`TCQ wr_pntr + 1; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + reg [1:0] tmp_ecc_err; + begin + rd_pntr <= #`TCQ rd_pntr + 1; + + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) begin + $display("FAILURE : Data width must be >= 2 for double bit error injection."); + $finish; + end else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + + end + endtask + + + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + wr_pntr = 0; + rd_pntr = 0; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + err_type_d1 = 0; + err_type_both = 0; + ideal_dout_d1 = dout_reset_val; + ideal_dout_both = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + valid_both = 1'b0; + ideal_overflow = C_OVERFLOW_LOW; + ideal_underflow = C_UNDERFLOW_LOW; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire WR_EN; + */ + + // Assign ALMOST_EPMTY + generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae + assign ALMOST_EMPTY = almost_empty_i; + end else begin : gnae + assign ALMOST_EMPTY = 0; + end endgenerate // gae + + // Assign ALMOST_FULL + generate if (C_HAS_ALMOST_FULL==1) begin : gaf + assign ALMOST_FULL = almost_full_i; + end else begin : gnaf + assign ALMOST_FULL = 0; + end endgenerate // gaf + + // Dout may change behavior based on latency + localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + + // Assign SBITERR and DBITERR based on latency + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + assign EMPTY = empty_i; + assign FULL = full_i; + //saftey_ckt with one register + + generate + if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin + + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge CLK) + begin + rst_delayed_sft1 <= #`TCQ rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) + begin + if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + valid_d1 <= #`TCQ 1'b0; + end + else begin + ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i)); + valid_d1 <= #`TCQ valid_i; + end + end + + always@(posedge rst_delayed_sft2 or posedge CLK) + begin + if (rst_delayed_sft2 == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + else if (srst_rrst_busy == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1[0] <= #`TCQ err_type[0]; + err_type_d1[1] <= #`TCQ err_type[1]; + end + end + end //if + endgenerate + +//safety ckt with both registers + +generate + if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin + + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge CLK) begin + rst_delayed_sft1 <= #`TCQ rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin + if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + valid_d1 <= #`TCQ 1'b0; + end else begin + ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i)); + fab_rd_en_d1 <= #`TCQ ram_rd_en_d1; + valid_both <= #`TCQ valid_i; + valid_d1 <= #`TCQ valid_both; + end + end + + always@(posedge rst_delayed_sft2 or posedge CLK) begin + if (rst_delayed_sft2 == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else if (srst_rrst_busy == 1'b1) begin + if (C_USE_DOUT_RST == 1'b1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else begin + if (ram_rd_en_d1) begin + ideal_dout_both <= #`TCQ ideal_dout; + err_type_both[0] <= #`TCQ err_type[0]; + err_type_both[1] <= #`TCQ err_type[1]; + end + if (fab_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout_both; + err_type_d1[0] <= #`TCQ err_type_both[0]; + err_type_d1[1] <= #`TCQ err_type_both[1]; + end + end + end + end //if + endgenerate + + + //Overflow may be active-low + generate if (C_HAS_OVERFLOW==1) begin : gof + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end else begin : gnof + assign OVERFLOW = 0; + end endgenerate // gof + + assign PROG_EMPTY = prog_empty_i; + assign PROG_FULL = prog_full_i; + + //Valid may change behavior based on latency or active-low + generate if (C_HAS_VALID==1) begin : gvalid + assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ? + valid_d1 : valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end else begin : gnvalid + assign VALID = 0; + end endgenerate // gvalid + + //Trim data count differently depending on set widths + generate if (C_HAS_DATA_COUNT == 1) begin : gdc + always @* begin + diff_count <= wr_pntr - rd_pntr; + if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin + DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count; + DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ; + end else begin + DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + end + end +// end else begin : gndc +// always @* DATA_COUNT <= 0; + end endgenerate // gdc + + //Underflow may change behavior based on latency or active-low + generate if (C_HAS_UNDERFLOW==1) begin : guf + assign underflow_i = ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end else begin : gnuf + assign UNDERFLOW = 0; + end endgenerate // guf + + + //Write acknowledge may be active low + generate if (C_HAS_WR_ACK==1) begin : gwr_ack + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end else begin : gnwr_ack + assign WR_ACK = 0; + end endgenerate // gwr_ack + + + /***************************************************************************** + * Internal reset logic + ****************************************************************************/ + assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0; + assign rst_i = C_HAS_RST ? RST : 0; + assign srst_wrst_busy = srst_i; + assign srst_rrst_busy = srst_i; + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20 + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= 1'b0; + end else begin + if (srst_rrst_busy) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate // blockVL20 + + generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= 1'b0; + valid_both <= 1'b0; + end else begin + if (srst_rrst_busy) begin + valid_d1 <= #`TCQ 1'b0; + valid_both <= #`TCQ 1'b0; + + end else begin + valid_both <= #`TCQ valid_i; + valid_d1 <= #`TCQ valid_both; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate // blockVL20 + + + // Determine which stage in FWFT registers are valid + reg stage1_valid = 0; + reg stage2_valid = 0; + generate + if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc + always @ (posedge CLK or posedge rst_i) begin + if (rst_i) begin + stage1_valid <= #`TCQ 0; + stage2_valid <= #`TCQ 0; + end else begin + + if (!stage1_valid && !stage2_valid) begin + if (!EMPTY) + stage1_valid <= #`TCQ 1'b1; + else + stage1_valid <= #`TCQ 1'b0; + end else if (stage1_valid && !stage2_valid) begin + if (EMPTY) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else if (!stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && RD_EN) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && !RD_EN) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end + end else if (stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + end + endgenerate + + + + //*************************************************************************** + // Assign the read data count value only if it is selected, + // otherwise output zeros. + //*************************************************************************** + generate + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}}; + end + endgenerate + + //*************************************************************************** + // Assign the write data count value only if it is selected, + // otherwise output zeros + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}}; + end + endgenerate + + //reg ram_rd_en_d1 = 1'b0; + //Capture delayed version of dout + generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + // DRAM and SRAM reset asynchronously + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + ram_rd_en_d1 <= #`TCQ 1'b0; + if (C_USE_DOUT_RST == 1) begin + @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else begin + ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY; + if (srst_rrst_busy) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + if (C_USE_DOUT_RST == 1) begin + // @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else begin + if (ram_rd_en_d1 ) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + end + end // always +end +endgenerate + +//no safety ckt with both registers + generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + fab_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + // DRAM and SRAM reset asynchronously + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + + end + if (C_USE_DOUT_RST == 1) begin + @(posedge CLK) + ideal_dout_d1 <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + end + end else begin + if (srst_rrst_busy) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + fab_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + if (C_USE_DOUT_RST == 1) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end else begin + ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY; + fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1); + if (ram_rd_en_d1 ) begin + ideal_dout_both <= #`TCQ ideal_dout; + err_type_both <= #`TCQ err_type; + end + if (fab_rd_en_d1 ) begin + ideal_dout_d1 <= #`TCQ ideal_dout_both; + err_type_d1 <= #`TCQ err_type_both; + end + end + end + end // always +end +endgenerate + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw + always @(posedge CLK) begin + ideal_overflow <= #`TCQ WR_EN & full_i; + end + end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw + always @(posedge CLK) begin + //ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i); + ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i); + end + end endgenerate // blockOF20 + + generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw + always @(posedge CLK) begin + ideal_underflow <= #`TCQ empty_i & RD_EN; + end + end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw + always @(posedge CLK) begin + //ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN; + ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN; + end + end endgenerate // blockUF20 + + + /************************** + * Read Data Count + *************************/ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************** + * Write Data Count + *************************/ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************************************************************* + * Write and Read Logic + ************************************************************************/ + wire write_allow; + wire read_allow; + wire read_allow_dc; + wire write_only; + wire read_only; + //wire write_only_q; + reg write_only_q; + //wire read_only_q; + reg read_only_q; + reg full_reg; + reg rst_full_ff_reg1; + reg rst_full_ff_reg2; + wire ram_full_comb; + wire carry; + + assign write_allow = WR_EN & ~full_i; + assign read_allow = RD_EN & ~empty_i; + assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB; + //assign write_only = write_allow & ~read_allow; + //assign write_only_q = write_allow_q; + //assign read_only = read_allow & ~write_allow; + //assign read_only_q = read_allow_q ; + wire [C_WR_PNTR_WIDTH-1:0] diff_pntr; + wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe; + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0; + reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0; + wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ; + wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym; + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max; + wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max; + + assign diff_pntr_pe_max = DIFF_MAX_RD; + assign diff_pntr_max = DIFF_MAX_WR; + + + + generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym + assign write_only = write_allow & ~read_allow; + assign read_only = read_allow & ~write_allow; + end endgenerate + generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd + assign read_only = read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow; + assign write_only = write_allow & ~(read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])); + end endgenerate + generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr + assign read_only = read_allow & ~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); + assign write_only = write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow; + end endgenerate + + + //----------------------------------------------------------------------------- + // Write and Read pointer generation + //----------------------------------------------------------------------------- + always @(posedge CLK or posedge rst_i) begin + if (rst_i && C_EN_SAFETY_CKT == 0) begin + wr_pntr <= 0; + rd_pntr <= 0; + end else begin + if (srst_i) begin + wr_pntr <= #`TCQ 0; + rd_pntr <= #`TCQ 0; + end else begin + if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1; + if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1; + end + end + end + + generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout + always @(posedge CLK) begin + if (write_allow) begin + if (ENABLE_ERR_INJECTION == 1) + memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN}; + else + memory[wr_pntr] <= #`TCQ DIN; + end + end + + reg [C_DATA_WIDTH-1:0] dout_tmp_q; + reg [C_DATA_WIDTH-1:0] dout_tmp = 0; + reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0; + always @(posedge CLK) begin + dout_tmp_q <= #`TCQ ideal_dout; + end + + + + always @* begin + if (read_allow) + ideal_dout <= memory[rd_pntr]; + else + ideal_dout <= dout_tmp_q; + end + end endgenerate // gll_dm_dout + + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + assign ram_rd_en = RD_EN & !EMPTY; + + //reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; + generate if (C_FIFO_TYPE != 2) begin : gnll_din + always @(posedge CLK or posedge rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (rst_i == 1'b1) begin + num_wr_bits <= #`TCQ 0; + next_num_wr_bits = #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ 0; + tmp_wr_listsize = #`TCQ 0; + rd_ptr_wrclk_next <= #`TCQ 0; + wr_pntr <= #`TCQ 0; + wr_pntr_rd1 <= #`TCQ 0; + + end else begin //rst_i==0 + if (srst_wrst_busy) begin + num_wr_bits <= #`TCQ 0; + next_num_wr_bits = #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ 0; + tmp_wr_listsize = #`TCQ 0; + rd_ptr_wrclk_next <= #`TCQ 0; + wr_pntr <= #`TCQ 0; + wr_pntr_rd1 <= #`TCQ 0; + end else begin//srst_i=0 + + wr_pntr_rd1 <= #`TCQ wr_pntr; + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + if (WR_EN == 1'b1) begin + if (FULL == 1'b1) begin + + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + end else begin + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Not even close to full. + ideal_wr_count <= num_write_words_sized_i; + + //end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end + num_wr_bits <= #`TCQ next_num_wr_bits; + rd_ptr_wrclk <= #`TCQ rd_ptr; + + end //srst_i==0 + end //wr_rst_i==0 + end // gen_fifo_w + end endgenerate + + generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout + always @(posedge CLK) begin + if (rst_i || srst_rrst_busy) begin + if (C_USE_DOUT_RST == 1) begin + ideal_dout <= #`TCQ dout_reset_val; + ideal_dout_both <= #`TCQ dout_reset_val; + end + end + end + end endgenerate + + + + + generate if (C_FIFO_TYPE != 2) begin : gnll_dout + always @(posedge CLK or posedge rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rst_i) begin + num_rd_bits <= #`TCQ 0; + next_num_rd_bits = #`TCQ 0; + rd_ptr <= #`TCQ C_RD_DEPTH -1; + rd_pntr <= #`TCQ 0; + //rd_pntr_wr1 <= #`TCQ 0; + wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1) + ideal_dout <= #`TCQ dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type <= #`TCQ 0; + err_type_d1 <= 0; + err_type_both <= 0; + end + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ 0; + + end else begin //rd_rst_i==0 + if (srst_rrst_busy) begin + num_rd_bits <= #`TCQ 0; + next_num_rd_bits = #`TCQ 0; + rd_ptr <= #`TCQ C_RD_DEPTH -1; + rd_pntr <= #`TCQ 0; + //rd_pntr_wr1 <= #`TCQ 0; + wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; + + // DRAM resets synchronously + if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1) + ideal_dout <= #`TCQ dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) begin + err_type <= #`TCQ 0; + err_type_d1 <= #`TCQ 0; + err_type_both <= #`TCQ 0; + end + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ 0; + end //srst_i + else begin + + //rd_pntr_wr1 <= #`TCQ rd_pntr; + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + if (RD_EN == 1'b1) begin + + if (EMPTY == 1'b1) begin + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + end + else + begin + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + end + + num_rd_bits <= #`TCQ next_num_rd_bits; + wr_ptr_rdclk <= #`TCQ wr_ptr; + end //s_rst_i==0 + end //rd_rst_i==0 + end //always + end endgenerate + + //----------------------------------------------------------------------------- + // Generate diff_pntr for PROG_FULL generation + // Generate diff_pntr_pe for PROG_EMPTY generation + //----------------------------------------------------------------------------- + generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow + always @(posedge CLK ) begin + if (rst_i) begin + write_only_q <= 1'b0; + read_only_q <= 1'b0; + diff_pntr_reg1 <= 0; + diff_pntr_pe_reg1 <= 0; + diff_pntr_reg2 <= 0; + diff_pntr_pe_reg2 <= 0; + end else begin + if (srst_i || srst_wrst_busy || srst_rrst_busy) begin + if (srst_rrst_busy) begin + read_only_q <= #`TCQ 1'b0; + diff_pntr_pe_reg1 <= #`TCQ 0; + diff_pntr_pe_reg2 <= #`TCQ 0; + end + if (srst_wrst_busy) begin + write_only_q <= #`TCQ 1'b0; + diff_pntr_reg1 <= #`TCQ 0; + diff_pntr_reg2 <= #`TCQ 0; + end + end else begin + write_only_q <= #`TCQ write_only; + read_only_q <= #`TCQ read_only; + diff_pntr_reg2 <= #`TCQ diff_pntr_reg1; + diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1; + + // Add 1 to the difference pointer value when only write happens. + if (write_only) + diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1; + else + diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr; + + // Add 1 to the difference pointer value when write or both write & read or no write & read happen. + if (read_only) + diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1; + else + diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr; + end + end + end + assign diff_pntr_pe = diff_pntr_pe_reg1; + assign diff_pntr = diff_pntr_reg1; + end endgenerate // reg_write_allow + + generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym + assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1}; + assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1}; + always @(posedge CLK ) begin + if (rst_i) begin + diff_pntr_pe_asym <= 0; + diff_pntr_reg1 <= 0; + full_reg <= 0; + rst_full_ff_reg1 <= 1; + rst_full_ff_reg2 <= 1; + diff_pntr_pe_reg1 <= 0; + end else begin + if (srst_i || srst_wrst_busy || srst_rrst_busy) begin + if (srst_wrst_busy) + diff_pntr_reg1 <= #`TCQ 0; + if (srst_rrst_busy) + full_reg <= #`TCQ 0; + rst_full_ff_reg1 <= #`TCQ 1; + rst_full_ff_reg2 <= #`TCQ 1; + diff_pntr_pe_asym <= #`TCQ 0; + diff_pntr_pe_reg1 <= #`TCQ 0; + end else begin + diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym; + full_reg <= #`TCQ full_i; + rst_full_ff_reg1 <= #`TCQ RST_FULL_FF; + rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1; + if (~full_i) begin + diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr; + end + end + end + end + assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1]))); + assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1]; + assign diff_pntr = diff_pntr_reg1; + end endgenerate // reg_write_allow_asym + + + //----------------------------------------------------------------------------- + // Generate FULL flag + //----------------------------------------------------------------------------- + wire comp0; + wire comp1; + wire going_full; + wire leaving_full; + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad + assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr; + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0; + end endgenerate + + generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim + assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end endgenerate + + assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1)); + assign comp0 = (adj_rd_pntr_wr == wr_pntr); + + generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp + assign going_full = (comp1 & write_allow & ~read_allow); + assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN; + end endgenerate + + // Write data width is bigger than read data width + // Write depth is smaller than read depth + // One write could be equal to 2 or 4 or 8 reads + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym + assign going_full = (comp1 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])))); + assign leaving_full = (comp0 & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN; + end endgenerate + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp + assign going_full = (comp1 & write_allow & ~read_allow); + assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN; + end endgenerate + + + assign ram_full_comb = going_full | (~leaving_full & full_i); + + generate if (C_HAS_RST == 1) begin : grst_full + always @(posedge CLK or posedge RST_FULL_FF) begin + if (RST_FULL_FF & C_HAS_RST) + full_i <= C_FULL_FLAGS_RST_VAL; + else + full_i <= #`TCQ ram_full_comb; + end + end endgenerate + + generate if (C_HAS_SRST == 1) begin : gsrst_full + always @(posedge CLK) begin + if (srst_wrst_busy) + full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else + full_i <= #`TCQ ram_full_comb; + end + end endgenerate + + generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_full + always @(posedge CLK) begin + full_i <= #`TCQ ram_full_comb; + end + end endgenerate + + //----------------------------------------------------------------------------- + // Generate EMPTY flag + //----------------------------------------------------------------------------- + wire ecomp0; + wire ecomp1; + wire going_empty; + wire leaving_empty; + wire ram_empty_comb; + + + generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad + assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0; + end endgenerate + + generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim + assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end endgenerate + + assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1)); + assign ecomp0 = (adj_wr_pntr_rd == rd_pntr); + + + generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp + assign going_empty = (ecomp1 & ~write_allow & read_allow); + assign leaving_empty = (ecomp0 & write_allow); + end endgenerate + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp + assign going_empty = (ecomp1 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])))); + assign leaving_empty = (ecomp0 & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); + end endgenerate + + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp + assign going_empty = (ecomp1 & ~write_allow & read_allow); + assign leaving_empty =(ecomp0 & write_allow); + end endgenerate + + + + assign ram_empty_comb = going_empty | (~leaving_empty & empty_i); + + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + empty_i <= 1'b1; + else if (srst_rrst_busy) + empty_i <= #`TCQ 1'b1; + else + empty_i <= #`TCQ ram_empty_comb; + end + always @(posedge CLK or posedge rst_i) begin + if (rst_i && C_EN_SAFETY_CKT == 0) begin + EMPTY_FB <= 1'b1; + end else begin + if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT)) + EMPTY_FB <= #`TCQ 1'b1; + else + EMPTY_FB <= #`TCQ ram_empty_comb; + end + end // always + + //----------------------------------------------------------------------------- + // Generate Read and write data counts for asymmetic common clock + //----------------------------------------------------------------------------- + + reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0; + wire [C_GRTR_PNTR_WIDTH :0] ratio; + wire decr_by_one; + wire incr_by_ratio; + wire incr_by_one; + wire decr_by_ratio; + + localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0; + + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr + assign ratio = C_DEPTH_RATIO_RD; + assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow; + assign incr_by_ratio = write_allow; + + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + count_dc <= #`TCQ 0; + else if (srst_wrst_busy) + count_dc <= #`TCQ 0; + else begin + if (decr_by_one) begin + if (!incr_by_ratio) + count_dc <= #`TCQ count_dc - 1; + else + count_dc <= #`TCQ count_dc - 1 + ratio ; + end + else begin + if (!incr_by_ratio) + count_dc <= #`TCQ count_dc ; + else + count_dc <= #`TCQ count_dc + ratio ; + end + end + end + + assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc; + assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + + end endgenerate + + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd + assign ratio = C_DEPTH_RATIO_WR; + assign incr_by_one = write_allow; + assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow; + + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + count_dc <= #`TCQ 0; + else if (srst_wrst_busy) + count_dc <= #`TCQ 0; + else begin + if (incr_by_one) begin + if (!decr_by_ratio) + count_dc <= #`TCQ count_dc + 1; + else + count_dc <= #`TCQ count_dc + 1 - ratio ; + end + else begin + if (!decr_by_ratio) + count_dc <= #`TCQ count_dc ; + else + count_dc <= #`TCQ count_dc - ratio ; + end + end + end + + assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc; + assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + + end endgenerate + + + + + + + //----------------------------------------------------------------------------- + // Generate WR_ACK flag + //----------------------------------------------------------------------------- + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + ideal_wr_ack <= 1'b0; + else if (srst_wrst_busy) + ideal_wr_ack <= #`TCQ 1'b0; + else if (WR_EN & ~full_i) + ideal_wr_ack <= #`TCQ 1'b1; + else + ideal_wr_ack <= #`TCQ 1'b0; + end + + //----------------------------------------------------------------------------- + // Generate VALID flag + //----------------------------------------------------------------------------- + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + ideal_valid <= 1'b0; + else if (srst_rrst_busy) + ideal_valid <= #`TCQ 1'b0; + else if (RD_EN & ~empty_i) + ideal_valid <= #`TCQ 1'b1; + else + ideal_valid <= #`TCQ 1'b0; + end + + + //----------------------------------------------------------------------------- + // Generate ALMOST_FULL flag + //----------------------------------------------------------------------------- + //generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss + + wire fcomp2; + wire going_afull; + wire leaving_afull; + wire ram_afull_comb; + + + assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2)); + + generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp + assign going_afull = (fcomp2 & write_allow & ~read_allow); + assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN; + end endgenerate + + // Write data width is bigger than read data width + // Write depth is smaller than read depth + // One write could be equal to 2 or 4 or 8 reads + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym + assign going_afull = (fcomp2 & write_allow & (~ (read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])))); + assign leaving_afull = (comp1 & (~write_allow) & read_allow & (&rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN; + end endgenerate + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp + assign going_afull = (fcomp2 & write_allow & ~read_allow); + assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN; + end endgenerate + + assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i); + + + generate if (C_HAS_RST == 1) begin : grst_afull + always @(posedge CLK or posedge RST_FULL_FF) begin + if (RST_FULL_FF & C_HAS_RST) + almost_full_i <= C_FULL_FLAGS_RST_VAL; + else + almost_full_i <= #`TCQ ram_afull_comb; + end + end endgenerate + + generate if (C_HAS_SRST == 1) begin : gsrst_afull + always @(posedge CLK) begin + if (srst_wrst_busy) + almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else + almost_full_i <= #`TCQ ram_afull_comb; + end + end endgenerate + + generate if (C_HAS_RST == 0 && C_HAS_SRST == 0) begin : gnrst_afull + always @(posedge CLK) begin + almost_full_i <= #`TCQ ram_afull_comb; + end + end endgenerate + + //----------------------------------------------------------------------------- + // Generate ALMOST_EMPTY flag + //----------------------------------------------------------------------------- + //generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss + + wire ecomp2; + wire going_aempty; + wire leaving_aempty; + wire ram_aempty_comb; + + assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2)); + + generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp + assign going_aempty = (ecomp2 & ~write_allow & read_allow); + assign leaving_aempty = (ecomp1 & write_allow & ~read_allow); + end endgenerate + + generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp + assign going_aempty = (ecomp2 & read_allow & (~(write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])))); + assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & (&wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0])); + end endgenerate + + generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp + assign going_aempty = (ecomp2 & ~write_allow & read_allow); + assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow); + end endgenerate + + + assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i); + + always @(posedge CLK or posedge rst_i) begin + if (rst_i) + almost_empty_i <= 1'b1; + else if (srst_rrst_busy) + almost_empty_i <= #`TCQ 1'b1; + else + almost_empty_i <= #`TCQ ram_aempty_comb; + end + // end endgenerate // gae_ss + + //----------------------------------------------------------------------------- + // Generate PROG_FULL + //----------------------------------------------------------------------------- + + localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? + C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT + C_PROG_FULL_THRESH_ASSERT_VAL; // STD + localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? + C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT + C_PROG_FULL_THRESH_NEGATE_VAL; // STD + + //----------------------------------------------------------------------------- + // Generate PROG_FULL for single programmable threshold constant + //----------------------------------------------------------------------------- + wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL; + generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const + always @(posedge CLK or posedge RST_FULL_FF) begin + if (RST_FULL_FF && C_HAS_RST) + prog_full_i <= C_FULL_FLAGS_RST_VAL; + else begin + if (srst_wrst_busy) + prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else if (IS_ASYMMETRY == 0) begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end + else begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~RST_FULL_GEN ) begin + if (diff_pntr>= C_PF_ASSERT_VAL ) + prog_full_i <= #`TCQ 1'b1; + else if ((diff_pntr) < C_PF_ASSERT_VAL ) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ 1'b0; + end + else + prog_full_i <= #`TCQ prog_full_i; + end + end + end + end endgenerate // single_pf_const + + //----------------------------------------------------------------------------- + // Generate PROG_FULL for multiple programmable threshold constants + //----------------------------------------------------------------------------- + generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const + always @(posedge CLK or posedge RST_FULL_FF) begin + //if (RST_FULL_FF) + if (RST_FULL_FF && C_HAS_RST) + prog_full_i <= C_FULL_FLAGS_RST_VAL; + else begin + if (srst_wrst_busy) + prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else if (IS_ASYMMETRY == 0) begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end + else begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~RST_FULL_GEN ) begin + if (diff_pntr >= C_PF_ASSERT_VAL ) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr < C_PF_NEGATE_VAL) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end + else + prog_full_i <= #`TCQ prog_full_i; + end + end + end + end endgenerate //multiple_pf_const + + //----------------------------------------------------------------------------- + // Generate PROG_FULL for single programmable threshold input port + //----------------------------------------------------------------------------- + wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ? + PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT + PROG_FULL_THRESH; // STD + generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input + + always @(posedge CLK or posedge RST_FULL_FF) begin//0 + //if (RST_FULL_FF) + if (RST_FULL_FF && C_HAS_RST) + prog_full_i <= C_FULL_FLAGS_RST_VAL; + else begin //1 + if (srst_wrst_busy) + prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else if (IS_ASYMMETRY == 0) begin//2 + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~almost_full_i) begin//3 + if (diff_pntr > pf3_assert_val) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr == pf3_assert_val) begin//4 + if (read_only_q) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ 1'b1; + end else//4 + prog_full_i <= #`TCQ 1'b0; + end else//3 + prog_full_i <= #`TCQ prog_full_i; + end //2 + else begin//5 + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~full_i ) begin//6 + if (diff_pntr >= pf3_assert_val ) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr < pf3_assert_val) begin//7 + prog_full_i <= #`TCQ 1'b0; + end//7 + end//6 + else + prog_full_i <= #`TCQ prog_full_i; + end//5 + end//1 + end//0 + end endgenerate //single_pf_input + + //----------------------------------------------------------------------------- + // Generate PROG_FULL for multiple programmable threshold input ports + //----------------------------------------------------------------------------- + wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT + PROG_FULL_THRESH_ASSERT; // STD + wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT + PROG_FULL_THRESH_NEGATE; // STD + + generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs + always @(posedge CLK or posedge RST_FULL_FF) begin + if (RST_FULL_FF && C_HAS_RST) + prog_full_i <= C_FULL_FLAGS_RST_VAL; + else begin + if (srst_wrst_busy) + prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL; + else if (IS_ASYMMETRY == 0) begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~almost_full_i) begin + if (diff_pntr >= pf_assert_val) + prog_full_i <= #`TCQ 1'b1; + else if ((diff_pntr == pf_negate_val && read_only_q) || + diff_pntr < pf_negate_val) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end else + prog_full_i <= #`TCQ prog_full_i; + end + else begin + if (RST_FULL_GEN) + prog_full_i <= #`TCQ 1'b0; + else if (~full_i ) begin + if (diff_pntr >= pf_assert_val ) + prog_full_i <= #`TCQ 1'b1; + else if (diff_pntr < pf_negate_val) + prog_full_i <= #`TCQ 1'b0; + else + prog_full_i <= #`TCQ prog_full_i; + end + else + prog_full_i <= #`TCQ prog_full_i; + end + + end + end + end endgenerate //multiple_pf_inputs + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY + //----------------------------------------------------------------------------- + localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ? + C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT + C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD + localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ? + C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT + C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY for single programmable threshold constant + //----------------------------------------------------------------------------- + generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const + always @(posedge CLK or posedge rst_i) begin + //if (rst_i) + if (rst_i && C_HAS_RST) + prog_empty_i <= 1'b1; + else begin + if (srst_rrst_busy) + prog_empty_i <= #`TCQ 1'b1; + else if (IS_ASYMMETRY == 0) begin + if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + else begin + if (~rst_i ) begin + if (diff_pntr_pe <= C_PE_ASSERT_VAL) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe > C_PE_ASSERT_VAL) + prog_empty_i <= #`TCQ 1'b0; + end + else + prog_empty_i <= #`TCQ prog_empty_i; + end + end + end + end endgenerate // single_pe_const + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY for multiple programmable threshold constants + //----------------------------------------------------------------------------- + generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const + always @(posedge CLK or posedge rst_i) begin + //if (rst_i) + if (rst_i && C_HAS_RST) + prog_empty_i <= 1'b1; + else begin + if (srst_rrst_busy) + prog_empty_i <= #`TCQ 1'b1; + else if (IS_ASYMMETRY == 0) begin + if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + else begin + if (~rst_i ) begin + if (diff_pntr_pe <= C_PE_ASSERT_VAL ) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe > C_PE_NEGATE_VAL) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + else + prog_empty_i <= #`TCQ prog_empty_i; + end + + end + + end + end endgenerate //multiple_pe_const + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY for single programmable threshold input port + //----------------------------------------------------------------------------- + wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_EMPTY_THRESH -2) : // FWFT + PROG_EMPTY_THRESH; // STD + generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input + always @(posedge CLK or posedge rst_i) begin + //if (rst_i) + if (rst_i && C_HAS_RST) + prog_empty_i <= 1'b1; + else begin + if (srst_rrst_busy) + prog_empty_i <= #`TCQ 1'b1; + else if (IS_ASYMMETRY == 0) begin + if (~almost_full_i) begin + if (diff_pntr_pe < pe3_assert_val) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe == pe3_assert_val) begin + if (write_only_q) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ 1'b1; + end else + prog_empty_i <= #`TCQ 1'b0; + end else + prog_empty_i <= #`TCQ prog_empty_i; + end + else begin + if (diff_pntr_pe <= pe3_assert_val ) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe > pe3_assert_val) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + end + + end + end endgenerate // single_pe_input + + //----------------------------------------------------------------------------- + // Generate PROG_EMPTY for multiple programmable threshold input ports + //----------------------------------------------------------------------------- + wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT + PROG_EMPTY_THRESH_ASSERT; // STD + wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ? + (PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT + PROG_EMPTY_THRESH_NEGATE; // STD + generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs + always @(posedge CLK or posedge rst_i) begin + //if (rst_i) + if (rst_i && C_HAS_RST) + prog_empty_i <= 1'b1; + else begin + if (srst_rrst_busy) + prog_empty_i <= #`TCQ 1'b1; + else if (IS_ASYMMETRY == 0) begin + if (~almost_full_i) begin + if (diff_pntr_pe <= pe4_assert_val) + prog_empty_i <= #`TCQ 1'b1; + else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) || + (diff_pntr_pe > pe4_negate_val)) begin + prog_empty_i <= #`TCQ 1'b0; + end else + prog_empty_i <= #`TCQ prog_empty_i; + end else + prog_empty_i <= #`TCQ prog_empty_i; + end + else begin + if (diff_pntr_pe <= pe4_assert_val ) + prog_empty_i <= #`TCQ 1'b1; + else if (diff_pntr_pe > pe4_negate_val) + prog_empty_i <= #`TCQ 1'b0; + else + prog_empty_i <= #`TCQ prog_empty_i; + end + end + end + end endgenerate // multiple_pe_inputs + +endmodule // fifo_generator_v13_2_4_bhv_ver_ss + + + +/************************************************************************** + * First-Word Fall-Through module (preload 0) + **************************************************************************/ +module fifo_generator_v13_2_4_bhv_ver_preload0 + #( + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_HAS_RST = 0, + parameter C_ENABLE_RST_SYNC = 0, + parameter C_HAS_SRST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_EN_SAFETY_CKT = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_ECC = 0, + parameter C_USERVALID_LOW = 0, + parameter C_USERUNDERFLOW_LOW = 0, + parameter C_MEMORY_TYPE = 0, + parameter C_FIFO_TYPE = 0 + ) + ( + //Inputs + input SAFETY_CKT_RD_RST, + input RD_CLK, + input RD_RST, + input SRST, + input WR_RST_BUSY, + input RD_RST_BUSY, + input RD_EN, + input FIFOEMPTY, + input [C_DOUT_WIDTH-1:0] FIFODATA, + input FIFOSBITERR, + input FIFODBITERR, + + //Outputs + output reg [C_DOUT_WIDTH-1:0] USERDATA, + output USERVALID, + output USERUNDERFLOW, + output USEREMPTY, + output USERALMOSTEMPTY, + output RAMVALID, + output FIFORDEN, + output reg USERSBITERR, + output reg USERDBITERR, + output reg STAGE2_REG_EN, + output fab_read_data_valid_i_o, + output read_data_valid_i_o, + output ram_valid_i_o, + output [1:0] VALID_STAGES + ); + //Internal signals + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg fab_valid; + reg read_data_valid_i; + reg fab_read_data_valid_i; + reg fab_read_data_valid_i_1; + reg ram_valid_i_d; + reg read_data_valid_i_d; + reg fab_read_data_valid_i_d; + wire ram_regout_en; + reg ram_regout_en_d1; + reg ram_regout_en_d2; + wire fab_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_sckt = 1'b1; + reg sckt_rrst_q = 1'b0; + reg sckt_rrst_done = 1'b0; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + wire srst_i; + reg [C_DOUT_WIDTH-1:0] userdata_both; + wire uservalid_both; + wire uservalid_one; + reg user_sbiterr_both = 1'b0; + reg user_dbiterr_both = 1'b0; + +assign ram_valid_i_o = ram_valid_i; +assign read_data_valid_i_o = read_data_valid_i; +assign fab_read_data_valid_i_o = fab_read_data_valid_i; + + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + //************************************************************************* + // Set power-on states for regs + //************************************************************************* + initial begin + ram_valid_i = 1'b0; + fab_valid = 1'b0; + read_data_valid_i = 1'b0; + fab_read_data_valid_i = 1'b0; + fab_read_data_valid_i_1 = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + userdata_both = hexstr_conv(C_DOUT_RST_VAL); + USERSBITERR = 1'b0; + USERDBITERR = 1'b0; + user_sbiterr_both = 1'b0; + user_dbiterr_both = 1'b0; + end //initial + + //*************************************************************************** + // connect up optional reset + //*************************************************************************** + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; + assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0; + + reg sckt_rd_rst_fwft = 1'b0; + reg fwft_rst_done_i = 1'b0; + wire fwft_rst_done; + assign fwft_rst_done = 1'b1;//C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1; + always @ (posedge RD_CLK) begin + sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST; + end + + always @ (posedge rd_rst_i or posedge RD_CLK) begin + if (rd_rst_i) + fwft_rst_done_i <= 1'b0; + else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST) + fwft_rst_done_i <= #`TCQ 1'b1; + end + + localparam INVALID = 0; + localparam STAGE1_VALID = 2; + localparam STAGE2_VALID = 1; + localparam BOTH_STAGES_VALID = 3; + + reg [1:0] curr_fwft_state = INVALID; + reg [1:0] next_fwft_state = INVALID; + + +generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin + always @* begin + case (curr_fwft_state) + INVALID: begin + if (~FIFOEMPTY) + next_fwft_state <= STAGE1_VALID; + else + next_fwft_state <= INVALID; + end + STAGE1_VALID: begin + if (FIFOEMPTY) + next_fwft_state <= STAGE2_VALID; + else + next_fwft_state <= BOTH_STAGES_VALID; + end + STAGE2_VALID: begin + if (FIFOEMPTY && RD_EN) + next_fwft_state <= INVALID; + else if (~FIFOEMPTY && RD_EN) + next_fwft_state <= STAGE1_VALID; + else if (~FIFOEMPTY && ~RD_EN) + next_fwft_state <= BOTH_STAGES_VALID; + else + next_fwft_state <= STAGE2_VALID; + end + BOTH_STAGES_VALID: begin + if (FIFOEMPTY && RD_EN) + next_fwft_state <= STAGE2_VALID; + else if (~FIFOEMPTY && RD_EN) + next_fwft_state <= BOTH_STAGES_VALID; + else + next_fwft_state <= BOTH_STAGES_VALID; + end + default: next_fwft_state <= INVALID; + endcase + end + + always @ (posedge rd_rst_i or posedge RD_CLK) begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) + curr_fwft_state <= INVALID; + else if (srst_i) + curr_fwft_state <= #`TCQ INVALID; + else + curr_fwft_state <= #`TCQ next_fwft_state; + end + + always @* begin + case (curr_fwft_state) + INVALID: STAGE2_REG_EN <= 1'b0; + STAGE1_VALID: STAGE2_REG_EN <= 1'b1; + STAGE2_VALID: STAGE2_REG_EN <= 1'b0; + BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN; + default: STAGE2_REG_EN <= 1'b0; + endcase + end + + + assign VALID_STAGES = curr_fwft_state; + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN ); + + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = preloadstage2; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + end +endgenerate // gnll_fifo + + reg curr_state = 0; + reg next_state = 0; + reg leaving_empty_fwft = 0; + reg going_empty_fwft = 0; + reg empty_i_q = 0; + reg ram_rd_en_fwft = 0; + generate if (C_FIFO_TYPE == 2) begin : gll_fifo + always @* begin // FSM fo FWFT + case (curr_state) + 1'b0: begin + if (~FIFOEMPTY) + next_state <= 1'b1; + else + next_state <= 1'b0; + end + 1'b1: begin + if (FIFOEMPTY && RD_EN) + next_state <= 1'b0; + else + next_state <= 1'b1; + end + default: next_state <= 1'b0; + endcase + end + + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + empty_i <= 1'b1; + empty_i_q <= 1'b1; + ram_valid_i <= 1'b0; + end else if (srst_i) begin + empty_i <= #`TCQ 1'b1; + empty_i_q <= #`TCQ 1'b1; + ram_valid_i <= #`TCQ 1'b0; + end else begin + empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i); + empty_i_q <= #`TCQ FIFOEMPTY; + ram_valid_i <= #`TCQ next_state; + end + end //always + + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin + curr_state <= 1'b0; + end else if (srst_i) begin + curr_state <= #`TCQ 1'b0; + end else begin + curr_state <= #`TCQ next_state; + end + end //always + + wire fe_of_empty; + assign fe_of_empty = empty_i_q & ~FIFOEMPTY; + + always @* begin // Finding leaving empty + case (curr_state) + 1'b0: leaving_empty_fwft <= fe_of_empty; + 1'b1: leaving_empty_fwft <= 1'b1; + default: leaving_empty_fwft <= 1'b0; + endcase + end + + always @* begin // Finding going empty + case (curr_state) + 1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN; + default: going_empty_fwft <= 1'b0; + endcase + end + + always @* begin // Generating FWFT rd_en + case (curr_state) + 1'b0: ram_rd_en_fwft <= ~FIFOEMPTY; + 1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN; + default: ram_rd_en_fwft <= 1'b0; + endcase + end + + assign ram_regout_en = ram_rd_en_fwft; + //assign ram_regout_en_d1 = ram_rd_en_fwft; + //assign ram_regout_en_d2 = ram_rd_en_fwft; + assign ram_rd_en = ram_rd_en_fwft; + end endgenerate // gll_fifo + + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (ram_rd_en == 1'b1) begin + ram_valid_i <= #`TCQ 1'b1; + end else begin + if (ram_regout_en == 1'b1) + ram_valid_i <= #`TCQ 1'b0; + else + ram_valid_i <= #`TCQ ram_valid_i; + end + end //srst_i + end //rd_rst_i + end //always + end endgenerate // gnll_fifo_ram_valid + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + + generate if(C_USE_EMBEDDED_REG < 3) begin + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + read_data_valid_i <= #`TCQ 1'b0; + else + read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always +end +endgenerate + + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + // rising clock edge + empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + end + end + end //always + end endgenerate // gnll_fifo_empty + + // Register RD_EN from user to calculate USERUNDERFLOW. + // Register empty_i to calculate USERUNDERFLOW. + always @ (posedge RD_CLK) begin + rd_en_q <= #`TCQ RD_EN; + empty_q <= #`TCQ empty_i; + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + generate if ( C_USE_EMBEDDED_REG < 3) begin + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= #`TCQ FIFOEMPTY; + end + almost_empty_q <= #`TCQ empty_i; + end + end + end //always +end +endgenerate + + + + // BRAM resets synchronously + generate + if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin + always @ ( posedge rd_rst_i) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) + @(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end //always + + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1) begin + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end else if (fwft_rst_done) begin + if (ram_regout_en) begin + USERDATA <= #`TCQ FIFODATA; + USERSBITERR <= #`TCQ FIFOSBITERR; + USERDBITERR <= #`TCQ FIFODBITERR; + end + end + end + end //always + end //if + endgenerate +//safety ckt with one register +generate + if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge RD_CLK) + begin + rst_delayed_sft1 <= #`TCQ rd_rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always @ (posedge RD_CLK) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin + @(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end + end //always + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high) + //@(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end + else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1) begin + // @(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end else if (fwft_rst_done) begin + if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin + USERDATA <= #`TCQ FIFODATA; + USERSBITERR <= #`TCQ FIFOSBITERR; + USERDBITERR <= #`TCQ FIFODBITERR; + end + end + end + end //always + end //if +endgenerate + + +generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin + + + always @* begin + case (curr_fwft_state) + INVALID: begin + if (~FIFOEMPTY) + next_fwft_state <= STAGE1_VALID; + else + next_fwft_state <= INVALID; + end + STAGE1_VALID: begin + if (FIFOEMPTY) + next_fwft_state <= STAGE2_VALID; + else + next_fwft_state <= BOTH_STAGES_VALID; + end + STAGE2_VALID: begin + if (FIFOEMPTY && RD_EN) + next_fwft_state <= INVALID; + else if (~FIFOEMPTY && RD_EN) + next_fwft_state <= STAGE1_VALID; + else if (~FIFOEMPTY && ~RD_EN) + next_fwft_state <= BOTH_STAGES_VALID; + else + next_fwft_state <= STAGE2_VALID; + end + BOTH_STAGES_VALID: begin + if (FIFOEMPTY && RD_EN) + next_fwft_state <= STAGE2_VALID; + else if (~FIFOEMPTY && RD_EN) + next_fwft_state <= BOTH_STAGES_VALID; + else + next_fwft_state <= BOTH_STAGES_VALID; + end + default: next_fwft_state <= INVALID; + endcase + end + + always @ (posedge rd_rst_i or posedge RD_CLK) begin + if (rd_rst_i && C_EN_SAFETY_CKT == 0) + curr_fwft_state <= INVALID; + else if (srst_i) + curr_fwft_state <= #`TCQ INVALID; + else + curr_fwft_state <= #`TCQ next_fwft_state; + end + + always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay + if (rd_rst_i == 1) begin + ram_regout_en_d1 <= #`TCQ 1'b0; + end + else begin + if (srst_i == 1'b1) + ram_regout_en_d1 <= #`TCQ 1'b0; + else + ram_regout_en_d1 <= #`TCQ ram_regout_en; + end + end //always + // assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i)); + assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0; + + always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1 + if (rd_rst_i == 1) begin + ram_regout_en_d2 <= #`TCQ 1'b0; + end + else begin + if (srst_i == 1'b1) + ram_regout_en_d2 <= #`TCQ 1'b0; + else + ram_regout_en_d2 <= #`TCQ ram_regout_en_d1; + end + end //always + + + + always @* begin + case (curr_fwft_state) + INVALID: STAGE2_REG_EN <= 1'b0; + STAGE1_VALID: STAGE2_REG_EN <= 1'b1; + STAGE2_VALID: STAGE2_REG_EN <= 1'b0; + BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN; + default: STAGE2_REG_EN <= 1'b0; + endcase + end + + always @ (posedge RD_CLK) begin + ram_valid_i_d <= #`TCQ ram_valid_i; + read_data_valid_i_d <= #`TCQ read_data_valid_i; + fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i; + + end + assign VALID_STAGES = curr_fwft_state; + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN ); + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1; + end + endgenerate // gnll_fifo + + + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid + + + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + fab_valid <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + fab_valid <= #`TCQ 1'b0; + end else begin + if (ram_regout_en == 1'b1) begin + fab_valid <= #`TCQ 1'b1; + end else begin + if (fab_regout_en == 1'b1) + fab_valid <= #`TCQ 1'b0; + else + fab_valid <= #`TCQ fab_valid; + end + end //srst_i + end //rd_rst_i + end //always + end endgenerate // gnll_fifo_fab_valid + + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + generate if(C_USE_EMBEDDED_REG == 3) begin + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + read_data_valid_i <= #`TCQ 1'b0; + else begin + if (ram_regout_en == 1'b1) begin + read_data_valid_i <= #`TCQ 1'b1; + end else begin + if (fab_regout_en == 1'b1) + read_data_valid_i <= #`TCQ 1'b0; + else + read_data_valid_i <= #`TCQ read_data_valid_i; + end + end + end //always +end +endgenerate + +//generate if(C_USE_EMBEDDED_REG == 3) begin +// always @ (posedge RD_CLK or posedge rd_rst_i) begin +// if (rd_rst_i) +// read_data_valid_i <= #`TCQ 1'b0; +// else if (srst_i) +// read_data_valid_i <= #`TCQ 1'b0; +// +// if (ram_regout_en == 1'b1) begin +// fab_read_data_valid_i <= #`TCQ 1'b0; +// end else begin +// if (fab_regout_en == 1'b1) +// fab_read_data_valid_i <= #`TCQ 1'b1; +// else +// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i; +// end +// end //always +//end +//endgenerate + + generate if(C_USE_EMBEDDED_REG == 3 ) begin + always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid + if (rd_rst_i) + fab_read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + fab_read_data_valid_i <= #`TCQ 1'b0; + else + fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN); + end //always +end +endgenerate + +always @ (posedge RD_CLK ) begin : proc_del1 + begin + fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i; + end + end //always + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + // rising clock edge + empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN); + end + end + end //always + end endgenerate // gnll_fifo_empty_both + + // Register RD_EN from user to calculate USERUNDERFLOW. + // Register empty_i to calculate USERUNDERFLOW. + always @ (posedge RD_CLK) begin + rd_en_q <= #`TCQ RD_EN; + empty_q <= #`TCQ empty_i; + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + reg FIFOEMPTY_1; + generate if (C_USE_EMBEDDED_REG == 3 ) begin + always @(posedge RD_CLK) begin + FIFOEMPTY_1 <= #`TCQ FIFOEMPTY; + end + end +endgenerate + generate if (C_USE_EMBEDDED_REG == 3 ) begin + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin + if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= #`TCQ (~ram_valid_i); + end + almost_empty_q <= #`TCQ empty_i; + end + end + end //always +end +endgenerate + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + empty_sckt <= #`TCQ 1'b1; + sckt_rrst_q <= #`TCQ 1'b0; + sckt_rrst_done <= #`TCQ 1'b0; + end else begin + sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST; + if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin + sckt_rrst_done <= #`TCQ 1'b1; + end else if (sckt_rrst_done) begin + // rising clock edge + empty_sckt <= #`TCQ 1'b0; + end + end + end //always + + +// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i; + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i; + assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0); + assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0); + assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one; + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; +//no safety ckt with both reg +generate + if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin + always @ (posedge RD_CLK) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end //always + + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end else begin + if (fwft_rst_done) begin + if (ram_regout_en) begin + userdata_both <= #`TCQ FIFODATA; + user_dbiterr_both <= #`TCQ FIFODBITERR; + user_sbiterr_both <= #`TCQ FIFOSBITERR; + end + if (fab_regout_en) begin + USERDATA <= #`TCQ userdata_both; + USERDBITERR <= #`TCQ user_dbiterr_both; + USERSBITERR <= #`TCQ user_sbiterr_both; + end + end + end + end + end //always + end //if + endgenerate + +//safety_ckt with both registers + generate + if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1; + reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2; + reg [1:0] rst_delayed_sft1 =1; + reg [1:0] rst_delayed_sft2 =1; + reg [1:0] rst_delayed_sft3 =1; + reg [1:0] rst_delayed_sft4 =1; + + always@(posedge RD_CLK) begin + rst_delayed_sft1 <= #`TCQ rd_rst_i; + rst_delayed_sft2 <= #`TCQ rst_delayed_sft1; + rst_delayed_sft3 <= #`TCQ rst_delayed_sft2; + rst_delayed_sft4 <= #`TCQ rst_delayed_sft3; + end + always @ (posedge RD_CLK) begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin + @(posedge RD_CLK) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end + end //always + + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + user_sbiterr_both <= #`TCQ 0; + user_dbiterr_both <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end else if (fwft_rst_done) begin + if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin + userdata_both <= #`TCQ FIFODATA; + user_dbiterr_both <= #`TCQ FIFODBITERR; + user_sbiterr_both <= #`TCQ FIFOSBITERR; + end + if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin + USERDATA <= #`TCQ userdata_both; + USERDBITERR <= #`TCQ user_dbiterr_both; + USERSBITERR <= #`TCQ user_sbiterr_both; + end + end + end + end //always + end //if +endgenerate + +endmodule //fifo_generator_v13_2_4_bhv_ver_preload0 + + +//----------------------------------------------------------------------------- +// +// Register Slice +// Register one AXI channel on forward and/or reverse signal path +// +// Verilog-standard: Verilog 2001 +//-------------------------------------------------------------------------- +// +// Structure: +// reg_slice +// +//-------------------------------------------------------------------------- + +module fifo_generator_v13_2_4_axic_reg_slice # + ( + parameter C_FAMILY = "virtex7", + parameter C_DATA_WIDTH = 32, + parameter C_REG_CONFIG = 32'h00000000 + ) + ( + // System Signals + input wire ACLK, + input wire ARESET, + + // Slave side + input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA, + input wire S_VALID, + output wire S_READY, + + // Master side + output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA, + output wire M_VALID, + input wire M_READY + ); + + localparam RST_SYNC_STAGES = 5; + localparam RST_BUSY_LEN = 6; + reg [1:0] arst_sync_wr = 2'b11; + reg [RST_BUSY_LEN-1:0] sckt_wr_rst_cc = 0; + wire sync_reset; + wire extnd_reset; + + + always @(posedge ARESET or posedge ACLK) begin + if (ARESET) + arst_sync_wr <= 2'b11; + else + arst_sync_wr <= #`TCQ {arst_sync_wr[0], 1'b0}; + end + + always @(posedge ACLK) begin + sckt_wr_rst_cc <= #`TCQ {sckt_wr_rst_cc[RST_BUSY_LEN-2:0], arst_sync_wr[1]}; + end + + assign sync_reset = |sckt_wr_rst_cc[RST_BUSY_LEN-5:0] | arst_sync_wr[1]; + assign extnd_reset = |sckt_wr_rst_cc | arst_sync_wr[1]; + generate + //////////////////////////////////////////////////////////////////// + // + // Both FWD and REV mode + // + //////////////////////////////////////////////////////////////////// + if (C_REG_CONFIG == 32'h00000000) + begin + reg [1:0] state; + localparam [1:0] + ZERO = 2'b10, + ONE = 2'b11, + TWO = 2'b01; + + reg [C_DATA_WIDTH-1:0] storage_data1 = 0; + reg [C_DATA_WIDTH-1:0] storage_data2 = 0; + reg load_s1; + wire load_s2; + wire load_s1_from_s2; + reg s_ready_i; //local signal of output + wire m_valid_i; //local signal of output + + // assign local signal to its output signal + assign S_READY = s_ready_i; + assign M_VALID = m_valid_i; + + reg areset_d1; // Reset delay register + always @(posedge ACLK) begin + areset_d1 <= extnd_reset; + end + + // Load storage1 with either slave side data or from storage2 + always @(posedge ACLK) + begin + if (load_s1) + if (load_s1_from_s2) + storage_data1 <= storage_data2; + else + storage_data1 <= S_PAYLOAD_DATA; + end + + // Load storage2 with slave side data + always @(posedge ACLK) + begin + if (load_s2) + storage_data2 <= S_PAYLOAD_DATA; + end + + assign M_PAYLOAD_DATA = storage_data1; + + // Always load s2 on a valid transaction even if it's unnecessary + assign load_s2 = S_VALID & s_ready_i; + + // Loading s1 + always @ * + begin + if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction + // Load when ONE if we both have read and write at the same time + ((state == ONE) && (S_VALID == 1) && (M_READY == 1)) || + // Load when TWO and we have a transaction on Master side + ((state == TWO) && (M_READY == 1))) + load_s1 = 1'b1; + else + load_s1 = 1'b0; + end // always @ * + + assign load_s1_from_s2 = (state == TWO); + + // State Machine for handling output signals + always @(posedge ACLK) begin + if (sync_reset || extnd_reset) begin + s_ready_i <= 1'b0; + state <= ZERO; + end else if (areset_d1 && ~extnd_reset) begin + s_ready_i <= 1'b1; + end else begin + case (state) + // No transaction stored locally + ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE + + // One transaction stored locally + ONE: begin + if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO + if (~M_READY & S_VALID) begin + state <= TWO; // Got another one so move to TWO + s_ready_i <= 1'b0; + end + end + + // TWO transaction stored locally + TWO: if (M_READY) begin + state <= ONE; // Read out one so move to ONE + s_ready_i <= 1'b1; + end + endcase // case (state) + end + end // always @ (posedge ACLK) + + assign m_valid_i = state[0]; + + end // if (C_REG_CONFIG == 1) + //////////////////////////////////////////////////////////////////// + // + // 1-stage pipeline register with bubble cycle, both FWD and REV pipelining + // Operates same as 1-deep FIFO + // + //////////////////////////////////////////////////////////////////// + else if (C_REG_CONFIG == 32'h00000001) + begin + reg [C_DATA_WIDTH-1:0] storage_data1 = 0; + reg s_ready_i; //local signal of output + reg m_valid_i; //local signal of output + + // assign local signal to its output signal + assign S_READY = s_ready_i; + assign M_VALID = m_valid_i; + + reg areset_d1; // Reset delay register + always @(posedge ACLK) begin + areset_d1 <= extnd_reset; + end + + // Load storage1 with slave side data + always @(posedge ACLK) + begin + if (sync_reset || extnd_reset) begin + s_ready_i <= 1'b0; + m_valid_i <= 1'b0; + end else if (areset_d1 && ~extnd_reset) begin + s_ready_i <= 1'b1; + end else if (m_valid_i & M_READY) begin + s_ready_i <= 1'b1; + m_valid_i <= 1'b0; + end else if (S_VALID & s_ready_i) begin + s_ready_i <= 1'b0; + m_valid_i <= 1'b1; + end + if (~m_valid_i) begin + storage_data1 <= S_PAYLOAD_DATA; + end + end + assign M_PAYLOAD_DATA = storage_data1; + end // if (C_REG_CONFIG == 7) + + else begin : default_case + // Passthrough + assign M_PAYLOAD_DATA = S_PAYLOAD_DATA; + assign M_VALID = S_VALID; + assign S_READY = M_READY; + end + + endgenerate +endmodule // reg_slice diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, 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a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/mem_init_files/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/README.txt new file mode 100644 index 00000000..41d9b74a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fifo_48m_to_122p88m.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fifo_48m_to_122p88m.sh' script. + +./fifo_48m_to_122p88m.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fifo_48m_to_122p88m.sh -noclean_files + +For more information on the script, please type './fifo_48m_to_122p88m.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/compile.do new file mode 100644 index 00000000..aaf473a9 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/compile.do @@ -0,0 +1,33 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm +vlib activehdl/fifo_generator_v13_2_4 + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm +vmap fifo_generator_v13_2_4 activehdl/fifo_generator_v13_2_4 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_4 -v2k5 \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_4 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_4 -v2k5 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/fifo_48m_to_122p88m.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/fifo_48m_to_122p88m.sh new file mode 100755 index 00000000..b96a3e12 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/fifo_48m_to_122p88m.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_48m_to_122p88m.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_48m_to_122p88m.sh [-help] +# usage: fifo_48m_to_122p88m.sh [-lib_map_path] +# usage: fifo_48m_to_122p88m.sh [-noclean_files] +# usage: fifo_48m_to_122p88m.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_48m_to_122p88m.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "fifo_48m_to_122p88m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_48m_to_122p88m.sh [-help]\n\ +Usage: fifo_48m_to_122p88m.sh [-lib_map_path]\n\ +Usage: fifo_48m_to_122p88m.sh [-reset_run]\n\ +Usage: fifo_48m_to_122p88m.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/fifo_48m_to_122p88m.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/fifo_48m_to_122p88m.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/file_info.txt new file mode 100644 index 00000000..c802fd31 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +fifo_48m_to_122p88m.v,verilog,xil_defaultlib,../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/simulate.do new file mode 100644 index 00000000..5dbd10b3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+fifo_48m_to_122p88m -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fifo_48m_to_122p88m xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {fifo_48m_to_122p88m.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/README.txt new file mode 100644 index 00000000..260a7279 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fifo_48m_to_122p88m.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fifo_48m_to_122p88m.sh' script. + +./fifo_48m_to_122p88m.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fifo_48m_to_122p88m.sh -noclean_files + +For more information on the script, please type './fifo_48m_to_122p88m.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/fifo_48m_to_122p88m.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/fifo_48m_to_122p88m.sh new file mode 100755 index 00000000..d3289955 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/fifo_48m_to_122p88m.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_48m_to_122p88m.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_48m_to_122p88m.sh [-help] +# usage: fifo_48m_to_122p88m.sh [-lib_map_path] +# usage: fifo_48m_to_122p88m.sh [-noclean_files] +# usage: fifo_48m_to_122p88m.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_48m_to_122p88m.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm fifo_generator_v13_2_4) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "fifo_48m_to_122p88m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.fifo_48m_to_122p88m \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_48m_to_122p88m.sh [-help]\n\ +Usage: fifo_48m_to_122p88m.sh [-lib_map_path]\n\ +Usage: fifo_48m_to_122p88m.sh [-reset_run]\n\ +Usage: fifo_48m_to_122p88m.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/file_info.txt new file mode 100644 index 00000000..c802fd31 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +fifo_48m_to_122p88m.v,verilog,xil_defaultlib,../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/run.f new file mode 100644 index 00000000..bd75ee2d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/ies/run.f @@ -0,0 +1,23 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/fifo_generator_v13_2_4 \ + "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ +-endlib +-makelib ies_lib/fifo_generator_v13_2_4 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ +-endlib +-makelib ies_lib/fifo_generator_v13_2_4 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/README.txt new file mode 100644 index 00000000..41d9b74a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fifo_48m_to_122p88m.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fifo_48m_to_122p88m.sh' script. + +./fifo_48m_to_122p88m.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fifo_48m_to_122p88m.sh -noclean_files + +For more information on the script, please type './fifo_48m_to_122p88m.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/compile.do new file mode 100644 index 00000000..4eac5446 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/compile.do @@ -0,0 +1,33 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/fifo_generator_v13_2_4 + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap xpm modelsim_lib/msim/xpm +vmap fifo_generator_v13_2_4 modelsim_lib/msim/fifo_generator_v13_2_4 + +vlog -work xil_defaultlib -64 -incr -sv \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_4 -64 -incr \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_4 -64 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_4 -64 -incr \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -64 -incr \ +"../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/fifo_48m_to_122p88m.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/fifo_48m_to_122p88m.sh new file mode 100755 index 00000000..491bfd64 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/fifo_48m_to_122p88m.sh @@ -0,0 +1,168 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_48m_to_122p88m.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_48m_to_122p88m.sh [-help] +# usage: fifo_48m_to_122p88m.sh [-lib_map_path] +# usage: fifo_48m_to_122p88m.sh [-noclean_files] +# usage: fifo_48m_to_122p88m.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_48m_to_122p88m.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "fifo_48m_to_122p88m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_48m_to_122p88m.sh [-help]\n\ +Usage: fifo_48m_to_122p88m.sh [-lib_map_path]\n\ +Usage: fifo_48m_to_122p88m.sh [-reset_run]\n\ +Usage: fifo_48m_to_122p88m.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/fifo_48m_to_122p88m.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/fifo_48m_to_122p88m.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/file_info.txt new file mode 100644 index 00000000..c802fd31 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +fifo_48m_to_122p88m.v,verilog,xil_defaultlib,../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/simulate.do new file mode 100644 index 00000000..824c6245 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.fifo_48m_to_122p88m xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {fifo_48m_to_122p88m.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/README.txt new file mode 100644 index 00000000..41d9b74a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fifo_48m_to_122p88m.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fifo_48m_to_122p88m.sh' script. + +./fifo_48m_to_122p88m.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fifo_48m_to_122p88m.sh -noclean_files + +For more information on the script, please type './fifo_48m_to_122p88m.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/compile.do new file mode 100644 index 00000000..35d8c7bb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/compile.do @@ -0,0 +1,33 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm +vlib questa_lib/msim/fifo_generator_v13_2_4 + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm +vmap fifo_generator_v13_2_4 questa_lib/msim/fifo_generator_v13_2_4 + +vlog -work xil_defaultlib -64 -sv \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_4 -64 \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_4 -64 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_4 -64 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -64 \ +"../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/elaborate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/elaborate.do new file mode 100644 index 00000000..511ae31f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.fifo_48m_to_122p88m xil_defaultlib.glbl -o fifo_48m_to_122p88m_opt diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/fifo_48m_to_122p88m.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/fifo_48m_to_122p88m.sh new file mode 100755 index 00000000..9c3a3ed5 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/fifo_48m_to_122p88m.sh @@ -0,0 +1,173 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_48m_to_122p88m.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_48m_to_122p88m.sh [-help] +# usage: fifo_48m_to_122p88m.sh [-lib_map_path] +# usage: fifo_48m_to_122p88m.sh [-noclean_files] +# usage: fifo_48m_to_122p88m.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_48m_to_122p88m.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "fifo_48m_to_122p88m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_48m_to_122p88m.sh [-help]\n\ +Usage: fifo_48m_to_122p88m.sh [-lib_map_path]\n\ +Usage: fifo_48m_to_122p88m.sh [-reset_run]\n\ +Usage: fifo_48m_to_122p88m.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/fifo_48m_to_122p88m.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/fifo_48m_to_122p88m.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/file_info.txt new file mode 100644 index 00000000..c802fd31 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +fifo_48m_to_122p88m.v,verilog,xil_defaultlib,../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/simulate.do new file mode 100644 index 00000000..c9043b75 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib fifo_48m_to_122p88m_opt + +do {wave.do} + +view wave +view structure +view signals + +do {fifo_48m_to_122p88m.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/README.txt new file mode 100644 index 00000000..41d9b74a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fifo_48m_to_122p88m.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fifo_48m_to_122p88m.sh' script. + +./fifo_48m_to_122p88m.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fifo_48m_to_122p88m.sh -noclean_files + +For more information on the script, please type './fifo_48m_to_122p88m.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/compile.do new file mode 100644 index 00000000..7e9595ab --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/compile.do @@ -0,0 +1,33 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm +vlib riviera/fifo_generator_v13_2_4 + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm +vmap fifo_generator_v13_2_4 riviera/fifo_generator_v13_2_4 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work fifo_generator_v13_2_4 -v2k5 \ +"../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + +vcom -work fifo_generator_v13_2_4 -93 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + +vlog -work fifo_generator_v13_2_4 -v2k5 \ +"../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/fifo_48m_to_122p88m.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/fifo_48m_to_122p88m.sh new file mode 100755 index 00000000..d8bb0bde --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/fifo_48m_to_122p88m.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_48m_to_122p88m.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_48m_to_122p88m.sh [-help] +# usage: fifo_48m_to_122p88m.sh [-lib_map_path] +# usage: fifo_48m_to_122p88m.sh [-noclean_files] +# usage: fifo_48m_to_122p88m.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_48m_to_122p88m.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "fifo_48m_to_122p88m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_48m_to_122p88m.sh [-help]\n\ +Usage: fifo_48m_to_122p88m.sh [-lib_map_path]\n\ +Usage: fifo_48m_to_122p88m.sh [-reset_run]\n\ +Usage: fifo_48m_to_122p88m.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/fifo_48m_to_122p88m.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/fifo_48m_to_122p88m.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/file_info.txt new file mode 100644 index 00000000..c802fd31 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +fifo_48m_to_122p88m.v,verilog,xil_defaultlib,../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/simulate.do new file mode 100644 index 00000000..5dbd10b3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+fifo_48m_to_122p88m -L xil_defaultlib -L xpm -L fifo_generator_v13_2_4 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.fifo_48m_to_122p88m xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {fifo_48m_to_122p88m.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/README.txt new file mode 100644 index 00000000..41d9b74a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fifo_48m_to_122p88m.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fifo_48m_to_122p88m.sh' script. + +./fifo_48m_to_122p88m.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fifo_48m_to_122p88m.sh -noclean_files + +For more information on the script, please type './fifo_48m_to_122p88m.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/fifo_48m_to_122p88m.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/fifo_48m_to_122p88m.sh new file mode 100755 index 00000000..8a88c1b2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/fifo_48m_to_122p88m.sh @@ -0,0 +1,241 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_48m_to_122p88m.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_48m_to_122p88m.sh [-help] +# usage: fifo_48m_to_122p88m.sh [-lib_map_path] +# usage: fifo_48m_to_122p88m.sh [-noclean_files] +# usage: fifo_48m_to_122p88m.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_48m_to_122p88m.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm fifo_generator_v13_2_4) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "fifo_48m_to_122p88m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work fifo_generator_v13_2_4 $vlogan_opts +v2k \ + "$ref_dir/../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work fifo_generator_v13_2_4 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work fifo_generator_v13_2_4 $vlogan_opts +v2k \ + "$ref_dir/../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ + 2>&1 | tee -a vlogan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.fifo_48m_to_122p88m xil_defaultlib.glbl -o fifo_48m_to_122p88m_simv +} + +# RUN_STEP: +simulate() +{ + ./fifo_48m_to_122p88m_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key fifo_48m_to_122p88m_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc fifo_48m_to_122p88m_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_48m_to_122p88m.sh [-help]\n\ +Usage: fifo_48m_to_122p88m.sh [-lib_map_path]\n\ +Usage: fifo_48m_to_122p88m.sh [-reset_run]\n\ +Usage: fifo_48m_to_122p88m.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/file_info.txt new file mode 100644 index 00000000..c802fd31 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +fifo_48m_to_122p88m.v,verilog,xil_defaultlib,../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/README.txt new file mode 100644 index 00000000..260a7279 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fifo_48m_to_122p88m.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fifo_48m_to_122p88m.sh' script. + +./fifo_48m_to_122p88m.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fifo_48m_to_122p88m.sh -noclean_files + +For more information on the script, please type './fifo_48m_to_122p88m.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/fifo_48m_to_122p88m.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/fifo_48m_to_122p88m.sh new file mode 100755 index 00000000..e86ae5ae --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/fifo_48m_to_122p88m.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_48m_to_122p88m.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_48m_to_122p88m.sh [-help] +# usage: fifo_48m_to_122p88m.sh [-lib_map_path] +# usage: fifo_48m_to_122p88m.sh [-noclean_files] +# usage: fifo_48m_to_122p88m.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'fifo_48m_to_122p88m.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm fifo_generator_v13_2_4) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "fifo_48m_to_122p88m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.fifo_48m_to_122p88m \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_48m_to_122p88m.sh [-help]\n\ +Usage: fifo_48m_to_122p88m.sh [-lib_map_path]\n\ +Usage: fifo_48m_to_122p88m.sh [-reset_run]\n\ +Usage: fifo_48m_to_122p88m.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/file_info.txt new file mode 100644 index 00000000..c802fd31 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +fifo_generator_vlog_beh.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/simulation/fifo_generator_vlog_beh.v, +fifo_generator_v13_2_rfs.vhd,vhdl,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd, +fifo_generator_v13_2_rfs.v,verilog,fifo_generator_v13_2_4,../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v, +fifo_48m_to_122p88m.v,verilog,xil_defaultlib,../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/run.f new file mode 100644 index 00000000..7bc9d59b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xcelium/run.f @@ -0,0 +1,23 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/fifo_generator_v13_2_4 \ + "../../../ipstatic/simulation/fifo_generator_vlog_beh.v" \ +-endlib +-makelib xcelium_lib/fifo_generator_v13_2_4 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd" \ +-endlib +-makelib xcelium_lib/fifo_generator_v13_2_4 \ + "../../../ipstatic/hdl/fifo_generator_v13_2_rfs.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/README.txt new file mode 100644 index 00000000..41d9b74a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./fifo_48m_to_122p88m.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './fifo_48m_to_122p88m.sh' script. + +./fifo_48m_to_122p88m.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./fifo_48m_to_122p88m.sh -noclean_files + +For more information on the script, please type './fifo_48m_to_122p88m.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/cmd.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/fifo_48m_to_122p88m.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/fifo_48m_to_122p88m.sh new file mode 100755 index 00000000..8c2ad921 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/fifo_48m_to_122p88m.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : fifo_48m_to_122p88m.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: fifo_48m_to_122p88m.sh [-help] +# usage: fifo_48m_to_122p88m.sh [-lib_map_path] +# usage: fifo_48m_to_122p88m.sh [-noclean_files] +# usage: fifo_48m_to_122p88m.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" +xvhdl_opts="--relax" + + +# Script info +echo -e "fifo_48m_to_122p88m.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L fifo_generator_v13_2_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot fifo_48m_to_122p88m xil_defaultlib.fifo_48m_to_122p88m xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim fifo_48m_to_122p88m -key {Behavioral:sim_1:Functional:fifo_48m_to_122p88m} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb fifo_48m_to_122p88m.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./fifo_48m_to_122p88m.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: fifo_48m_to_122p88m.sh [-help]\n\ +Usage: fifo_48m_to_122p88m.sh [-lib_map_path]\n\ +Usage: fifo_48m_to_122p88m.sh [-reset_run]\n\ +Usage: fifo_48m_to_122p88m.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/file_info.txt new file mode 100644 index 00000000..59e31411 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/file_info.txt @@ -0,0 +1,2 @@ +fifo_48m_to_122p88m.v,verilog,xil_defaultlib,../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/vhdl.prj b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/vhdl.prj new file mode 100644 index 00000000..359cbd5e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/vhdl.prj @@ -0,0 +1,2 @@ + +nosort diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/vlog.prj new file mode 100644 index 00000000..a7eaf67a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/fifo_48m_to_122p88m/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../ip/fifo_48m_to_122p88m/sim/fifo_48m_to_122p88m.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/README.txt new file mode 100644 index 00000000..329d7e8b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_test.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_test.sh' script. + +./ila_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_test.sh -noclean_files + +For more information on the script, please type './ila_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/compile.do new file mode 100644 index 00000000..93bccf0a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ +"../../../ip/ila_rf_test/sim/ila_rf_test.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/file_info.txt new file mode 100644 index 00000000..b42182bb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" +ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/ila_rf_test.sh new file mode 100755 index 00000000..ef0405c1 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/ila_rf_test.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_test.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_test.sh [-help] +# usage: ila_rf_test.sh [-lib_map_path] +# usage: ila_rf_test.sh [-noclean_files] +# usage: ila_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_test.sh [-help]\n\ +Usage: ila_rf_test.sh [-lib_map_path]\n\ +Usage: ila_rf_test.sh [-reset_run]\n\ +Usage: ila_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/ila_rf_test.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/ila_rf_test.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/simulate.do new file mode 100644 index 00000000..7f077af0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+ila_rf_test -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_rf_test xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ila_rf_test.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/README.txt new file mode 100644 index 00000000..a417301d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_test.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_test.sh' script. + +./ila_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_test.sh -noclean_files + +For more information on the script, please type './ila_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/file_info.txt new file mode 100644 index 00000000..b42182bb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" +ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/ila_rf_test.sh new file mode 100755 index 00000000..b28aaf5f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/ila_rf_test.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_test.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_test.sh [-help] +# usage: ila_rf_test.sh [-lib_map_path] +# usage: ila_rf_test.sh [-noclean_files] +# usage: ila_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "ila_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ila_rf_test \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/ila_rf_test/hdl/verilog" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_test.sh [-help]\n\ +Usage: ila_rf_test.sh [-lib_map_path]\n\ +Usage: ila_rf_test.sh [-reset_run]\n\ +Usage: ila_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/run.f new file mode 100644 index 00000000..858d1c03 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/ila_rf_test/sim/ila_rf_test.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/README.txt new file mode 100644 index 00000000..329d7e8b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_test.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_test.sh' script. + +./ila_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_test.sh -noclean_files + +For more information on the script, please type './ila_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/compile.do new file mode 100644 index 00000000..9f6d2b3d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ +"../../../ip/ila_rf_test/sim/ila_rf_test.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/file_info.txt new file mode 100644 index 00000000..bd70b315 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/file_info.txt @@ -0,0 +1,2 @@ +ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/ila_rf_test.sh new file mode 100755 index 00000000..74f64123 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/ila_rf_test.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_test.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_test.sh [-help] +# usage: ila_rf_test.sh [-lib_map_path] +# usage: ila_rf_test.sh [-noclean_files] +# usage: ila_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_test.sh [-help]\n\ +Usage: ila_rf_test.sh [-lib_map_path]\n\ +Usage: ila_rf_test.sh [-reset_run]\n\ +Usage: ila_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/ila_rf_test.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/ila_rf_test.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/simulate.do new file mode 100644 index 00000000..fc7771fc --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.ila_rf_test xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {ila_rf_test.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/README.txt new file mode 100644 index 00000000..329d7e8b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_test.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_test.sh' script. + +./ila_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_test.sh -noclean_files + +For more information on the script, please type './ila_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/compile.do new file mode 100644 index 00000000..52ed87f9 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ +"../../../ip/ila_rf_test/sim/ila_rf_test.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/elaborate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/elaborate.do new file mode 100644 index 00000000..e5b27cf4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.ila_rf_test xil_defaultlib.glbl -o ila_rf_test_opt diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/file_info.txt new file mode 100644 index 00000000..b42182bb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" +ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/ila_rf_test.sh new file mode 100755 index 00000000..6136d58d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/ila_rf_test.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_test.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_test.sh [-help] +# usage: ila_rf_test.sh [-lib_map_path] +# usage: ila_rf_test.sh [-noclean_files] +# usage: ila_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_test.sh [-help]\n\ +Usage: ila_rf_test.sh [-lib_map_path]\n\ +Usage: ila_rf_test.sh [-reset_run]\n\ +Usage: ila_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/ila_rf_test.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/ila_rf_test.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/simulate.do new file mode 100644 index 00000000..4f3a8bf0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib ila_rf_test_opt + +do {wave.do} + +view wave +view structure +view signals + +do {ila_rf_test.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/README.txt new file mode 100644 index 00000000..329d7e8b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_test.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_test.sh' script. + +./ila_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_test.sh -noclean_files + +For more information on the script, please type './ila_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/compile.do new file mode 100644 index 00000000..df3ecb23 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/ila_rf_test/hdl/verilog" \ +"../../../ip/ila_rf_test/sim/ila_rf_test.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/file_info.txt new file mode 100644 index 00000000..b42182bb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" +ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/ila_rf_test.sh new file mode 100755 index 00000000..a7cb2d74 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/ila_rf_test.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_test.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_test.sh [-help] +# usage: ila_rf_test.sh [-lib_map_path] +# usage: ila_rf_test.sh [-noclean_files] +# usage: ila_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "ila_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_test.sh [-help]\n\ +Usage: ila_rf_test.sh [-lib_map_path]\n\ +Usage: ila_rf_test.sh [-reset_run]\n\ +Usage: ila_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/ila_rf_test.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/ila_rf_test.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/simulate.do new file mode 100644 index 00000000..7f077af0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+ila_rf_test -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.ila_rf_test xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {ila_rf_test.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/README.txt new file mode 100644 index 00000000..329d7e8b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_test.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_test.sh' script. + +./ila_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_test.sh -noclean_files + +For more information on the script, please type './ila_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/file_info.txt new file mode 100644 index 00000000..bd70b315 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/file_info.txt @@ -0,0 +1,2 @@ +ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/ila_rf_test.sh new file mode 100755 index 00000000..285de8ba --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/ila_rf_test.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_test.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_test.sh [-help] +# usage: ila_rf_test.sh [-lib_map_path] +# usage: ila_rf_test.sh [-noclean_files] +# usage: ila_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "ila_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/ila_rf_test/hdl/verilog" \ + "$ref_dir/../../../ip/ila_rf_test/sim/ila_rf_test.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.ila_rf_test xil_defaultlib.glbl -o ila_rf_test_simv +} + +# RUN_STEP: +simulate() +{ + ./ila_rf_test_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key ila_rf_test_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc ila_rf_test_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_test.sh [-help]\n\ +Usage: ila_rf_test.sh [-lib_map_path]\n\ +Usage: ila_rf_test.sh [-reset_run]\n\ +Usage: ila_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/README.txt new file mode 100644 index 00000000..a417301d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_test.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_test.sh' script. + +./ila_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_test.sh -noclean_files + +For more information on the script, please type './ila_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/file_info.txt new file mode 100644 index 00000000..b42182bb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/ila_rf_test/hdl/verilog" +xpm_VCOMP.vhd,vhdl,xpm,../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/ila_rf_test/hdl/verilog" +ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/ila_rf_test.sh new file mode 100755 index 00000000..1008c3bc --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/ila_rf_test.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_test.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_test.sh [-help] +# usage: ila_rf_test.sh [-lib_map_path] +# usage: ila_rf_test.sh [-noclean_files] +# usage: ila_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'ila_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "ila_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.ila_rf_test \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/ila_rf_test/hdl/verilog" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_test.sh [-help]\n\ +Usage: ila_rf_test.sh [-lib_map_path]\n\ +Usage: ila_rf_test.sh [-reset_run]\n\ +Usage: ila_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/run.f new file mode 100644 index 00000000..6e8625bd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/ila_rf_test/sim/ila_rf_test.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/README.txt new file mode 100644 index 00000000..329d7e8b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:21 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./ila_rf_test.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './ila_rf_test.sh' script. + +./ila_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./ila_rf_test.sh -noclean_files + +For more information on the script, please type './ila_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/cmd.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/file_info.txt new file mode 100644 index 00000000..bd70b315 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/file_info.txt @@ -0,0 +1,2 @@ +ila_rf_test.v,verilog,xil_defaultlib,../../../ip/ila_rf_test/sim/ila_rf_test.v,incdir="../../../ip/ila_rf_test/hdl/verilog" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/ila_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/ila_rf_test.sh new file mode 100755 index 00000000..69fb6008 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/ila_rf_test.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : ila_rf_test.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:21 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: ila_rf_test.sh [-help] +# usage: ila_rf_test.sh [-lib_map_path] +# usage: ila_rf_test.sh [-noclean_files] +# usage: ila_rf_test.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "ila_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ila_rf_test xil_defaultlib.ila_rf_test xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim ila_rf_test -key {Behavioral:sim_1:Functional:ila_rf_test} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb ila_rf_test.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./ila_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: ila_rf_test.sh [-help]\n\ +Usage: ila_rf_test.sh [-lib_map_path]\n\ +Usage: ila_rf_test.sh [-reset_run]\n\ +Usage: ila_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/vlog.prj new file mode 100644 index 00000000..fe6a127b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/ila_rf_test/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/ila_rf_test/hdl/verilog" \ +"../../../ip/ila_rf_test/sim/ila_rf_test.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/README.txt new file mode 100644 index 00000000..3cc4a429 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:38 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./lpf_125k.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './lpf_125k.sh' script. + +./lpf_125k.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./lpf_125k.sh -noclean_files + +For more information on the script, please type './lpf_125k.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/compile.do new file mode 100644 index 00000000..c9d4ab08 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/compile.do @@ -0,0 +1,37 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm +vlib activehdl/xbip_utils_v3_0_10 +vlib activehdl/axi_utils_v2_0_6 +vlib activehdl/fir_compiler_v7_2_12 + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm +vmap xbip_utils_v3_0_10 activehdl/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6 +vmap fir_compiler_v7_2_12 activehdl/fir_compiler_v7_2_12 + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/lpf_125k/cmodel" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work fir_compiler_v7_2_12 -93 \ +"../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../ip/lpf_125k/sim/lpf_125k.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/file_info.txt new file mode 100644 index 00000000..4f2848ec --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/lpf_125k/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +lpf_125k.vhd,vhdl,xil_defaultlib,../../../ip/lpf_125k/sim/lpf_125k.vhd,incdir="../../../ip/lpf_125k/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git 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+00000000 0 16 0 0 1036 0 +00000000 0 16 0 0 1061 0 +00000000 0 16 0 0 1086 0 +00000000 0 16 0 0 1047 0 +00000000 0 16 0 0 1072 0 +00000000 0 16 0 0 1033 0 +00000000 0 16 0 0 1058 0 +00000000 0 16 0 0 1083 0 +00000000 0 16 0 0 1044 0 +00000000 0 16 0 0 1069 0 +00000000 0 16 0 0 1030 0 +00000000 0 16 0 0 1055 0 +00000000 0 16 0 0 1080 0 +00000000 0 16 0 0 1041 0 +00000000 0 16 0 0 1066 0 +00000000 0 16 0 0 1027 0 +00000000 0 16 0 0 1052 0 +00000000 0 16 0 0 1077 0 +00000000 0 16 0 0 1038 0 +00000000 0 16 0 0 1063 0 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/lpf_125k.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/lpf_125k.sh new file mode 100755 index 00000000..b2b4526a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/lpf_125k.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : lpf_125k.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:38 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: lpf_125k.sh [-help] +# usage: lpf_125k.sh [-lib_map_path] +# usage: lpf_125k.sh [-noclean_files] +# usage: lpf_125k.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'lpf_125k.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "lpf_125k.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: lpf_125k.sh [-help]\n\ +Usage: lpf_125k.sh [-lib_map_path]\n\ +Usage: lpf_125k.sh [-reset_run]\n\ +Usage: lpf_125k.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/lpf_125k.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/lpf_125k.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/simulate.do new file mode 100644 index 00000000..e7b26f4c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+lpf_125k -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.lpf_125k xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {lpf_125k.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/README.txt new file mode 100644 index 00000000..a51a8697 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:38 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./lpf_125k.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './lpf_125k.sh' script. + +./lpf_125k.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./lpf_125k.sh -noclean_files + +For more information on the script, please type './lpf_125k.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/file_info.txt new file mode 100644 index 00000000..4f2848ec --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/lpf_125k/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +lpf_125k.vhd,vhdl,xil_defaultlib,../../../ip/lpf_125k/sim/lpf_125k.vhd,incdir="../../../ip/lpf_125k/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/lpf_125k.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/lpf_125k.coe new file mode 100755 index 00000000..91ddd53d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/lpf_125k.coe @@ -0,0 +1,1027 @@ +RADIX = 10; +COEFDATA = +103, +100, +97, +93, +90, +86, +83, +79, +75, +70, +66, +62, +57, +53, +48, +43, +38, +33, +28, +22, +17, +12, +6, +0, +-5, +-11, +-17, +-23, +-29, +-35, +-41, +-47, +-53, +-59, +-65, +-72, +-78, +-84, +-90, +-96, +-103, +-109, +-115, +-121, +-127, +-133, +-138, +-144, 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b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/lpf_125k.mif new file mode 100644 index 00000000..c8bd992e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/lpf_125k.mif @@ -0,0 +1,1088 @@ +00000067 0 0 0 0 0 0 +fffffff5 0 0 0 0 25 0 +ffffff5f 0 0 0 0 50 0 +0000003e 0 0 0 0 11 0 +ffffffb2 0 0 0 0 36 0 +ffffff2e 0 0 0 0 61 0 +00000006 0 0 0 0 22 0 +ffffff70 0 0 0 0 47 0 +0000004b 0 0 0 0 8 0 +ffffffc5 0 0 0 0 33 0 +ffffff39 0 0 0 0 58 0 +00000016 0 0 0 0 19 0 +ffffff81 0 0 0 0 44 0 +00000056 0 0 0 0 5 0 +ffffffd7 0 0 0 0 30 0 +ffffff46 0 0 0 0 55 0 +00000026 0 0 0 0 16 0 +ffffff93 0 0 0 0 41 0 +00000061 0 0 0 0 2 0 +ffffffe9 0 0 0 0 27 0 +ffffff55 0 0 0 0 52 0 +00000035 0 0 0 0 13 0 +ffffffa6 0 0 0 0 38 0 +ffffff28 0 0 0 0 63 0 +fffffffb 0 0 0 0 24 0 +ffffff65 0 0 0 0 49 0 +00000042 0 0 0 0 10 0 +ffffffb8 0 0 0 0 35 0 +ffffff32 0 0 0 0 60 0 +0000000c 0 0 0 0 21 0 +ffffff76 0 0 0 0 46 0 +0000004f 0 0 0 0 7 0 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0 16 0 0 1031 0 +00000000 0 16 0 0 1056 0 +00000000 0 16 0 0 1081 0 +00000000 0 16 0 0 1042 0 +00000000 0 16 0 0 1067 0 +00000000 0 16 0 0 1028 0 +00000000 0 16 0 0 1053 0 +00000000 0 16 0 0 1078 0 +00000000 0 16 0 0 1039 0 +00000000 0 16 0 0 1064 0 +00000000 0 16 0 0 1025 0 +00000000 0 16 0 0 1050 0 +00000000 0 16 0 0 1075 0 +00000000 0 16 0 0 1036 0 +00000000 0 16 0 0 1061 0 +00000000 0 16 0 0 1086 0 +00000000 0 16 0 0 1047 0 +00000000 0 16 0 0 1072 0 +00000000 0 16 0 0 1033 0 +00000000 0 16 0 0 1058 0 +00000000 0 16 0 0 1083 0 +00000000 0 16 0 0 1044 0 +00000000 0 16 0 0 1069 0 +00000000 0 16 0 0 1030 0 +00000000 0 16 0 0 1055 0 +00000000 0 16 0 0 1080 0 +00000000 0 16 0 0 1041 0 +00000000 0 16 0 0 1066 0 +00000000 0 16 0 0 1027 0 +00000000 0 16 0 0 1052 0 +00000000 0 16 0 0 1077 0 +00000000 0 16 0 0 1038 0 +00000000 0 16 0 0 1063 0 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/lpf_125k.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/lpf_125k.sh new file mode 100755 index 00000000..c28b2a2e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/lpf_125k.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : lpf_125k.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:38 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: lpf_125k.sh [-help] +# usage: lpf_125k.sh [-lib_map_path] +# usage: lpf_125k.sh [-noclean_files] +# usage: lpf_125k.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'lpf_125k.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 fir_compiler_v7_2_12) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "lpf_125k.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.lpf_125k \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/lpf_125k/cmodel" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: lpf_125k.sh [-help]\n\ +Usage: lpf_125k.sh [-lib_map_path]\n\ +Usage: lpf_125k.sh [-reset_run]\n\ +Usage: lpf_125k.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/run.f new file mode 100644 index 00000000..0c8f0d87 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/ies/run.f @@ -0,0 +1,23 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xbip_utils_v3_0_10 \ + "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/axi_utils_v2_0_6 \ + "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/fir_compiler_v7_2_12 \ + "../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/lpf_125k/sim/lpf_125k.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/README.txt new file mode 100644 index 00000000..3cc4a429 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:38 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./lpf_125k.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './lpf_125k.sh' script. + +./lpf_125k.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./lpf_125k.sh -noclean_files + +For more information on the script, please type './lpf_125k.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/compile.do new file mode 100644 index 00000000..9863a8d7 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/compile.do @@ -0,0 +1,37 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/xpm +vlib modelsim_lib/msim/xbip_utils_v3_0_10 +vlib modelsim_lib/msim/axi_utils_v2_0_6 +vlib modelsim_lib/msim/fir_compiler_v7_2_12 + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap xpm modelsim_lib/msim/xpm +vmap xbip_utils_v3_0_10 modelsim_lib/msim/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6 +vmap fir_compiler_v7_2_12 modelsim_lib/msim/fir_compiler_v7_2_12 + +vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ip/lpf_125k/cmodel" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -64 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -64 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work fir_compiler_v7_2_12 -64 -93 \ +"../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../ip/lpf_125k/sim/lpf_125k.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/file_info.txt new file mode 100644 index 00000000..4f2848ec --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/lpf_125k/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +lpf_125k.vhd,vhdl,xil_defaultlib,../../../ip/lpf_125k/sim/lpf_125k.vhd,incdir="../../../ip/lpf_125k/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/lpf_125k.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/lpf_125k.coe new file mode 100755 index 00000000..91ddd53d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/lpf_125k.coe @@ -0,0 +1,1027 @@ +RADIX = 10; +COEFDATA = +103, +100, +97, +93, +90, +86, +83, +79, +75, +70, +66, +62, +57, +53, +48, +43, +38, +33, +28, +22, +17, +12, +6, +0, +-5, +-11, +-17, +-23, +-29, +-35, +-41, +-47, +-53, +-59, +-65, +-72, +-78, +-84, +-90, +-96, +-103, +-109, +-115, +-121, +-127, +-133, +-138, +-144, +-150, +-155, +-161, +-166, +-171, +-176, +-181, +-186, +-190, +-195, +-199, +-202, +-206, +-210, +-213, +-216, +-218, +-221, +-223, +-224, +-226, +-227, +-228, +-228, +-228, +-228, +-227, +-226, +-224, +-223, +-220, +-218, +-214, +-211, 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16 0 0 1064 0 +00000000 0 16 0 0 1025 0 +00000000 0 16 0 0 1050 0 +00000000 0 16 0 0 1075 0 +00000000 0 16 0 0 1036 0 +00000000 0 16 0 0 1061 0 +00000000 0 16 0 0 1086 0 +00000000 0 16 0 0 1047 0 +00000000 0 16 0 0 1072 0 +00000000 0 16 0 0 1033 0 +00000000 0 16 0 0 1058 0 +00000000 0 16 0 0 1083 0 +00000000 0 16 0 0 1044 0 +00000000 0 16 0 0 1069 0 +00000000 0 16 0 0 1030 0 +00000000 0 16 0 0 1055 0 +00000000 0 16 0 0 1080 0 +00000000 0 16 0 0 1041 0 +00000000 0 16 0 0 1066 0 +00000000 0 16 0 0 1027 0 +00000000 0 16 0 0 1052 0 +00000000 0 16 0 0 1077 0 +00000000 0 16 0 0 1038 0 +00000000 0 16 0 0 1063 0 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/lpf_125k.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/lpf_125k.sh new file mode 100755 index 00000000..59f1a526 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/lpf_125k.sh @@ -0,0 +1,168 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : lpf_125k.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:38 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: lpf_125k.sh [-help] +# usage: lpf_125k.sh [-lib_map_path] +# usage: lpf_125k.sh [-noclean_files] +# usage: lpf_125k.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'lpf_125k.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "lpf_125k.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: lpf_125k.sh [-help]\n\ +Usage: lpf_125k.sh [-lib_map_path]\n\ +Usage: lpf_125k.sh [-reset_run]\n\ +Usage: lpf_125k.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/lpf_125k.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/lpf_125k.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/simulate.do new file mode 100644 index 00000000..5a0b04c5 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.lpf_125k xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {lpf_125k.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/README.txt new file mode 100644 index 00000000..3cc4a429 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:38 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./lpf_125k.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './lpf_125k.sh' script. + +./lpf_125k.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./lpf_125k.sh -noclean_files + +For more information on the script, please type './lpf_125k.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/compile.do new file mode 100644 index 00000000..dcf4db85 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/compile.do @@ -0,0 +1,37 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm +vlib questa_lib/msim/xbip_utils_v3_0_10 +vlib questa_lib/msim/axi_utils_v2_0_6 +vlib questa_lib/msim/fir_compiler_v7_2_12 + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm +vmap xbip_utils_v3_0_10 questa_lib/msim/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6 +vmap fir_compiler_v7_2_12 questa_lib/msim/fir_compiler_v7_2_12 + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/lpf_125k/cmodel" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -64 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -64 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work fir_compiler_v7_2_12 -64 -93 \ +"../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -64 -93 \ +"../../../ip/lpf_125k/sim/lpf_125k.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/elaborate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/elaborate.do new file mode 100644 index 00000000..cb6f1d12 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.lpf_125k xil_defaultlib.glbl -o lpf_125k_opt diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/file_info.txt new file mode 100644 index 00000000..4f2848ec --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/lpf_125k/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +lpf_125k.vhd,vhdl,xil_defaultlib,../../../ip/lpf_125k/sim/lpf_125k.vhd,incdir="../../../ip/lpf_125k/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/lpf_125k.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/lpf_125k.coe new file mode 100755 index 00000000..91ddd53d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/lpf_125k.coe @@ -0,0 +1,1027 @@ +RADIX = 10; +COEFDATA = +103, +100, +97, +93, +90, +86, +83, +79, +75, +70, +66, +62, +57, +53, +48, +43, +38, +33, +28, +22, +17, +12, +6, +0, +-5, +-11, +-17, +-23, +-29, +-35, +-41, +-47, +-53, +-59, +-65, +-72, +-78, +-84, +-90, +-96, +-103, +-109, +-115, +-121, +-127, +-133, +-138, +-144, +-150, +-155, +-161, +-166, +-171, +-176, +-181, +-186, +-190, +-195, +-199, +-202, +-206, +-210, +-213, +-216, +-218, +-221, +-223, +-224, +-226, +-227, +-228, +-228, +-228, +-228, +-227, +-226, +-224, +-223, +-220, +-218, +-214, +-211, +-207, +-203, +-198, +-192, +-187, +-180, +-174, +-167, +-159, +-151, +-143, +-134, +-124, +-115, +-104, +-94, +-83, +-71, +-59, +-47, +-34, +-21, +-8, +6, +20, +35, +49, +64, +80, +95, +111, +127, +143, +159, +176, +192, +209, +225, +242, +259, +275, +292, +309, +325, +341, +357, +373, +389, +404, +419, +434, +449, +463, +476, +489, +502, +514, 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0 +00000000 0 16 0 0 1055 0 +00000000 0 16 0 0 1080 0 +00000000 0 16 0 0 1041 0 +00000000 0 16 0 0 1066 0 +00000000 0 16 0 0 1027 0 +00000000 0 16 0 0 1052 0 +00000000 0 16 0 0 1077 0 +00000000 0 16 0 0 1038 0 +00000000 0 16 0 0 1063 0 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/lpf_125k.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/lpf_125k.sh new file mode 100755 index 00000000..fcf5e3a8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/lpf_125k.sh @@ -0,0 +1,173 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : lpf_125k.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:38 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: lpf_125k.sh [-help] +# usage: lpf_125k.sh [-lib_map_path] +# usage: lpf_125k.sh [-noclean_files] +# usage: lpf_125k.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'lpf_125k.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "lpf_125k.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: lpf_125k.sh [-help]\n\ +Usage: lpf_125k.sh [-lib_map_path]\n\ +Usage: lpf_125k.sh [-reset_run]\n\ +Usage: lpf_125k.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/lpf_125k.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/lpf_125k.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/simulate.do new file mode 100644 index 00000000..0768c216 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib lpf_125k_opt + +do {wave.do} + +view wave +view structure +view signals + +do {lpf_125k.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/README.txt new file mode 100644 index 00000000..3cc4a429 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:38 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./lpf_125k.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './lpf_125k.sh' script. + +./lpf_125k.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./lpf_125k.sh -noclean_files + +For more information on the script, please type './lpf_125k.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/compile.do new file mode 100644 index 00000000..6254df63 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/compile.do @@ -0,0 +1,37 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm +vlib riviera/xbip_utils_v3_0_10 +vlib riviera/axi_utils_v2_0_6 +vlib riviera/fir_compiler_v7_2_12 + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm +vmap xbip_utils_v3_0_10 riviera/xbip_utils_v3_0_10 +vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6 +vmap fir_compiler_v7_2_12 riviera/fir_compiler_v7_2_12 + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/lpf_125k/cmodel" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vcom -work xbip_utils_v3_0_10 -93 \ +"../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + +vcom -work axi_utils_v2_0_6 -93 \ +"../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + +vcom -work fir_compiler_v7_2_12 -93 \ +"../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ + +vcom -work xil_defaultlib -93 \ +"../../../ip/lpf_125k/sim/lpf_125k.vhd" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/file_info.txt new file mode 100644 index 00000000..4f2848ec --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/lpf_125k/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +lpf_125k.vhd,vhdl,xil_defaultlib,../../../ip/lpf_125k/sim/lpf_125k.vhd,incdir="../../../ip/lpf_125k/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/lpf_125k.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/lpf_125k.coe new file mode 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+00000000 0 16 0 0 1044 0 +00000000 0 16 0 0 1069 0 +00000000 0 16 0 0 1030 0 +00000000 0 16 0 0 1055 0 +00000000 0 16 0 0 1080 0 +00000000 0 16 0 0 1041 0 +00000000 0 16 0 0 1066 0 +00000000 0 16 0 0 1027 0 +00000000 0 16 0 0 1052 0 +00000000 0 16 0 0 1077 0 +00000000 0 16 0 0 1038 0 +00000000 0 16 0 0 1063 0 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/lpf_125k.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/lpf_125k.sh new file mode 100755 index 00000000..87c316eb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/lpf_125k.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : lpf_125k.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:38 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: lpf_125k.sh [-help] +# usage: lpf_125k.sh [-lib_map_path] +# usage: lpf_125k.sh [-noclean_files] +# usage: lpf_125k.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'lpf_125k.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "lpf_125k.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: lpf_125k.sh [-help]\n\ +Usage: lpf_125k.sh [-lib_map_path]\n\ +Usage: lpf_125k.sh [-reset_run]\n\ +Usage: lpf_125k.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/lpf_125k.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/lpf_125k.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/simulate.do new file mode 100644 index 00000000..e7b26f4c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+lpf_125k -L xil_defaultlib -L xpm -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.lpf_125k xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {lpf_125k.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/README.txt new file mode 100644 index 00000000..3cc4a429 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:38 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./lpf_125k.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './lpf_125k.sh' script. + +./lpf_125k.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./lpf_125k.sh -noclean_files + +For more information on the script, please type './lpf_125k.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/file_info.txt new file mode 100644 index 00000000..4f2848ec --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/lpf_125k/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +lpf_125k.vhd,vhdl,xil_defaultlib,../../../ip/lpf_125k/sim/lpf_125k.vhd,incdir="../../../ip/lpf_125k/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/lpf_125k.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/lpf_125k.coe new file mode 100755 index 00000000..91ddd53d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/lpf_125k.coe @@ -0,0 +1,1027 @@ +RADIX = 10; +COEFDATA = +103, +100, +97, +93, +90, +86, +83, +79, +75, +70, +66, +62, +57, +53, +48, +43, +38, +33, +28, +22, +17, +12, +6, +0, +-5, +-11, +-17, +-23, +-29, +-35, +-41, +-47, +-53, +-59, +-65, +-72, +-78, +-84, +-90, +-96, +-103, +-109, +-115, +-121, +-127, +-133, +-138, +-144, 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b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/lpf_125k.mif new file mode 100644 index 00000000..c8bd992e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/lpf_125k.mif @@ -0,0 +1,1088 @@ +00000067 0 0 0 0 0 0 +fffffff5 0 0 0 0 25 0 +ffffff5f 0 0 0 0 50 0 +0000003e 0 0 0 0 11 0 +ffffffb2 0 0 0 0 36 0 +ffffff2e 0 0 0 0 61 0 +00000006 0 0 0 0 22 0 +ffffff70 0 0 0 0 47 0 +0000004b 0 0 0 0 8 0 +ffffffc5 0 0 0 0 33 0 +ffffff39 0 0 0 0 58 0 +00000016 0 0 0 0 19 0 +ffffff81 0 0 0 0 44 0 +00000056 0 0 0 0 5 0 +ffffffd7 0 0 0 0 30 0 +ffffff46 0 0 0 0 55 0 +00000026 0 0 0 0 16 0 +ffffff93 0 0 0 0 41 0 +00000061 0 0 0 0 2 0 +ffffffe9 0 0 0 0 27 0 +ffffff55 0 0 0 0 52 0 +00000035 0 0 0 0 13 0 +ffffffa6 0 0 0 0 38 0 +ffffff28 0 0 0 0 63 0 +fffffffb 0 0 0 0 24 0 +ffffff65 0 0 0 0 49 0 +00000042 0 0 0 0 10 0 +ffffffb8 0 0 0 0 35 0 +ffffff32 0 0 0 0 60 0 +0000000c 0 0 0 0 21 0 +ffffff76 0 0 0 0 46 0 +0000004f 0 0 0 0 7 0 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0 16 0 0 1031 0 +00000000 0 16 0 0 1056 0 +00000000 0 16 0 0 1081 0 +00000000 0 16 0 0 1042 0 +00000000 0 16 0 0 1067 0 +00000000 0 16 0 0 1028 0 +00000000 0 16 0 0 1053 0 +00000000 0 16 0 0 1078 0 +00000000 0 16 0 0 1039 0 +00000000 0 16 0 0 1064 0 +00000000 0 16 0 0 1025 0 +00000000 0 16 0 0 1050 0 +00000000 0 16 0 0 1075 0 +00000000 0 16 0 0 1036 0 +00000000 0 16 0 0 1061 0 +00000000 0 16 0 0 1086 0 +00000000 0 16 0 0 1047 0 +00000000 0 16 0 0 1072 0 +00000000 0 16 0 0 1033 0 +00000000 0 16 0 0 1058 0 +00000000 0 16 0 0 1083 0 +00000000 0 16 0 0 1044 0 +00000000 0 16 0 0 1069 0 +00000000 0 16 0 0 1030 0 +00000000 0 16 0 0 1055 0 +00000000 0 16 0 0 1080 0 +00000000 0 16 0 0 1041 0 +00000000 0 16 0 0 1066 0 +00000000 0 16 0 0 1027 0 +00000000 0 16 0 0 1052 0 +00000000 0 16 0 0 1077 0 +00000000 0 16 0 0 1038 0 +00000000 0 16 0 0 1063 0 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/lpf_125k.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/lpf_125k.sh new file mode 100755 index 00000000..dcbe37cc --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/lpf_125k.sh @@ -0,0 +1,241 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : lpf_125k.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:38 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: lpf_125k.sh [-help] +# usage: lpf_125k.sh [-lib_map_path] +# usage: lpf_125k.sh [-noclean_files] +# usage: lpf_125k.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'lpf_125k.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 fir_compiler_v7_2_12) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "lpf_125k.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ip/lpf_125k/cmodel" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work axi_utils_v2_0_6 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work fir_compiler_v7_2_12 $vhdlan_opts \ + "$ref_dir/../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ + 2>&1 | tee -a vhdlan.log + + vhdlan -work xil_defaultlib $vhdlan_opts \ + "$ref_dir/../../../ip/lpf_125k/sim/lpf_125k.vhd" \ + 2>&1 | tee -a vhdlan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.lpf_125k xil_defaultlib.glbl -o lpf_125k_simv +} + +# RUN_STEP: +simulate() +{ + ./lpf_125k_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key lpf_125k_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc lpf_125k_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: lpf_125k.sh [-help]\n\ +Usage: lpf_125k.sh [-lib_map_path]\n\ +Usage: lpf_125k.sh [-reset_run]\n\ +Usage: lpf_125k.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/README.txt new file mode 100644 index 00000000..a51a8697 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:38 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./lpf_125k.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './lpf_125k.sh' script. + +./lpf_125k.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./lpf_125k.sh -noclean_files + +For more information on the script, please type './lpf_125k.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/file_info.txt new file mode 100644 index 00000000..4f2848ec --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/file_info.txt @@ -0,0 +1,8 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/lpf_125k/cmodel" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/lpf_125k/cmodel" +xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +axi_utils_v2_0_vh_rfs.vhd,vhdl,axi_utils_v2_0_6,../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +fir_compiler_v7_2_vh_rfs.vhd,vhdl,fir_compiler_v7_2_12,../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd,incdir="../../../ip/lpf_125k/cmodel" +lpf_125k.vhd,vhdl,xil_defaultlib,../../../ip/lpf_125k/sim/lpf_125k.vhd,incdir="../../../ip/lpf_125k/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/lpf_125k.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/lpf_125k.coe new file mode 100755 index 00000000..91ddd53d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/lpf_125k.coe @@ -0,0 +1,1027 @@ +RADIX = 10; +COEFDATA = +103, +100, +97, +93, +90, +86, +83, +79, +75, +70, +66, +62, +57, +53, +48, +43, +38, +33, +28, +22, +17, +12, +6, +0, +-5, +-11, +-17, +-23, +-29, +-35, +-41, +-47, +-53, +-59, +-65, +-72, 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a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/lpf_125k.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/lpf_125k.mif new file mode 100644 index 00000000..c8bd992e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/lpf_125k.mif @@ -0,0 +1,1088 @@ +00000067 0 0 0 0 0 0 +fffffff5 0 0 0 0 25 0 +ffffff5f 0 0 0 0 50 0 +0000003e 0 0 0 0 11 0 +ffffffb2 0 0 0 0 36 0 +ffffff2e 0 0 0 0 61 0 +00000006 0 0 0 0 22 0 +ffffff70 0 0 0 0 47 0 +0000004b 0 0 0 0 8 0 +ffffffc5 0 0 0 0 33 0 +ffffff39 0 0 0 0 58 0 +00000016 0 0 0 0 19 0 +ffffff81 0 0 0 0 44 0 +00000056 0 0 0 0 5 0 +ffffffd7 0 0 0 0 30 0 +ffffff46 0 0 0 0 55 0 +00000026 0 0 0 0 16 0 +ffffff93 0 0 0 0 41 0 +00000061 0 0 0 0 2 0 +ffffffe9 0 0 0 0 27 0 +ffffff55 0 0 0 0 52 0 +00000035 0 0 0 0 13 0 +ffffffa6 0 0 0 0 38 0 +ffffff28 0 0 0 0 63 0 +fffffffb 0 0 0 0 24 0 +ffffff65 0 0 0 0 49 0 +00000042 0 0 0 0 10 0 +ffffffb8 0 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a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/lpf_125k.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/lpf_125k.sh new file mode 100755 index 00000000..c216d07b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/lpf_125k.sh @@ -0,0 +1,176 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : lpf_125k.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:38 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: lpf_125k.sh [-help] +# usage: lpf_125k.sh [-lib_map_path] +# usage: lpf_125k.sh [-noclean_files] +# usage: lpf_125k.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'lpf_125k.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm xbip_utils_v3_0_10 axi_utils_v2_0_6 fir_compiler_v7_2_12) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "lpf_125k.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.lpf_125k \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/lpf_125k/cmodel" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: lpf_125k.sh [-help]\n\ +Usage: lpf_125k.sh [-lib_map_path]\n\ +Usage: lpf_125k.sh [-reset_run]\n\ +Usage: lpf_125k.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/run.f new file mode 100644 index 00000000..b9d1d022 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xcelium/run.f @@ -0,0 +1,23 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xbip_utils_v3_0_10 \ + "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/axi_utils_v2_0_6 \ + "../../../ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/fir_compiler_v7_2_12 \ + "../../../ipstatic/hdl/fir_compiler_v7_2_vh_rfs.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/lpf_125k/sim/lpf_125k.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/README.txt new file mode 100644 index 00000000..3cc4a429 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:38 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./lpf_125k.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './lpf_125k.sh' script. + +./lpf_125k.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./lpf_125k.sh -noclean_files + +For more information on the script, please type './lpf_125k.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/cmd.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/file_info.txt new file mode 100644 index 00000000..d952599a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/file_info.txt @@ -0,0 +1,2 @@ +lpf_125k.vhd,vhdl,xil_defaultlib,../../../ip/lpf_125k/sim/lpf_125k.vhd,incdir="../../../ip/lpf_125k/cmodel" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/lpf_125k.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/lpf_125k.coe new file mode 100755 index 00000000..91ddd53d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/lpf_125k.coe @@ -0,0 +1,1027 @@ +RADIX = 10; +COEFDATA = +103, +100, +97, +93, +90, +86, +83, +79, +75, +70, +66, +62, +57, +53, +48, +43, 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+00000000 0 16 0 0 1063 0 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/lpf_125k.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/lpf_125k.sh new file mode 100755 index 00000000..94fd558a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/lpf_125k.sh @@ -0,0 +1,214 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : lpf_125k.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:38 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: lpf_125k.sh [-help] +# usage: lpf_125k.sh [-lib_map_path] +# usage: lpf_125k.sh [-noclean_files] +# usage: lpf_125k.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" +xvhdl_opts="--relax" + + +# Script info +echo -e "lpf_125k.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L fir_compiler_v7_2_12 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot lpf_125k xil_defaultlib.lpf_125k xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim lpf_125k -key {Behavioral:sim_1:Functional:lpf_125k} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb lpf_125k.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./lpf_125k.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: lpf_125k.sh [-help]\n\ +Usage: lpf_125k.sh [-lib_map_path]\n\ +Usage: lpf_125k.sh [-reset_run]\n\ +Usage: lpf_125k.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/vhdl.prj b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/vhdl.prj new file mode 100644 index 00000000..8508e38e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/vhdl.prj @@ -0,0 +1,4 @@ +vhdl xil_defaultlib \ +"../../../ip/lpf_125k/sim/lpf_125k.vhd" \ + +nosort diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/vlog.prj new file mode 100644 index 00000000..35119d5b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/lpf_125k/xsim/vlog.prj @@ -0,0 +1,4 @@ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt new file mode 100644 index 00000000..13d33d7c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do new file mode 100644 index 00000000..1e5ae39c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/compile.do @@ -0,0 +1,27 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm +vlib activehdl/blk_mem_gen_v8_4_3 + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm +vmap blk_mem_gen_v8_4_3 activehdl/blk_mem_gen_v8_4_3 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_3 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt new file mode 100644 index 00000000..78704c4b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh new file mode 100755 index 00000000..df34cfa1 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/rom_freq_word.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/simulate.do new file mode 100644 index 00000000..b880455d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+rom_freq_word -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rom_freq_word xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {rom_freq_word.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt new file mode 100644 index 00000000..76068bd4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt new file mode 100644 index 00000000..78704c4b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh new file mode 100755 index 00000000..41e3e518 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/rom_freq_word.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.rom_freq_word \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f new file mode 100644 index 00000000..09c85501 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/ies/run.f @@ -0,0 +1,17 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/blk_mem_gen_v8_4_3 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/rom_freq_word/sim/rom_freq_word.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt new file mode 100644 index 00000000..13d33d7c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/compile.do new file mode 100644 index 00000000..8b8458a0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/file_info.txt new file mode 100644 index 00000000..fe59d479 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/file_info.txt @@ -0,0 +1,2 @@ +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh new file mode 100755 index 00000000..4b14ed75 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/rom_freq_word.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/simulate.do new file mode 100644 index 00000000..3bc7aaf4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.rom_freq_word xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {rom_freq_word.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt new file mode 100644 index 00000000..13d33d7c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do new file mode 100644 index 00000000..bd408354 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/compile.do @@ -0,0 +1,27 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm +vlib questa_lib/msim/blk_mem_gen_v8_4_3 + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm +vmap blk_mem_gen_v8_4_3 questa_lib/msim/blk_mem_gen_v8_4_3 + +vlog -work xil_defaultlib -64 -sv \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_3 -64 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -64 \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/elaborate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/elaborate.do new file mode 100644 index 00000000..f81f2bb9 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.rom_freq_word xil_defaultlib.glbl -o rom_freq_word_opt diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt new file mode 100644 index 00000000..78704c4b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh new file mode 100755 index 00000000..4bea2f53 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/rom_freq_word.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/simulate.do new file mode 100644 index 00000000..d8b2f89d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib rom_freq_word_opt + +do {wave.do} + +view wave +view structure +view signals + +do {rom_freq_word.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt new file mode 100644 index 00000000..13d33d7c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do new file mode 100644 index 00000000..1baef140 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/compile.do @@ -0,0 +1,27 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm +vlib riviera/blk_mem_gen_v8_4_3 + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm +vmap blk_mem_gen_v8_4_3 riviera/blk_mem_gen_v8_4_3 + +vlog -work xil_defaultlib -sv2k12 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work blk_mem_gen_v8_4_3 -v2k5 \ +"../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ + +vlog -work xil_defaultlib -v2k5 \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt new file mode 100644 index 00000000..78704c4b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh new file mode 100755 index 00000000..aad4981f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/rom_freq_word.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/simulate.do new file mode 100644 index 00000000..b880455d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+rom_freq_word -L xil_defaultlib -L xpm -L blk_mem_gen_v8_4_3 -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.rom_freq_word xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {rom_freq_word.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt new file mode 100644 index 00000000..13d33d7c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/file_info.txt new file mode 100644 index 00000000..fe59d479 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/file_info.txt @@ -0,0 +1,2 @@ +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh new file mode 100755 index 00000000..d943a270 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/rom_freq_word.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + "$ref_dir/../../../ip/rom_freq_word/sim/rom_freq_word.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.rom_freq_word xil_defaultlib.glbl -o rom_freq_word_simv +} + +# RUN_STEP: +simulate() +{ + ./rom_freq_word_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key rom_freq_word_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc rom_freq_word_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt new file mode 100644 index 00000000..76068bd4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt new file mode 100644 index 00000000..78704c4b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +blk_mem_gen_v8_4.v,verilog,blk_mem_gen_v8_4_3,../../../ipstatic/simulation/blk_mem_gen_v8_4.v, +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh new file mode 100755 index 00000000..890369be --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/rom_freq_word.sh @@ -0,0 +1,175 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'rom_freq_word.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm blk_mem_gen_v8_4_3) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.rom_freq_word \ + -f run.f \ + -top glbl \ + glbl.v +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f new file mode 100644 index 00000000..7720194b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xcelium/run.f @@ -0,0 +1,17 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/blk_mem_gen_v8_4_3 \ + "../../../ipstatic/simulation/blk_mem_gen_v8_4.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/rom_freq_word/sim/rom_freq_word.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt new file mode 100644 index 00000000..13d33d7c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:49:45 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./rom_freq_word.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './rom_freq_word.sh' script. + +./rom_freq_word.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./rom_freq_word.sh -noclean_files + +For more information on the script, please type './rom_freq_word.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/cmd.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/file_info.txt new file mode 100644 index 00000000..fe59d479 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/file_info.txt @@ -0,0 +1,2 @@ +rom_freq_word.v,verilog,xil_defaultlib,../../../ip/rom_freq_word/sim/rom_freq_word.v, +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe new file mode 100755 index 00000000..590747a4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/freq_word.coe @@ -0,0 +1,83 @@ +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +1624, +1611, +1598, +1585, +1572, +1559, +1546, +1533, +1520, +1507, +1494, +1481, +1468, +1455, +1442, +1429, +1416, +1403, +1390, +1377, +1364, +1351, +1338, +1325, +1312, +1299, +1286, +1273, +1260, +1247, +1234, +1221, +1208, +1195, +1182, +1169, +1156, +1143, +1130, +1117, +1104, +1091, +1078, +1065, +1052, +1039, +1026, +1013, +1000, +987, +974, +961, +948, +935, +922, +909, +896, +883, +870, +857, +844, +831, +818, +805, +792, +779, +766, +753, +740, +727, +714, +701, +688, +675, +662, +649, +636, +623, +610, +597, +584, diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif new file mode 100644 index 00000000..355400b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.mif @@ -0,0 +1,81 @@ +11001011000 +11001001011 +11000111110 +11000110001 +11000100100 +11000010111 +11000001010 +10111111101 +10111110000 +10111100011 +10111010110 +10111001001 +10110111100 +10110101111 +10110100010 +10110010101 +10110001000 +10101111011 +10101101110 +10101100001 +10101010100 +10101000111 +10100111010 +10100101101 +10100100000 +10100010011 +10100000110 +10011111001 +10011101100 +10011011111 +10011010010 +10011000101 +10010111000 +10010101011 +10010011110 +10010010001 +10010000100 +10001110111 +10001101010 +10001011101 +10001010000 +10001000011 +10000110110 +10000101001 +10000011100 +10000001111 +10000000010 +01111110101 +01111101000 +01111011011 +01111001110 +01111000001 +01110110100 +01110100111 +01110011010 +01110001101 +01110000000 +01101110011 +01101100110 +01101011001 +01101001100 +01100111111 +01100110010 +01100100101 +01100011000 +01100001011 +01011111110 +01011110001 +01011100100 +01011010111 +01011001010 +01010111101 +01010110000 +01010100011 +01010010110 +01010001001 +01001111100 +01001101111 +01001100010 +01001010101 +01001001000 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh new file mode 100755 index 00000000..21276799 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/rom_freq_word.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : rom_freq_word.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:49:45 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: rom_freq_word.sh [-help] +# usage: rom_freq_word.sh [-lib_map_path] +# usage: rom_freq_word.sh [-noclean_files] +# usage: rom_freq_word.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "rom_freq_word.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L blk_mem_gen_v8_4_3 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot rom_freq_word xil_defaultlib.rom_freq_word xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim rom_freq_word -key {Behavioral:sim_1:Functional:rom_freq_word} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb rom_freq_word.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./rom_freq_word.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: rom_freq_word.sh [-help]\n\ +Usage: rom_freq_word.sh [-lib_map_path]\n\ +Usage: rom_freq_word.sh [-reset_run]\n\ +Usage: rom_freq_word.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/vlog.prj new file mode 100644 index 00000000..5f7fb546 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/rom_freq_word/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib \ +"../../../ip/rom_freq_word/sim/rom_freq_word.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/README.txt new file mode 100644 index 00000000..d69c94d2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sig_clk_gen.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sig_clk_gen.sh' script. + +./sig_clk_gen.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sig_clk_gen.sh -noclean_files + +For more information on the script, please type './sig_clk_gen.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/compile.do new file mode 100644 index 00000000..9d28f9ca --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/compile.do @@ -0,0 +1,23 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ipstatic" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" \ +"../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v" \ +"../../../ip/sig_clk_gen/sig_clk_gen.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/file_info.txt new file mode 100644 index 00000000..eeb5e5fb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/sig_clk_gen.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/sig_clk_gen.sh new file mode 100755 index 00000000..4c56474a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/sig_clk_gen.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : sig_clk_gen.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: sig_clk_gen.sh [-help] +# usage: sig_clk_gen.sh [-lib_map_path] +# usage: sig_clk_gen.sh [-noclean_files] +# usage: sig_clk_gen.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sig_clk_gen.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "sig_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sig_clk_gen.sh [-help]\n\ +Usage: sig_clk_gen.sh [-lib_map_path]\n\ +Usage: sig_clk_gen.sh [-reset_run]\n\ +Usage: sig_clk_gen.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/sig_clk_gen.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/sig_clk_gen.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/simulate.do new file mode 100644 index 00000000..45bfcbbd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+sig_clk_gen -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.sig_clk_gen xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {sig_clk_gen.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/README.txt new file mode 100644 index 00000000..3dc81349 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sig_clk_gen.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sig_clk_gen.sh' script. + +./sig_clk_gen.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sig_clk_gen.sh -noclean_files + +For more information on the script, please type './sig_clk_gen.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/file_info.txt new file mode 100644 index 00000000..46e24277 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/run.f new file mode 100644 index 00000000..db00246d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/run.f @@ -0,0 +1,15 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v" \ + "../../../ip/sig_clk_gen/sig_clk_gen.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/sig_clk_gen.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/sig_clk_gen.sh new file mode 100755 index 00000000..e262c86f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/ies/sig_clk_gen.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : sig_clk_gen.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: sig_clk_gen.sh [-help] +# usage: sig_clk_gen.sh [-lib_map_path] +# usage: sig_clk_gen.sh [-noclean_files] +# usage: sig_clk_gen.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sig_clk_gen.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "sig_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.sig_clk_gen \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../ipstatic" \ + +incdir+"../../../ipstatic" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sig_clk_gen.sh [-help]\n\ +Usage: sig_clk_gen.sh [-lib_map_path]\n\ +Usage: sig_clk_gen.sh [-reset_run]\n\ +Usage: sig_clk_gen.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/README.txt new file mode 100644 index 00000000..d69c94d2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sig_clk_gen.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sig_clk_gen.sh' script. + +./sig_clk_gen.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sig_clk_gen.sh -noclean_files + +For more information on the script, please type './sig_clk_gen.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/compile.do new file mode 100644 index 00000000..8cc30ebb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/compile.do @@ -0,0 +1,23 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib +vlib modelsim_lib/msim/xpm + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib +vmap xpm modelsim_lib/msim/xpm + +vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ipstatic" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic" \ +"../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v" \ +"../../../ip/sig_clk_gen/sig_clk_gen.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/file_info.txt new file mode 100644 index 00000000..eeb5e5fb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/sig_clk_gen.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/sig_clk_gen.sh new file mode 100755 index 00000000..388afb1a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/sig_clk_gen.sh @@ -0,0 +1,168 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : sig_clk_gen.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: sig_clk_gen.sh [-help] +# usage: sig_clk_gen.sh [-lib_map_path] +# usage: sig_clk_gen.sh [-noclean_files] +# usage: sig_clk_gen.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sig_clk_gen.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "sig_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "" && -e $1) ]]; then + lib_map_path="$1" + else + echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sig_clk_gen.sh [-help]\n\ +Usage: sig_clk_gen.sh [-lib_map_path]\n\ +Usage: sig_clk_gen.sh [-reset_run]\n\ +Usage: sig_clk_gen.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/sig_clk_gen.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/sig_clk_gen.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/simulate.do new file mode 100644 index 00000000..9cae8bb2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.sig_clk_gen xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {sig_clk_gen.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/README.txt new file mode 100644 index 00000000..d69c94d2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sig_clk_gen.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sig_clk_gen.sh' script. + +./sig_clk_gen.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sig_clk_gen.sh -noclean_files + +For more information on the script, please type './sig_clk_gen.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/compile.do new file mode 100644 index 00000000..b187104f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/compile.do @@ -0,0 +1,23 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ipstatic" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic" \ +"../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v" \ +"../../../ip/sig_clk_gen/sig_clk_gen.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/elaborate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/elaborate.do new file mode 100644 index 00000000..208174c1 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.sig_clk_gen xil_defaultlib.glbl -o sig_clk_gen_opt diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/file_info.txt new file mode 100644 index 00000000..eeb5e5fb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/sig_clk_gen.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/sig_clk_gen.sh new file mode 100755 index 00000000..c2a8e85d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/sig_clk_gen.sh @@ -0,0 +1,173 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : sig_clk_gen.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: sig_clk_gen.sh [-help] +# usage: sig_clk_gen.sh [-lib_map_path] +# usage: sig_clk_gen.sh [-noclean_files] +# usage: sig_clk_gen.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sig_clk_gen.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "sig_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sig_clk_gen.sh [-help]\n\ +Usage: sig_clk_gen.sh [-lib_map_path]\n\ +Usage: sig_clk_gen.sh [-reset_run]\n\ +Usage: sig_clk_gen.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/sig_clk_gen.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/sig_clk_gen.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/simulate.do new file mode 100644 index 00000000..4718a7ea --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib sig_clk_gen_opt + +do {wave.do} + +view wave +view structure +view signals + +do {sig_clk_gen.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/README.txt new file mode 100644 index 00000000..d69c94d2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sig_clk_gen.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sig_clk_gen.sh' script. + +./sig_clk_gen.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sig_clk_gen.sh -noclean_files + +For more information on the script, please type './sig_clk_gen.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/compile.do new file mode 100644 index 00000000..011bc7fe --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/compile.do @@ -0,0 +1,23 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ipstatic" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" \ +"../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v" \ +"../../../ip/sig_clk_gen/sig_clk_gen.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/file_info.txt new file mode 100644 index 00000000..eeb5e5fb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen.v,incdir="../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/sig_clk_gen.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/sig_clk_gen.sh new file mode 100755 index 00000000..801dc072 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/sig_clk_gen.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : sig_clk_gen.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: sig_clk_gen.sh [-help] +# usage: sig_clk_gen.sh [-lib_map_path] +# usage: sig_clk_gen.sh [-noclean_files] +# usage: sig_clk_gen.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sig_clk_gen.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "sig_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sig_clk_gen.sh [-help]\n\ +Usage: sig_clk_gen.sh [-lib_map_path]\n\ +Usage: sig_clk_gen.sh [-reset_run]\n\ +Usage: sig_clk_gen.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/sig_clk_gen.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/sig_clk_gen.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/simulate.do new file mode 100644 index 00000000..45bfcbbd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+sig_clk_gen -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.sig_clk_gen xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {sig_clk_gen.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/README.txt new file mode 100644 index 00000000..d69c94d2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sig_clk_gen.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sig_clk_gen.sh' script. + +./sig_clk_gen.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sig_clk_gen.sh -noclean_files + +For more information on the script, please type './sig_clk_gen.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/file_info.txt new file mode 100644 index 00000000..46e24277 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/sig_clk_gen.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/sig_clk_gen.sh new file mode 100755 index 00000000..7d6a4148 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/sig_clk_gen.sh @@ -0,0 +1,230 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : sig_clk_gen.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: sig_clk_gen.sh [-help] +# usage: sig_clk_gen.sh [-lib_map_path] +# usage: sig_clk_gen.sh [-noclean_files] +# usage: sig_clk_gen.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sig_clk_gen.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "sig_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ipstatic" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + 2>&1 | tee -a vlogan.log + + vhdlan -work xpm $vhdlan_opts \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + 2>&1 | tee -a vhdlan.log + + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic" \ + "$ref_dir/../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v" \ + "$ref_dir/../../../ip/sig_clk_gen/sig_clk_gen.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.sig_clk_gen xil_defaultlib.glbl -o sig_clk_gen_simv +} + +# RUN_STEP: +simulate() +{ + ./sig_clk_gen_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key sig_clk_gen_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc sig_clk_gen_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sig_clk_gen.sh [-help]\n\ +Usage: sig_clk_gen.sh [-lib_map_path]\n\ +Usage: sig_clk_gen.sh [-reset_run]\n\ +Usage: sig_clk_gen.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/README.txt new file mode 100644 index 00000000..3dc81349 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sig_clk_gen.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sig_clk_gen.sh' script. + +./sig_clk_gen.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sig_clk_gen.sh -noclean_files + +For more information on the script, please type './sig_clk_gen.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/file_info.txt new file mode 100644 index 00000000..46e24277 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/file_info.txt @@ -0,0 +1,6 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_memory.sv,systemverilog,xil_defaultlib,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +xpm_VCOMP.vhd,vhdl,xpm,../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/run.f new file mode 100644 index 00000000..b19be638 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/run.f @@ -0,0 +1,15 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v" \ + "../../../ip/sig_clk_gen/sig_clk_gen.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/sig_clk_gen.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/sig_clk_gen.sh new file mode 100755 index 00000000..3cdf74b2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xcelium/sig_clk_gen.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : sig_clk_gen.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: sig_clk_gen.sh [-help] +# usage: sig_clk_gen.sh [-lib_map_path] +# usage: sig_clk_gen.sh [-noclean_files] +# usage: sig_clk_gen.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'sig_clk_gen.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "sig_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.sig_clk_gen \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"$ref_dir/../../../ipstatic" \ + +incdir+"../../../ipstatic" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sig_clk_gen.sh [-help]\n\ +Usage: sig_clk_gen.sh [-lib_map_path]\n\ +Usage: sig_clk_gen.sh [-reset_run]\n\ +Usage: sig_clk_gen.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/README.txt new file mode 100644 index 00000000..d69c94d2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu Apr 13 10:59:39 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./sig_clk_gen.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './sig_clk_gen.sh' script. + +./sig_clk_gen.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./sig_clk_gen.sh -noclean_files + +For more information on the script, please type './sig_clk_gen.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/cmd.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/file_info.txt new file mode 100644 index 00000000..52acc685 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/file_info.txt @@ -0,0 +1,3 @@ +sig_clk_gen_clk_wiz.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +sig_clk_gen.v,verilog,xil_defaultlib,../../../ip/sig_clk_gen/sig_clk_gen.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/sig_clk_gen.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/sig_clk_gen.sh new file mode 100755 index 00000000..f0254df1 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/sig_clk_gen.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : sig_clk_gen.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu Apr 13 10:59:39 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: sig_clk_gen.sh [-help] +# usage: sig_clk_gen.sh [-lib_map_path] +# usage: sig_clk_gen.sh [-noclean_files] +# usage: sig_clk_gen.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "sig_clk_gen.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot sig_clk_gen xil_defaultlib.sig_clk_gen xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim sig_clk_gen -key {Behavioral:sim_1:Functional:sig_clk_gen} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=(xil_defaultlib) + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb sig_clk_gen.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./sig_clk_gen.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: sig_clk_gen.sh [-help]\n\ +Usage: sig_clk_gen.sh [-lib_map_path]\n\ +Usage: sig_clk_gen.sh [-reset_run]\n\ +Usage: sig_clk_gen.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/vlog.prj new file mode 100644 index 00000000..94ba6a4a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/sig_clk_gen/xsim/vlog.prj @@ -0,0 +1,7 @@ +verilog xil_defaultlib --include "../../../ipstatic" \ +"../../../ip/sig_clk_gen/sig_clk_gen_clk_wiz.v" \ +"../../../ip/sig_clk_gen/sig_clk_gen.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt new file mode 100644 index 00000000..2fa77f2b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do new file mode 100644 index 00000000..1f6495c2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/simulate.do new file mode 100644 index 00000000..dc4a0b81 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_manual_ctrl -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_manual_ctrl.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh new file mode 100755 index 00000000..edb0b36b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/vio_manual_ctrl.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt new file mode 100644 index 00000000..348c0719 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f new file mode 100644 index 00000000..36f5e07d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh new file mode 100755 index 00000000..c5f1490f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/ies/vio_manual_ctrl.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_manual_ctrl \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_manual_ctrl/hdl/verilog" \ + +incdir+"../../../ip/vio_manual_ctrl/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt new file mode 100644 index 00000000..2fa77f2b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/compile.do new file mode 100644 index 00000000..59c2be37 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/file_info.txt new file mode 100644 index 00000000..23d1ee0b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/file_info.txt @@ -0,0 +1,2 @@ +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/simulate.do new file mode 100644 index 00000000..2dedf95d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {vio_manual_ctrl.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh new file mode 100755 index 00000000..c5be1668 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/vio_manual_ctrl.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt new file mode 100644 index 00000000..2fa77f2b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/compile.do new file mode 100644 index 00000000..a2f2d23e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/elaborate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/elaborate.do new file mode 100644 index 00000000..e5aaa3c5 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl -o vio_manual_ctrl_opt diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/simulate.do new file mode 100644 index 00000000..f829579e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib vio_manual_ctrl_opt + +do {wave.do} + +view wave +view structure +view signals + +do {vio_manual_ctrl.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh new file mode 100755 index 00000000..61c3a61f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/vio_manual_ctrl.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt new file mode 100644 index 00000000..2fa77f2b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/compile.do new file mode 100644 index 00000000..8710eef1 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_manual_ctrl/hdl/verilog" "+incdir+../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/simulate.do new file mode 100644 index 00000000..dc4a0b81 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_manual_ctrl -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_manual_ctrl.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh new file mode 100755 index 00000000..9f2c82be --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/vio_manual_ctrl.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt new file mode 100644 index 00000000..2fa77f2b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/file_info.txt new file mode 100644 index 00000000..23d1ee0b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/file_info.txt @@ -0,0 +1,2 @@ +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh new file mode 100755 index 00000000..bf5e5f8f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/vcs/vio_manual_ctrl.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_manual_ctrl/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_manual_ctrl/hdl" \ + "$ref_dir/../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl -o vio_manual_ctrl_simv +} + +# RUN_STEP: +simulate() +{ + ./vio_manual_ctrl_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key vio_manual_ctrl_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_manual_ctrl_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt new file mode 100644 index 00000000..348c0719 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/file_info.txt new file mode 100644 index 00000000..f5242d57 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/run.f new file mode 100644 index 00000000..f65ce74a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh new file mode 100755 index 00000000..9d1b0838 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xcelium/vio_manual_ctrl.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_manual_ctrl.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_manual_ctrl \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_manual_ctrl/hdl/verilog" \ + +incdir+"../../../ip/vio_manual_ctrl/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt new file mode 100644 index 00000000..2fa77f2b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Mon May 08 17:55:43 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_manual_ctrl.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_manual_ctrl.sh' script. + +./vio_manual_ctrl.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_manual_ctrl.sh -noclean_files + +For more information on the script, please type './vio_manual_ctrl.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/cmd.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/file_info.txt new file mode 100644 index 00000000..23d1ee0b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/file_info.txt @@ -0,0 +1,2 @@ +vio_manual_ctrl.v,verilog,xil_defaultlib,../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v,incdir="../../../ip/vio_manual_ctrl/hdl/verilog"incdir="../../../ip/vio_manual_ctrl/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh new file mode 100755 index 00000000..e9df6963 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vio_manual_ctrl.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_manual_ctrl.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Mon May 08 17:55:43 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_manual_ctrl.sh [-help] +# usage: vio_manual_ctrl.sh [-lib_map_path] +# usage: vio_manual_ctrl.sh [-noclean_files] +# usage: vio_manual_ctrl.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "vio_manual_ctrl.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_manual_ctrl xil_defaultlib.vio_manual_ctrl xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim vio_manual_ctrl -key {Behavioral:sim_1:Functional:vio_manual_ctrl} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_manual_ctrl.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_manual_ctrl.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_manual_ctrl.sh [-help]\n\ +Usage: vio_manual_ctrl.sh [-lib_map_path]\n\ +Usage: vio_manual_ctrl.sh [-reset_run]\n\ +Usage: vio_manual_ctrl.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vlog.prj new file mode 100644 index 00000000..5036d554 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_manual_ctrl/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/vio_manual_ctrl/hdl/verilog" --include "../../../ip/vio_manual_ctrl/hdl" \ +"../../../ip/vio_manual_ctrl/sim/vio_manual_ctrl.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/README.txt new file mode 100644 index 00000000..cf9b236c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/compile.do new file mode 100644 index 00000000..192201b2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/file_info.txt new file mode 100644 index 00000000..5d1c0b80 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/simulate.do new file mode 100644 index 00000000..ffcd11d6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_rf_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rf_control xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_rf_control.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.sh new file mode 100755 index 00000000..57722fc1 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_control.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/vio_rf_control.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/README.txt new file mode 100644 index 00000000..5f27dcbd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/file_info.txt new file mode 100644 index 00000000..5d1c0b80 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/run.f new file mode 100644 index 00000000..e4edaabe --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/vio_rf_control/sim/vio_rf_control.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/vio_rf_control.sh new file mode 100755 index 00000000..58e0866d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/ies/vio_rf_control.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_control.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_rf_control \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_rf_control/hdl/verilog" \ + +incdir+"../../../ip/vio_rf_control/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/README.txt new file mode 100644 index 00000000..cf9b236c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/compile.do new file mode 100644 index 00000000..747a39e2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/file_info.txt new file mode 100644 index 00000000..6afb6a11 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/file_info.txt @@ -0,0 +1,2 @@ +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/simulate.do new file mode 100644 index 00000000..a8dfaf75 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_rf_control xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {vio_rf_control.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.sh new file mode 100755 index 00000000..b1fbd79c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_control.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/vio_rf_control.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/README.txt new file mode 100644 index 00000000..cf9b236c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/compile.do new file mode 100644 index 00000000..d50d8c8e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/elaborate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/elaborate.do new file mode 100644 index 00000000..904131c9 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_rf_control xil_defaultlib.glbl -o vio_rf_control_opt diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/file_info.txt new file mode 100644 index 00000000..5d1c0b80 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/simulate.do new file mode 100644 index 00000000..5aa3f82e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib vio_rf_control_opt + +do {wave.do} + +view wave +view structure +view signals + +do {vio_rf_control.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.sh new file mode 100755 index 00000000..c459e240 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_control.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/vio_rf_control.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/README.txt new file mode 100644 index 00000000..cf9b236c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/compile.do new file mode 100644 index 00000000..72ffdcee --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rf_control/hdl/verilog" "+incdir+../../../ip/vio_rf_control/hdl" \ +"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/file_info.txt new file mode 100644 index 00000000..5d1c0b80 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/simulate.do new file mode 100644 index 00000000..ffcd11d6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_rf_control -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rf_control xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_rf_control.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.sh new file mode 100755 index 00000000..48413816 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_control.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/vio_rf_control.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/README.txt new file mode 100644 index 00000000..cf9b236c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/file_info.txt new file mode 100644 index 00000000..6afb6a11 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/file_info.txt @@ -0,0 +1,2 @@ +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/vio_rf_control.sh new file mode 100755 index 00000000..d5e47f1b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/vcs/vio_rf_control.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_control.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_rf_control/hdl" \ + "$ref_dir/../../../ip/vio_rf_control/sim/vio_rf_control.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.vio_rf_control xil_defaultlib.glbl -o vio_rf_control_simv +} + +# RUN_STEP: +simulate() +{ + ./vio_rf_control_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key vio_rf_control_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_rf_control_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/README.txt new file mode 100644 index 00000000..5f27dcbd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/file_info.txt new file mode 100644 index 00000000..5d1c0b80 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/run.f new file mode 100644 index 00000000..60d4bd69 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/vio_rf_control/sim/vio_rf_control.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/vio_rf_control.sh new file mode 100755 index 00000000..bc9d642d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xcelium/vio_rf_control.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_control.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_control.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_rf_control \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_rf_control/hdl/verilog" \ + +incdir+"../../../ip/vio_rf_control/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/README.txt new file mode 100644 index 00000000..cf9b236c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 11:36:22 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_control.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_control.sh' script. + +./vio_rf_control.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_control.sh -noclean_files + +For more information on the script, please type './vio_rf_control.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/cmd.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/file_info.txt new file mode 100644 index 00000000..6afb6a11 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/file_info.txt @@ -0,0 +1,2 @@ +vio_rf_control.v,verilog,xil_defaultlib,../../../ip/vio_rf_control/sim/vio_rf_control.v,incdir="../../../ip/vio_rf_control/hdl/verilog"incdir="../../../ip/vio_rf_control/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vio_rf_control.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vio_rf_control.sh new file mode 100755 index 00000000..4efab4f6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vio_rf_control.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_control.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 11:36:22 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_control.sh [-help] +# usage: vio_rf_control.sh [-lib_map_path] +# usage: vio_rf_control.sh [-noclean_files] +# usage: vio_rf_control.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "vio_rf_control.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_rf_control xil_defaultlib.vio_rf_control xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim vio_rf_control -key {Behavioral:sim_1:Functional:vio_rf_control} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_rf_control.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_control.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_control.sh [-help]\n\ +Usage: vio_rf_control.sh [-lib_map_path]\n\ +Usage: vio_rf_control.sh [-reset_run]\n\ +Usage: vio_rf_control.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vlog.prj new file mode 100644 index 00000000..b28359a7 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_control/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/vio_rf_control/hdl/verilog" --include "../../../ip/vio_rf_control/hdl" \ +"../../../ip/vio_rf_control/sim/vio_rf_control.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/README.txt new file mode 100644 index 00000000..f3d66c82 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/README.txt @@ -0,0 +1,83 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required +# to simulate the design for a simulator, the directory structure +# and the generated exported files. +# +################################################################################ + +1. Simulate Design + +To simulate design, cd to the simulator directory and execute the script. + +For example:- + +% cd questa +% ./top.sh + +The export simulation flow requires the Xilinx pre-compiled simulation library +components for the target simulator. These components are referred using the +'-lib_map_path' switch. If this switch is specified, then the export simulation +will automatically set this library path in the generated script and update, +copy the simulator setup file(s) in the exported directory. + +If '-lib_map_path' is not specified, then the pre-compiled simulation library +information will not be included in the exported scripts and that may cause +simulation errors when running this script. Alternatively, you can provide the +library information using this switch while executing the generated script. + +For example:- + +% ./top.sh -lib_map_path /design/questa/clibs + +Please refer to the generated script header 'Prerequisite' section for more details. + +2. Directory Structure + +By default, if the -directory switch is not specified, export_simulation will +create the following directory structure:- + +/export_sim/ + +For example, if the current working directory is /tmp/test, export_simulation +will create the following directory path:- + +/tmp/test/export_sim/questa + +If -directory switch is specified, export_simulation will create a simulator +sub-directory under the specified directory path. + +For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim' +command will create the following directory:- + +/tmp/test/my_test_area/func_sim/questa + +By default, if -simulator is not specified, export_simulation will create a +simulator sub-directory for each simulator and export the files for each simulator +in this sub-directory respectively. + +IMPORTANT: Please note that the simulation library path must be specified manually +in the generated script for the respective simulator. Please refer to the generated +script header 'Prerequisite' section for more details. + +3. Exported script and files + +Export simulation will create the driver shell script, setup files and copy the +design sources in the output directory path. + +By default, when the -script_name switch is not specified, export_simulation will +create the following script name:- + +.sh (Unix) +When exporting the files for an IP using the -of_objects switch, export_simulation +will create the following script name:- + +.sh (Unix) +Export simulation will create the setup files for the target simulator specified +with the -simulator switch. + +For example, if the target simulator is "ies", export_simulation will create the +'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib' +file. + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/README.txt new file mode 100644 index 00000000..6760b784 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_test.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_test.sh' script. + +./vio_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_test.sh -noclean_files + +For more information on the script, please type './vio_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/compile.do new file mode 100644 index 00000000..ccd5b864 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib activehdl + +vlib activehdl/xil_defaultlib +vlib activehdl/xpm + +vmap xil_defaultlib activehdl/xil_defaultlib +vmap xpm activehdl/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ +"../../../ip/vio_rf_test/sim/vio_rf_test.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/file_info.txt new file mode 100644 index 00000000..90af45a6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/simulate.do new file mode 100644 index 00000000..19aa03d3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_rf_test -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rf_test xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_rf_test.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/vio_rf_test.sh new file mode 100755 index 00000000..34dc2659 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/vio_rf_test.sh @@ -0,0 +1,152 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_test.sh +# Simulator : Aldec Active-HDL Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:23 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_test.sh [-help] +# usage: vio_rf_test.sh [-lib_map_path] +# usage: vio_rf_test.sh [-noclean_files] +# usage: vio_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + lib_map_path="" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_test.sh [-help]\n\ +Usage: vio_rf_test.sh [-lib_map_path]\n\ +Usage: vio_rf_test.sh [-reset_run]\n\ +Usage: vio_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/vio_rf_test.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/vio_rf_test.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/activehdl/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/README.txt new file mode 100644 index 00000000..467b8785 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_test.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_test.sh' script. + +./vio_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_test.sh -noclean_files + +For more information on the script, please type './vio_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/file_info.txt new file mode 100644 index 00000000..90af45a6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/run.f new file mode 100644 index 00000000..e85f930f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/run.f @@ -0,0 +1,14 @@ +-makelib ies_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib ies_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + "../../../ip/vio_rf_test/sim/vio_rf_test.v" \ +-endlib +-makelib ies_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/vio_rf_test.sh new file mode 100755 index 00000000..99e30094 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/ies/vio_rf_test.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_test.sh +# Simulator : Cadence Incisive Enterprise Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:23 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_test.sh [-help] +# usage: vio_rf_test.sh [-lib_map_path] +# usage: vio_rf_test.sh [-noclean_files] +# usage: vio_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="ies_lib" + +# Script info +echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + irun $irun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_rf_test \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_rf_test/hdl/verilog" \ + +incdir+"../../../ip/vio_rf_test/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_test.sh [-help]\n\ +Usage: vio_rf_test.sh [-lib_map_path]\n\ +Usage: vio_rf_test.sh [-reset_run]\n\ +Usage: vio_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/README.txt new file mode 100644 index 00000000..6760b784 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_test.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_test.sh' script. + +./vio_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_test.sh -noclean_files + +For more information on the script, please type './vio_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/compile.do new file mode 100644 index 00000000..d2f17c3d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/compile.do @@ -0,0 +1,14 @@ +vlib modelsim_lib/work +vlib modelsim_lib/msim + +vlib modelsim_lib/msim/xil_defaultlib + +vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib + +vlog -work xil_defaultlib -64 -incr "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ +"../../../ip/vio_rf_test/sim/vio_rf_test.v" \ + + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/file_info.txt new file mode 100644 index 00000000..7d0ff7cd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/file_info.txt @@ -0,0 +1,2 @@ +vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/simulate.do new file mode 100644 index 00000000..476df0a8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.vio_rf_test xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure +view signals + +do {vio_rf_test.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/vio_rf_test.sh new file mode 100755 index 00000000..99640f03 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/vio_rf_test.sh @@ -0,0 +1,167 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_test.sh +# Simulator : Mentor Graphics ModelSim Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:23 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_test.sh [-help] +# usage: vio_rf_test.sh [-lib_map_path] +# usage: vio_rf_test.sh [-noclean_files] +# usage: vio_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/Model/2019.1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="modelsim_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_test.sh [-help]\n\ +Usage: vio_rf_test.sh [-lib_map_path]\n\ +Usage: vio_rf_test.sh [-reset_run]\n\ +Usage: vio_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/vio_rf_test.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/vio_rf_test.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/modelsim/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/README.txt new file mode 100644 index 00000000..6760b784 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_test.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_test.sh' script. + +./vio_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_test.sh -noclean_files + +For more information on the script, please type './vio_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/compile.do new file mode 100644 index 00000000..208a8940 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/compile.do @@ -0,0 +1,22 @@ +vlib questa_lib/work +vlib questa_lib/msim + +vlib questa_lib/msim/xil_defaultlib +vlib questa_lib/msim/xpm + +vmap xil_defaultlib questa_lib/msim/xil_defaultlib +vmap xpm questa_lib/msim/xpm + +vlog -work xil_defaultlib -64 -sv "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -64 -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -64 "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ +"../../../ip/vio_rf_test/sim/vio_rf_test.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/elaborate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/elaborate.do new file mode 100644 index 00000000..a6051f2c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/elaborate.do @@ -0,0 +1 @@ +vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.vio_rf_test xil_defaultlib.glbl -o vio_rf_test_opt diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/file_info.txt new file mode 100644 index 00000000..90af45a6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/simulate.do new file mode 100644 index 00000000..71d9432f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/simulate.do @@ -0,0 +1,16 @@ +onbreak {quit -f} +onerror {quit -f} + +vsim -t 1ps -lib xil_defaultlib vio_rf_test_opt + +do {wave.do} + +view wave +view structure +view signals + +do {vio_rf_test.udo} + +run -all + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/vio_rf_test.sh new file mode 100755 index 00000000..784bd298 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/vio_rf_test.sh @@ -0,0 +1,174 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_test.sh +# Simulator : Mentor Graphics Questa Advanced Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:23 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_test.sh [-help] +# usage: vio_rf_test.sh [-lib_map_path] +# usage: vio_rf_test.sh [-noclean_files] +# usage: vio_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +elaborate() +{ + source elaborate.do 2>&1 | tee -a elaborate.log +} + +# RUN_STEP: +simulate() +{ + vsim -64 -c -do "do {simulate.do}" -l simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Copy modelsim.ini file +copy_setup_file() +{ + file="modelsim.ini" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/questa" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + cp $src_file . + fi +} + +# Create design library directory +create_lib_dir() +{ + lib_dir="questa_lib" + if [[ -e $lib_dir ]]; then + rm -rf $lib_dir + fi + + mkdir $lib_dir + +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_test.sh [-help]\n\ +Usage: vio_rf_test.sh [-lib_map_path]\n\ +Usage: vio_rf_test.sh [-reset_run]\n\ +Usage: vio_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/vio_rf_test.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/vio_rf_test.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/questa/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/README.txt new file mode 100644 index 00000000..6760b784 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_test.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_test.sh' script. + +./vio_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_test.sh -noclean_files + +For more information on the script, please type './vio_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/compile.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/compile.do new file mode 100644 index 00000000..1516448e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/compile.do @@ -0,0 +1,22 @@ +vlib work +vlib riviera + +vlib riviera/xil_defaultlib +vlib riviera/xpm + +vmap xil_defaultlib riviera/xil_defaultlib +vmap xpm riviera/xpm + +vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + +vcom -work xpm -93 \ +"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + +vlog -work xil_defaultlib -v2k5 "+incdir+../../../ip/vio_rf_test/hdl/verilog" "+incdir+../../../ip/vio_rf_test/hdl" \ +"../../../ip/vio_rf_test/sim/vio_rf_test.v" \ + +vlog -work xil_defaultlib \ +"glbl.v" + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/file_info.txt new file mode 100644 index 00000000..90af45a6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/simulate.do new file mode 100644 index 00000000..19aa03d3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/simulate.do @@ -0,0 +1,17 @@ +onbreak {quit -force} +onerror {quit -force} + +asim -t 1ps +access +r +m+vio_rf_test -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.vio_rf_test xil_defaultlib.glbl + +do {wave.do} + +view wave +view structure + +do {vio_rf_test.udo} + +run -all + +endsim + +quit -force diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/vio_rf_test.sh new file mode 100755 index 00000000..f6be4aaa --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/vio_rf_test.sh @@ -0,0 +1,153 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_test.sh +# Simulator : Aldec Riviera-PRO Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:23 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_test.sh [-help] +# usage: vio_rf_test.sh [-lib_map_path] +# usage: vio_rf_test.sh [-noclean_files] +# usage: vio_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + + +# Script info +echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + source compile.do 2>&1 | tee -a compile.log + +} + +# RUN_STEP: +simulate() +{ + runvsimsa -l simulate.log -do "do {simulate.do}" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + map_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + map_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Map library.cfg file +map_setup_file() +{ + file="library.cfg" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/compile_simlib/riviera" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + vmap -link $lib_map_path + fi + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_test.sh [-help]\n\ +Usage: vio_rf_test.sh [-lib_map_path]\n\ +Usage: vio_rf_test.sh [-reset_run]\n\ +Usage: vio_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/vio_rf_test.udo b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/vio_rf_test.udo new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/wave.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/wave.do new file mode 100644 index 00000000..70157b0c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/riviera/wave.do @@ -0,0 +1,2 @@ +add wave * +add wave /glbl/GSR diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/README.txt new file mode 100644 index 00000000..6760b784 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_test.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_test.sh' script. + +./vio_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_test.sh -noclean_files + +For more information on the script, please type './vio_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/file_info.txt new file mode 100644 index 00000000..7d0ff7cd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/file_info.txt @@ -0,0 +1,2 @@ +vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/simulate.do b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/simulate.do new file mode 100644 index 00000000..58afc787 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/simulate.do @@ -0,0 +1,2 @@ +run +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/vio_rf_test.sh new file mode 100755 index 00000000..eaa918ef --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/vcs/vio_rf_test.sh @@ -0,0 +1,221 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_test.sh +# Simulator : Synopsys Verilog Compiler Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:23 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_test.sh [-help] +# usage: vio_rf_test.sh [-lib_map_path] +# usage: vio_rf_test.sh [-noclean_files] +# usage: vio_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Command line options +vlogan_opts="-full64" +vhdlan_opts="-full64" +vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log" +vcs_sim_opts="-ucli -licqueue -l simulate.log" + +# Design libraries +design_libs=(xil_defaultlib) + +# Simulation root library directory +sim_lib_dir="vcs_lib" + +# Script info +echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ip/vio_rf_test/hdl/verilog" +incdir+"$ref_dir/../../../ip/vio_rf_test/hdl" \ + "$ref_dir/../../../ip/vio_rf_test/sim/vio_rf_test.v" \ + 2>&1 | tee -a vlogan.log + + + vlogan -work xil_defaultlib $vlogan_opts +v2k \ + glbl.v \ + 2>&1 | tee -a vlogan.log + +} + +# RUN_STEP: +elaborate() +{ + vcs $vcs_elab_opts xil_defaultlib.vio_rf_test xil_defaultlib.glbl -o vio_rf_test_simv +} + +# RUN_STEP: +simulate() +{ + ./vio_rf_test_simv $vcs_sim_opts -do simulate.do +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + create_lib_mappings $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + create_lib_mappings $2 + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Define design library mappings +create_lib_mappings() +{ + file="synopsys_sim.setup" + if [[ -e $file ]]; then + if [[ ($1 == "") ]]; then + return + else + rm -rf $file + fi + fi + + touch $file + + if [[ ($1 != "") ]]; then + lib_map_path="$1" + else + lib_map_path="/home/josh/Software/Xilinx/CompLib/VCS/2019.1" + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + mapping="$lib:$sim_lib_dir/$lib" + echo $mapping >> $file + done + + if [[ ($lib_map_path != "") ]]; then + incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup" + echo $incl_ref >> $file + fi +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(ucli.key vio_rf_test_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc vio_rf_test_simv.daidir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_test.sh [-help]\n\ +Usage: vio_rf_test.sh [-lib_map_path]\n\ +Usage: vio_rf_test.sh [-reset_run]\n\ +Usage: vio_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/README.txt new file mode 100644 index 00000000..467b8785 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/README.txt @@ -0,0 +1,48 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_test.sh + +This command will launch the 'execute' function for the single-step flow. This +function is called from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_test.sh' script. + +./vio_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_test.sh -noclean_files + +For more information on the script, please type './vio_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/file_info.txt new file mode 100644 index 00000000..90af45a6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/file_info.txt @@ -0,0 +1,5 @@ +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +xpm_memory.sv,systemverilog,xil_defaultlib,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +xpm_VCOMP.vhd,vhdl,xpm,../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/run.f b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/run.f new file mode 100644 index 00000000..4ca48e89 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/run.f @@ -0,0 +1,14 @@ +-makelib xcelium_lib/xil_defaultlib -sv \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +-endlib +-makelib xcelium_lib/xpm \ + "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + "../../../ip/vio_rf_test/sim/vio_rf_test.v" \ +-endlib +-makelib xcelium_lib/xil_defaultlib \ + glbl.v +-endlib + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/vio_rf_test.sh new file mode 100755 index 00000000..eec41381 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xcelium/vio_rf_test.sh @@ -0,0 +1,177 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_test.sh +# Simulator : Cadence Xcelium Parallel Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:23 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_test.sh [-help] +# usage: vio_rf_test.sh [-lib_map_path] +# usage: vio_rf_test.sh [-noclean_files] +# usage: vio_rf_test.sh [-reset_run] +# +# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the +# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the +# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch +# that points to these libraries and rerun export_simulation. For more information about this switch please +# type 'export_simulation -help' in the Tcl shell. +# +# You can also point to the simulation libraries by either replacing the in this +# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when +# executing this script. Please type 'vio_rf_test.sh -help' for more information. +# +# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)' +# +#********************************************************************************************************* + +# Directory path for design sources and include directories (if any) wrt this path +ref_dir="." + +# Override directory with 'export_sim_ref_dir' env path value if set in the shell +if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then + ref_dir="$export_sim_ref_dir" +fi + +# Set the compiled library directory +ref_lib_dir="." + +# Command line options +xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen" + +# Design libraries +design_libs=(xil_defaultlib xpm) + +# Simulation root library directory +sim_lib_dir="xcelium_lib" + +# Script info +echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + execute +} + +# RUN_STEP: +execute() +{ + xrun $xrun_opts \ + -reflib "$ref_lib_dir/unisim:unisim" \ + -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \ + -reflib "$ref_lib_dir/secureip:secureip" \ + -reflib "$ref_lib_dir/unimacro:unimacro" \ + -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \ + -top xil_defaultlib.vio_rf_test \ + -f run.f \ + -top glbl \ + glbl.v \ + +incdir+"../../../ip/vio_rf_test/hdl/verilog" \ + +incdir+"../../../ip/vio_rf_test/hdl" +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + else + ref_lib_dir=$2 + fi + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + esac + + create_lib_dir + + # Add any setup/initialization commands here:- + + # + +} + +# Create design library directory paths +create_lib_dir() +{ + if [[ -e $sim_lib_dir ]]; then + rm -rf $sim_lib_dir + fi + + for (( i=0; i<${#design_libs[*]}; i++ )); do + lib="${design_libs[i]}" + lib_dir="$sim_lib_dir/$lib" + if [[ ! -e $lib_dir ]]; then + mkdir -p $lib_dir + fi + done +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done + + create_lib_dir +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_test.sh [-help]\n\ +Usage: vio_rf_test.sh [-lib_map_path]\n\ +Usage: vio_rf_test.sh [-reset_run]\n\ +Usage: vio_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/README.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/README.txt new file mode 100644 index 00000000..6760b784 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/README.txt @@ -0,0 +1,49 @@ +################################################################################ +# Vivado (TM) v2019.1.3 (64-bit) +# +# README.txt: Please read the sections below to understand the steps required to +# run the exported script and information about the source files. +# +# Generated by export_simulation on Thu May 18 12:54:23 CST 2023 +# +################################################################################ + +1. How to run the generated simulation script:- + +From the shell prompt in the current directory, issue the following command:- + +./vio_rf_test.sh + +This command will launch the 'compile', 'elaborate' and 'simulate' functions +implemented in the script file for the 3-step flow. These functions are called +from the main 'run' function in the script file. + +The 'run' function first executes the 'setup' function, the purpose of which is to +create simulator specific setup files, create design library mappings and library +directories and copy 'glbl.v' from the Vivado software install location into the +current directory. + +The 'setup' function is also used for removing the simulator generated data in +order to reset the current directory to the original state when export_simulation +was launched from Vivado. This generated data can be removed by specifying the +'-reset_run' switch to the './vio_rf_test.sh' script. + +./vio_rf_test.sh -reset_run + +To keep the generated data from the previous run but regenerate the setup files and +library directories, use the '-noclean_files' switch. + +./vio_rf_test.sh -noclean_files + +For more information on the script, please type './vio_rf_test.sh -help'. + +2. Additional design information files:- + +export_simulation generates following additional file that can be used for fetching +the design files information or for integrating with external custom scripts. + +Name : file_info.txt +Purpose: This file contains detail design file information based on the compile order + when export_simulation was executed from Vivado. The file contains information + about the file type, name, whether it is part of the IP, associated library + and the file path information. diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/cmd.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/cmd.tcl new file mode 100644 index 00000000..eef7a0f0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/cmd.tcl @@ -0,0 +1,12 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run -all +quit diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/file_info.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/file_info.txt new file mode 100644 index 00000000..7d0ff7cd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/file_info.txt @@ -0,0 +1,2 @@ +vio_rf_test.v,verilog,xil_defaultlib,../../../ip/vio_rf_test/sim/vio_rf_test.v,incdir="../../../ip/vio_rf_test/hdl/verilog"incdir="../../../ip/vio_rf_test/hdl" +glbl.v,Verilog,xil_defaultlib,glbl.v diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/glbl.v b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/glbl.v new file mode 100644 index 00000000..be642335 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/glbl.v @@ -0,0 +1,71 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/vio_rf_test.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/vio_rf_test.sh new file mode 100755 index 00000000..12529a4f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/vio_rf_test.sh @@ -0,0 +1,212 @@ +#!/bin/bash -f +#********************************************************************************************************* +# Vivado (TM) v2019.1.3 (64-bit) +# +# Filename : vio_rf_test.sh +# Simulator : Xilinx Vivado Simulator +# Description : Simulation script for compiling, elaborating and verifying the project source files. +# The script will automatically create the design libraries sub-directories in the run +# directory, add the library logical mappings in the simulator setup file, create default +# 'do/prj' file, execute compilation, elaboration and simulation steps. +# +# Generated by Vivado on Thu May 18 12:54:23 CST 2023 +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# +# usage: vio_rf_test.sh [-help] +# usage: vio_rf_test.sh [-lib_map_path] +# usage: vio_rf_test.sh [-noclean_files] +# usage: vio_rf_test.sh [-reset_run] +# +#********************************************************************************************************* + +# Command line options +xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xvlog_opts="--relax" + + +# Script info +echo -e "vio_rf_test.sh - Script generated by export_simulation (Vivado v2019.1.3 (64-bit)-id)\n" + +# Main steps +run() +{ + check_args $# $1 + setup $1 $2 + compile + elaborate + simulate +} + +# RUN_STEP: +compile() +{ + # Compile design files + xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log + +} + +# RUN_STEP: +elaborate() +{ + xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot vio_rf_test xil_defaultlib.vio_rf_test xil_defaultlib.glbl -log elaborate.log +} + +# RUN_STEP: +simulate() +{ + xsim vio_rf_test -key {Behavioral:sim_1:Functional:vio_rf_test} -tclbatch cmd.tcl -log simulate.log +} + +# STEP: setup +setup() +{ + case $1 in + "-lib_map_path" ) + if [[ ($2 == "") ]]; then + echo -e "ERROR: Simulation library directory path not specified (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + copy_setup_file $2 + ;; + "-reset_run" ) + reset_run + echo -e "INFO: Simulation run files deleted.\n" + exit 0 + ;; + "-noclean_files" ) + # do not remove previous data + ;; + * ) + copy_setup_file $2 + esac + + # Add any setup/initialization commands here:- + + # + +} + +# Copy xsim.ini file +copy_setup_file() +{ + file="xsim.ini" + lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + if [[ ($1 != "") ]]; then + lib_map_path="$1" + fi + if [[ ($lib_map_path != "") ]]; then + src_file="$lib_map_path/$file" + if [[ -e $src_file ]]; then + cp $src_file . + fi + + # Map local design libraries to xsim.ini + map_local_libs + + fi +} + +# Map local design libraries +map_local_libs() +{ + updated_mappings=() + local_mappings=() + + # Local design libraries + local_libs=() + + if [[ 0 == ${#local_libs[@]} ]]; then + return + fi + + file="xsim.ini" + file_backup="xsim.ini.bak" + + if [[ -e $file ]]; then + rm -f $file_backup + # Create a backup copy of the xsim.ini file + cp $file $file_backup + # Read libraries from backup file and search in local library collection + while read -r line + do + IN=$line + # Split mapping entry with '=' delimiter to fetch library name and mapping + read lib_name mapping <<<$(IFS="="; echo $IN) + # If local library found, then construct the local mapping and add to local mapping collection + if `echo ${local_libs[@]} | grep -wq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + local_mappings+=("$lib_name") + fi + # Add to updated library mapping collection + updated_mappings+=("$line") + done < "$file_backup" + # Append local libraries not found originally from xsim.ini + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then + line="$lib_name=xsim.dir/$lib_name" + updated_mappings+=("$line") + fi + done + # Write updated mappings in xsim.ini + rm -f $file + for (( i=0; i<${#updated_mappings[*]}; i++ )); do + lib_name="${updated_mappings[i]}" + echo $lib_name >> $file + done + else + for (( i=0; i<${#local_libs[*]}; i++ )); do + lib_name="${local_libs[i]}" + mapping="$lib_name=xsim.dir/$lib_name" + echo $mapping >> $file + done + fi +} + +# Delete generated data from the previous run +reset_run() +{ + files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb vio_rf_test.wdb xsim.dir) + for (( i=0; i<${#files_to_remove[*]}; i++ )); do + file="${files_to_remove[i]}" + if [[ -e $file ]]; then + rm -rf $file + fi + done +} + +# Check command line arguments +check_args() +{ + if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then + echo -e "ERROR: Unknown option specified '$2' (type \"./vio_rf_test.sh -help\" for more information)\n" + exit 1 + fi + + if [[ ($2 == "-help" || $2 == "-h") ]]; then + usage + fi +} + +# Script usage +usage() +{ + msg="Usage: vio_rf_test.sh [-help]\n\ +Usage: vio_rf_test.sh [-lib_map_path]\n\ +Usage: vio_rf_test.sh [-reset_run]\n\ +Usage: vio_rf_test.sh [-noclean_files]\n\n\ +[-help] -- Print help information for this script\n\n\ +[-lib_map_path ] -- Compiled simulation library directory path. The simulation library is compiled\n\ +using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\ +[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\ +from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\ +-noclean_files switch.\n\n\ +[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n" + echo -e $msg + exit 1 +} + +# Launch script +run $1 $2 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/vlog.prj b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/vlog.prj new file mode 100644 index 00000000..4d5e02ee --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/sim_scripts/vio_rf_test/xsim/vlog.prj @@ -0,0 +1,6 @@ +verilog xil_defaultlib --include "../../../ip/vio_rf_test/hdl/verilog" --include "../../../ip/vio_rf_test/hdl" \ +"../../../ip/vio_rf_test/sim/vio_rf_test.v" \ + +verilog xil_defaultlib "glbl.v" + +nosort diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/lpf_125k.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/lpf_125k.xcix new file mode 100644 index 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b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/06d53c7bf3a5a806/vio_rf_test.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9b36c6a847ba74b9f326d84a2cb26e4eea4dfb57596bf95b719d1f6fa8c6e4f7 +size 216934 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/06d53c7bf3a5a806/vio_rf_test_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/06d53c7bf3a5a806/vio_rf_test_sim_netlist.v new file mode 100755 index 00000000..e2a1b42e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/06d53c7bf3a5a806/vio_rf_test_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8c42987bab0129dd421a68c4a393932191c5075c398855d59f91d3f62de13aff +size 477770 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/06d53c7bf3a5a806/vio_rf_test_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/06d53c7bf3a5a806/vio_rf_test_sim_netlist.vhdl new file mode 100755 index 00000000..27af24c2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/06d53c7bf3a5a806/vio_rf_test_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7755f1ba476129a7b35bbe4f528864ba555a161856980a2097e6f92bdeafd361 +size 843700 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/06d53c7bf3a5a806/vio_rf_test_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/06d53c7bf3a5a806/vio_rf_test_stub.v new file mode 100755 index 00000000..1c9a162e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/06d53c7bf3a5a806/vio_rf_test_stub.v @@ -0,0 +1,34 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu May 18 12:54:39 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_test_stub.v +// Design : vio_rf_test +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]" */; + input clk; + output [0:0]probe_out0; + output [7:0]probe_out1; + output [7:0]probe_out2; + output [31:0]probe_out3; + output [0:0]probe_out4; + output [11:0]probe_out5; + output [11:0]probe_out6; + output [31:0]probe_out7; + output [31:0]probe_out8; + output [63:0]probe_out9; + output [4:0]probe_out10; + output [0:0]probe_out11; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/06d53c7bf3a5a806/vio_rf_test_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/06d53c7bf3a5a806/vio_rf_test_stub.vhdl new file mode 100755 index 00000000..1bbfc0f8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/06d53c7bf3a5a806/vio_rf_test_stub.vhdl @@ -0,0 +1,42 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu May 18 12:54:39 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_test_stub.vhdl +-- Design : vio_rf_test +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 63 downto 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/0789e4a10aba5413.xci b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/0789e4a10aba5413.xci new file mode 100644 index 00000000..ef9d34d2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/0789e4a10aba5413.xci @@ -0,0 +1,109 @@ + + + xilinx.com + ipcache + 0789e4a10aba5413 + 0 + + + rom_freq_word + + + 100000000 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../coe/freq_word.coe + ALL + rom_freq_word + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_ROM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 0 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 11 + 11 + false + true + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 81 + 11 + 11 + No_ECC + false + false + false + Stand_Alone + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 0789e4a10aba5413 + 0137cb81 + 42 + IP_Unknown + 3 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word.dcp new file mode 100644 index 00000000..1df86faa --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fc1be69239719f0fd3eef9f40b77e07263f777ee9a1bdd6d3239c1b5c908e590 +size 25932 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_sim_netlist.v new file mode 100755 index 00000000..1138426b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:c8863a7436d3a7e705252dc609290565df5ba97112e23a395887a831161aaee6 +size 28875 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_sim_netlist.vhdl new file mode 100755 index 00000000..b32d2444 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b8c205d7844ce045523bd9915ebb342f79637c8d36a5047015902b4ccf7d8b65 +size 44740 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_stub.v new file mode 100755 index 00000000..cd2f58a5 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 18:56:10 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.v +// Design : rom_freq_word +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[10:0]" */; + input clka; + input [6:0]addra; + output [10:0]douta; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_stub.vhdl new file mode 100755 index 00000000..c060bdb7 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/rom_freq_word_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 18:56:10 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.vhdl +-- Design : rom_freq_word +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clka : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[10:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/stats.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/stats.txt new file mode 100644 index 00000000..fed64f8b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/0789e4a10aba5413/stats.txt @@ -0,0 +1,2 @@ +NumberHits:2 +Timestamp: Thu May 18 03:49:44 UTC 2023 diff --git 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a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/2d405617321a842f/ila_rf_test_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/2d405617321a842f/ila_rf_test_sim_netlist.v new file mode 100755 index 00000000..5a0723ba --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/2d405617321a842f/ila_rf_test_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8296f32e3334e8318546da8b975db809629bf49c025304ced2bf5dfb969261d8 +size 1832040 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/2d405617321a842f/ila_rf_test_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/2d405617321a842f/ila_rf_test_sim_netlist.vhdl new file mode 100755 index 00000000..6ad0bb60 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/2d405617321a842f/ila_rf_test_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:04d6ddc70d296b2e9cefe33cb1845e29880b8bee4973a25a850c2ebac5755fc8 +size 3736917 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/2d405617321a842f/ila_rf_test_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/2d405617321a842f/ila_rf_test_stub.v new file mode 100755 index 00000000..20878f2a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/2d405617321a842f/ila_rf_test_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu May 18 12:55:27 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_test_stub.v +// Design : ila_rf_test +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]" */; + input clk; + input [11:0]probe0; + input [0:0]probe1; + input [0:0]probe2; + input [0:0]probe3; + input [0:0]probe4; + input [0:0]probe5; + input [0:0]probe6; + input [0:0]probe7; + input [0:0]probe8; + input [11:0]probe9; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/2d405617321a842f/ila_rf_test_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/2d405617321a842f/ila_rf_test_stub.vhdl new file mode 100755 index 00000000..d808c4d9 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/2d405617321a842f/ila_rf_test_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu May 18 12:55:27 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_test_stub.vhdl +-- Design : ila_rf_test +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe3 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe4 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe5 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe6 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe7 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe8 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe9 : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/5a3cca384525487e.xci b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/5a3cca384525487e.xci new file mode 100644 index 00000000..1eb7bdc1 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/5a3cca384525487e.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + 5a3cca384525487e + 0 + + + vio_rf_control + + + 100000000 + 0 + 1 + 1 + 16 + 11 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 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1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + 0x0 + 1 + vio_rf_control + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 5a3cca384525487e + 9a10a187 + 14 + IP_Unknown + 20 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control.dcp new file mode 100644 index 00000000..c3236c20 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:b80dbf5c28b957d3bb992f06be47ec1eebe765418737ca95e0066cfc9219036a +size 186738 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control_sim_netlist.v new file mode 100755 index 00000000..f4158506 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:949e0bb776f862e5d731005906cb314c42f0245d24352febb8d21493ee18e5cd +size 419444 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control_sim_netlist.vhdl new file mode 100755 index 00000000..756b4dd7 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3ecd5205201d65226c5646ab384cc1dfac15ad751e3be9906ea76cd5c9d32e69 +size 765071 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control_stub.v new file mode 100755 index 00000000..e41a6cf0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control_stub.v @@ -0,0 +1,39 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu May 11 18:52:11 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.v +// Design : vio_rf_control +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */; + input clk; + input [10:0]probe_in0; + output [0:0]probe_out0; + output [1:0]probe_out1; + output [0:0]probe_out2; + output [5:0]probe_out3; + output [5:0]probe_out4; + output [10:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; + output [0:0]probe_out9; + output [0:0]probe_out10; + output [0:0]probe_out11; + output [0:0]probe_out12; + output [31:0]probe_out13; + output [0:0]probe_out14; + output [31:0]probe_out15; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control_stub.vhdl new file mode 100755 index 00000000..6bb8a86e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/5a3cca384525487e/vio_rf_control_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu May 11 18:52:11 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.vhdl +-- Design : vio_rf_control +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 10 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/6c6203d172e581d2.xci b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/6c6203d172e581d2.xci new file mode 100644 index 00000000..24581bff --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/6c6203d172e581d2.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + 6c6203d172e581d2 + 0 + + + vio_rf_control + + + 100000000 + 0 + 1 + 1 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b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control.dcp new file mode 100644 index 00000000..6412a3c4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:3b4410080039a3dcfb464d8b84ebf3c2fce7cfc4c930081fec93fd2dfc92e22e +size 158846 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_sim_netlist.v new file mode 100755 index 00000000..f5411698 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:1a377e907e4c1862468589fc034a5d64ec916ca30b0834d8f9576f01db965871 +size 376176 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_sim_netlist.vhdl new file mode 100755 index 00000000..58e506d6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:16567dd0947209a5e3572fa3482fcf3fede36d7283acddef2745b3e6797e2ca6 +size 705727 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_stub.v new file mode 100755 index 00000000..19c5de2c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_stub.v @@ -0,0 +1,37 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Sun May 7 19:30:42 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.v +// Design : vio_rf_control +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11, probe_out12, probe_out13) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[15:0]" */; + input clk; + input [10:0]probe_in0; + output [0:0]probe_out0; + output [1:0]probe_out1; + output [0:0]probe_out2; + output [5:0]probe_out3; + output [5:0]probe_out4; + output [10:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; + output [0:0]probe_out9; + output [0:0]probe_out10; + output [0:0]probe_out11; + output [0:0]probe_out12; + output [15:0]probe_out13; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_stub.vhdl new file mode 100755 index 00000000..313783ad --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6c6203d172e581d2/vio_rf_control_stub.vhdl @@ -0,0 +1,45 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Sun May 7 19:30:42 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.vhdl +-- Design : vio_rf_control +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 10 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[10:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[15:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/af26366c91bcf19e.xci b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/af26366c91bcf19e.xci new file mode 100644 index 00000000..b3b99e1e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/af26366c91bcf19e.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + af26366c91bcf19e + 0 + + + vio_manual_ctrl + + + 100000000 + 0 + 1 + 0 + 5 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 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b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl.dcp new file mode 100644 index 00000000..56de7bb8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:be465582ee86c6c71050c881d6849a69826700b65bec767372e49531f61d9433 +size 145067 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_sim_netlist.v new file mode 100755 index 00000000..ccc2f537 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ba64402ef87fa7cf0612f20096dc39f48c6a0441f266fddb26a2b5538c3c242f +size 353387 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_sim_netlist.vhdl new file mode 100755 index 00000000..d158c084 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9e506290eb6188999540083616ec4fdf679a657aebbf2f58879a577f12d46ffe +size 669971 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_stub.v new file mode 100755 index 00000000..6a1391f8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 17:56:00 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.v +// Design : vio_manual_ctrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; + input clk; + output [2:0]probe_out0; + output [0:0]probe_out1; + output [31:0]probe_out2; + output [1:0]probe_out3; + output [3:0]probe_out4; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_stub.vhdl new file mode 100755 index 00000000..db37386f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/af26366c91bcf19e/vio_manual_ctrl_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 17:56:00 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.vhdl +-- Design : vio_manual_ctrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/caeedda65f3825d9.xci b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/caeedda65f3825d9.xci new file mode 100644 index 00000000..d783257a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/caeedda65f3825d9.xci @@ -0,0 +1,810 @@ + + + xilinx.com + ipcache + caeedda65f3825d9 + 0 + + + vio_rf_control + + + 100000000 + 0 + 1 + 1 + 16 + 11 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 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2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control.dcp new file mode 100644 index 00000000..8634b85d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:64d9e7431511faa169f0f5431ae17dc4be7e0077bdb2b08442be0eba277cccd3 +size 187044 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control_sim_netlist.v new file mode 100755 index 00000000..d95172e6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:972abd1e71d957f7fff391ae6d557d21b8aeca0838405e43eae3839298411ef4 +size 419703 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control_sim_netlist.vhdl new file mode 100755 index 00000000..194b8d44 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:46fda0e192d674295a268f4678b6dbb56e6d4342b57daf2a33ea89f8d3541f8d +size 765736 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control_stub.v new file mode 100755 index 00000000..77c77a78 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control_stub.v @@ -0,0 +1,39 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu May 18 11:36:40 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.v +// Design : vio_rf_control +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */; + input clk; + input [10:0]probe_in0; + output [0:0]probe_out0; + output [1:0]probe_out1; + output [0:0]probe_out2; + output [5:0]probe_out3; + output [5:0]probe_out4; + output [11:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; + output [0:0]probe_out9; + output [0:0]probe_out10; + output [0:0]probe_out11; + output [0:0]probe_out12; + output [31:0]probe_out13; + output [0:0]probe_out14; + output [31:0]probe_out15; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control_stub.vhdl new file mode 100755 index 00000000..bcaf2cd0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/caeedda65f3825d9/vio_rf_control_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu May 18 11:36:40 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.vhdl +-- Design : vio_rf_control +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/e64b5bd88b1a9e5c.xci b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/e64b5bd88b1a9e5c.xci new file mode 100644 index 00000000..c7f2b8b8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/e64b5bd88b1a9e5c.xci @@ -0,0 +1,109 @@ + + + xilinx.com + ipcache + e64b5bd88b1a9e5c + 0 + + + rom_freq_word + + + 100000000 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + ../coe/freq_word.coe + ALL + rom_freq_word + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + true + no_mem_loaded + Single_Port_ROM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 0 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 11 + 11 + false + true + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 81 + 11 + 11 + No_ECC + false + false + false + Stand_Alone + zynq + xc7z100 + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + e64b5bd88b1a9e5c + 0137cb81 + 42 + IP_Unknown + 3 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word.dcp new file mode 100644 index 00000000..efe6b55c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:f96d74795d18bcf73097952088143f65568b2cc188dfac35ffe84f776371de1c +size 25874 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_sim_netlist.v new file mode 100755 index 00000000..bbb064fb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:16051672c9348609da16879fccb89024402fddae4bd46743b3a36561dd648603 +size 28875 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_sim_netlist.vhdl new file mode 100755 index 00000000..8a9f76c8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7de45451f808c9c0ca85bb25409f21c3a387a7abe5b133ff12a54232b17241ac +size 44740 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_stub.v new file mode 100755 index 00000000..8f66d363 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_stub.v @@ -0,0 +1,22 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Sun May 7 19:30:29 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.v +// Design : rom_freq_word +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "blk_mem_gen_v8_4_3,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clka, addra, douta) +/* synthesis syn_black_box black_box_pad_pin="clka,addra[6:0],douta[10:0]" */; + input clka; + input [6:0]addra; + output [10:0]douta; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_stub.vhdl new file mode 100755 index 00000000..1219c641 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/e64b5bd88b1a9e5c/rom_freq_word_stub.vhdl @@ -0,0 +1,32 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Sun May 7 19:30:29 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rom_freq_word_stub.vhdl +-- Design : rom_freq_word +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + clka : in STD_LOGIC; + addra : in STD_LOGIC_VECTOR ( 6 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 10 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clka,addra[6:0],douta[10:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_3,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf new file mode 100644 index 00000000..c0228156 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -0,0 +1,37 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:34:00:00 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+ + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.hw/managed_ip_project.lpr b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.hw/managed_ip_project.lpr new file mode 100644 index 00000000..29d8123e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.hw/managed_ip_project.lpr @@ -0,0 +1,6 @@ + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_1.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_1.xml new file mode 100644 index 00000000..62b77e3c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_2.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_2.xml new file mode 100644 index 00000000..6abe9d9f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_3.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_3.xml new file mode 100644 index 00000000..e9efe6b0 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_3.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_4.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_4.xml new file mode 100644 index 00000000..62b77e3c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_5.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_5.xml new file mode 100644 index 00000000..6abe9d9f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_6.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_6.xml new file mode 100644 index 00000000..8267f974 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_7.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_7.xml new file mode 100644 index 00000000..a0ac8b6a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.vivado.begin.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..276b0a90 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.vivado.end.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ISEWrap.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ISEWrap.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/__synthesis_is_complete__ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/dont_touch.xdc b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/dont_touch.xdc new file mode 100644 index 00000000..b0ee3d71 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/dont_touch.xdc @@ -0,0 +1,32 @@ +# This file is automatically generated. +# It contains project source information necessary for synthesis and implementation. + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci +# IP: The module: 'ila_rf_test' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila_impl.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rf_test'. Do not add the DONT_TOUCH constraint. +set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rf_test'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rf_test'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# IP: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci +# IP: The module: 'ila_rf_test' is the root of the design. Do not add the DONT_TOUCH constraint. + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila_impl.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rf_test'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rf_test'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet + +# XDC: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test_ooc.xdc +# XDC: The top module name and the constraint reference have the same name: 'ila_rf_test'. Do not add the DONT_TOUCH constraint. +#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/gen_run.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/gen_run.xml new file mode 100644 index 00000000..edd4ab0b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/gen_run.xml @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/htr.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/htr.txt new file mode 100644 index 00000000..e6ad1c38 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log ila_rf_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rf_test.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.dcp new file mode 100644 index 00000000..4fb538ac --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:48cb571da4d59aee5fa06a02e4b28dec6359bb3021537818e7565b5a09633ff6 +size 752324 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.tcl new file mode 100644 index 00000000..5864a4fd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.tcl @@ -0,0 +1,159 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci +set_property used_in_synthesis false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila_impl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila_impl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1 -new_name ila_rf_test -ip [get_ips ila_rf_test]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top ila_rf_test -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix ila_rf_test_ ila_rf_test.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_test_stub.v + lappend ipCachedFiles ila_rf_test_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_test_stub.vhdl + lappend ipCachedFiles ila_rf_test_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_test_sim_netlist.v + lappend ipCachedFiles ila_rf_test_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_rf_test_sim_netlist.vhdl + lappend ipCachedFiles ila_rf_test_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp ila_rf_test.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips ila_rf_test] +} + +rename_ref -prefix_all ila_rf_test_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef ila_rf_test.dcp +create_report "ila_rf_test_synth_1_synth_report_utilization_0" "report_utilization -file ila_rf_test_utilization_synth.rpt -pb ila_rf_test_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/ila_rf_test + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.vds b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.vds new file mode 100644 index 00000000..6d2a9a3c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.vds @@ -0,0 +1,1430 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Thu May 18 12:54:22 2023 +# Process ID: 520461 +# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1 +# Command line: vivado -log ila_rf_test.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rf_test.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/vivado.jou +#----------------------------------------------------------- +source ila_rf_test.tcl -notrace +Command: synth_design -top ila_rf_test -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 520729 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1882.547 ; gain = 161.719 ; free physical = 558 ; free virtual = 47853 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'ila_rf_test' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/synth/ila_rf_test.v:84] +INFO: [Synth 8-6157] synthesizing module 'CFGLUT5' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] +INFO: [Synth 8-6155] done synthesizing module 'CFGLUT5' (8#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1516] +INFO: [Synth 8-6157] synthesizing module 'CARRY4' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1479] +INFO: [Synth 8-6155] done synthesizing module 'CARRY4' (9#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:1479] +INFO: [Synth 8-6157] synthesizing module 'SRLC32E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77850] +INFO: [Synth 8-6155] done synthesizing module 'SRLC32E' (19#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77850] +INFO: [Synth 8-6157] synthesizing module 'SRL16E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700] +INFO: [Synth 8-6155] done synthesizing module 'SRL16E' (21#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77700] +INFO: [Synth 8-6157] synthesizing module 'SRLC16E' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] +INFO: [Synth 8-6155] done synthesizing module 'SRLC16E' (23#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:77789] +INFO: [Synth 8-6157] synthesizing module 'FDRE' [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] +INFO: [Synth 8-6155] done synthesizing module 'FDRE' (28#1) [/tools/Xilinx/Vivado/2019.1/scripts/rt/data/unisim_comp.v:13664] +WARNING: [Synth 8-7023] instance 'inst' of module 'ila_v6_2_9_ila' has 1033 connections declared, but only 1027 given [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/synth/ila_rf_test.v:3227] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity ila_rf_test does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/synth/ila_rf_test.v:116] +INFO: [Synth 8-6155] done synthesizing module 'ila_rf_test' (46#1) [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/synth/ila_rf_test.v:84] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port SSRA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port REGCEA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port SSRB +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port WEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port DINB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port SLEEP +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 has unconnected port ECCPIPECE +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port SSRA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port REGCEA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port SSRB +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port WEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port DINB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port SLEEP +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 has unconnected port ECCPIPECE +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port SSRA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port REGCEA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port SSRB +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port WEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port DINB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port SLEEP +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 has unconnected port ECCPIPECE +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port SSRA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port REGCEA +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port SSRB +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port WEB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[8] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[7] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[6] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[5] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[4] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port DINB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port SLEEP +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper has unconnected port ECCPIPECE +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port RSTA[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port WEA[3] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port WEA[2] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port WEA[1] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port RSTB[0] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port WEB[3] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port WEB[2] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port WEB[1] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port INJECTSBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr has unconnected port INJECTDBITERR +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port CLKB +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[32] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[31] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[30] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[29] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[28] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[27] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[26] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[25] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[24] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[23] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[22] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[21] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[20] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[19] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[18] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[17] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[16] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[15] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[14] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[13] +WARNING: [Synth 8-3331] design blk_mem_gen_v8_4_3_blk_mem_output_block has unconnected port DOUTA_I[12] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 2233.242 ; gain = 512.414 ; free physical = 1624 ; free virtual = 48717 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 2233.242 ; gain = 512.414 ; free physical = 1639 ; free virtual = 48731 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:35 ; elapsed = 00:00:45 . Memory (MB): peak = 2233.242 ; gain = 512.414 ; free physical = 1639 ; free virtual = 48731 +--------------------------------------------------------------------------------- +INFO: [Netlist 29-17] Analyzing 132 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test_ooc.xdc] for cell 'inst' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_rf_test_ooc.xdc] for cell 'inst' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila.xdc] for cell 'inst' +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ila_rf_test/ila_v6_2/constraints/ila.xdc] for cell 'inst' +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/dont_touch.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/dont_touch.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2329.086 ; gain = 0.000 ; free physical = 1573 ; free virtual = 48668 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 94 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 80 instances + CFGLUT5 => SRLC32E: 14 instances + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2329.086 ; gain = 0.000 ; free physical = 1572 ; free virtual = 48667 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:38 ; elapsed = 00:00:49 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1676 ; free virtual = 48772 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:38 ; elapsed = 00:00:49 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1676 ; free virtual = 48772 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +Applied set_property DONT_TOUCH = true for inst. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/dont_touch.xdc, line 9). +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:38 ; elapsed = 00:00:49 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1676 ; free virtual = 48772 +--------------------------------------------------------------------------------- +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized10' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized2' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized3' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized4' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized5' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized6' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized7' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized8' +INFO: [Synth 8-802] inferred FSM for state register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized9' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized10' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized0' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized1' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized2' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized3' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized4' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized5' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized6' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized7' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized8' +--------------------------------------------------------------------------------------------------- + State | New Encoding | Previous Encoding +--------------------------------------------------------------------------------------------------- +* + IDLE | 0001 | 0001 + REG | 0010 | 0010 + P2S | 0100 | 0100 + S2P | 1000 | 1000 +--------------------------------------------------------------------------------------------------- +INFO: [Synth 8-3898] No Re-encoding of one hot register 'current_state_reg' in module 'xsdbs_v1_0_2_reg_p2s__parameterized9' +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:39 ; elapsed = 00:00:50 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1672 ; free virtual = 48769 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 12 Bit Adders := 1 + 2 Input 9 Bit Adders := 1 + 2 Input 7 Bit Adders := 2 + 2 Input 6 Bit Adders := 1 + 2 Input 4 Bit Adders := 12 + 2 Input 2 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 26 + 2 Input 1 Bit XORs := 4 ++---Registers : + 1024 Bit Registers := 2 + 128 Bit Registers := 1 + 48 Bit Registers := 1 + 33 Bit Registers := 2 + 32 Bit Registers := 9 + 17 Bit Registers := 2 + 16 Bit Registers := 109 + 12 Bit Registers := 11 + 10 Bit Registers := 1 + 9 Bit Registers := 1 + 7 Bit Registers := 3 + 6 Bit Registers := 2 + 4 Bit Registers := 14 + 2 Bit Registers := 6 + 1 Bit Registers := 159 ++---Muxes : + 2 Input 32 Bit Muxes := 1 + 2 Input 16 Bit Muxes := 21 + 4 Input 16 Bit Muxes := 1 + 3 Input 16 Bit Muxes := 2 + 8 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 12 + 3 Input 15 Bit Muxes := 1 + 8 Input 12 Bit Muxes := 1 + 3 Input 7 Bit Muxes := 1 + 8 Input 7 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 4 + 2 Input 5 Bit Muxes := 2 + 5 Input 4 Bit Muxes := 12 + 2 Input 4 Bit Muxes := 37 + 2 Input 3 Bit Muxes := 12 + 10 Input 3 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 5 + 8 Input 2 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 95 + 3 Input 1 Bit Muxes := 12 + 9 Input 1 Bit Muxes := 1 + 4 Input 1 Bit Muxes := 1 + 8 Input 1 Bit Muxes := 5 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 17 Bit Registers := 1 + 16 Bit Registers := 4 + 1 Bit Registers := 4 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_stat +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_ctl +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized29 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized30 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized44 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized45 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized46 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized47 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized48 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_ctl__parameterized1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +Module xsdbs_v1_0_2_reg__parameterized49 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized50 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized51 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized52 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized53 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized54 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg__parameterized55 +Detailed RTL Component Info : ++---XORs : + 2 Input 13 Bit XORs := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized10 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_stream +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module xsdbs_v1_0_2_reg_p2s +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized0 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized1 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized2 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized3 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized4 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized5 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized6 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized7 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized8 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module xsdbs_v1_0_2_reg_p2s__parameterized9 +Detailed RTL Component Info : ++---Adders : + 2 Input 4 Bit Adders := 1 ++---XORs : + 2 Input 13 Bit XORs := 1 ++---Registers : + 16 Bit Registers := 2 + 4 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 15 Bit Muxes := 1 + 5 Input 4 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 3 + 2 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 5 + 3 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_register +Detailed RTL Component Info : ++---Adders : + 2 Input 9 Bit Adders := 1 + 2 Input 7 Bit Adders := 2 + 2 Input 6 Bit Adders := 1 ++---Registers : + 1024 Bit Registers := 2 + 17 Bit Registers := 1 + 16 Bit Registers := 12 + 9 Bit Registers := 1 + 7 Bit Registers := 2 + 6 Bit Registers := 1 + 1 Bit Registers := 31 ++---Muxes : + 2 Input 16 Bit Muxes := 8 + 4 Input 16 Bit Muxes := 1 + 3 Input 16 Bit Muxes := 1 + 8 Input 16 Bit Muxes := 1 + 3 Input 15 Bit Muxes := 1 + 2 Input 6 Bit Muxes := 4 + 2 Input 5 Bit Muxes := 2 + 10 Input 3 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 13 + 9 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_all_typeA_slice__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized0 +Detailed RTL Component Info : ++---Registers : + 12 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA__parameterized1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 2 +Module ltlib_v1_0_0_match__parameterized1 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ltlib_v1_0_0_allx_typeA +Detailed RTL Component Info : ++---Registers : + 10 Bit Registers := 1 +Module ltlib_v1_0_0_match +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 +Module ila_v6_2_9_ila_trigger +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 3 +Module ltlib_v1_0_0_async_edge_xfer +Detailed RTL Component Info : ++---XORs : + 2 Input 1 Bit XORs := 1 ++---Registers : + 1 Bit Registers := 5 +Module ltlib_v1_0_0_rising_edge_detection +Detailed RTL Component Info : ++---Registers : + 2 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 2 Bit Muxes := 2 +Module ila_v6_2_9_ila_reset_ctrl +Detailed RTL Component Info : ++---Registers : + 6 Bit Registers := 1 + 1 Bit Registers := 2 +Module ltlib_v1_0_0_cfglut7 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 3 +Module ltlib_v1_0_0_cfglut6 +Detailed RTL Component Info : ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_allx_typeA_nodelay +Detailed RTL Component Info : ++---Registers : + 12 Bit Registers := 1 +Module ila_v6_2_9_ila_cap_addrgen +Detailed RTL Component Info : ++---Registers : + 33 Bit Registers := 2 + 16 Bit Registers := 1 + 12 Bit Registers := 3 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 12 +Module ltlib_v1_0_0_cfglut6__parameterized0 +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module ila_v6_2_9_ila_cap_ctrl_legacy +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 3 ++---Muxes : + 2 Input 1 Bit Muxes := 1 + 4 Input 1 Bit Muxes := 1 +Module ltlib_v1_0_0_generic_mux +Detailed RTL Component Info : ++---Muxes : + 3 Input 16 Bit Muxes := 1 +Module ltlib_v1_0_0_generic_memrd +Detailed RTL Component Info : ++---Adders : + 2 Input 12 Bit Adders := 1 + 2 Input 2 Bit Adders := 1 ++---Registers : + 48 Bit Registers := 1 + 12 Bit Registers := 1 + 7 Bit Registers := 1 + 4 Bit Registers := 2 + 2 Bit Registers := 1 + 1 Bit Registers := 3 ++---Muxes : + 8 Input 12 Bit Muxes := 1 + 3 Input 7 Bit Muxes := 1 + 8 Input 7 Bit Muxes := 1 + 2 Input 4 Bit Muxes := 1 + 2 Input 2 Bit Muxes := 1 + 8 Input 2 Bit Muxes := 1 + 8 Input 1 Bit Muxes := 5 +Module ila_v6_2_9_ila_core +Detailed RTL Component Info : ++---Registers : + 32 Bit Registers := 9 + 16 Bit Registers := 2 + 2 Bit Registers := 3 + 1 Bit Registers := 5 ++---Muxes : + 2 Input 32 Bit Muxes := 1 +Module ila_v6_2_9_ila +Detailed RTL Component Info : ++---Registers : + 1 Bit Registers := 6 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1008] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1008] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1009] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1009] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1010] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1010] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1011] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1011] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1012] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1012] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1013] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1013] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1014] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1014] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1015] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1015] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1016] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1016] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1017] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1017] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1018] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1018] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1019] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1019] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1020] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1020] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1021] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1021] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1022] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1022] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg1_reg[1023] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/shift_reg0_reg[1023] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_trig/shift_cap_strg_qual_reg ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_trig/CAP_QUAL_STRG_reg' (FD) to 'inst/ila_core_inst/u_trig/shift_cap_strg_qual_reg' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[0]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[5]' +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[0] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_892/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[7].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[5].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[3].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[2].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[0]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[1]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[1] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_892/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[7].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[5].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[3].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[2].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[1]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[2]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[2] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_892/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_887/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[7].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[5].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[3].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[2].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_11/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_10/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_e/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_d/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_c/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_b/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_4/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_2/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[2]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[3]' (FDRE) to 'inst/ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[4]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[3] ) +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_892/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[9].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[8].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[7].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[6].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[5].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[4].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[3].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE_MU1.MU_STATUS[2].mu_tpid_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/N_DDR_MODE.PROBE_STATUS[0].probe_width_reg/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_3/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_14/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_13/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/ila_core_inst/u_ila_regs/reg_12/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[3]' (FDE) to 'inst/ila_core_inst/u_ila_regs/reg_88f/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[4]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[4] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[10] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[11] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[12] ) +INFO: [Synth 8-3333] propagating constant 1 across sequential element (inst/\ila_core_inst/u_ila_regs/reg_1/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[12] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[13] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff8_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_ff7_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/reg_0/I_EN_STAT_EQ1.U_STAT/xsdb_reg_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[0] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[1] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[2] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[3] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[4] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[10] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[11] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[12] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[13] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_6_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_trig/shift_cap_strg_qual_reg ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[4] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[5] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[6] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[7] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[8] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[9] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[10] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[11] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[12] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[13] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[14] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\ila_core_inst/u_ila_regs/slaveRegDo_mux_1_reg[15] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:42 ; elapsed = 00:00:53 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1635 ; free virtual = 48744 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:46 ; elapsed = 00:00:57 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1517 ; free virtual = 48631 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:46 ; elapsed = 00:00:57 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1511 ; free virtual = 48624 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:46 ; elapsed = 00:00:57 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1508 ; free virtual = 48621 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +INFO: [Synth 8-3295] tying undriven pin dummy_inferred:in0 to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:trig_in to constant 0 +INFO: [Synth 8-3295] tying undriven pin inst:trig_out_ack to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:47 ; elapsed = 00:00:57 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1497 ; free virtual = 48611 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:47 ; elapsed = 00:00:57 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1497 ; free virtual = 48611 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1498 ; free virtual = 48612 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1498 ; free virtual = 48612 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1498 ; free virtual = 48612 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1498 ; free virtual = 48612 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++---------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++---------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|ila_v6_2_9_ila | ila_core_inst/u_ila_regs/adv_rb_drdy4_reg | 5 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/shifted_data_in_reg[8][31] | 9 | 32 | NO | NO | YES | 32 | 0 | +|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_read_latency.read_enable_out_reg[3] | 3 | 1 | NO | NO | YES | 1 | 0 | +|ila_v6_2_9_ila | ila_core_inst/xsdb_memory_read_inst/multiple_enable_latency.enable_out_reg[3] | 3 | 1 | NO | NO | YES | 1 | 0 | ++---------------+----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP and Shift Register Reporting +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+---------+------+ +| |Cell |Count | ++------+---------+------+ +|1 |CARRY4 | 43| +|2 |CFGLUT5 | 94| +|3 |LUT1 | 39| +|4 |LUT2 | 49| +|5 |LUT3 | 117| +|6 |LUT4 | 172| +|7 |LUT5 | 42| +|8 |LUT6 | 544| +|9 |MUXF7 | 4| +|10 |RAMB36E1 | 4| +|11 |SRL16E | 36| +|12 |SRLC16E | 2| +|13 |SRLC32E | 17| +|14 |FDRE | 1620| +|15 |FDSE | 9| ++------+---------+------+ + +Report Instance Areas: ++------+------------------------------------------------------------------------+------------------------------------------------------------+------+ +| |Instance |Module |Cells | ++------+------------------------------------------------------------------------+------------------------------------------------------------+------+ +|1 |top | | 2792| +|2 | inst |ila_v6_2_9_ila | 2792| +|3 | ila_core_inst |ila_v6_2_9_ila_core | 2785| +|4 | ila_trace_memory_inst |ila_v6_2_9_ila_trace_memory | 4| +|5 | \SUBCORE_RAM_BLK_MEM_1.trace_block_memory |blk_mem_gen_v8_4_3 | 4| +|6 | inst_blk_mem_gen |blk_mem_gen_v8_4_3_synth | 4| +|7 | \gnbram.gnativebmg.native_blk_mem_gen |blk_mem_gen_v8_4_3_blk_mem_gen_top | 4| +|8 | \valid.cstr |blk_mem_gen_v8_4_3_blk_mem_gen_generic_cstr | 4| +|9 | \ramloop[0].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width | 1| +|10 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper | 1| +|11 | \ramloop[1].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized0 | 1| +|12 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized0 | 1| +|13 | \ramloop[2].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized1 | 1| +|14 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized1 | 1| +|15 | \ramloop[3].ram.r |blk_mem_gen_v8_4_3_blk_mem_gen_prim_width__parameterized2 | 1| +|16 | \prim_noinit.ram |blk_mem_gen_v8_4_3_blk_mem_gen_prim_wrapper__parameterized2 | 1| +|17 | u_ila_cap_ctrl |ila_v6_2_9_ila_cap_ctrl_legacy | 279| +|18 | U_CDONE |ltlib_v1_0_0_cfglut6__parameterized0 | 5| +|19 | U_NS0 |ltlib_v1_0_0_cfglut7 | 6| +|20 | U_NS1 |ltlib_v1_0_0_cfglut7_58 | 6| +|21 | u_cap_addrgen |ila_v6_2_9_ila_cap_addrgen | 257| +|22 | U_CMPRESET |ltlib_v1_0_0_cfglut6 | 3| +|23 | u_cap_sample_counter |ila_v6_2_9_ila_cap_sample_counter | 48| +|24 | U_SCE |ltlib_v1_0_0_cfglut4_65 | 1| +|25 | U_SCMPCE |ltlib_v1_0_0_cfglut5_66 | 1| +|26 | U_SCRST |ltlib_v1_0_0_cfglut6_67 | 5| +|27 | u_scnt_cmp |ltlib_v1_0_0_match_nodelay_68 | 24| +|28 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_69 | 24| +|29 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_70 | 12| +|30 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_71 | 5| +|31 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_72 | 5| +|32 | u_cap_window_counter |ila_v6_2_9_ila_cap_window_counter | 57| +|33 | U_WCE |ltlib_v1_0_0_cfglut4 | 1| +|34 | U_WHCMPCE |ltlib_v1_0_0_cfglut5 | 1| +|35 | U_WLCMPCE |ltlib_v1_0_0_cfglut5_59 | 1| +|36 | u_wcnt_hcmp |ltlib_v1_0_0_match_nodelay | 12| +|37 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay_61 | 12| +|38 | DUT |ltlib_v1_0_0_all_typeA__parameterized1_62 | 12| +|39 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1_63 | 5| +|40 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2_64 | 5| +|41 | u_wcnt_lcmp |ltlib_v1_0_0_match_nodelay_60 | 24| +|42 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA_nodelay | 24| +|43 | DUT |ltlib_v1_0_0_all_typeA__parameterized1 | 12| +|44 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized1 | 5| +|45 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized2 | 5| +|46 | u_ila_regs |ila_v6_2_9_ila_register | 2019| +|47 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 302| +|48 | reg_890 |xsdbs_v1_0_2_reg__parameterized62 | 16| +|49 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_57 | 16| +|50 | \MU_SRL[0].mu_srl_reg |xsdbs_v1_0_2_reg_p2s | 73| +|51 | \MU_SRL[1].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized0 | 89| +|52 | \MU_SRL[2].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized1 | 73| +|53 | \MU_SRL[3].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized2 | 73| +|54 | \MU_SRL[4].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized3 | 73| +|55 | \MU_SRL[5].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized4 | 105| +|56 | \MU_SRL[6].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized5 | 73| +|57 | \MU_SRL[7].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized6 | 73| +|58 | \MU_SRL[8].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized7 | 75| +|59 | \MU_SRL[9].mu_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized8 | 73| +|60 | \TC_SRL[0].tc_srl_reg |xsdbs_v1_0_2_reg_p2s__parameterized9 | 76| +|61 | reg_15 |xsdbs_v1_0_2_reg__parameterized44 | 20| +|62 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_56 | 20| +|63 | reg_16 |xsdbs_v1_0_2_reg__parameterized45 | 20| +|64 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_55 | 20| +|65 | reg_17 |xsdbs_v1_0_2_reg__parameterized46 | 30| +|66 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_54 | 30| +|67 | reg_18 |xsdbs_v1_0_2_reg__parameterized47 | 19| +|68 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_53 | 19| +|69 | reg_19 |xsdbs_v1_0_2_reg__parameterized48 | 31| +|70 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_52 | 31| +|71 | reg_1a |xsdbs_v1_0_2_reg__parameterized49 | 17| +|72 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1_51 | 17| +|73 | reg_6 |xsdbs_v1_0_2_reg__parameterized29 | 31| +|74 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_50 | 31| +|75 | reg_7 |xsdbs_v1_0_2_reg__parameterized30 | 30| +|76 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized0 | 30| +|77 | reg_8 |xsdbs_v1_0_2_reg__parameterized31 | 5| +|78 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_49 | 5| +|79 | reg_80 |xsdbs_v1_0_2_reg__parameterized50 | 20| +|80 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1_48 | 20| +|81 | reg_81 |xsdbs_v1_0_2_reg__parameterized51 | 61| +|82 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_47 | 61| +|83 | reg_82 |xsdbs_v1_0_2_reg__parameterized52 | 17| +|84 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl__parameterized1 | 17| +|85 | reg_83 |xsdbs_v1_0_2_reg__parameterized53 | 17| +|86 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_46 | 17| +|87 | reg_84 |xsdbs_v1_0_2_reg__parameterized54 | 17| +|88 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_45 | 17| +|89 | reg_85 |xsdbs_v1_0_2_reg__parameterized55 | 17| +|90 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl_44 | 17| +|91 | reg_887 |xsdbs_v1_0_2_reg__parameterized57 | 3| +|92 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_43 | 3| +|93 | reg_88d |xsdbs_v1_0_2_reg__parameterized59 | 6| +|94 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_42 | 6| +|95 | reg_9 |xsdbs_v1_0_2_reg__parameterized32 | 25| +|96 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat_41 | 25| +|97 | reg_srl_fff |xsdbs_v1_0_2_reg_p2s__parameterized10 | 95| +|98 | reg_stream_ffd |xsdbs_v1_0_2_reg_stream | 28| +|99 | \I_EN_CTL_EQ1.U_CTL |xsdbs_v1_0_2_reg_ctl | 28| +|100 | reg_stream_ffe |xsdbs_v1_0_2_reg_stream__parameterized0 | 24| +|101 | \I_EN_STAT_EQ1.U_STAT |xsdbs_v1_0_2_reg_stat | 24| +|102 | u_ila_reset_ctrl |ila_v6_2_9_ila_reset_ctrl | 46| +|103 | arm_detection_inst |ltlib_v1_0_0_rising_edge_detection | 5| +|104 | \asyncrounous_transfer.arm_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer | 7| +|105 | \asyncrounous_transfer.arm_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_37 | 6| +|106 | \asyncrounous_transfer.halt_in_transfer_inst |ltlib_v1_0_0_async_edge_xfer_38 | 7| +|107 | \asyncrounous_transfer.halt_out_transfer_inst |ltlib_v1_0_0_async_edge_xfer_39 | 6| +|108 | halt_detection_inst |ltlib_v1_0_0_rising_edge_detection_40 | 5| +|109 | u_trig |ila_v6_2_9_ila_trigger | 190| +|110 | \N_DDR_TC.N_DDR_TC_INST[0].U_TC |ltlib_v1_0_0_match | 25| +|111 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA | 23| +|112 | DUT |ltlib_v1_0_0_all_typeA_34 | 13| +|113 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_35 | 5| +|114 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_36 | 6| +|115 | U_TM |ila_v6_2_9_ila_trig_match | 164| +|116 | \N_DDR_MODE.G_NMU[0].U_M |ltlib_v1_0_0_match__parameterized0 | 38| +|117 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0_30 | 37| +|118 | DUT |ltlib_v1_0_0_all_typeA_31 | 13| +|119 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice_32 | 5| +|120 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_33 | 6| +|121 | \N_DDR_MODE.G_NMU[1].U_M |ltlib_v1_0_0_match__parameterized1 | 11| +|122 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_27 | 10| +|123 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_28 | 8| +|124 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_29 | 6| +|125 | \N_DDR_MODE.G_NMU[2].U_M |ltlib_v1_0_0_match__parameterized1_0 | 11| +|126 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_24 | 10| +|127 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_25 | 8| +|128 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_26 | 6| +|129 | \N_DDR_MODE.G_NMU[3].U_M |ltlib_v1_0_0_match__parameterized1_1 | 11| +|130 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_21 | 10| +|131 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_22 | 8| +|132 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_23 | 6| +|133 | \N_DDR_MODE.G_NMU[4].U_M |ltlib_v1_0_0_match__parameterized1_2 | 11| +|134 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_18 | 10| +|135 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_19 | 8| +|136 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_20 | 6| +|137 | \N_DDR_MODE.G_NMU[5].U_M |ltlib_v1_0_0_match__parameterized1_3 | 11| +|138 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_15 | 10| +|139 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_16 | 8| +|140 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_17 | 6| +|141 | \N_DDR_MODE.G_NMU[6].U_M |ltlib_v1_0_0_match__parameterized1_4 | 11| +|142 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_12 | 10| +|143 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_13 | 8| +|144 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_14 | 6| +|145 | \N_DDR_MODE.G_NMU[7].U_M |ltlib_v1_0_0_match__parameterized1_5 | 11| +|146 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1_9 | 10| +|147 | DUT |ltlib_v1_0_0_all_typeA__parameterized0_10 | 8| +|148 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_11 | 6| +|149 | \N_DDR_MODE.G_NMU[8].U_M |ltlib_v1_0_0_match__parameterized1_6 | 11| +|150 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized1 | 10| +|151 | DUT |ltlib_v1_0_0_all_typeA__parameterized0 | 8| +|152 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0_8 | 6| +|153 | \N_DDR_MODE.G_NMU[9].U_M |ltlib_v1_0_0_match__parameterized0_7 | 38| +|154 | \allx_typeA_match_detection.ltlib_v1_0_0_allx_typeA_inst |ltlib_v1_0_0_allx_typeA__parameterized0 | 37| +|155 | DUT |ltlib_v1_0_0_all_typeA | 13| +|156 | \I_WHOLE_SLICE.G_SLICE_IDX[0].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice | 5| +|157 | \I_WHOLE_SLICE.G_SLICE_IDX[1].U_ALL_SRL_SLICE |ltlib_v1_0_0_all_typeA_slice__parameterized0 | 6| +|158 | xsdb_memory_read_inst |ltlib_v1_0_0_generic_memrd | 124| ++------+------------------------------------------------------------------------+------------------------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1498 ; free virtual = 48612 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 1163 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:45 ; elapsed = 00:00:56 . Memory (MB): peak = 2329.086 ; gain = 512.414 ; free physical = 1553 ; free virtual = 48667 +Synthesis Optimization Complete : Time (s): cpu = 00:00:47 ; elapsed = 00:00:58 . Memory (MB): peak = 2329.086 ; gain = 608.258 ; free physical = 1566 ; free virtual = 48680 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 145 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2329.086 ; gain = 0.000 ; free physical = 1503 ; free virtual = 48619 +INFO: [Project 1-111] Unisim Transformation Summary: + A total of 94 instances were transformed. + CFGLUT5 => CFGLUT5 (SRLC32E, SRL16E): 80 instances + CFGLUT5 => SRLC32E: 14 instances + +INFO: [Common 17-83] Releasing license: Synthesis +274 Infos, 102 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:50 ; elapsed = 00:01:01 . Memory (MB): peak = 2329.086 ; gain = 918.160 ; free physical = 1601 ; free virtual = 48716 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2329.086 ; gain = 0.000 ; free physical = 1601 ; free virtual = 48716 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP ila_rf_test, cache-ID = 2d405617321a842f +INFO: [Coretcl 2-1174] Renamed 157 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2353.098 ; gain = 0.000 ; free physical = 1585 ; free virtual = 48709 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file ila_rf_test_utilization_synth.rpt -pb ila_rf_test_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Thu May 18 12:55:29 2023... diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.v new file mode 100644 index 00000000..cbf75d90 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:19d8ad4109babf969bdfe516c397a62b469ce49220b24c8d85e150a3319d7151 +size 1824426 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.vhdl new file mode 100644 index 00000000..680381a6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:449f65ac341f50fe588c835e11213443114b29b0fa40133ee2f5f46c10dbcd55 +size 3440051 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v new file mode 100644 index 00000000..be350621 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v @@ -0,0 +1,31 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu May 18 12:55:28 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.v +// Design : ila_rf_test +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "ila,Vivado 2019.1.3" *) +module ila_rf_test(clk, probe0, probe1, probe2, probe3, probe4, probe5, + probe6, probe7, probe8, probe9) +/* synthesis syn_black_box black_box_pad_pin="clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]" */; + input clk; + input [11:0]probe0; + input [0:0]probe1; + input [0:0]probe2; + input [0:0]probe3; + input [0:0]probe4; + input [0:0]probe5; + input [0:0]probe6; + input [0:0]probe7; + input [0:0]probe8; + input [11:0]probe9; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl new file mode 100644 index 00000000..ae79d844 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl @@ -0,0 +1,40 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu May 18 12:55:28 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_stub.vhdl +-- Design : ila_rf_test +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity ila_rf_test is + Port ( + clk : in STD_LOGIC; + probe0 : in STD_LOGIC_VECTOR ( 11 downto 0 ); + probe1 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe2 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe3 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe4 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe5 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe6 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe7 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe8 : in STD_LOGIC_VECTOR ( 0 to 0 ); + probe9 : in STD_LOGIC_VECTOR ( 11 downto 0 ) + ); + +end ila_rf_test; + +architecture stub of ila_rf_test is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe0[11:0],probe1[0:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[11:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_utilization_synth.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_utilization_synth.pb new file mode 100644 index 00000000..77c679d5 Binary files /dev/null and b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_utilization_synth.pb differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_utilization_synth.rpt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_utilization_synth.rpt new file mode 100644 index 00000000..8270de28 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/ila_rf_test_utilization_synth.rpt @@ -0,0 +1,190 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Thu May 18 12:55:28 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file ila_rf_test_utilization_synth.rpt -pb ila_rf_test_utilization_synth.pb +| Design : ila_rf_test +| Device : 7z100ffg900-2 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 1013 | 0 | 277400 | 0.37 | +| LUT as Logic | 864 | 0 | 277400 | 0.31 | +| LUT as Memory | 149 | 0 | 108200 | 0.14 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 149 | 0 | | | +| Slice Registers | 1629 | 0 | 554800 | 0.29 | +| Register as Flip Flop | 1629 | 0 | 554800 | 0.29 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 4 | 0 | 138700 | <0.01 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | ++----------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 9 | Yes | Set | - | +| 1620 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++-------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------+------+-------+-----------+-------+ +| Block RAM Tile | 4 | 0 | 755 | 0.53 | +| RAMB36/FIFO* | 4 | 0 | 755 | 0.53 | +| RAMB36E1 only | 4 | | | | +| RAMB18 | 0 | 0 | 1510 | 0.00 | ++-------------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 1620 | Flop & Latch | +| LUT6 | 544 | LUT | +| LUT4 | 172 | LUT | +| LUT3 | 117 | LUT | +| SRL16E | 116 | Distributed Memory | +| SRLC32E | 111 | Distributed Memory | +| LUT2 | 49 | LUT | +| CARRY4 | 43 | CarryLogic | +| LUT5 | 42 | LUT | +| LUT1 | 39 | LUT | +| FDSE | 9 | Flop & Latch | +| RAMB36E1 | 4 | Block Memory | +| MUXF7 | 4 | MuxFx | +| SRLC16E | 2 | Distributed Memory | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/project.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/project.wdf new file mode 100644 index 00000000..b7d95384 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/project.wdf @@ -0,0 +1,39 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3130:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/rundef.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/rundef.js new file mode 100644 index 00000000..e293d0ce --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log ila_rf_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rf_test.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/runme.bat b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/runme.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/runme.sh new file mode 100755 index 00000000..c70e213c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log ila_rf_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_rf_test.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/vivado.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/vivado.pb new file mode 100644 index 00000000..ca725632 Binary files /dev/null and b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/ila_rf_test_synth_1/vivado.pb differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..5477b9b4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.end.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/__synthesis_is_complete__ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml new file mode 100644 index 00000000..6cf8268b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/gen_run.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/htr.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/htr.txt new file mode 100644 index 00000000..998ecb35 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log vio_manual_ctrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf new file mode 100644 index 00000000..68d10e56 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/project.wdf @@ -0,0 +1,37 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3130:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3130:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3130:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3665393633363431666561663437633339616462383862306139303537636232:506172656e742050412070726f6a656374204944:00 +eof:1725321426 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/rundef.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/rundef.js new file mode 100644 index 00000000..33a47a99 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log vio_manual_ctrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.bat b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.sh new file mode 100755 index 00000000..a2412a07 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log vio_manual_ctrl.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp new file mode 100644 index 00000000..dcc3e3bd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:126e2b8371bf84e12573a21740ebe52096d272c63293f528f35f6a48b1c9c3b2 +size 145343 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl new file mode 100644 index 00000000..33a0aa85 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.tcl @@ -0,0 +1,155 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1 -new_name vio_manual_ctrl -ip [get_ips vio_manual_ctrl]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top vio_manual_ctrl -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix vio_manual_ctrl_ vio_manual_ctrl.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.v + lappend ipCachedFiles vio_manual_ctrl_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_stub.vhdl + lappend ipCachedFiles vio_manual_ctrl_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_sim_netlist.v + lappend ipCachedFiles vio_manual_ctrl_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_manual_ctrl_sim_netlist.vhdl + lappend ipCachedFiles vio_manual_ctrl_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp vio_manual_ctrl.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_manual_ctrl] +} + +rename_ref -prefix_all vio_manual_ctrl_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef vio_manual_ctrl.dcp +create_report "vio_manual_ctrl_synth_1_synth_report_utilization_0" "report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/ip_user_files/ip/vio_manual_ctrl + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds new file mode 100644 index 00000000..c99630a3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds @@ -0,0 +1,574 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Mon May 8 17:55:43 2023 +# Process ID: 2601945 +# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1 +# Command line: vivado -log vio_manual_ctrl.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_manual_ctrl.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.jou +#----------------------------------------------------------- +source vio_manual_ctrl.tcl -notrace +Command: synth_design -top vio_manual_ctrl -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 2602036 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.445 ; gain = 150.688 ; free physical = 550 ; free virtual = 42199 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'vio_manual_ctrl' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:59] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_manual_ctrl does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:79] +INFO: [Synth 8-6155] done synthesizing module 'vio_manual_ctrl' (7#1) [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/synth/vio_manual_ctrl.v:59] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[1] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in0[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in31[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1922.133 ; gain = 212.375 ; free physical = 654 ; free virtual = 42213 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1926.102 ; gain = 216.344 ; free physical = 646 ; free virtual = 42206 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1926.102 ; gain = 216.344 ; free physical = 646 ; free virtual = 42205 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl_ooc.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2099.789 ; gain = 0.000 ; free physical = 1133 ; free virtual = 42662 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2105.727 ; gain = 5.938 ; free physical = 1130 ; free virtual = 42659 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1217 ; free virtual = 42714 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1217 ; free virtual = 42714 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1219 ; free virtual = 42715 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1209 ; free virtual = 42706 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 2 ++---Registers : + 128 Bit Registers := 1 + 32 Bit Registers := 1 + 16 Bit Registers := 13 + 9 Bit Registers := 1 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 4 Bit Registers := 1 + 3 Bit Registers := 4 + 2 Bit Registers := 3 + 1 Bit Registers := 18 ++---Muxes : + 2 Input 16 Bit Muxes := 3 + 3 Input 9 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 10 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module vio_v3_0_20_probe_out_one +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 3 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized1 +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 16 Bit Registers := 3 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized3 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_all +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 3 Bit Registers := 1 + 1 Bit Registers := 7 ++---Muxes : + 2 Input 1 Bit Muxes := 2 +Module vio_v3_0_20_probe_width +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 9 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 3 Input 9 Bit Muxes := 1 +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 16 Bit Registers := 2 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_decoder +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 3 Bit Registers := 2 + 1 Bit Registers := 9 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 +Module vio_v3_0_20_vio +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[2]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[3]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1145 ; free virtual = 42646 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1153 ; free virtual = 42653 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1146 ; free virtual = 42647 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1142 ; free virtual = 42642 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT2 | 7| +|2 |LUT3 | 59| +|3 |LUT4 | 10| +|4 |LUT5 | 25| +|5 |LUT6 | 82| +|6 |FDRE | 350| +|7 |FDSE | 6| ++------+-----+------+ + +Report Instance Areas: ++------+---------------------------------------+------------------------------------------+------+ +| |Instance |Module |Cells | ++------+---------------------------------------+------------------------------------------+------+ +|1 |top | | 539| +|2 | inst |vio_v3_0_20_vio | 539| +|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| +|4 | DECODER_INST |vio_v3_0_20_decoder | 82| +|5 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 183| +|6 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 9| +|7 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 3| +|8 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 104| +|9 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 6| +|10 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 8| +|11 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 10| ++------+---------------------------------------+------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1154 ; free virtual = 42655 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 293 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2105.727 ; gain = 216.344 ; free physical = 1213 ; free virtual = 42714 +Synthesis Optimization Complete : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2105.727 ; gain = 395.969 ; free physical = 1229 ; free virtual = 42729 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.727 ; gain = 0.000 ; free physical = 1135 ; free virtual = 42636 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +72 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 2105.727 ; gain = 706.809 ; free physical = 1185 ; free virtual = 42685 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.727 ; gain = 0.000 ; free physical = 1185 ; free virtual = 42685 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_manual_ctrl, cache-ID = af26366c91bcf19e +INFO: [Coretcl 2-1174] Renamed 10 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2129.738 ; gain = 0.000 ; free physical = 1203 ; free virtual = 42705 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Mon May 8 17:56:01 2023... diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v new file mode 100644 index 00000000..c7abe00f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:cb065d0eddb5b655bab77fb0852a87bb5011a810896d8e714356346485691606 +size 353149 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl new file mode 100644 index 00000000..69476f18 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:ce8bf1803b3191b816081504adefaa817efc0507189277d23ceb58cfe1deba32 +size 635009 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v new file mode 100644 index 00000000..4ca646b3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v @@ -0,0 +1,26 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon May 8 17:56:01 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.v +// Design : vio_manual_ctrl +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_manual_ctrl(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]" */; + input clk; + output [2:0]probe_out0; + output [0:0]probe_out1; + output [31:0]probe_out2; + output [1:0]probe_out3; + output [3:0]probe_out4; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl new file mode 100644 index 00000000..7883d1ed --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl @@ -0,0 +1,35 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon May 8 17:56:01 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_stub.vhdl +-- Design : vio_manual_ctrl +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_manual_ctrl is + Port ( + clk : in STD_LOGIC; + probe_out0 : out STD_LOGIC_VECTOR ( 2 downto 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 3 downto 0 ) + ); + +end vio_manual_ctrl; + +architecture stub of vio_manual_ctrl is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[2:0],probe_out1[0:0],probe_out2[31:0],probe_out3[1:0],probe_out4[3:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb new file mode 100644 index 00000000..fba31ae8 Binary files /dev/null and b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.pb differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt new file mode 100644 index 00000000..353de78c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vio_manual_ctrl_utilization_synth.rpt @@ -0,0 +1,180 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Mon May 8 17:56:01 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file vio_manual_ctrl_utilization_synth.rpt -pb vio_manual_ctrl_utilization_synth.pb +| Design : vio_manual_ctrl +| Device : 7z100ffg900-2 +| Design State : Synthesized +------------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 150 | 0 | 277400 | 0.05 | +| LUT as Logic | 150 | 0 | 277400 | 0.05 | +| LUT as Memory | 0 | 0 | 108200 | 0.00 | +| Slice Registers | 356 | 0 | 554800 | 0.06 | +| Register as Flip Flop | 356 | 0 | 554800 | 0.06 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 0 | 0 | 138700 | 0.00 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 6 | Yes | Set | - | +| 350 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 755 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 0 | 0 | 1510 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 350 | Flop & Latch | +| LUT6 | 82 | LUT | +| LUT3 | 59 | LUT | +| LUT5 | 25 | LUT | +| LUT4 | 10 | LUT | +| LUT2 | 7 | LUT | +| FDSE | 6 | Flop & Latch | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb new file mode 100644 index 00000000..3c75efdb Binary files /dev/null and b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_manual_ctrl_synth_1/vivado.pb differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.vivado.begin.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..d6d135b3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.vivado.end.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/ISEWrap.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/ISEWrap.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/__synthesis_is_complete__ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/gen_run.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/gen_run.xml new file mode 100644 index 00000000..07b201fe --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/gen_run.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/htr.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/htr.txt new file mode 100644 index 00000000..e1d888e9 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log vio_rf_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_control.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/project.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/project.wdf new file mode 100644 index 00000000..de5d35f9 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/project.wdf @@ -0,0 +1,37 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:38:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3133:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3133:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3665393633363431666561663437633339616462383862306139303537636232:506172656e742050412070726f6a656374204944:00 +eof:298239738 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/rundef.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/rundef.js new file mode 100644 index 00000000..775d1146 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log vio_rf_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_control.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/runme.bat b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/runme.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/runme.sh new file mode 100755 index 00000000..441e08aa --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log vio_rf_control.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_control.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp new file mode 100644 index 00000000..ebbfd5d4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:403a566a4d857f7eecb54e66d0e2af879bf1bdebaffa20b5c0ba1e8f0c117e3f +size 187108 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.tcl new file mode 100644 index 00000000..80a9ecdf --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.tcl @@ -0,0 +1,155 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1 -new_name vio_rf_control -ip [get_ips vio_rf_control]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top vio_rf_control -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix vio_rf_control_ vio_rf_control.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.v + lappend ipCachedFiles vio_rf_control_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_stub.vhdl + lappend ipCachedFiles vio_rf_control_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_sim_netlist.v + lappend ipCachedFiles vio_rf_control_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_control_sim_netlist.vhdl + lappend ipCachedFiles vio_rf_control_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp vio_rf_control.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_rf_control] +} + +rename_ref -prefix_all vio_rf_control_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef vio_rf_control.dcp +create_report "vio_rf_control_synth_1_synth_report_utilization_0" "report_utilization -file vio_rf_control_utilization_synth.rpt -pb vio_rf_control_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_control + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.vds b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.vds new file mode 100644 index 00000000..125d4363 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.vds @@ -0,0 +1,665 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Thu May 18 11:36:23 2023 +# Process ID: 437325 +# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1 +# Command line: vivado -log vio_rf_control.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_control.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vivado.jou +#----------------------------------------------------------- +source vio_rf_control.tcl -notrace +Command: synth_design -top vio_rf_control -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 437390 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.445 ; gain = 150.688 ; free physical = 453 ; free virtual = 49921 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'vio_rf_control' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/synth/vio_rf_control.v:59] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_rf_control does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/synth/vio_rf_control.v:102] +INFO: [Synth 8-6155] done synthesizing module 'vio_rf_control' (8#1) [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/synth/vio_rf_control.v:59] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_in_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1922.133 ; gain = 212.375 ; free physical = 546 ; free virtual = 49951 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.102 ; gain = 215.344 ; free physical = 543 ; free virtual = 49950 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.102 ; gain = 215.344 ; free physical = 543 ; free virtual = 49950 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control_ooc.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control_ooc.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control/vio_rf_control.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.789 ; gain = 0.000 ; free physical = 425 ; free virtual = 49861 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2113.727 ; gain = 7.938 ; free physical = 424 ; free virtual = 49860 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 489 ; free virtual = 49938 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 489 ; free virtual = 49938 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 489 ; free virtual = 49939 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 474 ; free virtual = 49928 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 + 2 Input 2 Bit Adders := 2 ++---Registers : + 128 Bit Registers := 1 + 32 Bit Registers := 2 + 16 Bit Registers := 26 + 13 Bit Registers := 1 + 12 Bit Registers := 1 + 11 Bit Registers := 4 + 7 Bit Registers := 1 + 6 Bit Registers := 2 + 5 Bit Registers := 1 + 4 Bit Registers := 1 + 3 Bit Registers := 3 + 2 Bit Registers := 3 + 1 Bit Registers := 40 ++---Muxes : + 2 Input 16 Bit Muxes := 4 + 8 Input 13 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 21 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module vio_v3_0_20_probe_in_one +Detailed RTL Component Info : ++---Registers : + 11 Bit Registers := 4 + 1 Bit Registers := 2 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized1 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 6 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 6 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized3 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 12 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized4 +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 16 Bit Registers := 3 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_all +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 1 + 1 Bit Registers := 18 ++---Muxes : + 2 Input 1 Bit Muxes := 2 +Module vio_v3_0_20_probe_width +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 ++---Registers : + 13 Bit Registers := 1 + 3 Bit Registers := 1 ++---Muxes : + 8 Input 13 Bit Muxes := 1 +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 16 Bit Registers := 2 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_decoder +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 3 Bit Registers := 2 + 1 Bit Registers := 9 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 +Module vio_v3_0_20_vio +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[14].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[12].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[9].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[8].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[7].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[3].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 516 ; free virtual = 49925 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 457 ; free virtual = 49815 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 456 ; free virtual = 49814 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 449 ; free virtual = 49809 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+------+------+ +| |Cell |Count | ++------+------+------+ +|1 |LUT1 | 1| +|2 |LUT2 | 14| +|3 |LUT3 | 80| +|4 |LUT4 | 9| +|5 |LUT5 | 28| +|6 |LUT6 | 100| +|7 |MUXF7 | 7| +|8 |MUXF8 | 1| +|9 |FDRE | 532| +|10 |FDSE | 20| ++------+------+------+ + +Report Instance Areas: ++------+----------------------------------------+--------------------------------------------+------+ +| |Instance |Module |Cells | ++------+----------------------------------------+--------------------------------------------+------+ +|1 |top | | 792| +|2 | inst |vio_v3_0_20_vio | 792| +|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| +|4 | DECODER_INST |vio_v3_0_20_decoder | 86| +|5 | PROBE_IN_INST |vio_v3_0_20_probe_in_one | 58| +|6 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 368| +|7 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| +|8 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3| +|9 | \G_PROBE_OUT[11].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_1 | 3| +|10 | \G_PROBE_OUT[12].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 3| +|11 | \G_PROBE_OUT[13].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4 | 101| +|12 | \G_PROBE_OUT[14].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_3 | 3| +|13 | \G_PROBE_OUT[15].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4_4 | 106| +|14 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 6| +|15 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_5 | 3| +|16 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 12| +|17 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 12| +|18 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 24| +|19 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_6 | 3| +|20 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_7 | 3| +|21 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_8 | 3| +|22 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_9 | 3| +|23 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 16| ++------+----------------------------------------+--------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 443 ; free virtual = 49806 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 292 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2113.727 ; gain = 215.344 ; free physical = 499 ; free virtual = 49862 +Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2113.727 ; gain = 403.969 ; free physical = 512 ; free virtual = 49876 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Netlist 29-17] Analyzing 8 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2113.727 ; gain = 0.000 ; free physical = 440 ; free virtual = 49737 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +130 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2113.727 ; gain = 714.809 ; free physical = 539 ; free virtual = 49831 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2113.727 ; gain = 0.000 ; free physical = 539 ; free virtual = 49831 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rf_control, cache-ID = caeedda65f3825d9 +INFO: [Coretcl 2-1174] Renamed 22 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2137.738 ; gain = 0.000 ; free physical = 503 ; free virtual = 49794 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file vio_rf_control_utilization_synth.rpt -pb vio_rf_control_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Thu May 18 11:36:41 2023... diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v new file mode 100644 index 00000000..a82bf59b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:61871bc56b34526261f6ee93952fb8c48de88deae16fa932900a16de7cd4b693 +size 418849 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl new file mode 100644 index 00000000..285e9cc8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7d4547a5ef5862f5cc376f41a5d671a805063b6777f0f60d9e8d278616fba128 +size 727945 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v new file mode 100644 index 00000000..e5624f99 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v @@ -0,0 +1,39 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu May 18 11:36:40 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.v +// Design : vio_rf_control +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_rf_control(clk, probe_in0, probe_out0, probe_out1, + probe_out2, probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11, probe_out12, probe_out13, probe_out14, probe_out15) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]" */; + input clk; + input [10:0]probe_in0; + output [0:0]probe_out0; + output [1:0]probe_out1; + output [0:0]probe_out2; + output [5:0]probe_out3; + output [5:0]probe_out4; + output [11:0]probe_out5; + output [0:0]probe_out6; + output [0:0]probe_out7; + output [0:0]probe_out8; + output [0:0]probe_out9; + output [0:0]probe_out10; + output [0:0]probe_out11; + output [0:0]probe_out12; + output [31:0]probe_out13; + output [0:0]probe_out14; + output [31:0]probe_out15; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl new file mode 100644 index 00000000..a80bc92f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl @@ -0,0 +1,47 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu May 18 11:36:40 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_stub.vhdl +-- Design : vio_rf_control +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_rf_control is + Port ( + clk : in STD_LOGIC; + probe_in0 : in STD_LOGIC_VECTOR ( 10 downto 0 ); + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 5 downto 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out12 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out13 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out14 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out15 : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end vio_rf_control; + +architecture stub of vio_rf_control is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_in0[10:0],probe_out0[0:0],probe_out1[1:0],probe_out2[0:0],probe_out3[5:0],probe_out4[5:0],probe_out5[11:0],probe_out6[0:0],probe_out7[0:0],probe_out8[0:0],probe_out9[0:0],probe_out10[0:0],probe_out11[0:0],probe_out12[0:0],probe_out13[31:0],probe_out14[0:0],probe_out15[31:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_utilization_synth.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_utilization_synth.pb new file mode 100644 index 00000000..760ddc80 Binary files /dev/null and b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_utilization_synth.pb differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_utilization_synth.rpt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_utilization_synth.rpt new file mode 100644 index 00000000..69768854 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vio_rf_control_utilization_synth.rpt @@ -0,0 +1,183 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Thu May 18 11:36:40 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file vio_rf_control_utilization_synth.rpt -pb vio_rf_control_utilization_synth.pb +| Design : vio_rf_control +| Device : 7z100ffg900-2 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 189 | 0 | 277400 | 0.07 | +| LUT as Logic | 189 | 0 | 277400 | 0.07 | +| LUT as Memory | 0 | 0 | 108200 | 0.00 | +| Slice Registers | 552 | 0 | 554800 | 0.10 | +| Register as Flip Flop | 552 | 0 | 554800 | 0.10 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 7 | 0 | 138700 | <0.01 | +| F8 Muxes | 1 | 0 | 69350 | <0.01 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 20 | Yes | Set | - | +| 532 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 755 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 0 | 0 | 1510 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 532 | Flop & Latch | +| LUT6 | 100 | LUT | +| LUT3 | 80 | LUT | +| LUT5 | 28 | LUT | +| FDSE | 20 | Flop & Latch | +| LUT2 | 14 | LUT | +| LUT4 | 9 | LUT | +| MUXF7 | 7 | MuxFx | +| MUXF8 | 1 | MuxFx | +| LUT1 | 1 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vivado.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vivado.pb new file mode 100644 index 00000000..e166a01e Binary files /dev/null and b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_control_synth_1/vivado.pb differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.Vivado_Synthesis.queue.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.vivado.begin.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.vivado.begin.rst new file mode 100644 index 00000000..c61ffe5b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.vivado.end.rst b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/.vivado.end.rst new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/ISEWrap.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/ISEWrap.js new file mode 100755 index 00000000..3e83de11 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/ISEWrap.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/ISEWrap.sh new file mode 100755 index 00000000..f679f2e8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/__synthesis_is_complete__ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/__synthesis_is_complete__ new file mode 100644 index 00000000..e69de29b diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/gen_run.xml b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/gen_run.xml new file mode 100644 index 00000000..35b57724 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/gen_run.xml @@ -0,0 +1,64 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/htr.txt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/htr.txt new file mode 100644 index 00000000..fb099950 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/htr.txt @@ -0,0 +1,9 @@ +# +# Vivado(TM) +# htr.txt: a Vivado-generated description of how-to-repeat the +# the basic steps of a run. Note that runme.bat/sh needs +# to be invoked for Vivado to track run status. +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +vivado -log vio_rf_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_test.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/project.wdf b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/project.wdf new file mode 100644 index 00000000..b7d95384 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/project.wdf @@ -0,0 +1,39 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3130:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 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a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/rundef.js b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/rundef.js new file mode 100644 index 00000000..4e5aae25 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +echo "This script was generated under a different operating system." +echo "Please update the PATH variable below, before executing this script" +exit + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; +} else { + PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log vio_rf_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_test.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/runme.bat b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/runme.bat new file mode 100644 index 00000000..ba55218d --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/runme.bat @@ -0,0 +1,11 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +set PATH=%SYSTEMROOT%\system32;%PATH% +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/runme.sh b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/runme.sh new file mode 100755 index 00000000..c30677cd --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/runme.sh @@ -0,0 +1,39 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +if [ -z "$PATH" ]; then + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin +else + PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log vio_rf_test.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_test.tcl diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.dcp b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.dcp new file mode 100644 index 00000000..f890da71 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:24264de632f3c11f0b2d857dbfcbc618aa7cefc401ff56a7bf2779bd9fb40439 +size 217220 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.tcl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.tcl new file mode 100644 index 00000000..c31353c5 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.tcl @@ -0,0 +1,155 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin +set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin +set_param project.vivado.isBlockSynthRun true +set_msg_config -msgmgr_mode ooc_run +create_project -in_memory -part xc7z100ffg900-2 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/wt [current_project] +set_property parent.project_path /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property ip_output_repo /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_ip -quiet /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xci +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xdc] +set_property used_in_implementation false [get_files -all /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test_ooc.xdc] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 + +set cached_ip [config_ip_cache -export -no_bom -dir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1 -new_name vio_rf_test -ip [get_ips vio_rf_test]] + +if { $cached_ip eq {} } { +close [open __synthesis_is_running__ w] + +synth_design -top vio_rf_test -part xc7z100ffg900-2 -mode out_of_context + +#--------------------------------------------------------- +# Generate Checkpoint/Stub/Simulation Files For IP Cache +#--------------------------------------------------------- +# disable binary constraint mode for IPCache checkpoints +set_param constraints.enableBinaryConstraints false + +catch { + write_checkpoint -force -noxdef -rename_prefix vio_rf_test_ vio_rf_test.dcp + + set ipCachedFiles {} + write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_test_stub.v + lappend ipCachedFiles vio_rf_test_stub.v + + write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_test_stub.vhdl + lappend ipCachedFiles vio_rf_test_stub.vhdl + + write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_test_sim_netlist.v + lappend ipCachedFiles vio_rf_test_sim_netlist.v + + write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_rf_test_sim_netlist.vhdl + lappend ipCachedFiles vio_rf_test_sim_netlist.vhdl +set TIME_taken [expr [clock seconds] - $TIME_start] + + config_ip_cache -add -dcp vio_rf_test.dcp -move_files $ipCachedFiles -use_project_ipc -synth_runtime $TIME_taken -ip [get_ips vio_rf_test] +} + +rename_ref -prefix_all vio_rf_test_ + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef vio_rf_test.dcp +create_report "vio_rf_test_synth_1_synth_report_utilization_0" "report_utilization -file vio_rf_test_utilization_synth.rpt -pb vio_rf_test_utilization_synth.pb" + +if { [catch { + write_verilog -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode synth_stub /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT" +} + +if { [catch { + write_verilog -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.v +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + +if { [catch { + write_vhdl -force -mode funcsim /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.vhdl +} _RESULT ] } { + puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT" +} + + +} else { + + +}; # end if cached_ip + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.v -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.vhdl -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xci] + +add_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.dcp -of_objects [get_files /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xci] + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test + } +} + +if {[file isdir /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test]} { + catch { + file copy -force /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/ip_user_files/ip/vio_rf_test + } +} +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.vds b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.vds new file mode 100644 index 00000000..68837bf2 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.vds @@ -0,0 +1,653 @@ +#----------------------------------------------------------- +# Vivado v2019.1.3 (64-bit) +# SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# Start of session at: Thu May 18 12:54:22 2023 +# Process ID: 520460 +# Current directory: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1 +# Command line: vivado -log vio_rf_test.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source vio_rf_test.tcl +# Log file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.vds +# Journal file: /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vivado.jou +#----------------------------------------------------------- +source vio_rf_test.tcl -notrace +Command: synth_design -top vio_rf_test -part xc7z100ffg900-2 -mode out_of_context +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z100' +INFO: [Device 21-403] Loading part xc7z100ffg900-2 +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 520694 +--------------------------------------------------------------------------------- +Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1860.508 ; gain = 153.719 ; free physical = 488 ; free virtual = 48108 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'vio_rf_test' [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/synth/vio_rf_test.v:59] +WARNING: [Synth 8-3848] Net sl_iport0 in module/entity vio_rf_test does not have driver. [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/synth/vio_rf_test.v:93] +INFO: [Synth 8-6155] done synthesizing module 'vio_rf_test' (7#1) [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/synth/vio_rf_test.v:59] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[4] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[3] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[2] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Bus_Data_in[1] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[7] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[6] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Bus_Data_in[5] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized7 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized6 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized5 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized4 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized3 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized2 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized1 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Read +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[15] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[14] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[13] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[12] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[11] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[10] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[9] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Bus_Data_in[8] +WARNING: [Synth 8-3331] design vio_v3_0_20_probe_out_one__parameterized0 has unconnected port Internal_cnt_rst +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in0[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in1[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in2[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in3[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in4[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in5[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in6[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in7[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in8[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in9[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in10[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in11[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in12[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in13[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in14[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in15[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in16[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in17[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in18[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in19[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in20[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in21[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in22[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in23[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in24[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in25[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in26[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in27[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in28[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in29[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in30[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in31[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in32[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in33[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in34[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in35[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in36[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in37[0] +WARNING: [Synth 8-3331] design vio_v3_0_20_vio has unconnected port probe_in38[0] +INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. +--------------------------------------------------------------------------------- +Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1922.195 ; gain = 215.406 ; free physical = 474 ; free virtual = 48095 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.164 ; gain = 218.375 ; free physical = 473 ; free virtual = 48095 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1925.164 ; gain = 218.375 ; free physical = 473 ; free virtual = 48095 +--------------------------------------------------------------------------------- +INFO: [Project 1-570] Preparing netlist for logic optimization + +Processing XDC Constraints +Initializing timing engine +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test_ooc.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test_ooc.xdc] +Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xdc] +Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test/vio_rf_test.xdc] +Completed Processing XDC Constraints + +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2106.820 ; gain = 0.000 ; free physical = 465 ; free virtual = 47975 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2114.758 ; gain = 7.938 ; free physical = 465 ; free virtual = 47975 +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 513 ; free virtual = 47799 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z100ffg900-2 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 513 ; free virtual = 47799 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Applying 'set_property' XDC Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 513 ; free virtual = 47800 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 507 ; free virtual = 47794 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 2 + 2 Input 2 Bit Adders := 3 ++---Registers : + 128 Bit Registers := 1 + 64 Bit Registers := 1 + 32 Bit Registers := 3 + 16 Bit Registers := 28 + 14 Bit Registers := 1 + 12 Bit Registers := 2 + 8 Bit Registers := 2 + 7 Bit Registers := 1 + 5 Bit Registers := 2 + 4 Bit Registers := 1 + 3 Bit Registers := 4 + 2 Bit Registers := 3 + 1 Bit Registers := 27 ++---Muxes : + 2 Input 16 Bit Muxes := 5 + 4 Input 16 Bit Muxes := 1 + 6 Input 14 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 14 +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +Module vio_v3_0_20_probe_out_one +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized0 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 8 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized1 +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 16 Bit Registers := 3 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized2 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 12 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized3 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 12 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized4 +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 16 Bit Registers := 3 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized5 +Detailed RTL Component Info : ++---Adders : + 2 Input 2 Bit Adders := 1 ++---Registers : + 32 Bit Registers := 1 + 16 Bit Registers := 3 + 2 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized6 +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 ++---Registers : + 64 Bit Registers := 1 + 16 Bit Registers := 5 + 3 Bit Registers := 1 ++---Muxes : + 4 Input 16 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_one__parameterized7 +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 5 Bit Registers := 1 ++---Muxes : + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_probe_out_all +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 + 4 Bit Registers := 1 + 1 Bit Registers := 14 ++---Muxes : + 2 Input 1 Bit Muxes := 2 +Module vio_v3_0_20_probe_width +Detailed RTL Component Info : ++---Adders : + 2 Input 3 Bit Adders := 1 ++---Registers : + 14 Bit Registers := 1 + 3 Bit Registers := 1 ++---Muxes : + 6 Input 14 Bit Muxes := 1 +Module xsdbs_v1_0_2_xsdbs +Detailed RTL Component Info : ++---Registers : + 128 Bit Registers := 1 + 16 Bit Registers := 2 + 1 Bit Registers := 1 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 1 +Module vio_v3_0_20_decoder +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 2 + 7 Bit Registers := 1 + 5 Bit Registers := 1 + 3 Bit Registers := 2 + 1 Bit Registers := 9 ++---Muxes : + 2 Input 16 Bit Muxes := 1 + 2 Input 1 Bit Muxes := 3 +Module vio_v3_0_20_vio +Detailed RTL Component Info : ++---Registers : + 16 Bit Registers := 1 +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 2020 (col length:140) +BRAMs: 1510 (col length: RAMB18 140 RAMB36 70) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[1]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[2]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[3]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[4]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[5]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[6]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[7]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[8]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[9]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[10]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[11]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[12]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[13]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[14]' (FDRE) to 'inst/PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[11].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[10].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[6].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[5].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[4].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[2].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[1].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_ALL_INST/G_PROBE_OUT[0].PROBE_OUT0_INST/data_int_reg[15] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[0]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[0]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[1]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_ALL_INST/addr_p1_reg[2]' (FD) to 'inst/DECODER_INST/xsdb_addr_2_0_p1_reg[2]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[0]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[1]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[12]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[4]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[13]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[5]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[6]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[7]' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (inst/\PROBE_OUT_WIDTH_INST/probe_width_int_reg[7] ) +INFO: [Synth 8-3886] merging instance 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[8]' (FD) to 'inst/PROBE_OUT_WIDTH_INST/probe_width_int_reg[9]' +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 490 ; free virtual = 47781 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Applying XDC Timing Constraints +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 427 ; free virtual = 47708 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 427 ; free virtual = 47708 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 423 ; free virtual = 47705 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[36] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[35] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[34] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[33] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[32] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[31] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[30] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[29] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[28] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[27] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[26] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[25] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[24] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[23] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[22] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[21] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[20] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[19] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[18] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[17] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[16] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[15] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[14] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[13] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[12] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[11] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[10] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[9] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[8] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[7] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[6] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[5] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[4] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[3] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[2] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[1] to constant 0 +WARNING: [Synth 8-3295] tying undriven pin inst:sl_iport0[0] to constant 0 +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 573 ; free virtual = 47825 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 573 ; free virtual = 47825 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 575 ; free virtual = 47828 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 575 ; free virtual = 47828 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 575 ; free virtual = 47828 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 575 ; free virtual = 47828 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-----+------+ +| |Cell |Count | ++------+-----+------+ +|1 |LUT2 | 13| +|2 |LUT3 | 85| +|3 |LUT4 | 7| +|4 |LUT5 | 35| +|5 |LUT6 | 143| +|6 |FDRE | 678| +|7 |FDSE | 78| ++------+-----+------+ + +Report Instance Areas: ++------+----------------------------------------+--------------------------------------------+------+ +| |Instance |Module |Cells | ++------+----------------------------------------+--------------------------------------------+------+ +|1 |top | | 1039| +|2 | inst |vio_v3_0_20_vio | 1039| +|3 | U_XSDB_SLAVE |xsdbs_v1_0_2_xsdbs | 248| +|4 | DECODER_INST |vio_v3_0_20_decoder | 79| +|5 | PROBE_OUT_ALL_INST |vio_v3_0_20_probe_out_all | 676| +|6 | \G_PROBE_OUT[0].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one | 3| +|7 | \G_PROBE_OUT[10].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized7 | 10| +|8 | \G_PROBE_OUT[11].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_0 | 3| +|9 | \G_PROBE_OUT[1].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0 | 16| +|10 | \G_PROBE_OUT[2].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized0_1 | 16| +|11 | \G_PROBE_OUT[3].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized1 | 100| +|12 | \G_PROBE_OUT[4].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one_2 | 3| +|13 | \G_PROBE_OUT[5].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized2 | 24| +|14 | \G_PROBE_OUT[6].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized3 | 24| +|15 | \G_PROBE_OUT[7].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized4 | 105| +|16 | \G_PROBE_OUT[8].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized5 | 104| +|17 | \G_PROBE_OUT[9].PROBE_OUT0_INST |vio_v3_0_20_probe_out_one__parameterized6 | 171| +|18 | PROBE_OUT_WIDTH_INST |vio_v3_0_20_probe_width | 20| ++------+----------------------------------------+--------------------------------------------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 575 ; free virtual = 47828 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 293 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2114.758 ; gain = 218.375 ; free physical = 607 ; free virtual = 47881 +Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 2114.758 ; gain = 407.969 ; free physical = 621 ; free virtual = 47890 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2114.758 ; gain = 0.000 ; free physical = 535 ; free virtual = 47811 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +102 Infos, 138 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2114.758 ; gain = 715.840 ; free physical = 607 ; free virtual = 47894 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2114.758 ; gain = 0.000 ; free physical = 604 ; free virtual = 47893 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.dcp' has been generated. +WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP vio_rf_test, cache-ID = 06d53c7bf3a5a806 +INFO: [Coretcl 2-1174] Renamed 17 cell refs. +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2138.770 ; gain = 0.000 ; free physical = 553 ; free virtual = 47840 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file vio_rf_test_utilization_synth.rpt -pb vio_rf_test_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Thu May 18 12:54:40 2023... diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.v new file mode 100644 index 00000000..b0f9aad4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:5c56114c4d1dbd4de738da259f25557427b35cb18dfeb59dda5bf2598412b05e +size 477028 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.vhdl new file mode 100644 index 00000000..0ffb41e3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:0d14ce253bc7bd29c3d5ba48eb5bde1db77a4576966d51a7f7133d0cfa5da73e +size 802152 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v new file mode 100644 index 00000000..374e48d6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v @@ -0,0 +1,34 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Thu May 18 12:54:39 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub +// /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.v +// Design : vio_rf_test +// Purpose : Stub declaration of top-level module interface +// Device : xc7z100ffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "vio,Vivado 2019.1.3" *) +module vio_rf_test(clk, probe_out0, probe_out1, probe_out2, + probe_out3, probe_out4, probe_out5, probe_out6, probe_out7, probe_out8, probe_out9, + probe_out10, probe_out11) +/* synthesis syn_black_box black_box_pad_pin="clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]" */; + input clk; + output [0:0]probe_out0; + output [7:0]probe_out1; + output [7:0]probe_out2; + output [31:0]probe_out3; + output [0:0]probe_out4; + output [11:0]probe_out5; + output [11:0]probe_out6; + output [31:0]probe_out7; + output [31:0]probe_out8; + output [63:0]probe_out9; + output [4:0]probe_out10; + output [0:0]probe_out11; +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl new file mode 100644 index 00000000..290eaedb --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl @@ -0,0 +1,42 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Thu May 18 12:54:39 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub +-- /home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_stub.vhdl +-- Design : vio_rf_test +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z100ffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity vio_rf_test is + Port ( + clk : in STD_LOGIC; + probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out1 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out2 : out STD_LOGIC_VECTOR ( 7 downto 0 ); + probe_out3 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out4 : out STD_LOGIC_VECTOR ( 0 to 0 ); + probe_out5 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out6 : out STD_LOGIC_VECTOR ( 11 downto 0 ); + probe_out7 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out8 : out STD_LOGIC_VECTOR ( 31 downto 0 ); + probe_out9 : out STD_LOGIC_VECTOR ( 63 downto 0 ); + probe_out10 : out STD_LOGIC_VECTOR ( 4 downto 0 ); + probe_out11 : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end vio_rf_test; + +architecture stub of vio_rf_test is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "clk,probe_out0[0:0],probe_out1[7:0],probe_out2[7:0],probe_out3[31:0],probe_out4[0:0],probe_out5[11:0],probe_out6[11:0],probe_out7[31:0],probe_out8[31:0],probe_out9[63:0],probe_out10[4:0],probe_out11[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "vio,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_utilization_synth.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_utilization_synth.pb new file mode 100644 index 00000000..7a0dd59b Binary files /dev/null and b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_utilization_synth.pb differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_utilization_synth.rpt b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_utilization_synth.rpt new file mode 100644 index 00000000..e51bb4dc --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vio_rf_test_utilization_synth.rpt @@ -0,0 +1,180 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +----------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +| Date : Thu May 18 12:54:39 2023 +| Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +| Command : report_utilization -file vio_rf_test_utilization_synth.rpt -pb vio_rf_test_utilization_synth.pb +| Design : vio_rf_test +| Device : 7z100ffg900-2 +| Design State : Synthesized +----------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Memory +3. DSP +4. IO and GT Specific +5. Clocking +6. Specific Feature +7. Primitives +8. Black Boxes +9. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs* | 236 | 0 | 277400 | 0.09 | +| LUT as Logic | 236 | 0 | 277400 | 0.09 | +| LUT as Memory | 0 | 0 | 108200 | 0.00 | +| Slice Registers | 756 | 0 | 554800 | 0.14 | +| Register as Flip Flop | 756 | 0 | 554800 | 0.14 | +| Register as Latch | 0 | 0 | 554800 | 0.00 | +| F7 Muxes | 0 | 0 | 138700 | 0.00 | +| F8 Muxes | 0 | 0 | 69350 | 0.00 | ++-------------------------+------+-------+-----------+-------+ +* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 78 | Yes | Set | - | +| 678 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 755 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 755 | 0.00 | +| RAMB18 | 0 | 0 | 1510 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +3. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 2020 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +4. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 362 | 0.00 | +| Bonded IPADs | 0 | 0 | 50 | 0.00 | +| Bonded OPADs | 0 | 0 | 32 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 8 | 0.00 | +| PHASER_REF | 0 | 0 | 8 | 0.00 | +| OUT_FIFO | 0 | 0 | 32 | 0.00 | +| IN_FIFO | 0 | 0 | 32 | 0.00 | +| IDELAYCTRL | 0 | 0 | 8 | 0.00 | +| IBUFDS | 0 | 0 | 348 | 0.00 | +| GTXE2_COMMON | 0 | 0 | 4 | 0.00 | +| GTXE2_CHANNEL | 0 | 0 | 16 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 32 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 32 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 400 | 0.00 | +| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 150 | 0.00 | +| IBUFDS_GTE2 | 0 | 0 | 8 | 0.00 | +| ILOGIC | 0 | 0 | 362 | 0.00 | +| OLOGIC | 0 | 0 | 362 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +5. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 32 | 0.00 | +| MMCME2_ADV | 0 | 0 | 8 | 0.00 | +| PLLE2_ADV | 0 | 0 | 8 | 0.00 | +| BUFMRCE | 0 | 0 | 16 | 0.00 | +| BUFHCE | 0 | 0 | 168 | 0.00 | +| BUFR | 0 | 0 | 32 | 0.00 | ++------------+------+-------+-----------+-------+ + + +6. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| PCIE_2_1 | 0 | 0 | 1 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +7. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ +| FDRE | 678 | Flop & Latch | +| LUT6 | 143 | LUT | +| LUT3 | 85 | LUT | +| FDSE | 78 | Flop & Latch | +| LUT5 | 35 | LUT | +| LUT2 | 13 | LUT | +| LUT4 | 7 | LUT | ++----------+------+---------------------+ + + +8. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +9. Instantiated Netlists +------------------------ + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vivado.pb b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vivado.pb new file mode 100644 index 00000000..ee19ad8e Binary files /dev/null and b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.runs/vio_rf_test_synth_1/vivado.pb differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr new file mode 100644 index 00000000..5df05218 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/managed_ip_project/managed_ip_project.xpr @@ -0,0 +1,452 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word.xcix new file mode 100644 index 00000000..1eb11f2e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/rom_freq_word.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:23ec4e23d084d178d24316d6f54d8dcd71b612c1fb375fd559a93237b59d8885 +size 11664035 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/sig_clk_gen.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/sig_clk_gen.xcix new file mode 100644 index 00000000..156f8841 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/sig_clk_gen.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:533644b17a1cbea30e65b69b38c4f370aa16211eb5185c4805b874678c030e2c +size 93062 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/vio_manual_ctrl.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/vio_manual_ctrl.xcix new file mode 100644 index 00000000..20961c70 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/vio_manual_ctrl.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:7cfaeb668faf2b1a9d4767a389ae58c4d3d6c0d249171785b9414bb91604b9f6 +size 721507 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control.xcix new file mode 100644 index 00000000..81013c3b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_control.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:74e7166d8bda8c3824a8ab80ef948f950fabd3f401c14a10bbd6e0bb92b13a42 +size 777513 diff --git a/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test.xcix b/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test.xcix new file mode 100644 index 00000000..2806cf80 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/ip/vio_rf_test.xcix @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8cf2a0a93c53f8015dc532e9053c8d45d71205773e5dd65d3813ecdb9b892583 +size 817412 diff --git a/projects/dl814_dj/dl814_dj_new_48m/project.tcl b/projects/dl814_dj/dl814_dj_new_48m/project.tcl new file mode 100644 index 00000000..84143cd6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project.tcl @@ -0,0 +1,692 @@ +#***************************************************************************************** +# Vivado (TM) v2019.1.3 (64-bit) +# +# project.tcl: Tcl script for re-creating project 'project' +# +# Generated by Vivado on Fri May 12 10:01:28 CST 2023 +# IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (project.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# +# +# 3. The following remote source files that were added to the original project:- +# +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_rf_control/vio_rf_control.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/vio_manual_ctrl/vio_manual_ctrl.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/common_ip/basic_driver/ila_ctrl_signal/ila_ctrl_signal.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/common_ip/basic_driver/ila_4x16x131072/ila_4x16x131072.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/common_ip/basic_driver/ila_2x16x131072/ila_2x16x131072.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/lpf_125k/lpf_125k.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/common_ipi-bd/basic_driver_bd/system_bd.bd" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/sig_clk_gen/sig_clk_gen.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/rtl/rf_auto_switch_freq.v" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/rtl/rf_control.v" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/rtl/tx_control.v" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/rtl/tx_pn_seq_6mcps.v" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/rtl/tx_qpsk.v" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/rtl/system_top.v" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/coe/lpf_125k.coe" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe" +# "/home/josh/Workspace/vivado-git/modules/xc7z100ffg900-2/tx_qpsk/ip/coe/sweep_freq.coe" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/coe/freq_word.coe" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/ip/rom_freq_word/rom_freq_word.xci" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/constraints/z7100_ad9528_ad9371.xdc" +# "/home/josh/Workspace/vivado-git/projects/dl814_dj/dl814_dj_48m/testbenches/tb_tx_pn_seq.v" +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "project" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "project.tcl" + +# Help information for this script +proc print_help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { print_help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/project"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z100ffg900-2 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Set project properties +set obj [current_project] +set_property -name "corecontainer.enable" -value "1" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_core_container" -value "1" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "part" -value "xc7z100ffg900-2" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "target_simulator" -value "IES" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "36" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "36" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "36" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "36" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "36" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "36" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "36" -objects $obj +set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/ip/vio_rf_control/vio_rf_control.xci"] \ + [file normalize "${origin_dir}/ip/vio_manual_ctrl/vio_manual_ctrl.xci"] \ + [file normalize "${origin_dir}/../common_ip/basic_driver/ila_ctrl_signal/ila_ctrl_signal.xci"] \ + [file normalize "${origin_dir}/../common_ip/basic_driver/ila_4x16x131072/ila_4x16x131072.xci"] \ + [file normalize "${origin_dir}/../common_ip/basic_driver/ila_2x16x131072/ila_2x16x131072.xci"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci"] \ + [file normalize "${origin_dir}/ip/lpf_125k/lpf_125k.xci"] \ + [file normalize "${origin_dir}/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.xci"] \ + [file normalize "${origin_dir}/../common_ipi-bd/basic_driver_bd/system_bd.bd"] \ + [file normalize "${origin_dir}/ip/sig_clk_gen/sig_clk_gen.xci"] \ + [file normalize "${origin_dir}/rtl/rf_auto_switch_freq.v"] \ + [file normalize "${origin_dir}/rtl/rf_control.v"] \ + [file normalize "${origin_dir}/../common_ipi-bd/basic_driver_bd/hdl/system_bd_wrapper.v"] \ + [file normalize "${origin_dir}/rtl/tx_control.v"] \ + [file normalize "${origin_dir}/rtl/tx_pn_seq_6mcps.v"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/rtl/tx_qpsk.v"] \ + [file normalize "${origin_dir}/rtl/system_top.v"] \ + [file normalize "${origin_dir}/ip/coe/lpf_125k.coe"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/coe/hrc_64_12_025.coe"] \ + [file normalize "${origin_dir}/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/coe/sweep_freq.coe"] \ + [file normalize "${origin_dir}/ip/coe/freq_word.coe"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/ip/vio_rf_control/vio_rf_control.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/vio_manual_ctrl/vio_manual_ctrl.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/basic_driver/ila_ctrl_signal/ila_ctrl_signal.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/basic_driver/ila_4x16x131072/ila_4x16x131072.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ip/basic_driver/ila_2x16x131072/ila_2x16x131072.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/cmpy_18x8/cmpy_18x8.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/dds_32b_8b/dds_32b_8b.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/hop_rom/hop_rom.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../../../modules/xc7z100ffg900-2/tx_qpsk/ip/hrc_64_12_025/hrc_64_12_025.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/lpf_125k/lpf_125k.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/ip/fifo_48m_to_122p88m/fifo_48m_to_122p88m.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + +set file "$origin_dir/../common_ipi-bd/basic_driver_bd/system_bd.bd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "registered_with_manager" -value "1" -objects $file_obj + +set file "$origin_dir/ip/sig_clk_gen/sig_clk_gen.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "system_top" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/ip/rom_freq_word/rom_freq_word.xci"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/ip/rom_freq_word/rom_freq_word.xci" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Set 'sources_1' fileset file properties for local files +# None + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/constraints/z7100_ad9528_ad9371.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/constraints/z7100_ad9528_ad9371.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] +set_property -name "target_part" -value "xc7z100ffg900-2" -objects $obj + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +set files [list \ + [file normalize "${origin_dir}/testbenches/tb_tx_pn_seq.v"] \ +] +add_files -norecurse -fileset $obj $files + +# Set 'sim_1' fileset file properties for remote files +# None + +# Set 'sim_1' fileset file properties for local files +# None + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "top" -value "system_top" -objects $obj +set_property -name "top_auto_set" -value "0" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj + +# Set 'utils_1' fileset object +set obj [get_filesets utils_1] +# Empty (no sources present) + +# Set 'utils_1' fileset properties +set obj [get_filesets utils_1] + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xc7z100ffg900-2 -flow {Vivado Synthesis 2019} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2019" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "part" -value "xc7z100ffg900-2" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xc7z100ffg900-2 -flow {Vivado Implementation 2019} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2019" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { +set_property -name "options.verbose" -value "1" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "options.max_paths" -value "10" -objects $obj +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { +set_property -name "options.warn_on_violation" -value "1" -objects $obj + +} +set obj [get_runs impl_1] +set_property -name "part" -value "xc7z100ffg900-2" -objects $obj +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:${_xil_proj_name_}" +# Create 'drc_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "drc_1" ] ] ""]} { +create_dashboard_gadget -name {drc_1} -type drc +} +set obj [get_dashboard_gadgets [ list "drc_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj + +# Create 'methodology_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "methodology_1" ] ] ""]} { +create_dashboard_gadget -name {methodology_1} -type methodology +} +set obj [get_dashboard_gadgets [ list "methodology_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj + +# Create 'power_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "power_1" ] ] ""]} { +create_dashboard_gadget -name {power_1} -type power +} +set obj [get_dashboard_gadgets [ list "power_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj + +# Create 'timing_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "timing_1" ] ] ""]} { +create_dashboard_gadget -name {timing_1} -type timing +} +set obj [get_dashboard_gadgets [ list "timing_1" ] ] +set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj + +# Create 'utilization_1' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_1" ] ] ""]} { +create_dashboard_gadget -name {utilization_1} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_1" ] ] +set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj +set_property -name "run.step" -value "synth_design" -objects $obj +set_property -name "run.type" -value "synthesis" -objects $obj + +# Create 'utilization_2' gadget (if not found) +if {[string equal [get_dashboard_gadgets [ list "utilization_2" ] ] ""]} { +create_dashboard_gadget -name {utilization_2} -type utilization +} +set obj [get_dashboard_gadgets [ list "utilization_2" ] ] +set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj + +move_dashboard_gadget -name {utilization_1} -row 0 -col 0 +move_dashboard_gadget -name {power_1} -row 1 -col 0 +move_dashboard_gadget -name {drc_1} -row 2 -col 0 +move_dashboard_gadget -name {timing_1} -row 0 -col 1 +move_dashboard_gadget -name {utilization_2} -row 1 -col 1 +move_dashboard_gadget -name {methodology_1} -row 2 -col 1 diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.hw/project.lpr b/projects/dl814_dj/dl814_dj_new_48m/project/project.hw/project.lpr new file mode 100644 index 00000000..29d8123e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.hw/project.lpr @@ -0,0 +1,6 @@ + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/debug_nets.ltx b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/debug_nets.ltx new file mode 100644 index 00000000..22ac3eb7 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.runs/impl_1/debug_nets.ltx @@ -0,0 +1,2500 @@ +{ + "ltx_root": { + "version": 4, + "minor": 0, + "ltx_data": [ + { + "name": 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00000000..ea6ae6e1 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/.cproject @@ -0,0 +1,162 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/.project b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/.project new file mode 100644 index 00000000..a22cdc0b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/.project @@ -0,0 +1,26 @@ + + + dl814_dj + Created by SDK v2019.1. dl814_dj_bsp - ps7_cortexa9_0 + + dl814_dj_bsp + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/README.txt b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/README.txt new file mode 100644 index 00000000..c4d32efe --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/README.txt @@ -0,0 +1 @@ +Empty application. Add your own sources. diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/Xilinx.spec b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/Xilinx.spec new file mode 100644 index 00000000..8eea3774 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/Xilinx.spec @@ -0,0 +1,2 @@ +*startfile: +crti%O%s crtbegin%O%s diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/common.c b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/common.c new file mode 100644 index 00000000..c4323b2f --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/common.c @@ -0,0 +1,275 @@ +/** + * \file common.c + * \brief Contains Mykonos API common wrapper functions for user hardware platform drivers + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#include +#include +#include +#include +#include +#include "common.h" +#include "platform_drivers.h" +#include "parameters.h" + +ADI_LOGLEVEL CMB_LOGLEVEL = ADIHAL_LOG_NONE; + +static uint32_t _desired_time_to_elapse_us = 0; +struct spi_desc *spi_ad_desc; +struct gpio_desc *gpio_ad9371_resetb; +struct gpio_desc *gpio_ad9528_resetb; +struct gpio_desc *gpio_ad9528_sysref_req; + +commonErr_t CMB_initPlatform(void) +{ + struct spi_init_param spi_param; + int32_t status = COMMONERR_OK; + + status |= gpio_get(&gpio_ad9371_resetb, AD9371_RESET_B); + status |= gpio_get(&gpio_ad9528_resetb, AD9528_RESET_B); + status |= gpio_get(&gpio_ad9528_sysref_req, AD9528_SYSREF_REQ); + + spi_param.id = 0; + spi_param.mode = SPI_MODE_0; + spi_param.chip_select = AD9371_CS; + spi_param.max_speed_hz = 25000000u; + + status |= spi_init(&spi_ad_desc, &spi_param); + + if (status != SUCCESS) { + return COMMONERR_FAILED; + } + + return COMMONERR_OK; +} + +commonErr_t CMB_closeHardware(void) +{ + return(COMMONERR_OK); +} + +commonErr_t CMB_setGPIO(uint32_t GPIO) +{ + return(COMMONERR_OK); +} + +commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex) +{ + struct gpio_desc *reset_gpio; + + switch (spiChipSelectIndex) { + case AD9371_CS: + reset_gpio = gpio_ad9371_resetb; + break; + case AD9528_CS: + reset_gpio = gpio_ad9528_resetb; + break; + default: + return(COMMONERR_FAILED); + } + + gpio_direction_output(reset_gpio, 1); + CMB_wait_ms(1); + gpio_direction_output(reset_gpio, 0); + CMB_wait_ms(1); + gpio_direction_output(reset_gpio, 1); + CMB_wait_ms(1); + + return(COMMONERR_OK); +} + +commonErr_t CMB_setSPIOptions(spiSettings_t *spiSettings) +{ + return(COMMONERR_OK); +} + +commonErr_t CMB_setSPIChannel(uint16_t chipSelectIndex ) +{ + return(COMMONERR_OK); +} + +commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr, + uint8_t data) +{ + uint8_t buf[3]; + + spi_ad_desc->chip_select = spiSettings->chipSelectIndex - 1; + + buf[0] = (uint8_t) ((addr >> 8) & 0x7f); + buf[1] = (uint8_t) (addr & 0xff); + buf[2] = (uint8_t) data; + + spi_write_and_read(spi_ad_desc, buf, 3); + + return(COMMONERR_OK); +} + +commonErr_t CMB_SPIWriteBytes(spiSettings_t *spiSettings, uint16_t *addr, + uint8_t *data, uint32_t count) +{ + uint32_t index; + + for (index = 0; index < count; index++) + if (CMB_SPIWriteByte(spiSettings, *(addr + index), + *(data + index)) != COMMONERR_OK) + return(COMMONERR_FAILED); + + return(COMMONERR_OK); +} + +commonErr_t CMB_SPIReadByte(spiSettings_t *spiSettings, uint16_t addr, + uint8_t *readdata) +{ + uint8_t buf[3]; + + spi_ad_desc->chip_select = spiSettings->chipSelectIndex - 1; + + buf[0] = (uint8_t) ((addr >> 8) | 0x80); + buf[1] = (uint8_t) (addr & 0xff); + buf[2] = (uint8_t) 0x00; + + spi_write_and_read(spi_ad_desc, buf, 3); + *readdata = buf[2]; + + return(COMMONERR_OK); +} + +commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr, + uint8_t field_val, uint8_t mask, uint8_t start_bit) +{ + uint8_t data; + + if (CMB_SPIReadByte(spiSettings, addr, &data) != COMMONERR_OK) + return(COMMONERR_FAILED); + + data = (data & ~mask) | ((field_val << start_bit) & mask); + + if (CMB_SPIWriteByte(spiSettings, addr, data) != COMMONERR_OK) + return(COMMONERR_FAILED); + + return(COMMONERR_OK); +} + +/* read a field in a single register space (not multibyte fields) */ +commonErr_t CMB_SPIReadField(spiSettings_t *spiSettings, uint16_t addr, + uint8_t *field_val, uint8_t mask, uint8_t start_bit) +{ + uint8_t data; + + if (CMB_SPIReadByte(spiSettings, addr, &data) != COMMONERR_OK) + return(COMMONERR_FAILED); + + data = (data & mask) >> start_bit; + *field_val = data; + + return(COMMONERR_OK); +} + + +commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex, + uint32_t errorCode, const char *comment) +{ + + if((CMB_LOGLEVEL & ADIHAL_LOG_ERROR) && (level == ADIHAL_LOG_ERROR)) { + printf("ERROR: %d: %s", (int)errorCode, comment); + } else if((CMB_LOGLEVEL & ADIHAL_LOG_WARNING) + && (level == ADIHAL_LOG_WARNING)) { + printf("WARNING: %d: %s",(int)errorCode, comment); + } else if((CMB_LOGLEVEL & ADIHAL_LOG_MESSAGE) + && (level == ADIHAL_LOG_MESSAGE)) { + printf("MESSAGE: %d: %s",(int)errorCode, comment); + } else if(CMB_LOGLEVEL == ADIHAL_LOG_NONE ) { + //printf("MESSAGE: %d: %s",(int)errorCode, comment); + } else { + printf("Undefined Log Level: 0x%X", level); + } + + return(COMMONERR_OK); +} + +/* if filename null, a default path will be used in logging.c */ +commonErr_t CMB_openLog(const char *filename) +{ + return(COMMONERR_OK); +} + +commonErr_t CMB_closeLog(void) +{ + return(COMMONERR_OK); +} + +commonErr_t CMB_flushLog(void) +{ + return(COMMONERR_OK); +} + +commonErr_t CMB_wait_ms(uint32_t time_ms) +{ + mdelay(time_ms); + + return(COMMONERR_OK); +} + +commonErr_t CMB_wait_us(uint32_t time_us) +{ + udelay(time_us); + + return(COMMONERR_OK); +} + +commonErr_t CMB_setTimeout_ms(uint32_t timeOut_ms) +{ +#ifdef _XPARAMETERS_PS_H_ + _desired_time_to_elapse_us = timeOut_ms * 1000; +#else + _desired_time_to_elapse_us = timeOut_ms * 50; // FIXME +#endif + + return(COMMONERR_OK); +} + +commonErr_t CMB_setTimeout_us(uint32_t timeOut_us) +{ + _desired_time_to_elapse_us = timeOut_us; + + return(COMMONERR_OK); +} + + +commonErr_t CMB_hasTimeoutExpired() +{ + udelay(1); + + _desired_time_to_elapse_us--; + if (_desired_time_to_elapse_us > 0) + return(COMMONERR_OK); + + return(COMMONERR_FAILED); +} + +commonErr_t CMB_regRead(uint32_t offset, uint32_t *data) +{ + return(COMMONERR_OK); +} + +commonErr_t CMB_regWrite(uint32_t offset, uint32_t data) +{ + return(COMMONERR_OK); +} + +commonErr_t CMB_memRead(uint32_t offset, uint32_t *data, uint32_t len) +{ + return(COMMONERR_OK); +} + +commonErr_t CMB_memWrite(uint32_t offset, uint32_t *data, uint32_t len) +{ + return(COMMONERR_OK); +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/common.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/common.h new file mode 100644 index 00000000..785217d1 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/common.h @@ -0,0 +1,131 @@ +/** + * \file common.h + * \brief Contains type definitions and prototype declarations for common.c + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#ifndef _COMMON_H_ +#define _COMMON_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* build project settings include the path to the desired platform folder for correct includes */ +#include "stdint.h" + +#define THROW_ERROR() + +#define SPIARRAYSIZE 1024 + +/* assuming 3 byte SPI message - integer math enforces floor() */ +#define SPIARRAYTRIPSIZE ((SPIARRAYSIZE / 3) * 3) + +/*======================================== + * Enums and structures + *=======================================*/ +/* proposed to increase number of error return values to make unique for each return */ +typedef enum +{ + ADIERR_OK=0, + ADIERR_INV_PARM, + ADIERR_FAILED +} ADI_ERR; + +/*!< \brief COMMON layer error reporting enumerated types */ +typedef enum +{ + COMMONERR_OK=0, + COMMONERR_FAILED +} commonErr_t; + +/* bit 0 is MESSAGE, bit 1 is WARNING, bit 2 is ERROR */ +typedef enum +{ + ADIHAL_LOG_NONE = 0x0, + ADIHAL_LOG_MESSAGE = 0x1, + ADIHAL_LOG_WARNING = 0x2, + ADIHAL_LOG_ERROR = 0x4, + ADIHAL_LOG_SPI = 0x8, + ADIHAL_LOG_AXI_REG = 0x10, + ADIHAL_LOG_AXI_MEM = 0x20, + ADIHAL_LOG_ALL = 0x3F +} ADI_LOGLEVEL; + +/** + * \brief Data structure to hold SPI settings for all system device types + */ +typedef struct +{ + uint8_t chipSelectIndex; ///< valid 1~8 + uint8_t writeBitPolarity; ///< the level of the write bit of a SPI write instruction word, value is inverted for SPI read operation + uint8_t longInstructionWord; ///< 1 = 16bit instruction word, 0 = 8bit instruction word + uint8_t MSBFirst; ///< 1 = MSBFirst, 0 = LSBFirst + uint8_t CPHA; ///< clock phase, sets which clock edge the data updates (valid 0 or 1) + uint8_t CPOL; ///< clock polarity 0 = clock starts low, 1 = clock starts high + uint8_t enSpiStreaming; ///< Not implemented. SW feature to improve SPI throughput. + uint8_t autoIncAddrUp; ///< Not implemented. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr = addr-1 + uint8_t fourWireMode; ///< 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode. + uint32_t spiClkFreq_Hz; ///< SPI Clk frequency in Hz (default 25000000), platform will use next lowest frequency that it's baud rate generator can create */ + +} spiSettings_t; + +/* global variable so application layer can set the log level */ +extern ADI_LOGLEVEL CMB_LOGLEVEL; +extern struct spi_desc *spi_ad_desc; +extern struct gpio_desc *gpio_ad9371_resetb; +extern struct gpio_desc *gpio_ad9528_resetb; +extern struct gpio_desc *gpio_ad9528_sysref_req; + +/* initialize hardware platform */ +commonErr_t CMB_initPlatform(void); + +/* close hardware pointers */ +commonErr_t CMB_closeHardware(void); + +/* GPIO function */ +commonErr_t CMB_setGPIO(uint32_t GPIO); + +/* hardware reset function */ +commonErr_t CMB_hardReset(uint8_t spiChipSelectIndex); + +/* SPI read/write functions */ +commonErr_t CMB_setSPIOptions(spiSettings_t *spiSettings); /* allows the platform HAL to work with devices with various SPI settings */ +commonErr_t CMB_setSPIChannel(uint16_t chipSelectIndex ); /* value of 0 deasserts all chip selects */ +commonErr_t CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr, uint8_t data); /* single SPI byte write function */ +commonErr_t CMB_SPIWriteBytes(spiSettings_t *spiSettings, uint16_t *addr, uint8_t *data, uint32_t count); +commonErr_t CMB_SPIReadByte (spiSettings_t *spiSettings, uint16_t addr, uint8_t *readdata); /* single SPI byte read function */ +commonErr_t CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr, uint8_t field_val, uint8_t mask, uint8_t start_bit); /* write a field in a single register */ +commonErr_t CMB_SPIReadField (spiSettings_t *spiSettings, uint16_t addr, uint8_t *field_val, uint8_t mask, uint8_t start_bit); /* read a field in a single register */ + +/* platform timer functions */ +commonErr_t CMB_wait_ms(uint32_t time_ms); +commonErr_t CMB_wait_us(uint32_t time_us); +commonErr_t CMB_setTimeout_ms(uint32_t timeOut_ms); +commonErr_t CMB_setTimeout_us(uint32_t timeOut_us); +commonErr_t CMB_hasTimeoutExpired(); + +/* platform logging functions */ +commonErr_t CMB_openLog(const char *filename); +commonErr_t CMB_closeLog(void); +commonErr_t CMB_writeToLog(ADI_LOGLEVEL level, uint8_t deviceIndex, uint32_t errorCode, const char *comment); +commonErr_t CMB_flushLog(void); + +/* platform FPGA AXI register read/write functions */ +commonErr_t CMB_regRead(uint32_t offset, uint32_t *data); +commonErr_t CMB_regWrite(uint32_t offset, uint32_t data); + +/* platform DDR3 memory read/write functions */ +commonErr_t CMB_memRead(uint32_t offset, uint32_t *data, uint32_t len); +commonErr_t CMB_memWrite(uint32_t offset, uint32_t *data, uint32_t len); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/headless.c b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/headless.c new file mode 100644 index 00000000..99d82423 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/headless.c @@ -0,0 +1,1140 @@ +/***************************************************************************//** + * @file ad9371/src/app/headless.c + * @brief Implementation of Main Function. +******************************************************************************** + * Copyright 2017(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +/***************************** Include Files ********************************/ +#include "headless.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +//XGpio GpioFreqCtrl; +//XGpio GpioGainCtrl; +//XGpio GpioAttnCtrl; +XScuGic Intc; + +/************************** Function Prototypes ******************************/ + +int HARDWARE_initialize() +{ + int Status; + + // use configuration + mykDevice.rx->rxPllLoFrequency_Hz = 2500000000u; + mykDevice.tx->txPllLoFrequency_Hz = 2500000000u; + mykDevice.tx->tx1Atten_mdB = 20000; + mykDevice.tx->tx2Atten_mdB = 20000; + + Status = HARDWARE_ad9371Config(); + + if (Status != ADIERR_OK){ + return ADIERR_FAILED; + } + +// /**********************************************************/ +// /************ AD9371 Dynamical Reconfiguration ************/ +// /**********************************************************/ +// Status = HW_ad9371DynamicCfgInit(); +// if (Status != ADIERR_OK){ +// xil_printf("HW:: AD9371 dynamic configuration initialization failed!\n"); +// return ADIERR_FAILED; +// } +// +// xil_printf("HW:: AD9371 ready to be reconfigured!\n"); +// +// // main loop +// while(1); + + // never reach + return ADIERR_OK; +} + +// this function is NOT safe +int HARDWARE_ad9371Config(void) +{ + int Status; + uint8_t reg508; + uint8_t framerStatus; + uint8_t obsFramerStatus; + uint8_t deframerStatus; + + xil_printf("main: Hello\n"); + + /**********************************************************/ + /*********** Initialize Configuration Interface ***********/ + /**********************************************************/ + Status = CMB_initPlatform(); + if (Status != ADIERR_OK){ + return ADIERR_FAILED; + } + + Status = HW_adiCfgProfileInit(); + if (Status != ADIERR_OK){ + return ADIERR_FAILED; + } + + xil_printf("HW:: Initialize configuration interface done!\n"); + + /**********************************************************/ + /****************** AD9528 Configuration ******************/ + /**********************************************************/ + Status = HW_9528Config(ad9528Init); + if (Status != ADIERR_OK){ + return ADIERR_FAILED; + } + + xil_printf("HW:: AD9528 configuration done!\n"); + + Status = HW_9528GetLockStatus(ad9528Init, ®508); + if (Status != ADIERR_OK){ + return ADIERR_FAILED; + } + + xil_printf("HW:: AD9528 REG508: 0x%02x \n",reg508); + + /**********************************************************/ + /****************** AD9371 Configuration ******************/ + /**********************************************************/ + Status = HW_9371Config(ad9528Init, &mykDevice); + if (Status != ADIERR_OK){ + return ADIERR_FAILED; + } + + Status = HW_9371CheckJesdStatus(&mykDevice, &framerStatus, + &obsFramerStatus, &deframerStatus); + if (Status != ADIERR_OK){ + return ADIERR_FAILED; + } + else { + // typical value: 0x3E + printf("HW:: RxFramerStatus = 0x%x\n", framerStatus); + // typical value: 0x3E + printf("HW:: OrxFramerStatus = 0x%x\n", obsFramerStatus); + // typical value: 0x28 + printf("HW:: DeframerStatus = 0x%x\n", deframerStatus); + } + + xil_printf("HW:: All configuration done!\n"); + + return ADIERR_OK; +} + +// this function is NOT safe +//int HW_ad9371DynamicCfgInit(void) +//{ +// int Status; +// +// Status = HW_setupIntrSystem(INTC_DEVICE_ID, &Intc); +// if (Status != XST_SUCCESS) { +// printf("HW: HW_setupIntrSystem() failed!\n"); +// return XST_FAILURE; +// } +// +// Status = XGpio_Initialize(&GpioFreqCtrl, FREQ_CTRL_DEVICE_ID); +// Status |= XGpio_Initialize(&GpioGainCtrl, GAIN_CTRL_DEVICE_ID); +// Status |= XGpio_Initialize(&GpioAttnCtrl, ATTN_CTRL_DEVICE_ID); +// if (Status != XST_SUCCESS) { +// printf("HW: GPIO init failed!\n"); +// return XST_FAILURE; +// } +// +// /* Set the direction for all signals as inputs. */ +// XGpio_SetDataDirection(&GpioFreqCtrl, AXI_GPIO_BANK_1, 0xFFFFFFFF); +// XGpio_SetDataDirection(&GpioFreqCtrl, AXI_GPIO_BANK_2, 0xFFFFFFFF); +// +// XGpio_SetDataDirection(&GpioGainCtrl, AXI_GPIO_BANK_1, 0xFFFFFFFF); +// XGpio_SetDataDirection(&GpioGainCtrl, AXI_GPIO_BANK_2, 0xFFFFFFFF); +// +// XGpio_SetDataDirection(&GpioAttnCtrl, AXI_GPIO_BANK_1, 0xFFFFFFFF); +// XGpio_SetDataDirection(&GpioAttnCtrl, AXI_GPIO_BANK_2, 0xFFFFFFFF); +// +// Status = HW_connectIntr(&Intc, FREQ_CTRL_INTR_ID, +// (Xil_InterruptHandler)FreqIntrHandler, &GpioFreqCtrl, 0xA0, 0x3); +// Status |= HW_connectIntr(&Intc, GAIN_CTRL_INTR_ID, +// (Xil_InterruptHandler)GainIntrHandler, &GpioGainCtrl, 0xA0, 0x3); +// Status |= HW_connectIntr(&Intc, ATTN_CTRL_INTR_ID, +// (Xil_InterruptHandler)AttnIntrHandler, &GpioAttnCtrl, 0xA0, 0x3); +// +// XGpio_InterruptEnable(&GpioFreqCtrl, XGPIO_IR_MASK); +// XGpio_InterruptGlobalEnable(&GpioFreqCtrl); +// +// XGpio_InterruptEnable(&GpioGainCtrl, XGPIO_IR_MASK); +// XGpio_InterruptGlobalEnable(&GpioGainCtrl); +// +// XGpio_InterruptEnable(&GpioAttnCtrl, XGPIO_IR_MASK); +// XGpio_InterruptGlobalEnable(&GpioAttnCtrl); +// +// return XST_SUCCESS; +//} + +/*****************************************************************************/ +/* +* +* This function setups the interrupt system. +* +* @param DeviceId is the unique identifier for a GIC device. +* @param GicPtr is a pointer to the instance of the INTC. +* +* @return +* - XST_SUCCESS if successful, +* - XST_FAILURE.if not succesful +* +* @note None. +* +******************************************************************************/ +int HW_setupIntrSystem(u16 DeviceId, XScuGic * GicPtr) +{ + int Status; + XScuGic_Config *CfgPtr; + + /* + * Initialize the interrupt controller driver so that it is ready to + * use. + */ + CfgPtr = XScuGic_LookupConfig(DeviceId); + if (!CfgPtr) { + xil_printf("No interrupt config found for %d\r\n", DeviceId); + return XST_FAILURE; + } + + Status = XScuGic_CfgInitialize(GicPtr, CfgPtr, CfgPtr->CpuBaseAddress); + if (Status != XST_SUCCESS) { + xil_printf("No interrupt config found for %d\r\n", DeviceId); + return XST_FAILURE; + } + + Xil_ExceptionInit(); + Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, + (Xil_ExceptionHandler)XScuGic_InterruptHandler, + (void *)GicPtr); + Xil_ExceptionEnable(); + + return XST_SUCCESS; +} + + +int HW_connectIntr(XScuGic *GicPtr,u32 IntrId,Xil_InterruptHandler Handler, + void *CallBackRef, u8 Priority, u8 Trigger) +{ + int Status; + // Register interrupt handler + Status = XScuGic_Connect(GicPtr, IntrId, (Xil_InterruptHandler)Handler, + CallBackRef); + if(Status != XST_SUCCESS) + { + return XST_FAILURE; + } + XScuGic_SetPriorityTriggerType(GicPtr, IntrId, Priority, Trigger); + + XScuGic_Enable(GicPtr, IntrId); + + return XST_SUCCESS; +} + + +int HW_adiCfgProfileInit(void) +{ + if (!ad9528Init) { + printf("Cannot find ad9528 configuration profile with name 'ad9528Init'!"); + return ADIERR_FAILED; + } + + if (!&mykDevice) { + printf("Cannot find ad9371 configuration profile with name 'mykDevice'!"); + return ADIERR_FAILED; + } + + ad9528Init->spiSettings->chipSelectIndex = AD9528_CS; + mykDevice.spiSettings->chipSelectIndex = AD9371_CS; + + mykDevice.rx->framer->serializerLanesEnabled = 0x03; + mykDevice.rx->framer->serializerLaneCrossbar = 0xE4; + mykDevice.obsRx->framer->serializerLanesEnabled = 0x04; + mykDevice.tx->deframer->deserializerLanesEnabled = 0x03; + mykDevice.tx->deframer->deserializerLaneCrossbar = 0xE4; + + return ADIERR_OK; +} + + +int HW_9528Config(ad9528Device_t *clockAD9528_device) +{ + ADI_ERR error; + /**************************************************************************/ + /***** System Clocks Initialization Initialization Sequence *****/ + /**************************************************************************/ + + /* Perform a hard reset on the AD9528 DUT */ + error = AD9528_resetDevice(clockAD9528_device); + if (error != ADIERR_OK) { + printf("AD9528_resetDevice() failed\n"); + return ADIERR_FAILED; + } + + error = AD9528_initDeviceDataStruct(clockAD9528_device, + clockAD9528_device->pll1Settings->vcxo_Frequency_Hz, + clockAD9528_device->pll1Settings->refA_Frequency_Hz, + clockAD9528_device->outputSettings->outFrequency_Hz[1]); + if (error != ADIERR_OK) { + printf("AD9528_initDeviceDataStruct() failed\n"); + return ADIERR_FAILED; + } + + /* Initialize the AD9528 by writing all SPI registers */ + error = AD9528_initialize(clockAD9528_device); + if (error != ADIERR_OK) { + printf("WARNING: AD9528_initialize() issues.\n"); + } + + return ADIERR_OK; +} + + +int HW_9528GetLockStatus(ad9528Device_t *device, uint8_t *reg508) +{ + ADI_ERR error; + + error = CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, reg508); + if (error != ADIERR_OK) { + printf("HW_9528GetLockStatus failed.\n"); + return ADIERR_FAILED; + } + + return ADIERR_OK; +} + + +int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice) +{ + ADI_ERR error; + mykonosErr_t mykError; + const char *errorString; + uint8_t pllLockStatus; + uint8_t mcsStatus; + uint8_t arm_major; + uint8_t arm_minor; + uint8_t arm_release; + uint32_t initCalMask = TX_BB_FILTER | ADC_TUNER | TIA_3DB_CORNER | DC_OFFSET | + TX_ATTENUATION_DELAY | RX_GAIN_DELAY | FLASH_CAL | + PATH_DELAY | TX_LO_LEAKAGE_INTERNAL | TX_QEC_INIT | + LOOPBACK_RX_LO_DELAY | LOOPBACK_RX_RX_QEC_INIT | + RX_LO_DELAY | RX_QEC_INIT ; + uint8_t errorFlag = 0; + uint8_t errorCode = 0; + uint32_t initCalsCompleted; + uint32_t trackingCalMask = TRACK_ORX1_QEC | TRACK_ORX2_QEC | TRACK_RX1_QEC | + TRACK_RX2_QEC | TRACK_TX1_QEC | TRACK_TX2_QEC; + + /* Allocating memory for the errorString */ + errorString = NULL; + + + + /*************************************************************************/ + /***** Mykonos Initialization Sequence *****/ + /*************************************************************************/ + + /* Perform a hard reset on the MYKONOS DUT (Toggle RESETB pin on device) */ + if ((mykError = MYKONOS_resetDevice(mykDevice)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + if ((mykError = MYKONOS_initialize(mykDevice)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + /*************************************************************************/ + /***** Mykonos CLKPLL Status Check *****/ + /*************************************************************************/ + + if ((mykError = MYKONOS_checkPllsLockStatus(mykDevice, + &pllLockStatus)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + /*************************************************************************/ + /***** Mykonos Perform MultiChip Sync *****/ + /*************************************************************************/ + + if ((mykError = MYKONOS_enableMultichipSync(mykDevice, 1, + &mcsStatus)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + /* Minimum 3 SYSREF pulses from Clock Device has to be produced for MulticChip Sync */ + + AD9528_requestSysref(clockAD9528_device, 1); + mdelay(1); + AD9528_requestSysref(clockAD9528_device, 1); + mdelay(1); + AD9528_requestSysref(clockAD9528_device, 1); + mdelay(1); + AD9528_requestSysref(clockAD9528_device, 1); + mdelay(1); + + /*************************************************************************/ + /***** Mykonos Verify MultiChip Sync *****/ + /*************************************************************************/ + + if ((mykError = MYKONOS_enableMultichipSync(mykDevice, 0, + &mcsStatus)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + if ((mcsStatus & 0x0B) == 0x0B) + printf("MCS successful\n"); + else + printf("MCS failed\n"); + + /*************************************************************************/ + /***** Mykonos Load ARM file *****/ + /*************************************************************************/ + + if (pllLockStatus & 0x01) { + printf("CLKPLL locked\n"); + if ((mykError = MYKONOS_initArm(mykDevice)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + if ((mykError = MYKONOS_loadArmFromBinary(mykDevice, + &firmware_Mykonos_M3_bin[0], firmware_Mykonos_M3_bin_len)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + } else { + printf("CLKPLL not locked (0x%x)\n", pllLockStatus); + error = ADIERR_FAILED; + goto error_2; + } + + /* Read back the version of the ARM binary loaded into the Mykonos ARM memory */ + if ((mykError = MYKONOS_getArmVersion(mykDevice, &arm_major, &arm_minor, + &arm_release, NULL)) == MYKONOS_ERR_OK) + printf("AD9371 ARM version %d.%d.%d\n", arm_major, arm_minor, arm_release); + + /*************************************************************************/ + /***** Mykonos Set RF PLL Frequencies *****/ + /*************************************************************************/ + + if ((mykError = MYKONOS_setRfPllFrequency(mykDevice, RX_PLL, + mykDevice->rx->rxPllLoFrequency_Hz)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + if ((mykError = MYKONOS_setRfPllFrequency(mykDevice, TX_PLL, + mykDevice->tx->txPllLoFrequency_Hz)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + if ((mykError = MYKONOS_setRfPllFrequency(mykDevice, SNIFFER_PLL, + mykDevice->obsRx->snifferPllLoFrequency_Hz)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + /* Wait 200ms for PLLs to lock */ + mdelay(200); + + if ((mykError = MYKONOS_checkPllsLockStatus(mykDevice, + &pllLockStatus)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + if ((pllLockStatus & 0x0F) == 0x0F) + printf("PLLs locked\n"); + else { + printf("PLLs not locked (0x%x)\n", pllLockStatus); + error = ADIERR_FAILED; + goto error_2; + } + +// /*************************************************************************/ +// /***** Mykonos Set GPIOs *****/ +// /*************************************************************************/ +// +// if ((mykGpioErr = MYKONOS_setRx1GainCtrlPin(mykDevice, 0, 0, 0, 0, +// 0)) != MYKONOS_ERR_GPIO_OK) { +// errorString = getGpioMykonosErrorMessage(mykGpioErr); +// goto error_11; +// } +// +// if ((mykGpioErr = MYKONOS_setRx2GainCtrlPin(mykDevice, 0, 0, 0, 0, +// 0)) != MYKONOS_ERR_GPIO_OK) { +// errorString = getGpioMykonosErrorMessage(mykGpioErr); +// goto error_11; +// } +// +// if ((mykGpioErr = MYKONOS_setTx1AttenCtrlPin(mykDevice, 0, 0, 0, 0, +// 0)) != MYKONOS_ERR_GPIO_OK) { +// errorString = getGpioMykonosErrorMessage(mykGpioErr); +// goto error_11; +// } +// +// if ((mykGpioErr = MYKONOS_setTx2AttenCtrlPin(mykDevice, 0, 0, 0, +// 0)) != MYKONOS_ERR_GPIO_OK) { +// errorString = getGpioMykonosErrorMessage(mykGpioErr); +// goto error_11; +// } +// +// if ((mykGpioErr = MYKONOS_setupGpio(mykDevice)) != MYKONOS_ERR_GPIO_OK) { +// errorString = getGpioMykonosErrorMessage(mykGpioErr); +// goto error_11; +// } +// +// /*************************************************************************/ +// /***** Mykonos Set manual gains values *****/ +// /*************************************************************************/ +// +// if ((mykError = MYKONOS_setRx1ManualGain(mykDevice, 255)) != MYKONOS_ERR_OK) { +// errorString = getMykonosErrorMessage(mykError); +// goto error_11; +// } +// +// if ((mykError = MYKONOS_setRx2ManualGain(mykDevice, 255)) != MYKONOS_ERR_OK) { +// errorString = getMykonosErrorMessage(mykError); +// goto error_11; +// } +// +// if ((mykError = MYKONOS_setObsRxManualGain(mykDevice, OBS_RX1_TXLO, +// 255)) != MYKONOS_ERR_OK) { +// errorString = getMykonosErrorMessage(mykError); +// goto error_11; +// } +// +// if ((mykError = MYKONOS_setObsRxManualGain(mykDevice, OBS_RX2_TXLO, +// 255)) != MYKONOS_ERR_OK) { +// errorString = getMykonosErrorMessage(mykError); +// goto error_11; +// } +// +// if ((mykError = MYKONOS_setObsRxManualGain(mykDevice, OBS_SNIFFER_A, +// 255)) != MYKONOS_ERR_OK) { +// errorString = getMykonosErrorMessage(mykError); +// goto error_11; +// } +// +// if ((mykError = MYKONOS_setObsRxManualGain(mykDevice, OBS_SNIFFER_B, +// 255)) != MYKONOS_ERR_OK) { +// errorString = getMykonosErrorMessage(mykError); +// goto error_11; +// } +// +// if ((mykError = MYKONOS_setObsRxManualGain(mykDevice, OBS_SNIFFER_C, +// 255)) != MYKONOS_ERR_OK) { +// errorString = getMykonosErrorMessage(mykError); +// goto error_11; +// } +// +// /*************************************************************************/ +// /***** Mykonos Initialize attenuations *****/ +// /*************************************************************************/ +// +// mykError = MYKONOS_setTx1Attenuation(mykDevice, 10000); +// if (mykError != MYKONOS_ERR_OK) { +// errorString = getMykonosErrorMessage(mykError); +// goto error_11; +// } +// +// mykError = MYKONOS_setTx2Attenuation(mykDevice, 10000); +// if (mykError != MYKONOS_ERR_OK) { +// errorString = getMykonosErrorMessage(mykError); +// goto error_11; +// } + + /*************************************************************************/ + /***** Mykonos ARM Initialization Calibrations *****/ + /*************************************************************************/ + + if ((mykError = MYKONOS_runInitCals(mykDevice, + (initCalMask & ~TX_LO_LEAKAGE_EXTERNAL))) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + if ((mykError = MYKONOS_waitInitCals(mykDevice, 60000, &errorFlag, + &errorCode)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + if ((errorFlag != 0) || (errorCode != 0)) { + /*** < Info: abort init cals > ***/ + if ((mykError = MYKONOS_abortInitCals(mykDevice, + &initCalsCompleted)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + if (initCalsCompleted) + printf("Completed calibrations: %x\n", (unsigned int)initCalsCompleted); + } else + printf("Calibrations completed successfully\n"); + + /*************************************************************************/ + /***** Mykonos ARM Initialization External LOL Calibrations with PA *****/ + /*************************************************************************/ + + /* Please ensure PA is enabled operational at this time */ + if (initCalMask & TX_LO_LEAKAGE_EXTERNAL) { + if ((mykError = MYKONOS_runInitCals(mykDevice, + TX_LO_LEAKAGE_EXTERNAL)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + if ((mykError = MYKONOS_waitInitCals(mykDevice, 60000, &errorFlag, + &errorCode)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + if ((errorFlag != 0) || (errorCode != 0)) { + /*** < Info: abort init cals > ***/ + if ((mykError = MYKONOS_abortInitCals(mykDevice, + &initCalsCompleted)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + } else + printf("External LOL Calibrations completed successfully\n"); + } + + /*************************************************************************/ + /***** SYSTEM JESD bring up procedure *****/ + /*************************************************************************/ + + if ((mykError = MYKONOS_enableSysrefToRxFramer(mykDevice, + 1)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + /*** < Info: Mykonos is waiting for sysref in order to start + * transmitting CGS from the RxFramer> ***/ + + if ((mykError = MYKONOS_enableSysrefToObsRxFramer(mykDevice, + 1)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + /*** < Info: Mykonos is waiting for sysref in order to start + * transmitting CGS from the ObsRxFramer> ***/ + + if ((mykError = MYKONOS_enableSysrefToDeframer(mykDevice, + 0)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + if ((mykError = MYKONOS_resetDeframer(mykDevice)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + if ((mykError = MYKONOS_enableSysrefToDeframer(mykDevice, + 1)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + /*************************************************************************/ + /***** Enable SYSREF to Mykonos and BBIC *****/ + /*************************************************************************/ + + /* Request a SYSREF from the AD9528 */ + AD9528_requestSysref(clockAD9528_device, 1); + mdelay(1); + + /*** < Info: Mykonos is actively transmitting CGS from the RxFramer> ***/ + + /*** < Info: Mykonos is actively transmitting CGS from the ObsRxFramer> ***/ + + /* Request two SYSREFs from the AD9528 */ + AD9528_requestSysref(clockAD9528_device, 1); + mdelay(1); + AD9528_requestSysref(clockAD9528_device, 1); + mdelay(5); + + /*************************************************************************/ + /***** Mykonos enable tracking calibrations *****/ + /*************************************************************************/ + + if ((mykError = MYKONOS_enableTrackingCals(mykDevice, + trackingCalMask)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + /*** < Info: Allow Rx1/2 QEC tracking and Tx1/2 QEC tracking to run when in the radioOn state + * Tx calibrations will only run if radioOn and the obsRx path is set to OBS_INTERNAL_CALS > ***/ + + /*** < Info: Function to turn radio on, Enables transmitters and receivers + * that were setup during MYKONOS_initialize() > ***/ + if ((mykError = MYKONOS_radioOn(mykDevice)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + /*** < Info: Allow TxQEC to run when User: is not actively using ORx receive path > ***/ + if ((mykError = MYKONOS_setObsRxPathSource(mykDevice, + OBS_RXOFF)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + if ((mykError = MYKONOS_setObsRxPathSource(mykDevice, + OBS_INTERNALCALS)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + mdelay(1000); + + if ((mykError = MYKONOS_setObsRxPathSource(mykDevice, + OBS_RX1_SNIFFERLO)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + goto error_11; + } + + Xil_DCacheInvalidateRange(DDR_MEM_BASEADDR + 0x800000, 16384 * 8); + + printf("Done\n"); + + return 0; + +error_11: + printf("%s", errorString); + +error_2: +// axi_clkgen_remove(rx_clkgen); + return FAILURE; +} + + +int HW_9371CheckJesdStatus(mykonosDevice_t *mykDevice, uint8_t *framerStatus, + uint8_t *obsFramerStatus, uint8_t *deframerStatus) +{ + mykonosErr_t mykError; + const char *errorString; + /* Allocating memory for the errorString */ + errorString = NULL; + + /*************************************************************************/ + /***** Check Mykonos Framer Status *****/ + /*************************************************************************/ + + if ((mykError = MYKONOS_readRxFramerStatus(mykDevice, + framerStatus)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + return ADIERR_FAILED; + } + else { + // typical value: 0x3E + } + + if ((mykError = MYKONOS_readOrxFramerStatus(mykDevice, + obsFramerStatus)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + return ADIERR_FAILED; + } else { + // typical value: 0x3E + } + + /*************************************************************************/ + /***** Check Mykonos Deframer Status *****/ + /*************************************************************************/ + + if ((mykError = MYKONOS_readDeframerStatus(mykDevice, + deframerStatus)) != MYKONOS_ERR_OK) { + errorString = getMykonosErrorMessage(mykError); + return ADIERR_FAILED; + } else { + // typical value: 0x28 + } + + return ADIERR_OK; +} + + +int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz) +{ + mykonosErr_t mykError = MYKONOS_ERR_OK; + uint8_t pllLockStatus = 0; + /* + * Move the device into the radio off state. + */ + if((mykError = MYKONOS_radioOff(mykDevice)) != MYKONOS_ERR_OK) + { + xil_printf("Turn radio off failed!\n\r"); + return ADIERR_FAILED; + } + + /* + * Program the new local oscillator (LO) frequency. Check if PLL is locked. + */ + if((mykError = MYKONOS_setRfPllFrequency(mykDevice, TX_PLL, + freq_Hz)) != MYKONOS_ERR_OK) + { + xil_printf("Set TX PLL failed!\n\r"); + return ADIERR_FAILED; + } + mykError = MYKONOS_checkPllsLockStatus(mykDevice, &pllLockStatus); + if ((pllLockStatus & 0x07) != 0x07) + { + /*** < Info: Clock, Rx and Tx PLLs not locked > ***/ + xil_printf("Not all PLLs locked, lock status: 0x%02x\n", pllLockStatus); + } + + /* + * Reset the external channel. + */ +// If((mykError = MYKONOS_resetExtTxLolChannel(mykDevice, TX1_TX2)) +// != MYKONOS_ERR_OK) ; //where TX1_TX2 is part of the enum mykonosTxChannels_t +// { +// xil_printf("Reset external channel FAILED!"); +// } + + /* + * Move the device back into the radio on state. + */ + if ((mykError = MYKONOS_radioOn(mykDevice)) != MYKONOS_ERR_OK) + { + xil_printf("Turn radio on failed!\n\r"); + return ADIERR_FAILED; + } + + /* + * Reenable tracking calibrations. + */ +// If((mykError = MYKONOS_MYKONOS_setObsRxPathSource(mykDevice, OBS_INTERNALCALS)) +// != MYKONOS_ERR_OK) ; //where TX1_TX2 is part of the enum mykonosTxChannels_t +// { +// xil_printf("Reenable tracking calibrations FAILED!"); +// } + return ADIERR_OK; +} + + +int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz) +{ + mykonosErr_t mykError = MYKONOS_ERR_OK; + uint8_t pllLockStatus = 0; + uint8_t errorFlag = 0; + uint8_t errorCode = 0; + uint32_t initCalsCompleted = 0; + uint16_t errorWord = 0; + uint16_t statusWord = 0; + uint8_t status = 0; + mykonosInitCalStatus_t initCalStatus = {0}; + + /* + * Move the device into the radio off state. + */ + if((mykError = MYKONOS_radioOff(mykDevice)) != MYKONOS_ERR_OK) + { + xil_printf("Turn radio off failed!\n\r"); + return ADIERR_FAILED; + } + + /* + * Program the new local oscillator (LO) frequency. Check if PLL is locked. + */ + if((mykError = MYKONOS_setRfPllFrequency(mykDevice, TX_PLL, + freq_Hz)) != MYKONOS_ERR_OK) + { + printf("Set TX PLL failed!\n\r"); + return ADIERR_FAILED; + } + mykError = MYKONOS_checkPllsLockStatus(mykDevice, &pllLockStatus); + if ((pllLockStatus & 0x07) != 0x07) + { + /*** < Info: Clock, Rx and Tx PLLs not locked > ***/ + xil_printf("Not all PLLs locked, lock status: 0x%02x\n", pllLockStatus); + } + + /* + * Rerun the initialization calibrations. + */ + uint32_t initCalMask = TX_QEC_INIT | LOOPBACK_RX_LO_DELAY | + LOOPBACK_RX_RX_QEC_INIT | RX_LO_DELAY | RX_QEC_INIT; + if ((mykError = MYKONOS_runInitCals(mykDevice, initCalMask)) + != MYKONOS_ERR_OK) + { + printf("Rerun the initialization calibrations FAILED!"); + return ADIERR_FAILED; + } + if ((mykError = MYKONOS_waitInitCals(mykDevice, 60000, &errorFlag, + &errorCode)) != MYKONOS_ERR_OK) + { + printf("Initialize calibration TIME OUT!"); + return ADIERR_FAILED; + } + if ((errorFlag != 0) || (errorCode != 0)) + { + printf("initial cals error!\n\r"); + + if((mykError = MYKONOS_getInitCalStatus(mykDevice, &initCalStatus)) + != MYKONOS_ERR_OK) + { + /*** < User log error return value to debug why init failed > ***/ + } + + //abort init calibrations + if((mykError = MYKONOS_abortInitCals(mykDevice, &initCalsCompleted)) + != MYKONOS_ERR_OK) + { + /*** < User log error return value to debug why init failed > ***/ + + } + if(initCalsCompleted) + { + /*** < which calls had completed, per the mask > ***/ + } + if((mykError = MYKONOS_readArmCmdStatus(mykDevice, &errorWord, + &statusWord)) != MYKONOS_ERR_OK) + { + /*** < User log error return value to debug why init failed > ***/ + } + if((mykError = MYKONOS_readArmCmdStatusByte(mykDevice, 2, &status)) + != MYKONOS_ERR_OK) + { + + } + if(status!=0) + { + /*** < Arm Mailbox Status Error errorWord > ***/ + /*** < Pending Flag per opcode statusWord, this follows the mask > ***/ + } + } + + /* + * Move the device back into the radio on state. + */ + if ((mykError = MYKONOS_radioOn(mykDevice)) != MYKONOS_ERR_OK) + { + xil_printf("Turn radio on failed!\n\r"); + return ADIERR_FAILED; + } + + return ADIERR_OK; +} + + +//void FreqIntrHandler(void *CallbackRef) +//{ +// XGpio *GpioPtr = (XGpio *)CallbackRef; +// uint8_t IntrStatus; +// uint32_t NewFreqHz; +// IntrStatus = XGpio_InterruptGetStatus(GpioPtr); +// +// if (IntrStatus & XGPIO_IR_CH1_MASK) +// { +// /* Clear the Interrupt */ +// XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH1_MASK); +// +// NewFreqHz = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_1); +// if (NewFreqHz != mykDevice.tx->txPllLoFrequency_Hz) +// { +// if (NewFreqHz > 300000000 && NewFreqHz < 6000000000) +// { +// if (abs(NewFreqHz - mykDevice.tx->txPllLoFrequency_Hz) <= 100000000) +// { +// HW_9371SmallFrequencyChange(&mykDevice, NewFreqHz); +// } +// else +// { +// HW_9371LargeFrequencyChange(&mykDevice, NewFreqHz); +// } +// mykDevice.tx->txPllLoFrequency_Hz = NewFreqHz; +// printf("New Tx frequency set to %ld Hz!\n",NewFreqHz); +// } +// else +// { +// printf("The desired Tx Frequency is out of range(300 ~ 6000 MHz)!\n"); +// } +// } +// } +// +// if (IntrStatus & XGPIO_IR_CH2_MASK) +// { +// /* Clear the Interrupt */ +// XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH2_MASK); +// +// NewFreqHz = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_2); +// if (NewFreqHz != mykDevice.rx->rxPllLoFrequency_Hz) +// { +// if (NewFreqHz > 300000000 && NewFreqHz < 6000000000) +// { +// if (abs(NewFreqHz - mykDevice.rx->rxPllLoFrequency_Hz) <= 100000000) +// { +// HW_9371SmallFrequencyChange(&mykDevice, NewFreqHz); +// } +// else +// { +// HW_9371LargeFrequencyChange(&mykDevice, NewFreqHz); +// } +// mykDevice.rx->rxPllLoFrequency_Hz = NewFreqHz; +// printf("New Rx frequency set to %ld Hz!\n",NewFreqHz); +// } +// else +// { +// printf("The desired Rx Frequency is out of range(300 ~ 6000 MHz)!\n"); +// } +// } +// } +//} +// +// +//void GainIntrHandler(void *CallbackRef) +//{ +// XGpio *GpioPtr = (XGpio *)CallbackRef; +// uint8_t IntrStatus; +// uint32_t NewRxGain; +// IntrStatus = XGpio_InterruptGetStatus(GpioPtr); +// +// if (IntrStatus & XGPIO_IR_CH1_MASK) +// { +// /* Clear the Interrupt */ +// XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH1_MASK); +// +// NewRxGain = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_1); +// if (NewRxGain != mykDevice.rx->rxGainCtrl->rx1GainIndex) +// { +// if ((NewRxGain >= 195) && (NewRxGain <= 255)) +// { +// MYKONOS_setRx1ManualGain(&mykDevice, NewRxGain); +// mykDevice.rx->rxGainCtrl->rx1GainIndex = NewRxGain; +// char buf[BUFSIZ]; +// sprintf(buf, "%u", NewRxGain); +// printf("New Rx1 gain index set to %s!\n",buf); +// } +// else +// { +// printf("The desired Rx1 gain index is out of range(195 ~ 255), 0.5dB per stage!\n"); +// } +// } +// } +// +// if (IntrStatus & XGPIO_IR_CH2_MASK) +// { +// /* Clear the Interrupt */ +// XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH2_MASK); +// +// NewRxGain = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_2); +// if (NewRxGain != mykDevice.rx->rxGainCtrl->rx2GainIndex) +// { +// if ((NewRxGain >= 195) && (NewRxGain <= 255)) +// { +// MYKONOS_setRx2ManualGain(&mykDevice, NewRxGain); +// mykDevice.rx->rxGainCtrl->rx2GainIndex = NewRxGain; +// char buf[BUFSIZ]; +// sprintf(buf, "%u", NewRxGain); +// printf("New Rx2 gain index set to %s!\n",buf); +// } +// else +// { +// printf("The desired Rx2 gain index is out of range(195 ~ 255), 0.5dB per stage!\n"); +// } +// } +// } +//} +// +// +//void AttnIntrHandler(void *CallbackRef) +//{ +// XGpio *GpioPtr = (XGpio *)CallbackRef; +// uint8_t IntrStatus; +// uint32_t NewTxAttn; +// IntrStatus = XGpio_InterruptGetStatus(GpioPtr); +// +// if (IntrStatus & XGPIO_IR_CH1_MASK) +// { +// /* Clear the Interrupt */ +// XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH1_MASK); +// +// NewTxAttn = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_1); +// if (NewTxAttn != mykDevice.tx->tx1Atten_mdB) +// { +// if ((NewTxAttn >= 0) && (NewTxAttn <= 41950)) +// { +// MYKONOS_setTx1Attenuation(&mykDevice, NewTxAttn); +// mykDevice.tx->tx1Atten_mdB = NewTxAttn; +// char buf[BUFSIZ]; +// sprintf(buf, "%u", NewTxAttn); +// printf("New Tx1 attenuation set to %s dBm!\n",buf); +// } +// else +// { +// printf("The desired Tx1 attenuation is out of range(0 ~ 41950 dBm), 50 dBm step!\n"); +// } +// } +// } +// +// if (IntrStatus & XGPIO_IR_CH2_MASK) +// { +// /* Clear the Interrupt */ +// XGpio_InterruptClear(GpioPtr, XGPIO_IR_CH2_MASK); +// +// NewTxAttn = XGpio_DiscreteRead(GpioPtr, AXI_GPIO_BANK_2); +// if (NewTxAttn != mykDevice.tx->tx2Atten_mdB) +// { +// if ((NewTxAttn >= 0) && (NewTxAttn <= 41950)) +// { +// MYKONOS_setTx2Attenuation(&mykDevice, NewTxAttn); +// mykDevice.tx->tx2Atten_mdB = NewTxAttn; +// char buf[BUFSIZ]; +// sprintf(buf, "%u", NewTxAttn); +// printf("New Tx2 attenuation set to %s dBm!\n",buf); +// } +// else +// { +// printf("The desired Tx2 attenuation is out of range(0 ~ 41950 dBm), 50 dBm step!\n"); +// } +// } +// } +//} diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/headless.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/headless.h new file mode 100644 index 00000000..41efed43 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/headless.h @@ -0,0 +1,348 @@ +/* + * headless.h + * + * Created on: 202168 + * Author: Josh + */ + +#ifndef SRC_HEADLESS_H_ +#define SRC_HEADLESS_H_ + +/***************************** Include Files ********************************/ +#include +#include +#include "xil_cache.h" +#include "xscugic.h" +//#include "xgpio.h" + +#include "common.h" +#include "./mykonos/ad9528.h" +#include "./mykonos/mykonos.h" +#include "./mykonos/Mykonos_M3.h" +#include "./mykonos/mykonos_gpio.h" +#include "myk_ad9528init.h" +#include "myk_init.h" + +#include "parameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/* +* +* This function setups ad9528 and ad9371 via spi. +* +* @param None. +* +* @return +* - ADIERR_FAILED if successful, +* - ADIERR_OK if not succesful +* +* @note None. +* +******************************************************************************/ +int HARDWARE_initialize(); + +int HARDWARE_ad9371Config(void); + +/*****************************************************************************/ +/* +* +* Setup up Axi Gpio, through which ad9371 can be reconfigured. Axi Gpio +* instance and interrupt system initialization are included. +* +* @param None. +* +* @return +* - ADIERR_FAILED if successful, +* - ADIERR_OK if not succesful +* +* @note None. +* +******************************************************************************/ +int HW_ad9371DynamicCfgInit(void); + +/*****************************************************************************/ +/* +* +* Setup up interrupt system, initialize exception handlers. +* +* @param DeviceId is the unique identifier for a device. +* @param GicPtr is a pointer to the XScuGic instance. +* +* @return +* - XST_SUCCESS if successful, +* - XST_FAILURE if not succesful +* +* @note None. +* +******************************************************************************/ +int HW_setupIntrSystem(u16 DeviceId, XScuGic * GicPtr); + +/*****************************************************************************/ +/* +* +* Make the connection between the Int_Id of the interrupt source and the +* associated handler. Set the interrupt priority and trigger type for the +* specified IRQ source.. +* +* @param GicPtr is a pointer to the XScuGic instance. +* @param Int_Id contains the ID of the interrupt source and should be +* in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1 +* @param Handler to the handler for that interrupt. +* @param CallBackRef is the callback reference, usually the instance +* pointer of the connecting driver. +* @param Priority is the new priority for the IRQ source. 0 is highest +* priority, 0xF8(248) is lowest. There are 32 priority levels +* supported with a step of 8. Hence the supported priorities are +* 0, 8, 16, 32, 40 ..., 248. +* @param Trigger is the new trigger type for the IRQ source. +* Each bit pair describes the configuration for an INT_ID. +* SFI Read Only b10 always +* PPI Read Only depending on how the PPIs are configured. +* b01 Active HIGH level sensitive +* b11 Rising edge sensitive +* SPI LSB is read only. +* b01 Active HIGH level sensitive +* b11 Rising edge sensitive/ +* +* @return +* - XST_SUCCESS if successful, +* - XST_FAILURE if not succesful +* +* @note None. +* +******************************************************************************/ +int HW_connectIntr(XScuGic *GicPtr,u32 IntrId,Xil_InterruptHandler Handler, + void *CallBackRef, u8 Priority, u8 Trigger); + +/*****************************************************************************/ +/* +* +* Initialize Analog Device related configuration profile. This is a HARDWARE- +* ASSOTIATED function, which may differ between different board. +* +* @param None. +* +* @return +* - ADIERR_OK if configuration profile exists, +* - ADIERR_FAILED if onfiguration profile does not exist +* +* @note None. +* +******************************************************************************/ +int HW_adiCfgProfileInit(void); + +/******************************************************************************/ +/** +* +* This function conducts AD9528 device configuration initializing procedure. +* +* @param clockAD9528_device is a pointer to the data structure holding +* AD9528 settings, which contains basic AD9528 settings such as +* spi and gpio. +* +* @return +* - ADIERR_OK if successful. +* - ADIERR_FAILED if not successful. +* +* @note None. +* +*******************************************************************************/ +int HW_9528Config(ad9528Device_t *clockAD9528_device); + +/******************************************************************************/ +/** +* +* This function read AD9528 reg508 status, to check whether ad9528 is locked or +* not. +* +* @param clockAD9528_device is a pointer to the data structure holding +* AD9528 settings, which contains basic AD9528 settings. +* +* @return +* - ADIERR_OK if successful. +* - ADIERR_FAILED if not successful. +* +* @note None. +* +*******************************************************************************/ +int HW_9528GetLockStatus(ad9528Device_t *device, uint8_t *reg508); + +/******************************************************************************/ +/** +* +* Conduct AD9371 device configuration initializing procedure. +* +* @param clockAD9528_device is a pointer to the data structure holding +* AD9528 settings, which contains basic AD9528 settings. +* @param mykDevice is ADI hardware layer settings pointer specific to +* a Mykonos instance which contains basic settings such as spi, +* gpio, tx/rx and jesd configurations. +* +* @return +* - ADIERR_OK if successful. +* - ADIERR_FAILED if not successful. +* +* @note None. +* +*******************************************************************************/ +int HW_9371Config(ad9528Device_t *clockAD9528_device, mykonosDevice_t *mykDevice); + +/******************************************************************************/ +/** +* +* Read AD9371's RX framer, ORX framer and TX deframer status, to check jesd204b +* sync status. +* +* @param mykDevice is ADI hardware layer settings pointer specific to +* a Mykonos instance which contains basic settings such as spi, +* gpio, tx/rx and jesd configurations. +* @param framerStatus is the RX framer status byte read +* framerStatus | Description +* -------------|----------------------------------------------------------------------------- +* [7] | SYSREF phase error ? a new SYSREF had different timing than the first that set the LMFC timing. +* [6] | Framer lane FIFO read/write pointer delta has changed. Can help debug issues with deterministic latency. +* [5] | Framer has received the SYSREF and has retimed its LMFC +* [4:2] | Framer ILAS state: 0=CGS, 1= 1st Multframe, 2= 2nd Multiframe, 3= 3rd Multiframe, 4= 4th multiframe, 5= Last multiframe, 6=invalid, 7= ILAS complete +* [1:0] | Framer Tx state: 0=CGS, 1= ILAS, 2 = ADC Data +* @param obsFramerStatus is the ORX framer status byte read +* obsFramerStatus | Description +* ----------------|----------------------------------------------------------------------------- +* [7] | SYSREF phase error ? a new SYSREF had different timing than the first that set the LMFC timing. +* [6] | Framer lane FIFO read/write pointer delta has changed. Can help debug issues with deterministic latency. +* [5] | Framer has received the SYSREF and has retimed its LMFC +* [4:2] | Framer ILAS state: 0=CGS, 1= 1st Multframe, 2= 2nd Multiframe, 3= 3rd Multiframe, 4= 4th multiframe, 5= Last multiframe, 6=invalid, 7= ILAS complete +* [1:0] | Framer Tx state: 0=CGS, 1= ILAS, 2 = ADC Data +* @param deframerStatus is the TX deframer status byte read +* deframerStatus | Bit Name | Description +* ----------------|--------------------------|--------------------------------------------- +* [7] | Unused | Unused +* [6] | Deframer IRQ | This bit indicates that the IRQ interrupt was asserted. +* [5] | Deframer SYSREF Received | When this bit is set, it indicates that the SYSREF pulse was received by the deframer IP +* [4] | Deframer Receiver Error | This bit is set when PRBS has received an error. +* [3] | Valid Checksum | This bit is set when the received ILAS checksum is valid. +* [2] | EOF Event | This bit captures the internal status of the framer End of Frame event. Value =1 if framing error during ILAS +* [1] | EOMF Event | This bit captures the internal status of the framer End of Multi-Frame event. Value =1 if framing error during ILAS +* [0] | FS Lost | This bit captures the internal status of the framer Frame Symbol event. Value =1 if framing error during ILAS or user data (invalid replacement characters) +* +* @return +* - ADIERR_OK if successful. +* - ADIERR_FAILED if not successful. +* +* @note None. +* +*******************************************************************************/ +int HW_9371CheckJesdStatus(mykonosDevice_t *mykDevice, uint8_t *framerStatus, + uint8_t *obsFramerStatus, uint8_t *deframerStatus); + +/******************************************************************************/ +/** +* +* This function conducts AD9371/9375 samll RF PLL frequcny change procedure. The +* procedure is performed as follows: +* 1. Move the device into the radio off state. +* 2. Program the new local oscillator (LO) frequency. +* 3. Reset the external channel.(ignored) +* 4. Move the device back into the radio on state. +* 5. Reenable tracking calibrations.(ignored) +* +* @param mykDevice is ADI hardware layer settings pointer specific to +* a Mykonos instance which contains basic settings such as spi, +* gpio, tx/rx and jesd configurations. +* @param freq_Hz is the target frequancy in Hz. +* +* @return None. +* +* @note The procedure is used when a radio frequency (RF) phased-lock loop +* (PLL) change is required with the following conditions: +* - A desire to change the Rx, Tx, and ORx frequencies. +* - The frequency step change is less than 100 MHz. +* - The frequency step does not cross the divide by 2 boundaries outlined +* in AD9371/9375-UG-992-Rev.B-Table 96. +* +*******************************************************************************/ +int HW_9371SmallFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz); + +/******************************************************************************/ +/** +* +* This function conducts AD9371/9375 large RF PLL frequcny change procedure. The +* procedure is performed as follows: +* 1. Move the device into the radio off state. +* 2. Program the new local oscillator (LO) frequency. +* 3. Rerun the initialization calibrations. +* 4. Move the device back into the radio on state. +* 5. Reenable tracking calibrations.(ignored) +* +* @param mykDevice is ADI hardware layer settings pointer specific to +* a Mykonos instance which contains basic settings such as spi, +* gpio, tx/rx and jesd configurations. +* @param freq_Hz is the target frequancy in Hz. +* +* @return None. +* +* @note The procedure is used when a radio frequency (RF) phased-lock loop +* (PLL) change is required with the following conditions: +* - A desire to change the Rx, Tx, and ORx frequencies. +* - The frequency step change is more than 100 MHz. +* - The frequency step does cross the divide by 2 boundaries outlined +* in AD9371/9375-UG-992-Rev.B-Table 96. +* +*******************************************************************************/ +int HW_9371LargeFrequencyChange(mykonosDevice_t *mykDevice, uint64_t freq_Hz); + +/******************************************************************************/ +/** +* +* Handles AD9371 TX & RX frequency change axi gpio interruput. +* +* @param CallBackRef is the callback reference, usually the instance +* pointer of the connecting driver. +* +* @return None. +* +* @note None. +* +*******************************************************************************/ +void FreqIntrHandler(void *CallbackRef); + +/******************************************************************************/ +/** +* +* Handles AD9371 Rx gain index change axi gpio interruput. +* +* @param CallBackRef is the callback reference, usually the instance +* pointer of the connecting driver. +* +* @return None. +* +* @note None. +* +*******************************************************************************/ +void GainIntrHandler(void *CallbackRef); + +/******************************************************************************/ +/** +* +* Handles AD9371 Tx attenuation change axi gpio interruput. +* +* @param CallBackRef is the callback reference, usually the instance +* pointer of the connecting driver. +* +* @return None. +* +* @note None. +* +*******************************************************************************/ +void AttnIntrHandler(void *CallbackRef); + +#endif /* SRC_HEADLESS_H_ */ diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/myk_ad9528init.c b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/myk_ad9528init.c new file mode 100644 index 00000000..0cb935df --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/myk_ad9528init.c @@ -0,0 +1,189 @@ +///* +// * myk_clock_init.c +// * +// */ +// +///** +//* \page Disclaimer Legal Disclaimer +//* Copyright 2015-2017 Analog Devices Inc. +//* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +//* +//*/ +// +//#ifndef MYK_CLOCK_INIT_C_ +//#define MYK_CLOCK_INIT_C_ +//#include +//#include +//#include +//#include "common.h" +// +//#include "ad9528.h" +//#include "t_ad9528.h" +//#include "myk_ad9528init.h" +//#include "parameters.h" +// +//static ad9528pll1Settings_t clockPll1Settings = +//{ +// .refA_Frequency_Hz = 30720000, +// .refA_Divider = 1, +// .refA_bufferCtrl = DISABLED, +// .refB_Frequency_Hz = 0, +// .refB_Divider = 1, +// .refB_bufferCtrl = DISABLED, +// .vcxo_Frequency_Hz = 122880000, +// .vcxoBufferCtrl = NEG_SINGLE_ENDED, +// .nDivider = 4, +// .bypassPll1 = 0 +//}; +// +//static ad9528pll2Settings_t clockPll2Settings = +//{ +// .rfDivider = 4, +// .n2Divider = 10, +// .totalNdiv = 30 +//}; +// +//static ad9528outputSettings_t clockOutputSettings = +//{ +// .outPowerDown = 53237, // 0xCFF5 +// .outSource = { +// CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, SYSREF, +// CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, +// CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, +// SYSREF, CHANNEL_DIV}, +// .outBufferCtrl = {0,0,0,0,0,0,0,0,0,0,0,0,0,0}, +// .outAnalogDelay = {0,0,0,0,0,0,0,0,0,0,0,0,0,0}, +// .outDigitalDelay = {0,0,0,0,0,0,0,0,0,0,0,0,0,0}, +// .outChannelDiv = {10,10,10,10,10,10,10,10,10,10,10,10,10,10}, +// .outFrequency_Hz = {122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000, 122880000} +//}; +// +//static ad9528sysrefSettings_t clockSysrefSettings = +//{ +// .sysrefRequestMethod = PIN, +// .sysrefSource = INTERNAL, +// .sysrefPinEdgeMode = LEVEL_ACTIVE_HIGH, +// .sysrefPinBufferMode = DISABLED, +// .sysrefPatternMode = NSHOT, +// .sysrefNshotMode = ONE_PULSE, +// .sysrefDivide = 512 +//}; +// +//static spiSettings_t clockSpiSettings = +//{ +// .chipSelectIndex = AD9528_CS, //chip select Index +// .writeBitPolarity = 0, //Write bit polarity +// .longInstructionWord = 1, //16bit instruction word +// .MSBFirst = 1, //MSB first +// .CPHA = 0, //Clock phase +// .CPOL = 0, //Clock polarity +// .enSpiStreaming = 0, //uint8_t enSpiStreaming; +// .autoIncAddrUp = 1, //uint8_t autoIncAddrUp; +// .fourWireMode = 1 //uint8_t fourWireMode; +//}; +// +//ad9528Device_t clockAD9528_ = +//{ +// &clockSpiSettings, +// &clockPll1Settings, +// &clockPll2Settings, +// &clockOutputSettings, +// &clockSysrefSettings +//}; +// +//ad9528Device_t *ad9528Init = &clockAD9528_; +// +//#endif /* MYK_CLOCK_INIT_C_ */ + + +/* AD9528 data structure initialization file */ +#include +#include +#include +#include "common.h" + +#include "./mykonos/ad9528.h" +#include "./mykonos/t_ad9528.h" +#include "myk_ad9528init.h" +#include "parameters.h" + +static ad9528pll1Settings_t clockPll1Settings = { + .refA_Frequency_Hz = 122880000, + .refA_Divider = 1, + .refA_bufferCtrl = SINGLE_ENDED, + .refB_Frequency_Hz = 0, + .refB_Divider = 1, + .refB_bufferCtrl = DISABLED, + .vcxo_Frequency_Hz = 122880000, + .vcxoBufferCtrl = DIFFERENTIAL, + .nDivider = 1, + .bypassPll1 = 0 +}; + +static ad9528pll2Settings_t clockPll2Settings = { + .rfDivider = 3, + .n2Divider = 10, + .totalNdiv = 30 +}; + +/******************************************************************* + * Output Distribution Settings + * 9369CE02A uses the following clock outputs + * OUT 1: FPGA_REF_CLK + * OUT 2: FPGA_AUX_CLK + * OUT 3: FPGA_SYSREF + * OUT 12: SYSREF_IN + * OUT 13: DEV_CLK_IN + ******************************************************************* + */ +static ad9528outputSettings_t clockOutputSettings = { + .outPowerDown = 0x0, + .outSource = { + SYSREF, SYSREF, CHANNEL_DIV, SYSREF, + CHANNEL_DIV, CHANNEL_DIV, SYSREF, SYSREF, + CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, CHANNEL_DIV, + SYSREF , CHANNEL_DIV + }, + .outBufferCtrl = {0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + .outAnalogDelay = {0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + .outDigitalDelay = {0,0,0,0,0,0,0,0,0,0,0,0,0,0}, + .outChannelDiv = {10,10,10,10,10,10,10,10,10,10,10,10,10,10}, + .outFrequency_Hz = { + 122880000, 122880000, 122880000, 122880000, + 122880000, 122880000, 122880000, 122880000, + 122880000, 122880000, 122880000, 122880000, + 122880000, 122880000 + } +}; + +static ad9528sysrefSettings_t clockSysrefSettings = { + .sysrefRequestMethod = SPI, + .sysrefSource = INTERNAL, + .sysrefPinEdgeMode = LEVEL_ACTIVE_HIGH, + .sysrefPinBufferMode = DISABLED, + .sysrefPatternMode = CONTINUOUS, + .sysrefNshotMode = FOUR_PULSES, + .sysrefDivide = 512 +}; + +static spiSettings_t clockSpiSettings = { + .chipSelectIndex = 2, //chip select Index + .writeBitPolarity = 0, //Write bit polarity + .longInstructionWord = 1, //16bit instruction word + .MSBFirst = 1, //MSB first + .CPHA = 0, //Clock phase + .CPOL = 0, //Clock polarity + .enSpiStreaming = 0, //uint8_t enSpiStreaming; + .autoIncAddrUp = 1, //uint8_t autoIncAddrUp; + .fourWireMode = 1 //uint8_t fourWireMode; +}; + +ad9528Device_t clockAD9528_ = { + &clockSpiSettings, + &clockPll1Settings, + &clockPll2Settings, + &clockOutputSettings, + &clockSysrefSettings +}; + +ad9528Device_t *ad9528Init = &clockAD9528_; diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/myk_ad9528init.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/myk_ad9528init.h new file mode 100644 index 00000000..53e8be61 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/myk_ad9528init.h @@ -0,0 +1,20 @@ +/* + * myk_clock_init.h + * + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#ifndef MYK_CLOCK_INIT_H_ +#define MYK_CLOCK_INIT_H_ + +#include "./mykonos/ad9528.h" + +extern ad9528Device_t *ad9528Init; + +#endif /* MYK_CLOCK_INIT_H_ */ diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/myk_init.c b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/myk_init.c new file mode 100644 index 00000000..22f91160 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/myk_init.c @@ -0,0 +1,558 @@ +/** + * \file myk_init.c + * + * \brief Contains init setting structure declarations for the _instance API + * + * The top level structure mykonosDevice_t mykDevice uses keyword + * extern to allow the application layer main() to have visibility + * to these settings. + * + * All data structures required for operation have been initialized with values which reflect + * these settings: + * + * Device Clock = $122.88$ Mhz + * Rx enabled channels = $2$ + * Tx enabled channels = $2$ + * + * Mykonos Framer: + * Lane Rate = $4915.2$ Mbs + * L = $2$ + * K = $32$ + * M = $4$ + * F = $4$ + * + * Mykonos Deframer: + * Lane Rate = $4915.2$ Mbs + * L = $2$ + * K = $32$ + * M = $4$ + * F = $4$ + * + * Mykonos Observation framer: + * Lane Rate = $4915.2$ Mbs + * L = $2$ + * K = $32$ + * M = $4$ + * F = $4$ + * + * Using these profiles: + * $Rx 100Mhz, IQrate 122.88Mhz, Dec5$ + * $Tx 100/100Mhz, IQrate 122.88Mhz, Dec5$ + * $ORX 100Mhz, IQrate 122.88Mhz, Dec5$ + * $SRx 20Mhz, IQrate 30.72Mhz, Dec5$ + * + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#include +#include "./mykonos/t_mykonos.h" +#include "myk_init.h" +#include "parameters.h" +#include "./mykonos/mykonos_gpio.h" + +static int16_t txFirCoefs[] = {-94,-26,282,177,-438,-368,756,732,-1170,-1337,1758,2479,-2648,-5088,4064,16760,16759,4110,-4881,-2247,2888,1917,-1440,-1296,745,828,-358,-474,164,298,-16,-94}; + +static mykonosFir_t txFir = +{ + 6, /* Filter gain in dB*/ + 32, /* Number of coefficients in the FIR filter*/ + &txFirCoefs[0] /* A pointer to an array of filter coefficients*/ +}; + +static int16_t rxFirCoefs[] = {-20,6,66,22,-128,-54,240,126,-402,-248,634,444,-956,-756,1400,1244,-2028,-2050,2978,3538,-4646,-7046,9536,30880,30880,9536,-7046,-4646,3538,2978,-2050,-2028,1244,1400,-756,-956,444,634,-248,-402,126,240,-54,-128,22,66,6,-20}; + +static mykonosFir_t rxFir = +{ + -6, /* Filter gain in dB*/ + 48, /* Number of coefficients in the FIR filter*/ + &rxFirCoefs[0] /* A pointer to an array of filter coefficients*/ +}; + +static int16_t obsrxFirCoefs[] = {-14,-19,44,41,-89,-95,175,178,-303,-317,499,527,-779,-843,1184,1317,-1781,-2059,2760,3350,-4962,-7433,9822,32154,32154,9822,-7433,-4962,3350,2760,-2059,-1781,1317,1184,-843,-779,527,499,-317,-303,178,175,-95,-89,41,44,-19,-14}; +static mykonosFir_t obsrxFir = +{ + -6, /* Filter gain in dB*/ + 48, /* Number of coefficients in the FIR filter*/ + &obsrxFirCoefs[0]/* A pointer to an array of filter coefficients*/ +}; + +static int16_t snifferFirCoefs[] = {-1,-5,-14,-23,-16,24,92,137,80,-120,-378,-471,-174,507,1174,1183,98,-1771,-3216,-2641,942,7027,13533,17738,17738,13533,7027,942,-2641,-3216,-1771,98,1183,1174,507,-174,-471,-378,-120,80,137,92,24,-16,-23,-14,-5,-1}; +static mykonosFir_t snifferRxFir= +{ + -6, /* Filter gain in dB*/ + 48, /* Number of coefficients in the FIR filter*/ + &snifferFirCoefs[0]/* A pointer to an array of filter coefficients*/ +}; + +static mykonosJesd204bFramerConfig_t rxFramer = +{ + 0, /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/ + 0, /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/ + 0, /* JESD204B Configuration starting Lane ID. If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/ + 4, /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/ + 32, /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/ + 0, /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/ + 1, /* 0=use internal SYSREF, 1= use external SYSREF*/ + 0x03, /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/ + 0xE4, /* serializerLaneCrossbar*/ + 22, /* serializerAmplitude - default 22 (valid (0-31)*/ + 4, /* preEmphasis - < default 4 (valid 0 - 7)*/ + 0, /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/ + 0, /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/ + 0, /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/ + 0, /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/ + 0, /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/ + 0, /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/ + 0, /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/ + 0 /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/ +}; + +static mykonosJesd204bFramerConfig_t obsRxFramer = +{ + 0, /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/ + 0, /* JESD204B Configuration Device ID - link identification number. (Valid 0..255)*/ + 0, /* JESD204B Configuration starting Lane ID. If more than one lane used, each lane will increment from the Lane0 ID. (Valid 0..31)*/ + 2, /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/ + 32, /* number of frames in a multiframe (default=32), F*K must be a multiple of 4. (F=2*M/numberOfLanes)*/ + 0, /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is enabled.*/ + 1, /* 0=use internal SYSREF, 1= use external SYSREF*/ + 0x04, /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1 enabled*/ + 0xE4, /* Lane crossbar to map framer lane outputs to physical lanes*/ + 22, /* serializerAmplitude - default 22 (valid (0-31)*/ + 4, /* preEmphasis - < default 4 (valid 0 - 7)*/ + 0, /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert lane1)*/ + 0, /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/ + 0, /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set*/ + 0, /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/ + 1, /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer*/ + 0, /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/ + 0, /* Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/ + 0 /* Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used*/ +}; + +static mykonosJesd204bDeframerConfig_t deframer = +{ + 0, /* bankId extension to Device ID (Valid 0..15)*/ + 0, /* deviceId link identification number. (Valid 0..255)*/ + 0, /* lane0Id Lane0 ID. (Valid 0..31)*/ + 4, /* M number of DACss (0, 2, or 4) - 2 DACs per transmit chain */ + 32, /* K #frames in a multiframe (default=32), F*K=multiple of 4. (F=2*M/numberOfLanes)*/ + 0, /* scramble scrambling off if scramble= 0.*/ + 1, /* External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF*/ + 0x03, /* Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ + 0xE4, /* Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc */ + 1, /* Equalizer setting. Applied to all deserializer lanes. Range is 0..4*/ + 0, /* PN inversion per each lane. bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc).*/ + 0, /* LMFC_Offset offset value to adjust deterministic latency. Range is 0..31*/ + 0, /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set*/ + 0, /* Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set*/ + 0, /* Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS*/ + 0 /* Flag for determining if API will calculate the appropriate settings for deframer lane in to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in deserializerLaneCrossbar will be used*/ +}; + +static mykonosRxGainControl_t rxGainControl = +{ + MGC, /* Current Rx gain control mode setting*/ + 255, /* Rx1 Gain Index, can be used in different ways for manual and AGC gain control*/ + 255, /* Rx2 Gain Index, can be used in different ways for manual and AGC gain control*/ + 255, /* Max gain index for the currently loaded Rx1 Gain table*/ + 195, /* Min gain index for the currently loaded Rx1 Gain table*/ + 255, /* Max gain index for the currently loaded Rx2 Gain table*/ + 195, /* Min gain index for the currently loaded Rx2 Gain table*/ + 0, /* Stores Rx1 RSSI value read back from the Mykonos*/ + 0 /* Stores Rx2 RSSI value read back from the Mykonos*/ +}; + + +static mykonosORxGainControl_t orxGainControl = +{ + MGC, /* Current ORx gain control mode setting*/ + 255, /* ORx1 Gain Index, can be used in different ways for manual and AGC gain control*/ + 255, /* ORx2 Gain Index, can be used in different ways for manual and AGC gain control*/ + 255, /* Max gain index for the currently loaded ORx Gain table*/ + 237 /* Min gain index for the currently loaded ORx Gain table*/ +}; + +static mykonosSnifferGainControl_t snifferGainControl = +{ + MGC, /* Current Sniffer gain control mode setting*/ + 255, /* Current Sniffer gain index. Can be used differently for MANUAL Gain control/AGC*/ + 255, /* Max gain index for the currently loaded Sniffer Gain table*/ + 203 /* Min gain index for the currently loaded Sniffer Gain table*/ +}; + +static mykonosPeakDetAgcCfg_t rxPeakAgc = +{ + 0x0C, /* apdHighThresh: */ + 0x08, /* apdLowThresh */ + 0xB5, /* hb2HighThresh */ + 0x80, /* hb2LowThresh */ + 0x40, /* hb2VeryLowThresh */ + 0x06, /* apdHighThreshExceededCnt */ + 0x04, /* apdLowThreshExceededCnt */ + 0x06, /* hb2HighThreshExceededCnt */ + 0x04, /* hb2LowThreshExceededCnt */ + 0x04, /* hb2VeryLowThreshExceededCnt */ + 0x4, /* apdHighGainStepAttack */ + 0x2, /* apdLowGainStepRecovery */ + 0x4, /* hb2HighGainStepAttack */ + 0x2, /* hb2LowGainStepRecovery */ + 0x4, /* hb2VeryLowGainStepRecovery */ + 0x1, /* apdFastAttack */ + 0x1, /* hb2FastAttack */ + 0x1, /* hb2OverloadDetectEnable */ + 0x1, /* hb2OverloadDurationCnt */ + 0x1 /* hb2OverloadThreshCnt */ +}; + +static mykonosPowerMeasAgcCfg_t rxPwrAgc = +{ + 0x01, /* pmdUpperHighThresh */ + 0x03, /* pmdUpperLowThresh */ + 0x0C, /* pmdLowerHighThresh */ + 0x00, /* pmdLowerLowThresh */ + 0x4, /* pmdUpperHighGainStepAttack */ + 0x2, /* pmdUpperLowGainStepAttack */ + 0x2, /* pmdLowerHighGainStepRecovery */ + 0x4, /* pmdLowerLowGainStepRecovery */ + 0x08, /* pmdMeasDuration */ + 0x02 /* pmdMeasConfig */ +}; + +static mykonosAgcCfg_t rxAgcConfig = +{ + 255, /* agcRx1MaxGainIndex */ + 195, /* agcRx1MinGainIndex */ + 255, /* agcRx2MaxGainIndex */ + 195, /* agcRx2MinGainIndex: */ + 255, /* agcObsRxMaxGainIndex */ + 203, /* agcObsRxMinGainIndex */ + 1, /* agcObsRxSelect */ + 1, /* agcPeakThresholdMode */ + 1, /* agcLowThsPreventGainIncrease */ + 30720, /* agcGainUpdateCounter */ + 3, /* agcSlowLoopSettlingDelay */ + 2, /* agcPeakWaitTime */ + 1, /* agcResetOnRxEnable */ + 0, /* agcEnableSyncPulseForGainCounter */ + &rxPeakAgc, + &rxPwrAgc +}; + +static mykonosPeakDetAgcCfg_t obsRxPeakAgc = +{ + 0x1F, /* apdHighThresh: */ + 0x16, /* apdLowThresh */ + 0xB5, /* hb2HighThresh */ + 0x80, /* hb2LowThresh */ + 0x40, /* hb2VeryLowThresh */ + 0x06, /* apdHighThreshExceededCnt */ + 0x04, /* apdLowThreshExceededCnt */ + 0x06, /* hb2HighThreshExceededCnt */ + 0x04, /* hb2LowThreshExceededCnt */ + 0x04, /* hb2VeryLowThreshExceededCnt */ + 0x4, /* apdHighGainStepAttack */ + 0x2, /* apdLowGainStepRecovery */ + 0x4, /* hb2HighGainStepAttack */ + 0x2, /* hb2LowGainStepRecovery */ + 0x4, /* hb2VeryLowGainStepRecovery */ + 0x1, /* apdFastAttack */ + 0x1, /* hb2FastAttack */ + 0x1, /* hb2OverloadDetectEnable */ + 0x1, /* hb2OverloadDurationCnt */ + 0x1 /* hb2OverloadThreshCnt */ +}; + +static mykonosPowerMeasAgcCfg_t obsRxPwrAgc = +{ + 0x01, /* pmdUpperHighThresh */ + 0x03, /* pmdUpperLowThresh */ + 0x0C, /* pmdLowerHighThresh */ + 0x00, /* pmdLowerLowThresh */ + 0x4, /* pmdUpperHighGainStepAttack */ + 0x2, /* pmdUpperLowGainStepAttack */ + 0x2, /* pmdLowerHighGainStepRecovery */ + 0x4, /* pmdLowerLowGainStepRecovery */ + 0x08, /* pmdMeasDuration */ + 0x02 /* pmdMeasConfig */ +}; + +static mykonosAgcCfg_t obsRxAgcConfig = +{ + 255, /* agcRx1MaxGainIndex */ + 195, /* agcRx1MinGainIndex */ + 255, /* agcRx2MaxGainIndex */ + 195, /* agcRx2MinGainIndex: */ + 255, /* agcObsRxMaxGainIndex */ + 203, /* agcObsRxMinGainIndex */ + 1, /* agcObsRxSelect */ + 1, /* agcPeakThresholdMode */ + 1, /* agcLowThsPreventGainIncrease */ + 30720, /* agcGainUpdateCounter */ + 3, /* agcSlowLoopSettlingDelay */ + 2, /* agcPeakWaitTime */ + 1, /* agcResetOnRxEnable */ + 0, /* agcEnableSyncPulseForGainCounter */ + &obsRxPeakAgc, + &obsRxPwrAgc +}; + + +static mykonosRxProfile_t rxProfile = +{/* Rx 100MHz, IQrate 122.88MSPS, Dec5 */ + 1, /* The divider used to generate the ADC clock*/ + &rxFir, /* Pointer to Rx FIR filter structure*/ + 2, /* Rx FIR decimation (1,2,4)*/ + 5, /* Decimation of Dec5 or Dec4 filter (5,4)*/ + 1, /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/ + 1, /* RX Half band 1 decimation (1 or 2)*/ + 122880, /* Rx IQ data rate in kHz*/ + 100000000, /* The Rx RF passband bandwidth for the profile*/ + 100000, /* Rx BBF 3dB corner in kHz*/ + NULL /* pointer to custom ADC profile*/ +}; + +static mykonosRxProfile_t orxProfile = +{/* ORX 100MHz, IQrate 122.88MSPS, Dec5 */ + 1, /* The divider used to generate the ADC clock*/ + &obsrxFir, /* Pointer to Rx FIR filter structure or NULL*/ + 2, /* Rx FIR decimation (1,2,4)*/ + 5, /* Decimation of Dec5 or Dec4 filter (5,4)*/ + 0, /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/ + 1, /* RX Half band 1 decimation (1 or 2)*/ + 122880, /* Rx IQ data rate in kHz*/ + 100000000, /* The Rx RF passband bandwidth for the profile*/ + 100000, /* Rx BBF 3dB corner in kHz*/ + NULL /* pointer to custom ADC profile*/ +}; + + +static mykonosRxProfile_t snifferProfile = +{ /* SRx 20MHz, IQrate 30.72MSPS, Dec5 */ + 1, /* The divider used to generate the ADC clock*/ + &snifferRxFir, /* Pointer to Rx FIR filter structure or NULL*/ + 4, /* Rx FIR decimation (1,2,4)*/ + 5, /* Decimation of Dec5 or Dec4 filter (5,4)*/ + 0, /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter (1=Enabled, 0=Disabled)*/ + 2, /* RX Half band 1 decimation (1 or 2)*/ + 30720, /* Rx IQ data rate in kHz*/ + 10000000, /* The Rx RF passband bandwidth for the profile*/ + 100000, /* Rx BBF 3dB corner in kHz*/ + NULL /* pointer to custom ADC profile*/ +}; + + + +static mykonosTxProfile_t txProfile = +{ /* Tx 20/100MHz, IQrate 122.88MSPS, Dec5 */ + DACDIV_2p5, /* The divider used to generate the DAC clock*/ + &txFir, /* Pointer to Tx FIR filter structure*/ + 2, /* The Tx digital FIR filter interpolation (1,2,4)*/ + 2, /* Tx Halfband1 filter interpolation (1,2)*/ + 1, /* Tx Halfband2 filter interpolation (1,2)*/ + 1, /* TxInputHbInterpolation (1,2)*/ + 122880, /* Tx IQ data rate in kHz*/ + 100000000, /* Primary Signal BW*/ + 100000000, /* The Tx RF passband bandwidth for the profile*/ + 710539, /* The DAC filter 3dB corner in kHz*/ + 50000, /* Tx BBF 3dB corner in kHz*/ + 0 /* Enable DPD, only valid for AD9373*/ +}; + +static mykonosDigClocks_t mykonosClocks = +{ + 122880, /* CLKPLL and device reference clock frequency in kHz*/ + 9830400, /* CLKPLL VCO frequency in kHz*/ + VCODIV_2, /* CLKPLL VCO divider*/ + 4 /* CLKPLL high speed clock divider*/ +}; + +static mykonosRxSettings_t rxSettings = +{ + &rxProfile, /* Rx datapath profile, 3dB corner frequencies, and digital filter enables*/ + &rxFramer, /* Rx JESD204b framer configuration structure*/ + &rxGainControl, /* Rx Gain control settings structure*/ + &rxAgcConfig, /* Rx AGC control settings structure*/ + RX1_RX2, /* The desired Rx Channels to enable during initialization*/ + 0, /* Internal LO = 0, external LO*2 = 1*/ + 2550000000U, /* Rx PLL LO Frequency (internal or external LO)*/ + 0 /* Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where, if > 0 = real IF data, '0' = zero IF (IQ) data*/ +}; + +static mykonosDpdConfig_t dpdConfig = +{ + 5, /* 1/2^(damping + 8) fraction of power `forgotten' per sample (default: `1/8192' = 5, valid 0 to 15), 0 = infinite damping*/ + 1, /* number of weights to use for int8_cpx weights weights member of this structure (default = 1)*/ + 2, /* DPD model version: one of four different generalized polynomial models: 0 = same as R0 silicon, 1-3 are new and the best one depends on the PA (default: 2)*/ + 1, /* 1 = Update saved model whenever peak Tx digital RMS is within 1dB of historical peak Tx RMS*/ + 20, /* Determines how much weight the loaded prior model has on DPD modeling (Valid 0 - 32, default 20)*/ + 0, /* Default off = 0, 1=enables automatic outlier removal during DPD modeling */ + 512, /* Number of samples to capture (default: 512, valid 64-32768)*/ + 4096, /* threshold for sample in AM-AM plot outside of 1:1 line to be thrown out. (default: 50% = 8192/2, valid 8192 to 1)*/ + 0, /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/ + 255, /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to 8191)*/ + {{64,0},{0,0},{0,0}}/* DPD model error weighting (real/imag valid from -128 to 127)*/ +}; + +static mykonosClgcConfig_t clgcConfig = +{ + -2000, /* (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx1 output to ORx1 input in (dB * 100)*/ + -2000, /* (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx2 output to ORx2 input in (dB * 100)*/ + 0, /* (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx1Atten is not reduced below the limit*/ + 0, /* (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx2Atten is not reduced below the limit*/ + 75, /* valid range 1-100, default 75*/ + 75, /* valid range 1-100, default 45*/ + 0, /* 0= allow CLGC to run, but Tx1Atten will not be updated. User can still read back power measurements. 1=CLGC runs, and Tx1Atten automatically updated*/ + 0, /* 0= allow CLGC to run, but Tx2Atten will not be updated. User can still read back power measurements. 1=CLGC runs, and Tx2Atten automatically updated*/ + 0, /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/ + 255, /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to 8191)*/ + 600, /* Threshold for Tx1 in order to stop tracking, value = 100 * dB, default 6db then value = 600*/ + 600, /* Threshold for Tx2 in order to stop tracking, value = 100 * dB, default 6db then value = 600*/ + 0, /* Threshold feature enable for Tx1, 0 = disable, 1 = enable, default = 0*/ + 0 /* Threshold feature enable for Tx1, 0 = disable, 1 = enable, default = 0*/ +}; + +static mykonosVswrConfig_t vswrConfig = +{ + 0, /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/ + 255, /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to 8191)*/ + 0, /* 3p3V GPIO pin to use to control VSWR switch for Tx1 (valid 0-11) (output from Mykonos)*/ + 1, /* 3p3V GPIO pin to use to control VSWR switch for Tx2 (valid 0-11) (output from Mykonos)*/ + 0, /* 3p3v GPIO pin polarity for forward path of Tx1, opposite used for reflection path (1 = high level, 0 = low level)*/ + 0, /* 3p3v GPIO pin polarity for forward path of Tx2, opposite used for reflection path (1 = high level, 0 = low level)*/ + 50, /* Delay for Tx1 after flipping the VSWR switch until measurement is made. In us resolution*/ + 50 /* Delay for Tx2 after flipping the VSWR switch until measurement is made. In us resolution*/ +}; + +static mykonosTxSettings_t txSettings = +{ + &txProfile, /* Tx datapath profile, 3dB corner frequencies, and digital filter enables*/ + &deframer, /* Mykonos JESD204b deframer config for the Tx data path*/ + TX1_TX2, /* The desired Tx channels to enable during initialization*/ + 0, /* Internal LO=0, external LO*2 if =1*/ + 2500000000U, /* Tx PLL LO frequency (internal or external LO)*/ + TXATTEN_0P05_DB,/* Initial and current Tx1 Attenuation*/ + 10000, /* Initial and current Tx1 Attenuation mdB*/ + 10000, /* Initial and current Tx2 Attenuation mdB*/ + NULL, /* DPD,CLGC,VSWR settings. Only valid for AD9373 device, set pointer to NULL otherwise*/ + NULL, /* CLGC Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/ + NULL /* VSWR Config Structure. Only valid for AD9373 device, set pointer to NULL otherwise*/ +}; + + +static mykonosObsRxSettings_t obsRxSettings = +{ + &orxProfile, /* ORx datapath profile, 3dB corner frequencies, and digital filter enables*/ + &orxGainControl,/* ObsRx gain control settings structure*/ + &obsRxAgcConfig,/* ORx AGC control settings structure*/ + &snifferProfile,/* Sniffer datapath profile, 3dB corner frequencies, and digital filter enables*/ + &snifferGainControl,/* SnRx gain control settings structure*/ + &obsRxFramer, /* ObsRx JESD204b framer configuration structure */ + (MYK_ORX1_ORX2 | MYK_SNRXA_B_C),/* obsRxChannel */ + OBSLO_TX_PLL, /* (obsRxLoSource) The Obs Rx mixer can use the Tx Synth(TX_PLL) or Sniffer Synth (SNIFFER_PLL) */ + 2600000000U, /* SnRx PLL LO frequency in Hz */ + 0, /* Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where if > 0 = real IF data, '0' = complex data*/ + NULL, /* Custom Loopback ADC profile to set the bandwidth of the ADC response */ + OBS_RXOFF /* Default ObsRx channel to enter when radioOn called */ +}; + +static mykonosArmGpioConfig_t armGpio = +{ + 1, // useRx2EnablePin; /*!< 0= RX1_ENABLE controls RX1 and RX2, 1 = separate RX1_ENABLE/RX2_ENABLE pins */ + 1, // useTx2EnablePin; /*!< 0= TX1_ENABLE controls TX1 and TX2, 1 = separate TX1_ENABLE/TX2_ENABLE pins */ + 0, // txRxPinMode; /*!< 0= ARM command mode, 1 = Pin mode to power up Tx/Rx chains */ + 0, // orxPinMode; /*!< 0= ARM command mode, 1 = Pin mode to power up ObsRx receiver*/ + + /*Mykonos ARM input GPIO pins -- Only valid if orxPinMode = 1 */ + 0, // orxTriggerPin; /*!< Select desired GPIO pin (valid 4-15) */ + 0, // orxMode2Pin; /*!< Select desired GPIO pin (valid 0-18) */ + 0, // orxMode1Pin; /*!< Select desired GPIO pin (valid 0-18) */ + 0, // orxMode0Pin; /*!< Select desired GPIO pin (valid 0-18) */ + + /* Mykonos ARM output GPIO pins -- always available, even when pin mode not enabled*/ + 0, // rx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + 0, // rx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + 0, // tx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + 0, // tx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + 0, // orx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + 0, // orx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + 0, // srxEnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + 0 // txObsSelect; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + /* When 2Tx are used with only 1 ORx input, this GPIO tells the BBIC which Tx channel is */ + /* active for calibrations, so BBIC can route correct RF Tx path into the single ORx input*/ +}; + +static mykonosGpio3v3_t gpio3v3 = +{ + 0, /*!< Oe per pin, 1=output, 0 = input */ + GPIO3V3_BITBANG_MODE, /*!< Mode for GPIO3V3[3:0] */ + GPIO3V3_BITBANG_MODE, /*!< Mode for GPIO3V3[7:4] */ + GPIO3V3_BITBANG_MODE, /*!< Mode for GPIO3V3[11:8] */ +}; + +static mykonosGpioLowVoltage_t gpio = +{ + 0,/* Oe per pin, 1=output, 0 = input */ + GPIO_MONITOR_MODE,/* Mode for GPIO[3:0] */ + GPIO_MONITOR_MODE,/* Mode for GPIO[7:4] */ + GPIO_MONITOR_MODE,/* Mode for GPIO[11:8] */ + GPIO_MONITOR_MODE,/* Mode for GPIO[15:12] */ + GPIO_MONITOR_MODE,/* Mode for GPIO[18:16] */ +}; + +static mykonosAuxIo_t mykonosAuxIo = +{ + 0, //auxDacEnableMask uint16_t + {0,0,0,0,0,0,0,0,0,0}, //AuxDacValue uint16[10] + {0,0,0,0,0,0,0,0,0,0}, //AuxDacSlope uint8[10] + {0,0,0,0,0,0,0,0,0,0}, //AuxDacVref uint8[10] + &gpio3v3, //pointer to gpio3v3 struct + &gpio, //pointer to gpio1v8 struct + &armGpio +}; + +static spiSettings_t mykSpiSettings = +{ + 1, /* chip select index - valid 1~8 */ + 0, /* the level of the write bit of a SPI write instruction word, value is inverted for SPI read operation */ + 1, /* 1 = 16-bit instruction word, 0 = 8-bit instruction word */ + 1, /* 1 = MSBFirst, 0 = LSBFirst */ + 0, /* clock phase, sets which clock edge the data updates (valid 0 or 1) */ + 0, /* clock polarity 0 = clock starts low, 1 = clock starts high */ + 0, /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */ + 1, /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */ + 1 /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */ +}; + +static mykonosTempSensorConfig_t tempSensor = +{ + 7, /* 3-bit value that controls the AuxADC decimation factor when used for temp sensor calculations; AuxADC_decimation = 256 * 2^tempDecimation*/ + 67, /* 8-bit offset that gets added to temp sensor code internally*/ + 1, /* this bit overrides the factory-calibrated fuse offset and uses the value stored in the offset member*/ + 15, /* 4-bit code with a resolution of 1°C/LSB, each time a temperature measurement is performed, the device compares the current temperature against the previous value.*/ +}; + +static mykonosTempSensorStatus_t tempStatus = +{ + 0, /* 16-bit signed temperature value (in deg C) that is read back*/ + 0, /* If the absolute value of the difference is greater than the value in temperature configuration tempWindow, the windowExceeded flag is set.*/ + 0, /* when windowExceeded member gets set, this bit is set to 1 if current value is greater than previous value, else reset*/ + 0, /* when the reading is complete and a valid temperature value stored in tempCode.*/ +}; + +mykonosDevice_t mykDevice = +{ + &mykSpiSettings, /* SPI settings data structure pointer */ + &rxSettings, /* Rx settings data structure pointer */ + &txSettings, /* Tx settings data structure pointer */ + &obsRxSettings, /* ObsRx settings data structure pointer */ + &mykonosAuxIo, /* Auxiliary IO settings data structure pointer */ + &mykonosClocks, /* Holds settings for CLKPLL and reference clock */ + 0 /* Mykonos initialize function uses this as an output to remember which profile data structure pointers are valid */ +}; diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/myk_init.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/myk_init.h new file mode 100644 index 00000000..ef11bad5 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/myk_init.h @@ -0,0 +1,24 @@ +/** + * \file myk_init.h + * + * \brief Contains structure definitions for myk_init.c + * + * The top level structure mykonosDevice_t mykDevice uses keyword + * extern to allow the application layer main() to have visibility + * to these settings. + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#ifndef MYK_INIT_H_ +#define MYK_INIT_H_ + + +extern mykonosDevice_t mykDevice; + +#endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/Mykonos_M3.c b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/Mykonos_M3.c new file mode 100644 index 00000000..369ad923 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/Mykonos_M3.c @@ -0,0 +1,8518 @@ +/** + +SOFTWARE LICENSE AGREEMENT +20180301-AD937X-CTSLA + +This Software License Agreement (the 鈥淎greement鈥�) is a legal agreement +between Analog Devices, Inc., a Massachusetts corporation, with its principal +office at One Technology Way, Norwood, Massachusetts, USA 02062 (鈥淎nalog +Devices鈥�) and you (personally or on behalf of your employer, as applicable) +(鈥淟icensee鈥�) for the software and related documentation that accompanies +this Agreement (the 鈥淟icensed Software鈥�). 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Use, duplication, or disclosure by the Government is +subject to restrictions as set forth in subparagraphs (a) through (d) of the +Commercial Computer Software - Restricted Rights clause at FAR 52.227-19, +(c)(1)(ii) of The Rights in Technical Data and Computer Software clause at +DFARS 252.227-7013, and in similar clauses in the NASA FAR Supplement, as +applicable. The contractor/manufacturer of this Licensed Software is Analog +Devices, Inc., One Technology Way, Norwood, Massachusetts 02062 USA, or its +authorized licensors. + +18. Export. Licensee shall not export, directly or indirectly, Licensed +Software, or other information or materials provided by Analog Devices or its +suppliers hereunder, to any country for which the United States or any other +relevant jurisdiction requires any export license or other governmental +approval at the time of export without first obtaining such license or +approval. Licensee shall defend indemnify and hold harmless Analog Devices +from and against any damages, fines, penalties, assessments, liabilities, costs +and expenses (including reasonable attorneys鈥� fees and court costs) arising +out of any failure by Licensee to comply with this Section. + +19. Compliance with Laws of Other Jurisdictions. Licensee shall comply with +all laws, legislation, rules, regulations, governmental requirements and +industry standards with respect to Licensed Software, and the performance by +Licensee of its obligations hereunder, existing in any applicable jurisdiction. + +20. Assignment. This Agreement is personal to Licensee and Licensee may not +transfer, sublicense, lease, rent, or assign its rights under this License, and +any such attempt shall be null and void. Analog Devices may assign, transfer, +or sublicense this Agreement or any rights or obligations hereunder at any time +in its sole discretion. + +21. Waiver; Modification; Severability. No waiver, consent, modification or +change of terms of this Agreement shall bind either party unless in writing +signed by both parties, and then such waiver, consent, modification or change +shall be effective only in the specific instance and for the specific purpose +given. If any provision of this Agreement is unenforceable, such provision +shall be enforced to the extent possible under applicable law, and the +remaining provisions will remain in effect. + +22. Entire Agreement. This Agreement supersedes any and all other agreements, +either oral or in writing, between the parties with respect to the matters +stated herein. If, for any reason, any provision of this Agreement is held +invalid, such invalidity shall not affect the remainder of this Agreement, and +this Agreement shall continue in force and effect to the full extent allowed by +law. For the avoidance of doubt, all Licensed Software under this Agreement is +subject to the terms and conditions of this Agreement and not any agreement or +terms for purchase of Analog Devices products, even if the Licensed Software is +delivered with such products. + + +Appendix A + +License limited to Analog Devices transceiver / receiver / transmitter products. + +*/ +#include "Mykonos_M3.h" +// Version 5.2.2 + +unsigned char firmware_Mykonos_M3_bin[] = { + 0x90, 0xbc, 0x00, 0x20, 0x35, 0x6b, 0x01, 0x01, 0xf1, 0x66, 0x01, 0x01, + 0xf1, 0x66, 0x01, 0x01, 0xf1, 0x66, 0x01, 0x01, 0xf1, 0x66, 0x01, 0x01, + 0xf1, 0x66, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf5, 0x6a, 0x01, 0x01, + 0xf7, 0x6a, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x97, 0x7a, 0x00, 0x01, + 0x2d, 0x7a, 0x00, 0x01, 0xf9, 0x6a, 0x01, 0x01, 0xd7, 0x8b, 0x00, 0x01, + 0xe7, 0xeb, 0x00, 0x01, 0x71, 0x52, 0x00, 0x01, 0xfb, 0x6a, 0x01, 0x01, + 0x8d, 0x69, 0x00, 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0x28, 0xff, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, + 0x30, 0x31, 0x9d, 0xbd, 0x11, 0xe2, 0x5c, 0x09, 0x0d, 0x1b, 0x2b, 0x34, + 0x37, 0x39, 0x00, 0x00, 0x28, 0x00, 0x3c, 0x20, 0x05, 0x20, 0x05, 0xa0, + 0x0f, 0x11, 0x3c, 0x3c, 0x14, 0x02, 0x01, 0x55, 0x03, 0x3d, 0x26, 0x04, + 0x13, 0x00, 0xf4, 0x06, 0xf8, 0x03, 0x46, 0xff, 0xe6, 0xdb, 0x2e, 0x12, + 0x2a, 0x96, 0x01, 0xb2, 0x12, 0x32, 0x02, 0x2e, 0x20, 0xcb, 0x0c, 0xff, + 0x0c, 0x02, 0x00, 0x9c, 0x23, 0xfd, 0x07, 0x90, 0x03, 0xf1, 0x03, 0x14, + 0xa1, 0x01, 0x03, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xe7, 0x0c, 0x37, 0xfb, 0x00, 0x00, 0x00, 0x00, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff +}; +unsigned int firmware_Mykonos_M3_bin_len = 98304; diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/Mykonos_M3.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/Mykonos_M3.h new file mode 100644 index 00000000..30215b8e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/Mykonos_M3.h @@ -0,0 +1,13 @@ +/** +SOFTWARE LICENSE AGREEMENT +20180301-AD937X-CTSLA +**/ + +// Version 5.2.2 +#ifndef SRC_MYKONOS_BIN_H_ +#define SRC_MYKONOS_BIN_H_ + +unsigned char firmware_Mykonos_M3_bin[]; +unsigned int firmware_Mykonos_M3_bin_len; + +#endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/ad9528.c b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/ad9528.c new file mode 100644 index 00000000..645acf69 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/ad9528.c @@ -0,0 +1,740 @@ +/** + * \file ad9528.c + * \brief Contains source code for configuring and initializing AD9528 clock device + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#include "ad9528.h" + +/** + * \brief Performs a hard reset on the AD9528 DUT + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the AD9528 data structure containing settings + * \return Returns enum ADI_ERR, ADIERR_OK=pass, !ADIERR_OK=fail + */ +ADI_ERR AD9528_resetDevice(ad9528Device_t *device) +{ + /* toggle RESETB on device with matching spi chip select index */ + CMB_hardReset(device->spiSettings->chipSelectIndex); + return ADIERR_OK; +} + +/** + * \brief Sets the AD9528 device SPI settings (3wire/4wire, MSBFirst, etc). + * + * This function will use the settings in the device->spiSettings structure + * to set SPI stream mode, address auto increment direction, MSBFirst/LSBfirst, + * and 3wire/4wire mode. The AD9528 device always uses SPI MODE 0 (CPHA=0, CPOL=0). + * This function will update your device->spiSettings to set CHPA=0 and CPOL=0 and + * longInstructionWord =1 to use a 16bit instruction word. + * + * Dependencies + * - writes device->spiSettings->CPHA = 0 + * - writes device->spiSettings->CPOL = 0 + * - writes device->spiSettings->longInstructionWord = 1 + * + * - device->spiSettings->MSBFirst + * - device->spiSettings->enSpiStreaming + * - device->spiSettings->autoIncAddrUp + * - device->spiSettings->fourWireMode + * + * \param device is structure pointer to the AD9528 data structure containing settings + * + * \return Returns enum ADI_ERR, ADIERR_OK=pass, !ADIERR_OK=fail + */ +ADI_ERR AD9528_setSpiSettings(ad9528Device_t *device) +{ + //device->spiSettings->enSpiStreaming + uint8_t spiReg = 0; + + device->spiSettings->CPHA = 0; + device->spiSettings->CPOL = 0; + device->spiSettings->longInstructionWord = 1; + + if (device->spiSettings->MSBFirst == 0) + { + spiReg |= 0x42; /* SPI bit is 1=LSB first */ + } + + if (device->spiSettings->autoIncAddrUp > 0) + { + spiReg |= 0x24; + } + + if (device->spiSettings->fourWireMode > 0) + { + spiReg |= 0x18; + } + + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_A, spiReg); + + if (device->spiSettings->enSpiStreaming > 0) + { + /* Allow SPI streaming mode: SPI message ends when chip select deasserts */ + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_B, 0x00); + } + else + { + /* Force single instruction mode */ + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_B, 0x80); + } + + return ADIERR_OK; +} + + +/** + * \brief Helper function for ADI transceiver eval boards to init the AD9528 data structure + * + * This function inits the AD9528 device data structure with defaults that + * are known to work with the ADI AD9369 and AD9371 evaluation boards. NOTE: This function will + * modify the contents of the AD9528 device data structure. + * + * Dependencies + * - spi->chipSelectIndex + * - spi + * + * \param device Pointer to the AD9528 device data structure to initialize + * \param vcxoFrequency_Hz The VCXO frequency that is connected to the AD9528 + * \param refAFrequency_Hz The reference clock frequency being input into the AD9528 REFCLK A input + * \param outputDeviceClock_Hz Desired output clock frequency to the FPGA and transceiver device + * + * \return Returns enum ADI_ERR, 0=pass, >0 = fail +*/ +ADI_ERR AD9528_initDeviceDataStruct(ad9528Device_t *device, uint32_t vcxoFrequency_Hz, uint32_t refAFrequency_Hz, uint32_t outputDeviceClock_Hz) +{ +// uint16_t chDiv; +// uint8_t i = 0; +// +// uint32_t pll1PfdFreq_Hz = 0; +// uint8_t pll1Ndiv = 0; +// uint8_t validPll1DivSetting = 0; +// uint8_t refAdiv = 1; +// +// +// uint8_t pll2RfDiv = 3; /* Valid values 3,4,5 */ +// uint16_t pll2Ndiv = 1; /* Valid values 1-256 */ +// uint32_t pll2InputFreq_Hz = 0; +// uint64_t pll2VcoFreq_Hz = 0; +// uint16_t pll2NdivStart = 0; +// uint8_t validPll2DivSetting = 0; +// uint64_t chDivU64 = 0; +// +// static const uint64_t PLL2_MIN_VCO_FREQ_HZ = 3450000000ULL; +// static const uint64_t PLL2_MAX_VCO_FREQ_HZ = 4025000000ULL; +// /******************************************************************* +// * PLL1 Settings +// ******************************************************************* +// */ +// +// /* find valid PLL1 Ndiv and REFA div */ +// for (pll1Ndiv = 1; pll1Ndiv < 20; pll1Ndiv++) +// { +// pll1PfdFreq_Hz = vcxoFrequency_Hz / pll1Ndiv; +// +// if ((pll1PfdFreq_Hz <= 110000000) && (pll1PfdFreq_Hz >= 1000000) && +// (pll1PfdFreq_Hz <= refAFrequency_Hz) && +// (refAFrequency_Hz % pll1PfdFreq_Hz == 0) +// ) +// { +// validPll1DivSetting = 1; +// refAdiv = refAFrequency_Hz / pll1PfdFreq_Hz ; +// break; +// } +// } +// +// if (validPll1DivSetting == 0) +// { +// return ADIERR_INV_PARM; +// } +// +// device->pll1Settings->nDivider = pll1Ndiv; //This init function always runs PLL1 at 30.72MHz Pfd rate +// device->pll1Settings->refA_bufferCtrl = DIFFERENTIAL; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL +// device->pll1Settings->refA_Divider = refAdiv; +// device->pll1Settings->refA_Frequency_Hz = refAFrequency_Hz; +// device->pll1Settings->refB_bufferCtrl = DISABLED; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL +// device->pll1Settings->refB_Divider = 1; +// device->pll1Settings->refB_Frequency_Hz = 0; +// device->pll1Settings->vcxoBufferCtrl = NEG_SINGLE_ENDED; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL +// device->pll1Settings->vcxo_Frequency_Hz = vcxoFrequency_Hz; +// +// /******************************************************************* +// * PLL2 Settings +// ******************************************************************* +// */ +// +// /******************************************************************* +// * Output Distribution Settings +// * 9369CE02A uses the following clock outputs +// * OUT 1: FPGA REFCLK +// * OUT 3: FPGA SYSREF +// * OUT 12: DUT SYSREF +// * OUT 13: DUT REFCLK +// ******************************************************************* +// */ +// +// /* PLL 2 input clock can be several different things. Currently hard coded by this init funciton to use +// * PLL 1 output (VCXO Frequency) with no scaling +// */ +// pll2InputFreq_Hz = device->pll1Settings->vcxo_Frequency_Hz; +// validPll2DivSetting = 0; +// +// /* Sweep PLL2 Divider settings to find something that has a valid integer divide (3,4,5)*/ +// for (pll2RfDiv = 3; pll2RfDiv <= 5; pll2RfDiv++) +// { +// +// pll2NdivStart = (PLL2_MIN_VCO_FREQ_HZ / pll2RfDiv / pll2InputFreq_Hz); +// /* find valid PLL2 Ndiv (1-256) */ +// for (pll2Ndiv = pll2NdivStart; pll2Ndiv <= 256; pll2Ndiv++) +// { +// pll2VcoFreq_Hz = (pll2InputFreq_Hz * pll2RfDiv * pll2Ndiv); +// +// if (pll2VcoFreq_Hz < PLL2_MIN_VCO_FREQ_HZ) +// { +// /* Continue to next PLL2 N div */ +// continue; +// } +// else if (pll2VcoFreq_Hz > PLL2_MAX_VCO_FREQ_HZ) +// { +// /* Break to next PLL2 RF div */ +// break; +// } +// +// if (((pll2VcoFreq_Hz / pll2RfDiv) % outputDeviceClock_Hz) == 0) +// { +// +// device->pll2Settings->rfDivider = pll2RfDiv; +// device->pll2Settings->n2Divider = pll2Ndiv; +// device->pll2Settings->totalNdiv = pll2RfDiv * pll2Ndiv; +// chDivU64 = ((pll2VcoFreq_Hz / pll2RfDiv) / outputDeviceClock_Hz); +// +// if ((chDivU64 < 1) || (chDivU64 > 256)) +// { +// return ADIERR_INV_PARM; +// } +// else +// { +// chDiv = (uint16_t)(chDivU64); +// } +// +// validPll2DivSetting = 1; +// break; +// } +// } +// +// if (validPll2DivSetting == 1) +// { +// break; +// } +// } +// +// if (validPll2DivSetting == 0) +// { +// return ADIERR_INV_PARM; +// } +// +// device->outputSettings->outPowerDown = (uint16_t)(~0x300A); //enable outputs 13,12,3 and 1 +// +// for (i=0; i<14; i++){ +// device->outputSettings->outSource[i] = CHANNEL_DIV; //CHANNEL_DIV , PLL1_OUTPUT, SYSREF, INV_PLL1_OUTPUT +// device->outputSettings->outBufferCtrl[i] = LVDS; //LVDS, LVDS_BOOST, HSTL +// device->outputSettings->outChannelDiv[i] = chDiv; +// device->outputSettings->outFrequency_Hz[i] = outputDeviceClock_Hz; +// device->outputSettings->outAnalogDelay[i] = 0; +// device->outputSettings->outDigitalDelay[i] = 0; +// } +// +// +// device->outputSettings->outSource[3] = SYSREF; +// device->outputSettings->outSource[12] = SYSREF; +// +// +// device->sysrefSettings->sysrefDivide = 512; //SYSREF frequency = VCXO / 2 / sysrefDivde +// device->sysrefSettings->sysrefNshotMode = ONE_PULSE; //ONE_PULSE=0, TWO_PULSES=2, FOUR_PULSES=3, SIX_PULSES=4, EIGHT_PULSES=5 +// device->sysrefSettings->sysrefPatternMode = NSHOT; //NSHOT=0, CONTINUOUS=1, PRBS=2, STOP=3 +// device->sysrefSettings->sysrefPinBufferMode = DISABLED; //DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL +// device->sysrefSettings->sysrefPinEdgeMode = LEVEL_ACTIVE_HIGH; //LEVEL_ACTIVE_HIGH=0, LEVEL_ACTIVE_LOW=1, RISING_EDGE=2, FALLING_EDGE=3 +// device->sysrefSettings->sysrefRequestMethod = SPI; //SPI=0,PIN=1 +// device->sysrefSettings->sysrefSource = INTERNAL; //EXTERNAL=0, EXT_RESAMPLED=1, INTERNAL=2 + return ADIERR_OK; +} + +/** + * \brief Debug function to print out summary of AD9528 setup + * + * \param device AD9528 Device data structure describing setup of device. + * + * \return Returns enum ADI_ERR, 0=pass, >0 = fail +***********************************************************************************/ +ADI_ERR AD9528_reportClockRates(ad9528Device_t *device) +{ + + return ADIERR_OK; +} //debug function to help verify data structure is setup correctly. + +/** + * \brief Initializes the AD9528 by writing all SPI registers + * + * Initializes the AD9528 for use with the AD9369 transceiver. Designed to work with + * a reference clock of 122.88MHz. Reference clock is expected to be 30.72MHz. + * The output clocks from the AD9528 can run at 122.88M, 153.6M, 184.32M, 245.76M, or 307.2M. + * Typical setup: REFA frequency = 30.72, VCXO = 122.88MHz + * SYNC(SYSREF) pulses output at rate of 120kHz + * + * Dependencies + * - All parameters in device structure + * + * \param device is structure pointer to AD9528 clock device structure + * + * \return Returns enum ADI_ERR, 0=pass, >0 = fail + */ +ADI_ERR AD9528_initialize(ad9528Device_t *device) { //writes all registers to desired values, leaves clock outputs off, SYSREF output disabled. + uint8_t pll2_Adiv=0; + uint8_t pll2_Bdiv=0; + uint8_t reg108=0; + uint8_t reg109=0; + uint8_t i = 0; + uint8_t j = 0; + uint8_t reg508; + ADI_ERR retval = ADIERR_OK; + + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, ADIERR_OK, "\n// AD9528_initialize\n"); + + //CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_A, 0x18); //[4] and [3] =1 enable 4 wire SPI + //CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_ADI_SPI_CONFIG_B, 0x00); + retval = AD9528_setSpiSettings(device); + if (retval != ADIERR_OK) + { + return retval; + } + + /********************************************************************** + * Configure PLL1 + ********************************************************************** + */ + + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_A_DIVIDER_LSB, + device->pll1Settings->refA_Divider & 0xFF); //REF A div[7:0] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_A_DIVIDER_MSB, + (device->pll1Settings->refA_Divider >> 8) & 0x03); //REF A div[9:8] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_B_DIVIDER_LSB, + device->pll1Settings->refB_Divider & 0xFF); //REF B div[7:0] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_REF_B_DIVIDER_MSB, + (device->pll1Settings->refB_Divider >> 8) & 0x03); //REF B div[9:8] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_N_DIV_LSB, + device->pll1Settings->nDivider & 0xFF); //PLL1 N div[7:0] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_N_DIV_MSB, + (device->pll1Settings->nDivider >> 8) & 0x03); //PLL1 N div[9:8] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_CHARGEPUMP, + 0x0A); //PLL1 Charge Pump control 1 + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_CP_CTRL2, + 0x03); //PLL1 Charge Pump control 2 + + switch (device->pll1Settings->refA_bufferCtrl){ + case DISABLED: + reg108 &= ~0x28; + reg109 &= ~0x01; + break; //clear all REFA enable bits + case SINGLE_ENDED: + reg108 |= 0x08; + reg109 &= ~0x01; + break; //Set REFA receiver enable, clear REFA SE negative input enable + case NEG_SINGLE_ENDED: + reg108 |= 0x08; + reg108 &= ~0x10; + reg109 |= 0x01; + break; //Disable REFA diff receiver, enable REFA receiver and use negative REFA input + case DIFFERENTIAL: + reg108 |= 0x28; + reg109 &= ~0x01; + break; + default: + reg108 |= 0x08; + reg109 &= ~0x01; + break; //default to single ended case + } + switch (device->pll1Settings->refB_bufferCtrl){ + case DISABLED: + reg108 &= ~0x50; + reg109 &= ~0x02; + break; //clear all REFB enable bits + case SINGLE_ENDED: + reg108 |= 0x10; + reg109 &= ~0x02; + break; //Set REFB receiver enable, clear REFB SE negative input enable + case NEG_SINGLE_ENDED: + reg108 |= 0x10; + reg108 &= ~0x40; + reg109 |= 0x02; + break; //Disable REFB diff receiver, enable REFB receiver and use negative REFB input + case DIFFERENTIAL: + reg108 |= 0x50; + reg109 &= ~0x02; + break; + default: + reg108 |= 0x10; + reg109 &= ~0x02; + break; //default to single ended case + } + switch (device->pll1Settings->vcxoBufferCtrl){ + case DISABLED: + reg108 &= ~0x03; + reg108 |= 0x04; + break; //power down VCXO input + case SINGLE_ENDED: + reg108 &= ~0x07; + break; //Clear VCXO receiver power down, defaults to Single ended mode + case NEG_SINGLE_ENDED: + reg108 &= ~0x07; + reg108 |= 0x02; + break; //Clear VCXO power down, enable Negative single ended mode[1] + case DIFFERENTIAL: + reg108 &= ~0x07; + reg108 |= 0x01; + break; //Clear VCXO power down, enable differential input buffer[0] + default: + reg108 &= ~0x07; + break; //default to positive single ended case + } + + + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_INPUT_RECEIVERS1, + reg108); //Input receiver settings (single ended or differential clock inputs) + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_INPUT_RECEIVERS2, + reg109); //Input receiver settings + + + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_INPUT_RECEIVERS3, + 0x0A); //Reference selection mode + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL1_FASTLOCK, + 0x00); //Disable Fast lock + + /********************************************************************** + * Configure PLL2 + ********************************************************************** + */ + pll2_Bdiv = device->pll2Settings->totalNdiv / 4; + pll2_Adiv = device->pll2Settings->totalNdiv % 4; + + if (pll2_Adiv > 3) { //A div valid range (0 to 3) + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, ADIERR_INV_PARM, "\n// AD9528 PLL2 A Divider out of range (0 to 3)\n"); + return ADIERR_INV_PARM; + } + if (pll2_Bdiv < 3 || pll2_Bdiv > 63) { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, ADIERR_INV_PARM, "\n// AD9528 PLL2 B Divider out of range (3 to 63)\n"); + return ADIERR_INV_PARM; + } + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_CHARGEPUMP, + 0xE6); //PLL2 Charge Pump[7:0] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_N_DIV, + ((pll2_Adiv & 0x3) << 6) | (pll2_Bdiv & 0x3F)); //PLL2 A and B divider + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_CTRL, 0x03); //PLL2 control + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_VCO_CTRL, 0x01); //Manual VCO CAL + + if (device->pll2Settings->rfDivider < 3 || device->pll2Settings->rfDivider > 5) { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, ADIERR_INV_PARM, "\n// AD9528 PLL2 RF Divider out of range (3,4, or 5)\n"); + return ADIERR_INV_PARM; + } + + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_VCO_DIV, + device->pll2Settings->rfDivider); //VCO divider + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_LF_CTRL1, + 0x3A); //PLL2 Loop filter [7:0] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_LF_CTRL2, + 0x00); //PLL2 Loop filter [8] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_RDIV, + 0x00); //R divider + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_REPLICA_CHDIV, + (device->pll2Settings->totalNdiv / device->pll2Settings->rfDivider) + -1 ); //Replica channel divider: Ndivider = rfDivider * R divider + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_PLL2_REPLICA_DIV_PHASE, + 0x00); //Replica Channel Divider phase + + /********************************************************************** + * Configure Output Distribution + ********************************************************************** + */ + for (i=0; i<14; i=i+1){ + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_OUT0_CTRL1 + j, + ((device->outputSettings->outSource[i] & 0x7) << 5) | + (device->outputSettings->outAnalogDelay[i] & 0x1F)); + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_OUT0_CTRL2 + j, + ((device->outputSettings->outBufferCtrl[i] & 0x3) << 6) | + (device->outputSettings->outDigitalDelay[i] & 0x3F)); + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_OUT0_CHDIV + j, + device->outputSettings->outChannelDiv[i]-1); + j = j+3; + } + + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_OUTPUT_SYNC, 0x00); //Sync outputs + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_MASK_SYNC1, 0x00); //Mask SYNC[7:0] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_MASK_SYNC2, 0x00); //Mask SYNC[13:8] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_EN_OUTPUT_PATH_SEL1, + 0x00); //Bypass SYSREF resample [6:0], bit0:Enable VCXO to feed output distrubution + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_EN_OUTPUT_PATH_SEL2, + 0x00); //Bypass SYSREF resample [13:7] + + /********************************************************************** + * Configure SYSREF operation + ********************************************************************** + */ + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSERF_DIV_LSB, + device->sysrefSettings->sysrefDivide & 0xFF); //SYSREF divider [7:0] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSERF_DIV_MSB, + (device->sysrefSettings->sysrefDivide >> 8) & 0xFF); //SYSREF divider [7:0] + + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL3, + ((device->sysrefSettings->sysrefRequestMethod & 0x1) << 7) | + ((device->sysrefSettings->sysrefPinEdgeMode & 0x3) << 5) ); + + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, + ((device->sysrefSettings->sysrefSource & 0x03) << 6) | + ((device->sysrefSettings->sysrefPatternMode & 0x3) << 4 ) | + ((device->sysrefSettings->sysrefNshotMode & 0x7) << 1) ); + + if(device->sysrefSettings->sysrefPinBufferMode == DISABLED) + { + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5, + 0x04); //power down input buffer for external SYSREF + } + else if(device->sysrefSettings->sysrefPinBufferMode == SINGLE_ENDED) + { + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5, + 0x00); //enable positive singled ended input + } + else if(device->sysrefSettings->sysrefPinBufferMode == NEG_SINGLE_ENDED) + { + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5, + 0x02); //enable negative singled ended input + } + else if(device->sysrefSettings->sysrefPinBufferMode == DIFFERENTIAL) + { + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5, + 0x01); //enable differential input buffer + } + else + { + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL5, + 0x04); //power down input buffer for external SYSREF + } + + /********************************************************************** + * Power down control + ********************************************************************** + */ + + if (device->pll1Settings->bypassPll1 > 0) + { + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_POWERDOWN_CTRL, + 0x14);// power up PLL2 and output distribution, power down PLL1 + } + else + { + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_POWERDOWN_CTRL, + 0x10);// power up PLL1, PLL2 and output distribution + } + + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN1, + device->outputSettings->outPowerDown & 0xFF); //power down out[7:0] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN2, + ((device->outputSettings->outPowerDown >> 8) & 0x3F)); //power down out[13:8] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_LDO_ENABLES1, + 0xFF); //LDO enable per output channel [7:0] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_LDO_ENABLES2, + 0xFF); //LDO enable per output channel [15:8] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_STATUS0_CTRL, + 0x07); //STATUS 0 outputs REFA present + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_STATUS1_CTRL, + 0x01); //STATUS 1 outputs PLL1 and PLL2 locked + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_STATUS_OE, + 0x0C);// Make Status0 and Status1 outputs after reset. + + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE, + 0x01); //IO update to make all these settings valid in the 9528 + + CMB_setTimeout_ms(1000); + do{ + CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, ®508); + if(CMB_hasTimeoutExpired() > 0) + { + return ADIERR_FAILED; + } + }while((reg508 & 0xA2) != 0xA2); + + return ADIERR_OK; +} + +/// Send a SPI message to request a SYSREF pulse or continuous SYSREF from the AD9528. +/*******************************************************************************//** + * Requests a SYSREF from the AD9528. It will use whatever settings for SYSREF + * that are current configured in the AD9528. This could be a single pulse, + * multiple pulses, or continuous pulses. + * Dependencies + * - device->spiSettings + * - device->sysrefSettings->sysrefPatternMode + * + * \param device is structure pointer to AD9528 clock device structure + * \param enableSYSREF If NSHOT SYSREF mode, this parameter is ignored. If PRBS/CONTINUOUS SYSREF mode, 1= enable SYSREF, 0= disable SYSREF. + * + * \return Returns enum ADI_ERR, 0=pass, >0 = fail + ***********************************************************************************/ +ADI_ERR AD9528_requestSysref(ad9528Device_t *device, uint8_t enableSYSREF){ + uint8_t _enableSYSREF=0; + + if (device->sysrefSettings->sysrefPatternMode == NSHOT || enableSYSREF > 0) + { + _enableSYSREF = 1; + } + else + { + _enableSYSREF = 0; + } + + CMB_SPIWriteField(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, _enableSYSREF, 0x01, 0x00); //Set SPI SYSREF request bit + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE, 0x01); //IO update to make all these settings valid in the 9528 + + return ADIERR_OK; +} + +/// Allow changing the 9528 SYSREF frequency and pattern mode(CONTINUOUS, PRBS vs NSHOT mode) +/*******************************************************************************//** + * NOTE: this function will update the device structure with the parameter values passed + * into this function. The device->sysrefSettings->sysrefPatternMode, device->sysrefSettings->sysrefNshotMode, + * and device->sysrefSettings->sysrefDivide values will be updated in the device structure. + * + * Dependencies + * - device->spiSettings + * + * \param device is structure pointer to AD9528 clock device structure + * \param divideFromPll1Out Sets the SYSREF pulse frequency. SYSREF frequency = PLL1_VCXO frequency/divideFromPll1Out + * \param sysrefPatternMode Valid settings: NSHOT, CONTINUOUS, PRBS, STOP + * \param nShotPulses Valid settings: ONE_PULSE=0, TWO_PULSES=2, FOUR_PULSES=3, SIX_PULSES=4, EIGHT_PULSES=5 + * + * \return Returns enum ADI_ERR, 0=pass, >0 = fail + ***********************************************************************************/ +ADI_ERR AD9528_setupSYSREF(ad9528Device_t *device, uint16_t divideFromPll1Out, sysrefPatternMode_t sysrefPatternMode, sysrefNshotMode_t nShotPulses) +{ + uint8_t reg403=0; + + device->sysrefSettings->sysrefPatternMode = sysrefPatternMode; + device->sysrefSettings->sysrefNshotMode = nShotPulses; + device->sysrefSettings->sysrefDivide = divideFromPll1Out >> 1; //SYSREF frequency is (PLL1)VCXO frequency / 2 / device->sysrefSettings->sysrefDivide + + CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, ®403); + + reg403 = reg403 & ~0x01; //clear bit 0 to stop a continuous sysref if it is on. + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, reg403); + + reg403 = reg403 & ~0x3E; //clear bits for pattern mode and Nshot mode bitfields + reg403 = reg403 | ((sysrefPatternMode & 0x3) << 4) | ((nShotPulses & 0x7) << 1); + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_SYSREF_CTRL4, reg403); //update internal sysref pattern mode and Nshot mode (number of pulses) + + //SYSREF request bit x403[0] is left 0. The next call to AD9528_requestSysref will start the SYSREF + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE, 0x01); //IO update to make all these settings valid in the 9528 + + + return ADIERR_OK; +} + +/// Update the AD9528 clock outputs that are enabled. +/*******************************************************************************//** + * NOTE: this function will update the device structure with the parameter values passed + * into this function. The device->sysrefSettings->sysrefPatternMode, device->sysrefSettings->sysrefNshotMode, + * and device->sysrefSettings->sysrefDivide values will be updated in the device structure. + * + * Dependencies + * - device->spiSettings + * + * \param device is structure pointer to AD9528 clock device structure + * \param clkEnable Sets which clock outputs are enabled. Bit per clock output. bit0 = out0, etc. + * + * \return Returns enum ADI_ERR, 0=pass, >0 = fail + ***********************************************************************************/ +ADI_ERR AD9528_enableClockOutputs(ad9528Device_t *device, uint16_t clkEnable) +{ //clkEnable: bit per clock output + + device->outputSettings->outPowerDown = ~clkEnable; + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN1, device->outputSettings->outPowerDown & 0xFF); //power down out[7:0] + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_CH_POWERDOWN2, ((device->outputSettings->outPowerDown >> 8) & 0x3F)); //power down out[13:8] + + CMB_SPIWriteByte(device->spiSettings, AD9528_ADDR_IO_UPDATE, 0x01); //IO update to make all these settings valid in the 9528 + return ADIERR_OK; +} + +/// Waits for PLL1 and PLL2 to lock and the REFA and VCXO clocks to be present +/*******************************************************************************//** + * Waits until Reference A clock and VCXO clock input to be detected (present), + * and PLL1 and PLL2 to lock. Will timeout after 1 second and return ADIERR_FAILED. + * If clock are detected and PLLs locked, returns ADIERR_OK. + * + * Dependencies + * - device->spiSettings + * + * \param device is structure pointer to AD9528 clock device structure + * + * \return Returns enum ADI_ERR, 0=pass, >0 = fail + ***********************************************************************************/ +ADI_ERR AD9528_waitForPllLock(ad9528Device_t *device) +{ + uint8_t reg508; + + CMB_setTimeout_ms(1000); + do{ + CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, ®508); + if(CMB_hasTimeoutExpired() > 0) + { + return ADIERR_FAILED; + } + }while((reg508 & 0x27) != 0x27); + + return ADIERR_OK; +} + +/// Reads the Lock Status of the PLLs and present detect of the reference clocks +/*******************************************************************************//** + * NOTE: This is a non blocking function that reads a register to see if PLL1 + * and PLL2 are locked and Reference clock A and the VCXO input clock are + * detected (present). If the *status parameter is not NULL, the status will + * be returned. If *status is NULL, the error return value will denote if + * the PllStatus is locked or not with ADIERR_OK or ADIERR_FAILED. + * + * Dependencies + * - device->spiSettings + * + * \param device is structure pointer to AD9528 clock device structure + * + * \return Returns enum ADI_ERR, 0=pass, >0 = fail + ***********************************************************************************/ +ADI_ERR AD9528_readPllStatus(ad9528Device_t *device, uint8_t *status) +{ + uint8_t reg508; + + //bit5 is VCXO clock detected + //bit2 is REFCLK A detected + //bit1 is PLL2 lock detect + //bit0 is PLL1 lock detect + + /* read twice to refresh status bits */ + CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, ®508); + CMB_SPIReadByte(device->spiSettings, AD9528_ADDR_STATUS_READBACK0, ®508); + /* if status is a valid pointer, return the PLL status */ + if (status > 0) + { + *status = reg508; + } + + /* PLLs 1 and 2 are locked and VCXO and REFA detected if reg508 has bits 5,2,1 and 0 set */ + if((reg508 & 0x27) == 0x27) + return ADIERR_OK; + else + return ADIERR_FAILED; +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/ad9528.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/ad9528.h new file mode 100644 index 00000000..b7e6cfea --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/ad9528.h @@ -0,0 +1,44 @@ +/** + * \file ad9528.h + * \brief Contains function declarations and ad9528Device_t structure typedef for ad9528.c + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#ifndef _AD9528_LIB_H_ +#define _AD9528_LIB_H_ + +#include +#include "../common.h" +#include "t_ad9528.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define CLEMENTE_TDD_AD9528_CLKOUT_INDEX 13 + +//Helper function to setup the 9528 device data structure specifically for the ADI transceiver evaluation cards +ADI_ERR AD9528_initDeviceDataStruct(ad9528Device_t *device, uint32_t vcxoFrequency_Hz, uint32_t refAFrequency_Hz, uint32_t outputDeviceClock_Hz); +ADI_ERR AD9528_reportClockRates(ad9528Device_t *device); //debug function to help verify data structure is setup correctly. + +//AD9528 API functions +ADI_ERR AD9528_resetDevice(ad9528Device_t *device); +ADI_ERR AD9528_setSpiSettings(ad9528Device_t *device); +ADI_ERR AD9528_initialize(ad9528Device_t *device); //writes all registers to desired values, leaves clock outputs off. +ADI_ERR AD9528_waitForPllLock(ad9528Device_t *device); +ADI_ERR AD9528_readPllStatus(ad9528Device_t *device, uint8_t *status); +ADI_ERR AD9528_enableClockOutputs(ad9528Device_t *device, uint16_t clkEnable); //clkEnable: bit per clock output +ADI_ERR AD9528_setupSYSREF(ad9528Device_t *device, uint16_t divideFromPll1Out, sysrefPatternMode_t sysrefPatternMode, sysrefNshotMode_t nShotPulses); +ADI_ERR AD9528_requestSysref(ad9528Device_t *device, uint8_t enableSYSREF); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos.c b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos.c new file mode 100644 index 00000000..c8db0e3e --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos.c @@ -0,0 +1,18444 @@ +/** + *\file mykonos.c + * + *\brief Contains Mykonos APIs for transceiver configuration and control + * + * Mykonos API version: 1.5.2.3566 + */ + +/** + * \mainpage Overview + * + * This document is intended for use by software engineering professionals and + * includes detailed information regarding the data types and function calls + * which comprise the Mykonos ANSI C API. + * References to "Mykonos" in the API refer to the Analog Devices development name for the AD9371 family of devices. + * + */ + +/** + * \page Use Suggested Use + * The purpose of this API library is to add abstraction for the low level + * SPI control and calculations necessary to control the Mykonos family of transceiver devices + * + * Add the included source code as required to your baseband processor software build. Please reference the integration document + * as well for further instructions. + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#include +#include +#include "../common.h" +#include "mykonos.h" +#include "mykonos_gpio.h" +#include "mykonos_macros.h" +#include "mykonos_user.h" + +/* Private helper functions local to this file */ +static mykonosErr_t MYKONOS_calculateScaledDeviceClk_kHz(mykonosDevice_t *device, uint32_t *scaledRefClk_kHz, uint8_t *deviceClkDiv); +static mykonosErr_t MYKONOS_calculateDigitalClocks(mykonosDevice_t *device, uint32_t *hsDigClk_kHz, uint32_t *hsDigClkDiv4or5_kHz); +static mykonosErr_t enableDpdTracking(mykonosDevice_t *device, uint8_t tx1Enable, uint8_t tx2Enable); +static mykonosErr_t enableClgcTracking(mykonosDevice_t *device, uint8_t tx1Enable, uint8_t tx2Enable); + +/** + * \brief Verifies the Tx profile members are valid (in range) in the init structure + * + * If the Tx profile IQ data rate = 0, it is assumed that the Tx profile is + * not used. If Tx IQ data rate > 0, and Tx profile members are out of range, + * + * \pre This function is private and is not called directly by the user. + * + * Dependencies + * - device->tx->txProfile + * + * \param device Structure pointer to Mykonos device data structure + * \param txProfile txProfile settings to be verified + * \param txHsDigClk_kHz Return value of the calculated HS Dig Clock required by the Tx profile + * + * \retval MYKONOS_ERR_TXPROFILE_IQRATE Profile IQ rate out of range + * \retval MYKONOS_ERR_TXPROFILE_RFBW Tx Profile RF bandwidth out of range + * \retval MYKONOS_ERR_TXPROFILE_FILTER_INTERPOLATION Filter interpolation not valid + * \retval MYKONOS_ERR_TXPROFILE_FIR_INT FIR filter not valid + * \retval MYKONOS_ERR_OK All profile members are valid + */ +static mykonosErr_t mykVerifyTxProfile(mykonosDevice_t *device, mykonosTxProfile_t *txProfile, uint32_t *txHsDigClk_kHz) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + + *txHsDigClk_kHz = 0; + + /********************************/ + /* Check for a valid Tx profile */ + /********************************/ + + if ((txProfile->iqRate_kHz < MIN_TX_IQRATE_KHZ) || (txProfile->iqRate_kHz > MAX_TX_IQRATE_KHZ)) + { + return MYKONOS_ERR_TXPROFILE_IQRATE; + } + + if ((txProfile->rfBandwidth_Hz < MIN_TX_RFBW_HZ) || (txProfile->rfBandwidth_Hz > MAX_TX_RFBW_HZ)) + { + return MYKONOS_ERR_TXPROFILE_RFBW; + } + + if ((txProfile->thb1Interpolation != 1) && (txProfile->thb1Interpolation != 2)) + { + return MYKONOS_ERR_TXPROFILE_FILTER_INTERPOLATION; + } + + if ((txProfile->thb2Interpolation != 1) && (txProfile->thb2Interpolation != 2)) + { + return MYKONOS_ERR_TXPROFILE_FILTER_INTERPOLATION; + } + + if ((txProfile->txFirInterpolation != 1) && (txProfile->txFirInterpolation != 2) && (txProfile->txFirInterpolation != 4)) + { + return MYKONOS_ERR_TXPROFILE_FILTER_INTERPOLATION; + } + + if ((txProfile->txFir->coefs == NULL) && (txProfile->txFirInterpolation != 1)) + { + return MYKONOS_ERR_TXPROFILE_FIR_COEFS; + } + + if ((txProfile->dacDiv != DACDIV_2) && (txProfile->dacDiv != DACDIV_2p5) && (txProfile->dacDiv != DACDIV_4)) + { + return MYKONOS_ERR_TXPROFILE_DACDIV; + } + + *txHsDigClk_kHz = (txProfile->iqRate_kHz * txProfile->txFirInterpolation * txProfile->thb1Interpolation * txProfile->thb2Interpolation * (uint32_t)txProfile->dacDiv); + + device->profilesValid |= TX_PROFILE_VALID; + + return retVal; +} + +/** + * \brief Verifies the Rx profile members are valid (in range) and calculates HS Dig Clock require for the Rx Profile + * + * Private helper function to verify the Rx profile members are valid (in range) + * and calculates HS Dig Clock require for the Rx Profile + * If the Rx profile IQ data rate = 0, it is assumed that the Rx profile is + * not used. If Rx IQ data rate > 0, and Rx profile members are out of range. + * + * \pre This function is private and is not called directly by the user. + * + * Dependencies + * - device->rx->rxProfile + * + * \param device Structure pointer to Talise device data structure + * \param rxChannel receiver channel to be checked + * \param rxProfile rxProfile settings to be verified + * \param rxHsDigClk_kHz Return value of the calculated HS Dig Clock required by the Rx profile + * + * \retval MYKONOS_ERR_RXPROFILE_RXCHANNEL Rx channel is not valid. + * \retval MYKONOS_ERR_RXPROFILE_IQRATE out of range IQ rate + * \retval MYKONOS_ERR_RXPROFILE_RFBW out of range RF bandwidth + * \retval MYKONOS_ERR_RXPROFILE_FILTER_DECIMATION not valid filter decimation setting + * \retval MYKONOS_ERR_RXPROFILE_FIR_COEFS FIR filter not valid + * \retval MYKONOS_ERR_RXPROFILE_ADCDIV not valid ADC divider + * \retval MYKONOS_ERR_OK all profile members are valid + */ +static mykonosErr_t mykVerifyRxProfile(mykonosDevice_t *device, mykonosRxProfType_t rxChannel, mykonosRxProfile_t *rxProfile, uint32_t *rxHsDigClk_kHz) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint32_t minBwHz = 0; + uint32_t maxBwHz = 0; + + *rxHsDigClk_kHz = 0; + + switch (rxChannel) + { + case MYK_RX_PROFILE: + minBwHz = MIN_RX_RFBW_HZ; + maxBwHz = MAX_RX_RFBW_HZ; + break; + case MYK_OBS_PROFILE: + minBwHz = MIN_ORX_RFBW_HZ; + maxBwHz = MAX_ORX_RFBW_HZ; + break; + case MYK_SNIFFER_PROFILE: + minBwHz = MIN_SNIFFER_RFBW_HZ; + maxBwHz = MAX_SNIFFER_RFBW_HZ; + break; + + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RXPROFILE_RXCHANNEL, + getMykonosErrorMessage(MYKONOS_ERR_RXPROFILE_RXCHANNEL)); + return MYKONOS_ERR_RXPROFILE_RXCHANNEL; + } + + /********************************/ + /* Check for a valid Rx profile */ + /********************************/ + if ((rxProfile->iqRate_kHz < MIN_RX_IQRATE_KHZ) || (rxProfile->iqRate_kHz > MAX_RX_IQRATE_KHZ)) + { + return MYKONOS_ERR_RXPROFILE_IQRATE; + } + + /* check for Rx/Obs or Sniffer BW */ + if ((rxProfile->rfBandwidth_Hz < minBwHz) || (rxProfile->rfBandwidth_Hz > maxBwHz)) + { + return MYKONOS_ERR_RXPROFILE_RFBW; + } + + if ((rxProfile->rhb1Decimation != 1) && (rxProfile->rhb1Decimation != 2)) + { + return MYKONOS_ERR_RXPROFILE_FILTER_DECIMATION; + } + + if ((rxProfile->rxDec5Decimation != 4) && (rxProfile->rxDec5Decimation != 5)) + { + return MYKONOS_ERR_RXPROFILE_FILTER_DECIMATION; + } + + if ((rxProfile->rxFirDecimation != 1) && (rxProfile->rxFirDecimation != 2) && (rxProfile->rxFirDecimation != 4)) + { + return MYKONOS_ERR_RXPROFILE_FILTER_DECIMATION; + } + + if ((rxProfile->rxFir->coefs == NULL) && (rxProfile->rxFirDecimation != 1)) + { + return MYKONOS_ERR_RXPROFILE_FIR_COEFS; + } + + if ((rxProfile->adcDiv != 1) && (rxProfile->adcDiv != 2)) + { + return MYKONOS_ERR_RXPROFILE_ADCDIV; + } + + *rxHsDigClk_kHz = (rxProfile->iqRate_kHz * rxProfile->rxFirDecimation * rxProfile->rhb1Decimation * rxProfile->rxDec5Decimation * rxProfile->adcDiv); + + switch (rxChannel) + { + case MYK_RX_PROFILE: + device->profilesValid |= RX_PROFILE_VALID; + break; + case MYK_OBS_PROFILE: + device->profilesValid |= ORX_PROFILE_VALID; + break; + /*case MYK_SNIFFER_PROFILE:*/ + default: + device->profilesValid |= SNIFF_PROFILE_VALID; + break; + } + + return retVal; +} + +/** + * \brief Performs a hard reset on the MYKONOS DUT (Toggles RESETB pin on device) + * + * Toggles the Mykonos devices RESETB pin. Only resets the device with + * the SPI chip select indicated in the device->spiSettings structure. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to Mykonos device data structure containing settings + * + * \return Returns enum mykonosErr_t, MYKONOS_ERR_OK=pass, !MYKONOS_ERR_OK=fail + */ +mykonosErr_t MYKONOS_resetDevice(mykonosDevice_t *device) +{ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_resetDevice()\n"); +#endif + + /* toggle RESETB on device with matching spi chip select index */ + CMB_hardReset(device->spiSettings->chipSelectIndex); + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads back the silicon revision for the Mykonos Device + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to Mykonos device data structure containing settings + * \param revision Return value of the Mykonos silicon revision + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getDeviceRev(mykonosDevice_t *device, uint8_t *revision) +{ +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getDeviceRev()\n"); +#endif + + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_PRODUCT_ID, revision, 0x07, 0); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads back the Product ID for the Mykonos Device + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to Mykonos device data structure containing settings + * \param productId Return value of the Mykonos product Id + * + * \retval MYKONOS_ERR_GETPRODUCTID__NULL_PARAM recovery action for bad parameter check + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getProductId(mykonosDevice_t *device, uint8_t *productId) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getProductId()\n"); +#endif + + if (productId == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETPRODUCTID_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETPRODUCTID_NULL_PARAM)); + return MYKONOS_ERR_GETPRODUCTID_NULL_PARAM; + } + + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_PRODUCT_ID, productId, 0xF8, 3); + + return retVal; +} + +/** + * \brief Get API version number + * + * This function reads back the version number of the API + * + * \param device Pointer to the Mykonos data structure + * \param siVer A pointer to the current silicon version number. + * \param majorVer A pointer to the current major version number. + * \param minorVer A pointer to the current minor version number. + * \param buildVer A pointer to the current build version number. + * + * \retval MYKONOS_ERR_GET_API_VERSION_NULL_PARAM Null parameter passed to the function. + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getApiVersion(mykonosDevice_t *device, uint32_t *siVer, uint32_t *majorVer, uint32_t *minorVer, uint32_t *buildVer) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getApiVersion()\n"); +#endif + + if ((siVer == NULL) || (majorVer == NULL) || (minorVer == NULL) || (buildVer == NULL)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_API_VERSION_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_GET_API_VERSION_NULL_PARAM)); + return MYKONOS_ERR_GET_API_VERSION_NULL_PARAM; + } + + *siVer = (uint32_t)MYKONOS_CURRENT_SI_VERSION; + *majorVer = (uint32_t)MYKONOS_CURRENT_MAJOR_VERSION; + *minorVer = (uint32_t)MYKONOS_CURRENT_MINOR_VERSION; + *buildVer = (uint32_t)MYKONOS_CURRENT_BUILD_VERSION; + return retVal; +} + +/** + * \brief Sets the Mykonos device SPI settings (3wire/4wire, MSBFirst, etc). + * + * This function will use the settings in the device->spiSettings structure + * to set SPI stream mode, address auto increment direction, MSBFirst/LSBfirst, + * and 3wire/4wire mode. The Mykonos device always uses SPI MODE 0 (CPHA=0, CPOL=0). + * This function will update your device->spiSettings to set CHPA=0 and CPOL=0 and + * longInstructionWord =1 to use a 16bit instruction word. + * + * Dependencies + * - writes device->spiSettings->CPHA = 0 + * - writes device->spiSettings->CPOL = 0 + * - writes device->spiSettings->longInstructionWord = 1 + * + * - device->spiSettings->MSBFirst + * - device->spiSettings->enSpiStreaming + * - device->spiSettings->autoIncAddrUp + * - device->spiSettings->fourWireMode + * + * \param device Pointer to Mykonos device data structure containing settings + * + * \return Returns enum mykonosErr_t, MYKONOS_ERR_OK=pass, !MYKONOS_ERR_OK=fail + */ +mykonosErr_t MYKONOS_setSpiSettings(mykonosDevice_t *device) +{ + //device->spiSettings->enSpiStreaming + uint8_t spiReg = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setSpiSettings()\n"); +#endif + + device->spiSettings->CPHA = 0; + device->spiSettings->CPOL = 0; + device->spiSettings->longInstructionWord = 1; + + if (device->spiSettings->MSBFirst == 0) + { + spiReg |= 0x42; /* SPI bit is 1=LSB first */ + } + + if (device->spiSettings->autoIncAddrUp > 0) + { + spiReg |= 0x24; + } + + if (device->spiSettings->fourWireMode > 0) + { + spiReg |= 0x18; + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CONFIGURATION_CONTROL_0, spiReg); + + if (device->spiSettings->enSpiStreaming > 0) + { + /* Allow SPI streaming mode: SPI message ends when chip select deasserts */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SPI_CONFIGURATION_CONTROL_1, 0x00); + } + else + { + /* Force single instruction mode */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SPI_CONFIGURATION_CONTROL_1, 0x80); + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Verifies the integrity of the Mykonos device data structure. + * + * The Mykonos device data structure has many pointers to other structures. The + * main purpose of this function to verify that the necessary pointers within the + * device data structure have non zero pointers. The focus is on the Rx/Tx/ObsRx + * profiles and FIR filters where if a channel is disabled, it may be valid for + * some pointers to be NULL. This function updates device->profileValid to remember + * which profile pointers are valid. + * profileValid[3:0] = {SnifferProfileValid, ObsRxProfileValid, RxProfileValid, TxProfileValid}; + * + * Dependencies + * - device (all variables) + * + * \param device Pointer to Mykonos device data structure containing settings + * + * \return Returns enum mykonosErr_t, MYKONOS_ERR_OK=pass, !MYKONOS_ERR_OK=fail + */ +mykonosErr_t MYKONOS_verifyDeviceDataStructure(mykonosDevice_t *device) +{ + if (device == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, 0, MYKONOS_ERR_CHECKDEVSTRUCT_NULLDEVPOINTER, getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_NULLDEVPOINTER)); + return MYKONOS_ERR_CHECKDEVSTRUCT_NULLDEVPOINTER; + } + + device->profilesValid = 0; /* Reset */ + + if (device->spiSettings == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, 0, MYKONOS_ERR_CHECKDEVSTRUCT_SPI, getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_SPI)); + return MYKONOS_ERR_CHECKDEVSTRUCT_SPI; + } + + /* place this writeToLog after verifying the spiSettings structure is not NULL */ +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_verifyDeviceDataStructure()\n"); +#endif + + /************************************************************************** + * Check Rx stucture pointers + ************************************************************************** + */ + if (device->rx == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CHECKDEVSTRUCT_RX, getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_RX)); + return MYKONOS_ERR_CHECKDEVSTRUCT_RX; + } + else + { + if (device->rx->rxChannels == RXOFF) + {/* If no Rx channel enabled, ok to have null pointers for rx gain control, framer, and Rx profile/Rx FIR Filter */ + } + else + { + if ((device->rx->framer == NULL) || (device->rx->rxGainCtrl == NULL) || (device->rx->rxProfile == NULL)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CHECKDEVSTRUCT_RXSUB, + getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_RXSUB)); + return MYKONOS_ERR_CHECKDEVSTRUCT_RXSUB; + } + + if ((device->rx->rxProfile->rxFir == NULL) && (device->rx->rxProfile->rxFirDecimation != 1)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CHECKDEVSTRUCT_RXFIR, + getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_RXFIR)); + return MYKONOS_ERR_CHECKDEVSTRUCT_RXFIR; + } + } + } + + /************************************************************************** + * Check Tx stucture pointers + ************************************************************************** + */ + if (device->tx == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CHECKDEVSTRUCT_TX, getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_TX)); + return MYKONOS_ERR_CHECKDEVSTRUCT_TX; + } + else + { + if (device->tx->txChannels == TXOFF) + {/* If no Tx channel enabled, ok to have null pointers for deframer, and Tx profile/Tx FIR filter */ + } + else + { + if ((device->tx->deframer == NULL) || (device->tx->txProfile == NULL)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CHECKDEVSTRUCT_TXSUB, + getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_TXSUB)); + return MYKONOS_ERR_CHECKDEVSTRUCT_TXSUB; + } + + if ((device->tx->txProfile->txFir == NULL) && (device->tx->txProfile->txFirInterpolation != 1)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CHECKDEVSTRUCT_TXFIR, + getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_TXFIR)); + return MYKONOS_ERR_CHECKDEVSTRUCT_TXFIR; + } + } + } + + /************************************************************************** + * Check ObsRx stucture pointers + ************************************************************************** + */ + if (device->obsRx == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CHECKDEVSTRUCT_OBSRX, + getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_OBSRX)); + return MYKONOS_ERR_CHECKDEVSTRUCT_OBSRX; + } + else + { + if (device->obsRx->obsRxChannelsEnable == MYK_OBS_RXOFF) + {/* If no ObsRx channel enabled, ok to have null pointers for ObsRx gain control, framer, and ObsRx profile/FIR Filter */ + } + else + { + if ((device->obsRx->framer == NULL)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CHECKDEVSTRUCT_OBSRXFRAMER, + getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_OBSRXFRAMER)); + return MYKONOS_ERR_CHECKDEVSTRUCT_OBSRXFRAMER; + } + + if (device->obsRx->snifferProfile != NULL) + { + if (device->obsRx->snifferGainCtrl == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CHECKDEVSTRUCT_SNIFFERGAINCTRL, + getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_SNIFFERGAINCTRL)); + return MYKONOS_ERR_CHECKDEVSTRUCT_SNIFFERGAINCTRL; + } + + if ((device->obsRx->snifferProfile->rxFir == NULL) && (device->obsRx->snifferProfile->rxFirDecimation != 1)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CHECKDEVSTRUCT_SNIFFERFIR, + getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_SNIFFERFIR)); + return MYKONOS_ERR_CHECKDEVSTRUCT_SNIFFERFIR; + } + } + + if (device->obsRx->orxProfile != NULL) + { + if (device->obsRx->orxGainCtrl == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CHECKDEVSTRUCT_ORXGAINCTRL, + getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_ORXGAINCTRL)); + return MYKONOS_ERR_CHECKDEVSTRUCT_ORXGAINCTRL; + } + + if ((device->obsRx->orxProfile->rxFir == NULL) && (device->obsRx->orxProfile->rxFirDecimation != 1)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CHECKDEVSTRUCT_ORXFIR, + getMykonosErrorMessage(MYKONOS_ERR_CHECKDEVSTRUCT_ORXFIR)); + return MYKONOS_ERR_CHECKDEVSTRUCT_ORXFIR; + } + } + } + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Initializes the Mykonos device based on the desired device settings. + * + * This function initializes the mykonos device, setting up the CLKPLL, digital clocks, + * JESD204b settings, FIR Filters, digital filtering. It does not load the ARM + * or perform any of the ARM init calibrations. It also sets the Rx Manual gain indexes and + * TxAttenuation settings to the initial values found in the device data structure. It leaves the + * Mykonos in a state ready for multichip sync (which can bring up the JESD204 links), the + * ARM to be loaded, and the init calibartions run. + * + * Dependencies + * - device (all variables) + * + * \param device Pointer to Mykonos device data structure containing settings + * + * \return Returns enum mykonosErr_t, MYKONOS_ERR_OK=pass, !MYKONOS_ERR_OK=fail + */ +mykonosErr_t MYKONOS_initialize(mykonosDevice_t *device) +{ + uint8_t txChannelSettings = 0; + uint8_t rxChannelSettings = 0; + uint8_t orxChannelSettings = 0; + uint8_t sniffChannelSettings = 0; + uint8_t adcDacClockRateSelect = 0; + uint8_t enableDpd = 0; + uint8_t obsRxRealIf = 0; + uint8_t enRxHighRejDec5 = 0; + uint8_t rxRealIfData = 0; + uint8_t txSyncb = 0x00; + uint8_t rxSyncb = 0x00; + uint8_t orxSyncb = 0x00; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_initialize()\n"); +#endif + + retVal = MYKONOS_verifyDeviceDataStructure(device); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Verify Rx/Tx and ObsRx profiles are valid combinations */ + retVal = MYKONOS_verifyProfiles(device); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Set 3 or 4-wire SPI mode, MSBFirst/LSBfirst in device, pushes CPOL=0, CPHA=0, longInstWord=1 into device->spiSettings */ + retVal = MYKONOS_setSpiSettings(device); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Increase SPI_DO drive strength */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DIGITAL_IO_CONTROL, 0x10); + + /* Enable Reference clock - Set REFCLK pad common mode voltage */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_REF_PAD_CONFIG2, 0x07); + + /* Set Mykonos IO pin settings, GPIO direction, enable relevant LVDS pads */ + /* Enable SYSREF LVDS input pad + 100ohm internal termination */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SYSREF_PAD_CONFIG, 0x12); //Enable SYSREF input buffer + + if ((device->tx > 0) && (device->tx->txProfile > 0)) + { + /* Check for LVDS/CMOS mode */ + if (device->tx->deframer->txSyncbMode > 0) + { + txSyncb = 0xF0; + } + else + { + txSyncb = 0x02; + } + + /* Enable SYNCOUTB output buffer */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX1_SYNC_PAD_CONFIG, txSyncb); + } + + /* Look at each framer and enable the RXSYNCB used for each framer. + * It is possible that they use the same RXSYNCB pin */ + if ((device->rx > 0) && (device->rx->framer > 0)) + { + /* Check for LVDS/CMOS mode */ + if (device->rx->framer->rxSyncbMode > 0) + { + rxSyncb = 0x00; + } + else + { + rxSyncb = 0x12; + } + + if (device->rx->framer->obsRxSyncbSelect == 0) + { + /* Enable SYNCINB0 LVDS/CMOS input buffer */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX1_SYNC_CONFIG, rxSyncb); + } + else + { + /* Enable SYNCINB1 LVDS/CMOS input buffer */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX2_SYNC_CONFIG, rxSyncb); + } + } + if ((device->obsRx > 0) && (device->obsRx->framer > 0)) + { + /* Check for LVDS/CMOS mode */ + if (device->obsRx->framer->rxSyncbMode > 0) + { + orxSyncb = 0x00; + } + else + { + orxSyncb = 0x12; + } + + if (device->obsRx->framer->obsRxSyncbSelect == 0) + { + /* Check for rxSyncb and orxSyncb when using the same RXSYNCB */ + if ((orxSyncb != rxSyncb) && (device->rx->framer->obsRxSyncbSelect == 0)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_RXSYNCB_ORXSYNCB_MODE, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_RXSYNCB_ORXSYNCB_MODE)); + return MYKONOS_ERR_INIT_INV_RXSYNCB_ORXSYNCB_MODE; + } + + /* Enable SYNCINB0 LVDS input buffer */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX1_SYNC_CONFIG, orxSyncb); + } + else + { + /* Check for rxSyncb and orxSyncb when using the same ORXSYNCB */ + if ((orxSyncb != rxSyncb) && (device->rx->framer->obsRxSyncbSelect == 1)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_RXSYNCB_ORXSYNCB_MODE, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_RXSYNCB_ORXSYNCB_MODE)); + return MYKONOS_ERR_INIT_INV_RXSYNCB_ORXSYNCB_MODE; + } + + /* Enable SYNCINB1 LVDS input buffer */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX2_SYNC_CONFIG, orxSyncb); + } + } + + /* Set number of device clock cycles per microsecond [round(freq/2) - 1] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_REFERENCE_CLOCK_CYCLES, (uint8_t)((((device->clocks->deviceClock_kHz / 1000) + 1) >> 1) - 1)); + + /* Set profile specific digital clock dividers */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CONFIGURATION_CONTROL_1, 0x04); /* Negate Rx2 so phase matches Rx1 */ + + if (device->profilesValid & TX_PROFILE_VALID) + { + txChannelSettings = (((uint8_t)device->tx->txChannels & 0x3) << 6); + switch (device->tx->txProfile->thb2Interpolation) + { + case 1: + break; /* keep bit as 0 in bitfield */ + case 2: + txChannelSettings |= 0x20; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_TXHB2_INTERPOLATION, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_TXHB2_INTERPOLATION)); + return MYKONOS_ERR_INIT_INV_TXHB2_INTERPOLATION; + } + + switch (device->tx->txProfile->thb1Interpolation) + { + case 1: + break; /* keep bit as 0 in bitfield */ + case 2: + txChannelSettings |= 0x10; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_TXHB1_INTERPOLATION, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_TXHB1_INTERPOLATION)); + return MYKONOS_ERR_INIT_INV_TXHB1_INTERPOLATION; + } + + if (device->tx->txProfile->txFir == NULL) + { + /* If invalid pointer to FIR filter, Bypass programmable FIR, keep txChannelSettings[1:0] == 0 */ + } + else + { + switch (device->tx->txProfile->txFirInterpolation) + { + case 1: + txChannelSettings |= 0x01; + break; + case 2: + txChannelSettings |= 0x02; + break; + case 4: + txChannelSettings |= 0x03; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_TXFIR_INTERPOLATION, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_TXFIR_INTERPOLATION)); + return MYKONOS_ERR_INIT_INV_TXFIR_INTERPOLATION; + } + } + + switch (device->tx->txProfile->dacDiv) + { + case DACDIV_2: + break; /* Keep bit [1]=0 */ + case DACDIV_2p5: + break; /* Keep bit [1]=0, div 2.5 is set when Rx DEC5 filter enabled*/ + case DACDIV_4: + adcDacClockRateSelect |= 2; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_DACDIV, getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_DACDIV)); + return MYKONOS_ERR_INIT_INV_DACDIV; + } + } + + if (device->profilesValid & RX_PROFILE_VALID) + { + rxChannelSettings = (((uint8_t)device->rx->rxChannels & 0x3) << 6); + switch (device->rx->rxProfile->rxDec5Decimation) + { + case 4: + break; /* keep bit as 0 in bitfield */ + case 5: + rxChannelSettings |= 0x04; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_RXDEC5_DECIMATION, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_RXDEC5_DECIMATION)); + return MYKONOS_ERR_INIT_INV_RXDEC5_DECIMATION; + } + + switch (device->rx->rxProfile->rhb1Decimation) + { + case 1: + break; /* keep bit as 0 in bitfield */ + case 2: + rxChannelSettings |= 0x10; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_RXHB1_DECIMATION, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_RXHB1_DECIMATION)); + return MYKONOS_ERR_INIT_INV_RXHB1_DECIMATION; + } + + if (device->rx->rxProfile->rxFir == NULL) + { + /* If invalid pointer to FIR filter, Bypass programmable FIR, keep rxChannelSettings[1:0] == 0 */ + } + else + { + switch (device->rx->rxProfile->rxFirDecimation) + { + case 1: + rxChannelSettings |= 0x01; + break; + case 2: + rxChannelSettings |= 0x02; + break; + case 4: + rxChannelSettings |= 0x03; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_RXFIR_DECIMATION, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_RXFIR_DECIMATION)); + return MYKONOS_ERR_INIT_INV_RXFIR_DECIMATION; + } + } + + switch (device->rx->rxProfile->adcDiv) + { + case 1: + adcDacClockRateSelect |= 0; + break; + case 2: + adcDacClockRateSelect |= 1; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_ADCDIV, getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_ADCDIV)); + return MYKONOS_ERR_INIT_INV_ADCDIV; + } + + rxRealIfData = (device->rx->realIfData > 0) ? 1 : 0; + enRxHighRejDec5 = (device->rx->rxProfile->enHighRejDec5 > 0) ? 1 : 0; + } + else if (device->profilesValid & ORX_PROFILE_VALID) + { + /* if Rx profile not valid, but ORX profile valid, set RX ADC divider and dec5 to match orx profile setting */ + /* ARM clock is derived from Rx clocking, so Rx ADC div needs to be set */ + switch (device->obsRx->orxProfile->rxDec5Decimation) + { + case 4: + break; /* keep bit as 0 in bitfield */ + case 5: + rxChannelSettings |= 0x04; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_RXDEC5_DECIMATION, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_RXDEC5_DECIMATION)); + return MYKONOS_ERR_INIT_INV_RXDEC5_DECIMATION; + } + + switch (device->obsRx->orxProfile->adcDiv) + { + case 1: + adcDacClockRateSelect |= 0; + break; + case 2: + adcDacClockRateSelect |= 1; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_ADCDIV, getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_ADCDIV)); + return MYKONOS_ERR_INIT_INV_ADCDIV; + } + } + else if (device->profilesValid & SNIFF_PROFILE_VALID) + { + /* if Rx profile not valid, and ORX profile not valid, set RX ADC divider and dec5 to match sniffer profile setting */ + /* ARM clock is derived from Rx clocking, so Rx ADC div needs to be set */ + switch (device->obsRx->snifferProfile->rxDec5Decimation) + { + case 4: + break; /* keep bit as 0 in bitfield */ + case 5: + rxChannelSettings |= 0x04; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_RXDEC5_DECIMATION, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_RXDEC5_DECIMATION)); + return MYKONOS_ERR_INIT_INV_RXDEC5_DECIMATION; + } + + switch (device->obsRx->snifferProfile->adcDiv) + { + case 1: + adcDacClockRateSelect |= 0; + break; + case 2: + adcDacClockRateSelect |= 1; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_ADCDIV, getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_ADCDIV)); + return MYKONOS_ERR_INIT_INV_ADCDIV; + } + } + + /* determine ObsRx ADC Div setting */ + if (device->profilesValid & ORX_PROFILE_VALID) + { + switch (device->obsRx->orxProfile->adcDiv) + { + case 1: + break; /* Keep bit[4]=0 */ + case 2: + adcDacClockRateSelect |= 0x10; + break; /* Set bit[4]=1 */ + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_OBSRX_ADCDIV, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_OBSRX_ADCDIV)); + return MYKONOS_ERR_INIT_INV_OBSRX_ADCDIV; + } + } + else if (device->profilesValid & SNIFF_PROFILE_VALID) + { + switch (device->obsRx->snifferProfile->adcDiv) + { + case 1: + break; /* Keep bit[4]=0 */ + case 2: + adcDacClockRateSelect |= 0x10; + break; /* Set bit[4]=1 */ + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_OBSRX_ADCDIV, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_OBSRX_ADCDIV)); + return MYKONOS_ERR_INIT_INV_OBSRX_ADCDIV; + } + } + else if (device->profilesValid & RX_PROFILE_VALID) + { /* if OBSRX profiles are not valid, set obsRx ADC div to match Rx ADC divider */ + switch (device->rx->rxProfile->adcDiv) + { + case 1: + break; /* Keep bit[4]=0 */ + case 2: + adcDacClockRateSelect |= 0x10; + break; /* Set bit[4]=1 */ + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_OBSRX_ADCDIV, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_OBSRX_ADCDIV)); + return MYKONOS_ERR_INIT_INV_OBSRX_ADCDIV; + } + } + + /* Determine ORx and Sniffer channel settings */ + if (device->obsRx != NULL) + { + /* verify pointers in data structure are valid (non-zero) */ + if (device->profilesValid & (ORX_PROFILE_VALID | SNIFF_PROFILE_VALID)) + { + if (device->obsRx->realIfData > 0) + { + obsRxRealIf = 1; + } + } + + /* TODO: verify that the decimation matches the given IQ rate in the data structure */ + + /* Set Sniffer profile (digital filter enables) if sniffer profile enabled (valid pointer) */ + if (device->profilesValid & SNIFF_PROFILE_VALID) + { + sniffChannelSettings = 0; + switch (device->obsRx->snifferProfile->rhb1Decimation) + { + case 1: + break; + case 2: + sniffChannelSettings |= 0x10; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_SNIFFER_RHB1, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_SNIFFER_RHB1)); + return MYKONOS_ERR_INIT_INV_SNIFFER_RHB1; + } + + if (device->obsRx->snifferProfile->rxFir != NULL) + { + + switch (device->obsRx->snifferProfile->rxFirDecimation) + { + case 1: + sniffChannelSettings |= 0x01; + break; + case 2: + sniffChannelSettings |= 0x02; + break; + case 4: + sniffChannelSettings |= 0x03; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_SNIFFER_RFIR_DEC, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_SNIFFER_RFIR_DEC)); + return MYKONOS_ERR_INIT_INV_SNIFFER_RFIR_DEC; + } + } + } + + /* Set ORx profile (digital filter enables) if ORx profile enabled (valid pointer) */ + if (device->profilesValid & ORX_PROFILE_VALID) + { + orxChannelSettings = 0; + switch (device->obsRx->orxProfile->rhb1Decimation) + { + case 1: + break; + case 2: + orxChannelSettings |= 0x10; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_ORX_RHB1, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_ORX_RHB1)); + return MYKONOS_ERR_INIT_INV_ORX_RHB1; + } + + if (device->obsRx->orxProfile->rxFir != NULL) + {/* if pointer to orx rxFIR is valid */ + + switch (device->obsRx->orxProfile->rxFirDecimation) + { + case 1: + orxChannelSettings |= 0x01; + break; + case 2: + orxChannelSettings |= 0x02; + break; + case 4: + orxChannelSettings |= 0x03; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_ORX_RFIR_DEC, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_ORX_RFIR_DEC)); + return MYKONOS_ERR_INIT_INV_ORX_RFIR_DEC; + } + } + } + } + + /************************************************************************ + * Set channel config settings for Rx/Tx/oRx and Sniffer channels + *********************************************************************** + */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CONFIGURATION_CONTROL_2, txChannelSettings); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CONFIGURATION_CONTROL_4, rxChannelSettings); + + /* Set option to use new high rejection DEC5 filters in main Rx1/Rx2 path. */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CONFIGURATION_CONTROL_5, ((uint8_t)(rxRealIfData << 2) | (enRxHighRejDec5 ? 3 : 0))); + + if (rxRealIfData > 0) + { + /* Set Rx1 NCO frequency */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_3, 0x40); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_2, 0x00); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_1, 0x01); + + /* Set Rx2 NCO frequency */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_3, 0x40); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_2, 0x00); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_1, 0x01); + + /* Enable NCO for Rx1 and Rx2 to shift data from zero IF to real IF */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_RX_NCO_CONTROL, 3, 0x03, 0); + } + + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_2, obsRxRealIf, 0x40, 6); + + /* if sniffer profile disabled, Sniffer config reg is set to default = 0x80 */ + sniffChannelSettings |= 0x80; /* use PFIR coef set B = bit[7]=1*/ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SNIFFER_CONFIGURATION_CONTROL, sniffChannelSettings); + + /* if orx profile not valid, SPI reg for orx config is set to default = 0x00 */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DPD_CONFIGURATION_CONTROL, orxChannelSettings); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_LOOPBACK_CONFIGURATION_CONTROL, orxChannelSettings); + + /* Set ADC divider, DAC divider, and ObsRx/sniffer dividers */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_1, adcDacClockRateSelect, 0x13, 0); + + /* Disable ORx digital DC offset - bad default SPI setting for ObsRx DC offset */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DIGITAL_DC_OFFSET_CH3_DPD_M_SHIFT, 0x60); + + /* Necessary write for ARM init cals to work */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SNIFF_RXLOGEN_BYTE1, 0x0E); + + /* Increase Sniffer LNA gain */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SNRX_LNA_BIAS_C, 0x0F); + + /* Set the CLKPLL with the frequency from the device data structure */ + retVal = MYKONOS_initDigitalClocks(device); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Wait for CLKPLL CP Cal done and CLKPLL Lock or throw error message */ + CMB_wait_ms(500); + retVal = MYKONOS_waitForEvent(device, CLKPLLCP, 1000000); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_waitForEvent(device, CLKPLL_LOCK, 1000000); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Enable digital clocks - this is gated by the CLKPLL being locked */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_0, 0x14); + + /* Set the Tx PFIR synchronization clock */ + retVal = MYKONOS_setTxPfirSyncClk(device); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Set the Rx PFIR synchronization clock */ + retVal = MYKONOS_setRxPfirSyncClk(device); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + if (device->profilesValid & TX_PROFILE_VALID) + { + /* Set pre TxPFIR Half band filter interpolation */ + if (device->tx->txProfile->txInputHbInterpolation == 1) + { + /* disable TX input half band ([3:2]=00) - but allow DPD to still be enabled for tx profiles with wide BW [1] */ + enableDpd = (device->tx->txProfile->enableDpdDataPath > 0) ? 1 : 0; + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_FILTER_CONFIGURATION, enableDpd, 0x0E, 1); + } + else if (device->tx->txProfile->txInputHbInterpolation == 2) + { + if (device->tx->txProfile->iqRate_kHz > 160000) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_TXINPUTHB0_INV_RATE, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_TXINPUTHB0_INV_RATE)); + return MYKONOS_ERR_INIT_INV_TXINPUTHB0_INV_RATE; + } + + /* enable TX input half band[2]=1, and Enable DPD[1]=1*/ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_FILTER_CONFIGURATION, 3, 0x0E, 1); + } + else if (device->tx->txProfile->txInputHbInterpolation == 4) + { + if (device->tx->txProfile->iqRate_kHz > 80000) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_TXINPUTHB_INV_RATE, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_TXINPUTHB_INV_RATE)); + return MYKONOS_ERR_INIT_INV_TXINPUTHB_INV_RATE; + } + + /* enable TX input HB0[3]=1 and Tx input HB[2]=1, and Enable DPD[1]=1*/ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_FILTER_CONFIGURATION, 7, 0x0E, 1); + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INIT_INV_TXINPUTHB_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INIT_INV_TXINPUTHB_PARM)); + return MYKONOS_ERR_INIT_INV_TXINPUTHB_PARM; + } + + /* Enable SPI Tx Atten mode */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_TPC_CONFIG, 0x01, 0x03, 0); + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_TPC_CONFIG, 0x01, 0x0C, 2); + + /* Set Tx1 Atten step size */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_INCR_DECR_WORD, device->tx->txAttenStepSize, 0x60, 5); + + /* Set Tx2 Atten step size */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_TPC_CONFIG, device->tx->txAttenStepSize, 0x60, 5); + } + else + { + /* Power down DACs */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_PD_OVERIDE_7_0, 3, 0x0C, 2); + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_PD_OVERRIDE_CONTROL_7_0, 3, 0x0C, 2); + } + + /* Set RxFE LO Common mode */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RXFE1_LOCM, 0xF0); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RXFE2_LOCM, 0xF0); + + /* Set Rxloopback LO Common mode */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RXLOOPBACK1_CNTRL_1, 0xFF); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RXLOOPBACK2_CNTRL_1, 0xFF); + + /* Setup MGC or AGC Rx gain control */ + if ((retVal = MYKONOS_setupRxAgc(device)) != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Default Rx to use manual gain control until AGC enabled by user */ + if ((retVal = MYKONOS_setRxGainControlMode(device, MGC)) != MYKONOS_ERR_OK) + { + return retVal; + } + + + if ((retVal = MYKONOS_setupObsRxAgc(device)) != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Default ObsRx to use manual gain control until AGC enabled by user */ + if ((retVal = MYKONOS_setObsRxGainControlMode(device, MGC)) != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Disable GPIO select bits by setting to b11 */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_CONFIGURATION_CONTROL_1, 3, 0x30, 4); + + /* Extra settings for ARM calibrations */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DIGITAL_DC_OFFSET_SHIFT, 0x11); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX_LOOPBACK1_CNTRL_4, 0x04); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX_LOOPBACK2_CNTRL_4, 0x04); + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_CFG_2, 0x20, 0x20, 0); + + /* Extra settings for ADC initialisation */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX_ADC_FLASH_DELAY, 0x28); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX_ADC_FLASH_CTRL, 0x0E); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ORX_ADC_FLASH_DELAY, 0x28); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ORX_ADC_FLASH_CTRL, 0x0E); + + /* Move to Alert ENSM state */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ENSM_CONFIG_7_0, 0x05); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Verifies the init structure profiles are valid combinations + * + * This function checks that the Rx/Tx/ORx/Sniffer profiles have valid clock rates in + * order to operate together. Rx/Tx and ORx/Sniffer share a common high speed digital + * clock. If an invalid combination of profiles is detected, an error will be + * returned. If a profile in the init structure is unused, the user should zero + * out all members of that particular profile structure. If a Rx/Tx/ORx/Sniffer profile + * has an IQ rate = 0, it is assumed that the profile is disabled. + * + * \pre This function is private and is not called directly by the user. + * + * This function uses mykVerifyTxProfile() and mykVerifyRxProfile() as helper functions. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device Structure pointer to Mykonos device data structure + * + * \retval MYKONOS_ERR_PROFILES_HSDIGCLK profiles loaded are not valid + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_verifyProfiles(mykonosDevice_t *device) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + + uint32_t rxHsDigClk_kHz = 0; + uint32_t orxHsDigClk_kHz = 0; + uint32_t snifferHsDigClk_kHz = 0; + uint32_t txHsDigClk_kHz = 0; + + mykonosRxProfile_t *rxProfile = NULL; + mykonosTxProfile_t *txProfile = NULL; + mykonosRxProfile_t *orxProfile = NULL; + mykonosRxProfile_t *snifferProfile = NULL; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_verifyProfiles()\n"); +#endif + + device->profilesValid = 0; + + /* Check all loaded profiles */ + if (device->tx->txChannels != TXOFF) + { + txProfile = device->tx->txProfile; + retVal = mykVerifyTxProfile(device, txProfile, &txHsDigClk_kHz); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + } + + if (device->rx->rxChannels != RXOFF) + { + rxProfile = device->rx->rxProfile; + retVal = mykVerifyRxProfile(device, MYK_RX_PROFILE, rxProfile, &rxHsDigClk_kHz); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + } + + if (device->obsRx->obsRxChannelsEnable != MYK_OBS_RXOFF) + { + if ((uint32_t)device->obsRx->obsRxChannelsEnable & (uint32_t)MYK_ORX1_ORX2) + { + orxProfile = device->obsRx->orxProfile; + retVal = mykVerifyRxProfile(device, MYK_OBS_PROFILE, orxProfile, &orxHsDigClk_kHz); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + } + + if ((uint32_t)device->obsRx->obsRxChannelsEnable & (uint32_t)MYK_SNRXA_B_C) + { + snifferProfile = device->obsRx->snifferProfile; + retVal = mykVerifyRxProfile(device, MYK_SNIFFER_PROFILE, snifferProfile, &snifferHsDigClk_kHz); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + } + } + + return retVal; +} + +/** + * \brief Write indirect registers (Programmable FIRs, Rx gain tables, JESD204B settings). Must be done after Multi Chip Sync + * + * The BBP should never need to call this function. It is called automatically by the initArm function. + * This function is a continuation of the MYKONOS_initialize() function. This part of initialization must be done after + * the BBP has completed Multi chip Sync. These registers include FIR filters, Rx gain tables, and JESD204B framer/deframer + * config registers. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device data structure containing settings + * an error. + * \return Returns enum mykonosErr_t, MYKONOS_ERR_OK=pass, !MYKONOS_ERR_OK=fail + */ +mykonosErr_t MYKONOS_initSubRegisterTables(mykonosDevice_t *device) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + + /* ------------------------------------------------------------------------------------------- */ + /* Program submap register tables after digital clocks are up and running and Multi Chip Sync */ + /* has been completed by BBP */ + if (device->profilesValid & TX_PROFILE_VALID) + { + if (device->tx->txProfile->txFir != NULL) + { + retVal = MYKONOS_programFir(device, TX1TX2_FIR, device->tx->txProfile->txFir); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + } + } + + if (device->profilesValid & RX_PROFILE_VALID) + { + if (device->rx->rxProfile->rxFir != NULL) + { + retVal = MYKONOS_programFir(device, RX1RX2_FIR, device->rx->rxProfile->rxFir); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Load Rx gain table */ + retVal = MYKONOS_programRxGainTable(device, &RxGainTable[0][0], (sizeof(RxGainTable) >> 2), RX1_RX2_GT); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_setRx1ManualGain(device, device->rx->rxGainCtrl->rx1GainIndex); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_setRx2ManualGain(device, device->rx->rxGainCtrl->rx2GainIndex); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Enable Digital gain for Rx and ObsRx gain tables */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DIGITAL_GAIN_CONFIG, 0x80); + } + } + + if (device->profilesValid & SNIFF_PROFILE_VALID) + { + if (device->obsRx->snifferProfile->rxFir != NULL) + { + retVal = MYKONOS_programFir(device, OBSRX_B_FIR, device->obsRx->snifferProfile->rxFir); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Load Sniffer Rx gain table */ + retVal = MYKONOS_programRxGainTable(device, &SnRxGainTable[0][0], (sizeof(SnRxGainTable) >> 2), SNRX_GT); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_setObsRxManualGain(device, OBS_SNIFFER_A, device->obsRx->snifferGainCtrl->gainIndex); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + } + } + + if (device->profilesValid & ORX_PROFILE_VALID) + { + if (device->obsRx->orxProfile->rxFir != NULL) + {/* if pointer to orx rxFIR is valid */ + retVal = MYKONOS_programFir(device, OBSRX_A_FIR, device->obsRx->orxProfile->rxFir); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Load ORx gain table */ + retVal = MYKONOS_programRxGainTable(device, &ORxGainTable[0][0], (sizeof(ORxGainTable) >> 2), ORX_GT); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_setObsRxManualGain(device, OBS_RX1_TXLO, device->obsRx->orxGainCtrl->orx1GainIndex); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_setObsRxManualGain(device, OBS_RX2_TXLO, device->obsRx->orxGainCtrl->orx2GainIndex); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + } + } + + /* Load Loopback Gain Table for ARM calibrations */ + { + uint8_t loopBackGainTable[6][4] = { + /* Order: {FE table, External Ctl, Digital Gain/Atten, Enable Atten} */ + {0, 0, 0, 0}, /* Gain index 255 */ + {7, 0, 0, 0}, /* Gain index 254 */ + {13, 0, 1, 1}, /* Gain index 253 */ + {18, 0, 3, 1}, /* Gain index 252 */ + {23, 0, 3, 1}, /* Gain index 251 */ + {28, 0, 0, 0} /* Gain index 250 */ + }; + retVal = MYKONOS_programRxGainTable(device, &loopBackGainTable[0][0], (sizeof(loopBackGainTable) >> 2), LOOPBACK_GT); + } + + /* Enable Digital gain for ORx/Sniffer/Loopback gain table */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DPD_SNIFFER_DIGITAL_GAIN_CONFIG, 0x80); + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RCAL_CONTROL, 0x07);/* Set RCAL code to nominal */ + + /* If Valid Rx Profile or valid ObsRx profile, setup serializers */ + if ((device->profilesValid & RX_PROFILE_VALID) || (device->profilesValid & (ORX_PROFILE_VALID | SNIFF_PROFILE_VALID))) + { + retVal = MYKONOS_setupSerializers(device); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + } + + if ((device->rx->rxChannels != RXOFF) && (device->profilesValid & RX_PROFILE_VALID)) + { + retVal = MYKONOS_setupJesd204bFramer(device); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + } + + if ((device->obsRx->obsRxChannelsEnable != MYK_OBS_RXOFF) && (device->profilesValid & (ORX_PROFILE_VALID | SNIFF_PROFILE_VALID))) + { + retVal = MYKONOS_setupJesd204bObsRxFramer(device); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + } + + if ((device->tx->txChannels != TXOFF) && (device->profilesValid & TX_PROFILE_VALID)) + { + retVal = MYKONOS_setupDeserializers(device); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_setupJesd204bDeframer(device); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_setTx1Attenuation(device, device->tx->tx1Atten_mdB); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_setTx2Attenuation(device, device->tx->tx2Atten_mdB); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Performs a blocking wait for a Mykonos calibration or Pll Lock + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param waitEvent the enum value of the event to wait for + * \param timeout_us If timeout_us time has passed, function will return with + * an error. + * \return Returns enum mykonosErr_t, MYKONOS_ERR_OK=pass, !MYKONOS_ERR_OK=fail + */ +mykonosErr_t MYKONOS_waitForEvent(mykonosDevice_t *device, waitEvent_t waitEvent, uint32_t timeout_us) +{ + uint16_t spiAddr = 0; + uint8_t spiBit = 0; + uint8_t doneBitLevel = 0; + uint8_t data = 0; + mykonosErr_t errCode = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_waitForEvent()\n"); +#endif + + switch (waitEvent) + { + case CALPLL_LOCK:/* wait for x17F[7]=1 */ + spiAddr = MYKONOS_ADDR_CALPLL_SDM_CONTROL; + spiBit = 7; + doneBitLevel = 1; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_CALPLL_LOCK; + break; + case CLKPLLCP: /* wait for x154[5]=1 */ + spiAddr = MYKONOS_ADDR_CLK_SYNTH_CAL_STAT; + spiBit = 5; + doneBitLevel = 1; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_CLKPLLCP; + break; + case CLKPLL_LOCK: /* wait for x157[0]=1 */ + spiAddr = MYKONOS_ADDR_CLK_SYNTH_VCO_BAND_BYTE1; + spiBit = 0; + doneBitLevel = 1; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_CLKPLL_LOCK; + break; + case RF_RXPLLCP:/* wait for x254[5]=1 */ + spiAddr = MYKONOS_ADDR_RXSYNTH_CP_CAL_STAT; + spiBit = 5; + doneBitLevel = 1; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RXPLLCP; + break; + case RF_RXPLL_LOCK: /* wait for x257[0]=1 */ + spiAddr = MYKONOS_ADDR_RXSYNTH_VCO_BAND_BYTE1; + spiBit = 0; + doneBitLevel = 1; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RXPLL_LOCK; + break; + case RF_TXPLLCP: /* wait for x2C4[5]=1 */ + spiAddr = MYKONOS_ADDR_TXSYNTH_CP_CAL_STAT; + spiBit = 5; + doneBitLevel = 1; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_TXPLLCP; + break; + case RF_TXPLL_LOCK: /* wait for x2C7[0]=1 */ + spiAddr = MYKONOS_ADDR_TXSYNTH_VCO_BAND_BYTE1; + spiBit = 0; + doneBitLevel = 1; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_TXPLL_LOCK; + break; + case RF_SNIFFERPLLCP: /* wait for x354[7]=1 */ + spiAddr = MYKONOS_ADDR_SNIFF_RXSYNTH_CP_CAL_STAT; + spiBit = 5; + doneBitLevel = 1; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_SNIFFPLLCP; + break; + case RF_SNIFFERPLL_LOCK: /* wait for x357[0]=1 */ + spiAddr = MYKONOS_ADDR_SNIFF_RXSYNTH_VCO_BAND_BYTE1; + spiBit = 0; + doneBitLevel = 1; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_SNIFFPLL_LOCK; + break; + case RXBBF_CALDONE: /* wait for x1B2[5]=0 */ + spiAddr = MYKONOS_ADDR_CALIBRATION_CONTROL; + spiBit = 5; + doneBitLevel = 0; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RXBBFCALDONE; + break; + case TXBBF_CALDONE:/* wait for x1B2[0]=0 */ + spiAddr = MYKONOS_ADDR_CALIBRATION_CONTROL; + spiBit = 0; + doneBitLevel = 0; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_TXBBFCALDONE; + break; + case RX_RFDC_CALDONE: /* wait for x1B2[1]=0 */ + spiAddr = MYKONOS_ADDR_CALIBRATION_CONTROL; + spiBit = 1; + doneBitLevel = 0; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RFDCCALDONE; + break; + case RX_ADCTUNER_CALDONE:/* wait for x1B2[7]=0 */ + spiAddr = MYKONOS_ADDR_CALIBRATION_CONTROL; + spiBit = 7; + doneBitLevel = 0; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_ADCTUNECALDONE; + break; + case RX1_ADCPROFILE:/* wait for x5DD[5]=0 */ + spiAddr = MYKONOS_ADDR_RX_ADC1_PRFL; + spiBit = 5; + doneBitLevel = 0; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RX1ADCPROFILE; + break; + case RX2_ADCPROFILE:/* wait for x5DE[5]=0 */ + spiAddr = MYKONOS_ADDR_RX_ADC2_PRFL; + spiBit = 5; + doneBitLevel = 0; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RX2ADCPROFILE; + break; + case ORX_ADCPROFILE:/* wait for x5DF[5]=0 */ + spiAddr = MYKONOS_ADDR_ORX_ADC_PRFL; + spiBit = 5; + doneBitLevel = 0; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_ORXADCPROFILE; + break; + case RCAL_CALDONE: /* wait for x1B2[6]=0 */ + spiAddr = MYKONOS_ADDR_CALIBRATION_CONTROL; + spiBit = 6; + doneBitLevel = 0; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RCALDONE; + break; + case ARMBUSY:/* wait for xD30[7]=0 */ + spiAddr = MYKONOS_ADDR_ARM_CMD; + spiBit = 7; + doneBitLevel = 0; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_ARMBUSY; + break; + case INITARM_DONE: + spiAddr = MYKONOS_ADDR_ARM_CMD; + spiBit = 7; + doneBitLevel = 0; + errCode = MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_INITARMDONE; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WAITFOREVENT_INV_PARM, + getMykonosErrorMessage(MYKONOS_ERR_WAITFOREVENT_INV_PARM)); + return MYKONOS_ERR_WAITFOREVENT_INV_PARM; + } + + CMB_setTimeout_us(timeout_us); /* timeout after desired time */ + + do + { + CMB_SPIReadByte(device->spiSettings, spiAddr, &data); + + /* For SW verification tests, allow API to think all cals are complete*/ +#ifdef MYK_CALS_DONE_SWDEBUG + if (doneBitLevel == 0) + { + data = 0x00; + } + else + { + data = 0xFF; + } +#endif + + if ((uint32_t)CMB_hasTimeoutExpired() > 0) + { + CMB_writeToLog(ADIHAL_LOG_WARNING, device->spiSettings->chipSelectIndex, errCode, getMykonosErrorMessage(errCode)); + return errCode; + } + } while (((data >> spiBit) & 0x01) != doneBitLevel); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Performs a readback with no wait for a Mykonos calibration or Pll Lock + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param waitEvent the enum value of the event to wait for + * \param eventDone Return value: 1= calibration event is complete. 0 = Event is still pending + * \return Returns enum mykonosErr_t, MYKONOS_ERR_OK=pass, !MYKONOS_ERR_OK=fail + */ +mykonosErr_t MYKONOS_readEventStatus(mykonosDevice_t *device, waitEvent_t waitEvent, uint8_t *eventDone) +{ + uint16_t spiAddr = 0; + uint8_t data = 0; + uint8_t spiBit = 0; + uint8_t doneBitLevel = 0; + + switch (waitEvent) + { + case CALPLL_LOCK:/* wait for x17F[7]=1 */ + spiAddr = MYKONOS_ADDR_CALPLL_SDM_CONTROL; + spiBit = 7; + doneBitLevel = 1; + break; + case CLKPLLCP: /* wait for x154[5]=1 */ + spiAddr = MYKONOS_ADDR_CLK_SYNTH_CAL_STAT; + spiBit = 5; + doneBitLevel = 1; + break; + case CLKPLL_LOCK: /* wait for x157[0]=1 */ + spiAddr = MYKONOS_ADDR_CLK_SYNTH_VCO_BAND_BYTE1; + spiBit = 0; + doneBitLevel = 1; + break; + case RF_RXPLLCP:/* wait for x254[5]=1 */ + spiAddr = MYKONOS_ADDR_RXSYNTH_CP_CAL_STAT; + spiBit = 5; + doneBitLevel = 1; + break; + case RF_RXPLL_LOCK: /* wait for x257[0]=1 */ + spiAddr = MYKONOS_ADDR_RXSYNTH_VCO_BAND_BYTE1; + spiBit = 0; + doneBitLevel = 1; + break; + case RF_TXPLLCP: /* wait for x2C4[5]=1 */ + spiAddr = MYKONOS_ADDR_TXSYNTH_CP_CAL_STAT; + spiBit = 5; + doneBitLevel = 1; + break; + case RF_TXPLL_LOCK: /* wait for x2C7[0]=1 */ + spiAddr = MYKONOS_ADDR_TXSYNTH_VCO_BAND_BYTE1; + spiBit = 0; + doneBitLevel = 1; + break; + case RF_SNIFFERPLLCP: /* wait for x354[7]=1 */ + spiAddr = MYKONOS_ADDR_SNIFF_RXSYNTH_CP_CAL_STAT; + spiBit = 5; + doneBitLevel = 1; + break; + case RF_SNIFFERPLL_LOCK: /* wait for x357[0]=1 */ + spiAddr = MYKONOS_ADDR_SNIFF_RXSYNTH_VCO_BAND_BYTE1; + spiBit = 0; + doneBitLevel = 1; + break; + case RXBBF_CALDONE: /* wait for x1B2[5]=0 */ + spiAddr = MYKONOS_ADDR_CALIBRATION_CONTROL; + spiBit = 5; + doneBitLevel = 0; + break; + case TXBBF_CALDONE:/* wait for x1B2[0]=0 */ + spiAddr = MYKONOS_ADDR_CALIBRATION_CONTROL; + spiBit = 0; + doneBitLevel = 0; + break; + case RX_RFDC_CALDONE: /* wait for x1B2[1]=0 */ + spiAddr = MYKONOS_ADDR_CALIBRATION_CONTROL; + spiBit = 1; + doneBitLevel = 0; + break; + case RX_ADCTUNER_CALDONE:/* wait for x1B2[7]=0 */ + spiAddr = MYKONOS_ADDR_CALIBRATION_CONTROL; + spiBit = 7; + doneBitLevel = 0; + break; + case RX1_ADCPROFILE:/* wait for x5DD[5]=0 */ + spiAddr = MYKONOS_ADDR_RX_ADC1_PRFL; + spiBit = 5; + doneBitLevel = 0; + break; + case RX2_ADCPROFILE:/* wait for x5DE[5]=0 */ + spiAddr = MYKONOS_ADDR_RX_ADC2_PRFL; + spiBit = 5; + doneBitLevel = 0; + break; + case ORX_ADCPROFILE:/* wait for x5DF[5]=0 */ + spiAddr = MYKONOS_ADDR_ORX_ADC_PRFL; + spiBit = 5; + doneBitLevel = 0; + break; + case RCAL_CALDONE: /* wait for x1B2[6]=0 */ + spiAddr = MYKONOS_ADDR_CALIBRATION_CONTROL; + spiBit = 6; + doneBitLevel = 0; + break; + case ARMBUSY:/* wait for xD30[7]=0 */ + spiAddr = MYKONOS_ADDR_ARM_CMD; + spiBit = 7; + doneBitLevel = 0; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WAITFOREVENT_INV_PARM, + getMykonosErrorMessage(MYKONOS_ERR_WAITFOREVENT_INV_PARM)); + return MYKONOS_ERR_WAITFOREVENT_INV_PARM; + } + + CMB_SPIReadByte(device->spiSettings, spiAddr, &data); + + if (doneBitLevel) + { + *eventDone = (data >> spiBit) & 0x01; + } + else + { + *eventDone = (~(data >> spiBit) & 0x01); + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets the CLKPLL output frequency. + * + * This code updates the Synth and Loop filter settings based on a VCO + * frequency LUT. The VCO frequency break points for the Synth LUT can be + * found in an array called vcoFreqArrayMhz. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->spiSettings + * - device->deviceClock_kHz + * - device->rxSettings->rxProfile->vcoFreq_kHz + * - device->rxSettings->rxProfile->clkPllHsDiv + * - device->rxSettings->rxProfile->clkPllVcoDiv + * + * \param device is structure pointer to the MYKONOS data structure containing settings + * + * \return Returns enum MYKONOS_ERR, MYKONOS_ERR_OK=pass, !MYKONOS_ERR_OK=fail + */ +mykonosErr_t MYKONOS_initDigitalClocks(mykonosDevice_t *device) +{ + /* RF Synth variables */ + /* pull Synth and Loop filter values from a Look Up Table */ + uint8_t vcoOutLvl; + uint8_t vcoVaractor; /* [3:0] */ + uint8_t vcoBiasRef; /* [2:0] */ + uint8_t vcoBiasTcf; /* [1:0] */ + uint8_t vcoCalOffset; /* [3:0] */ + uint8_t vcoVaractorRef; /* [3:0] */ + uint8_t loopFilterIcp; /* Icp[5:0] */ + uint8_t loopFilterC2C1; /* C2[3:0],C1[3:0] */ + uint8_t loopFilterR1C3; /* R1[3:0],C3[3:0] */ + uint8_t loopFilterR3; /* R3[3:0] */ + uint8_t vcoIndex; + uint8_t i; + + /* RF PLL variables */ + uint16_t integerWord; + uint32_t fractionalWord; + uint32_t fractionalRemainder; + uint32_t scaledRefClk_Hz; + + /* common */ + uint64_t hsDigClk_Hz = 0; + uint32_t scaledRefClk_kHz = 0; + uint8_t deviceClkDiv = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + + uint8_t clockControl2 = 0; + uint8_t sdmSettings = 0; + uint8_t hsDiv = 4; + uint8_t vcoDiv = 0; + uint8_t vcoDivTimes10 = 10; + + /******************RF Synth Section************************/ + static const uint8_t icp_46p08[53] = {15, 15, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 27, 27, 28, 29, 30, 31, 32, 33, 32, 33, 32, 33, 33, 34, 27, 28, 29, + 29, 30, 39, 29, 30, 31, 31, 30, 31, 31, 32, 30, 31, 31, 32, 32, 31, 31, 32, 32, 33}; + + static const uint8_t icp_61p44[53] = {13, 13, 13, 14, 15, 16, 16, 17, 18, 19, 20, 21, 22, 22, 23, 24, 24, 25, 25, 26, 27, 28, 29, 28, 29, 28, 29, 29, 30, 24, 25, 25, + 26, 26, 35, 33, 34, 35, 35, 26, 27, 27, 28, 27, 27, 27, 28, 28, 27, 27, 28, 28, 29}; + + static const uint8_t icp_76p8[53] = {7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 13, 14, 14, 15, 15, 15, 16, 15, 16, 15, 16, 16, 17, 13, 14, 14, 14, 15, + 19, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 16, 15, 15, 15, 16, 16}; + + static const uint32_t vcoFreqArray_kHz[53] = {12605000UL, 12245000UL, 11906000UL, 11588000UL, 11288000UL, 11007000UL, 10742000UL, 10492000UL, 10258000UL, 10036000UL, + 9827800UL, 9631100UL, 9445300UL, 9269800UL, 9103600UL, 8946300UL, 8797000UL, 8655300UL, 8520600UL, 8392300UL, 8269900UL, 8153100UL, 8041400UL, 7934400UL, + 7831800UL, 7733200UL, 7638400UL, 7547100UL, 7459000UL, 7374000UL, 7291900UL, 7212400UL, 7135500UL, 7061000UL, 6988700UL, 6918600UL, 6850600UL, 6784600UL, + 6720500UL, 6658200UL, 6597800UL, 6539200UL, 6482300UL, 6427000UL, 6373400UL, 6321400UL, 6270900UL, 6222000UL, 6174500UL, 6128400UL, 6083600UL, 6040100UL, + 5997700UL}; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_initDigitalClocks()\n"); +#endif + + retVal = MYKONOS_calculateScaledDeviceClk_kHz(device, &scaledRefClk_kHz, &deviceClkDiv); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + hsDiv = device->clocks->clkPllHsDiv; + vcoDiv = device->clocks->clkPllVcoDiv; + + switch (hsDiv) + { + case 4: + hsDiv = 4; /* clockControl2[3:2] = 00 */ + break; + case 5: + hsDiv = 5; + clockControl2 |= 0x04; /* Set bit[2]=1 */ + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CLKPLL_INV_HSDIV, getMykonosErrorMessage(MYKONOS_ERR_CLKPLL_INV_HSDIV)); + return MYKONOS_ERR_CLKPLL_INV_HSDIV; + } + + switch (vcoDiv) + { + case VCODIV_1: + vcoDivTimes10 = 10; /* clockControl2[1:0] = 00 */ + break; + case VCODIV_1p5: + vcoDivTimes10 = 15; + clockControl2 |= 0x01; + break; + case VCODIV_2: + vcoDivTimes10 = 20; + clockControl2 |= 0x02; + break; + case VCODIV_3: + vcoDivTimes10 = 30; + clockControl2 |= 0x03; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CLKPLL_INV_VCODIV, getMykonosErrorMessage(MYKONOS_ERR_CLKPLL_INV_VCODIV)); + return MYKONOS_ERR_CLKPLL_INV_VCODIV; + } + + clockControl2 |= ((deviceClkDiv & 3) << 4); + + /* find vco table index based on vco frequency */ + for (i = 0; device->clocks->clkPllVcoFreq_kHz < vcoFreqArray_kHz[i]; i++) + { + /* Intentionally blank, for loop exits when condition met, index i used below */ + } + vcoIndex = i + 1; + + if (vcoIndex < 1 || vcoIndex > 53) + { + /* vco index out of range */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETCLKPLL_INV_VCOINDEX, + getMykonosErrorMessage(MYKONOS_ERR_SETCLKPLL_INV_VCOINDEX)); + return MYKONOS_ERR_SETCLKPLL_INV_VCOINDEX; + } + + /* valid for all refclk frequencies */ + vcoOutLvl = (vcoIndex <= 16) ? 13 : (vcoIndex <= 23) ? 12 : (vcoIndex <= 25) ? + 11 : (vcoIndex <= 35) ? 10 : (vcoIndex <= 39) ? 9 : (vcoIndex <= 43) ? + 8 : (vcoIndex <= 48) ? 7 : 6; + vcoVaractor = (vcoIndex <= 29 || vcoIndex == 35) ? 1 : 2; + vcoBiasRef = (vcoIndex <= 7 ) ? 4 : (vcoIndex <= 16) ? 6 : 7; + vcoBiasTcf = (vcoIndex <= 25 || (vcoIndex > 26 && vcoIndex <= 29) || + (vcoIndex > 37 && vcoIndex <= 39)) || (vcoIndex > 40 && vcoIndex <= 43) ? + 2 : 3; + + vcoVaractorRef = (vcoIndex <= 29) ? 12 : (vcoIndex == 35) ? 14 : 13; + + if ((scaledRefClk_kHz >= 40000) && (scaledRefClk_kHz < 53760)) + { /* Settings designed for 46.08 MHz PLL REFCLK */ + vcoCalOffset = (vcoIndex == 11 || (vcoIndex > 35 && vcoIndex <= 37) || (vcoIndex > 29 && vcoIndex <= 34)|| vcoIndex == 40 || vcoIndex == 44) ? + 14 :(vcoIndex <= 10 || vcoIndex > 44) ? + 15 : ((vcoIndex > 12 && vcoIndex <= 22) || (vcoIndex > 23 && vcoIndex <= 23) || (vcoIndex > 26 && vcoIndex <= 29) || (vcoIndex > 23 && vcoIndex <= 25) || vcoIndex == 35) ? + 12 : 13; + + loopFilterIcp = icp_46p08[vcoIndex - 1]; + loopFilterC2C1 = 0xF9; /* C2=0xF0 */ + loopFilterR1C3 = 0xD5; + loopFilterR3 = 0x0E; + } + else if ((scaledRefClk_kHz >= 53760) && (scaledRefClk_kHz < 69120)) + { /* Settings designed for 61.44 MHz PLL REFCLK */ + vcoCalOffset = (vcoIndex == 11 || (vcoIndex > 29 && vcoIndex <= 34) || vcoIndex == 40 || vcoIndex == 44) ? + 14 :(vcoIndex <= 10 || vcoIndex > 44) ? + 15 : ((vcoIndex > 12 && vcoIndex <= 22) || (vcoIndex > 23 && vcoIndex <= 25) || (vcoIndex > 26 && vcoIndex <= 29) || (vcoIndex > 34 && vcoIndex <= 37)) ? + 12 : (vcoIndex > 37 && vcoIndex <= 39) ? 11 : 13; + + vcoVaractor = (vcoIndex > 35 && vcoIndex <= 39) ? 1 : vcoVaractor; + vcoBiasRef = (vcoIndex > 4 && vcoIndex <= 7) ? 5 : vcoBiasRef; + vcoVaractorRef = (vcoIndex > 35 && vcoIndex <= 39) ? 14 : vcoVaractorRef; + loopFilterIcp = icp_61p44[vcoIndex-1]; + loopFilterC2C1 = ((vcoIndex > 2 && vcoIndex <= 6) || (vcoIndex > 8 && vcoIndex <= 13) || (vcoIndex > 14)) ? 0xFD : 0xFC; /* C2=0xF0 */ + loopFilterR1C3 = 0xC5; + loopFilterR3 = (vcoIndex <= 2 || (vcoIndex > 6 && vcoIndex <= 8) || vcoIndex == 14) ? 14 : 13 ; + } + else if ((scaledRefClk_kHz >= 69120) && (scaledRefClk_kHz <= 80000)) + { /* Settings designed for 76.8 MHz PLL REFCLK */ + vcoCalOffset = (vcoIndex == 11 || (vcoIndex > 35 && vcoIndex <= 37) || (vcoIndex > 29 && vcoIndex <= 34)|| vcoIndex == 40 || vcoIndex == 44) ? + 14 :(vcoIndex <= 10 || vcoIndex > 44) ? + 15 : ((vcoIndex > 12 && vcoIndex <= 22) || (vcoIndex > 23 && vcoIndex <= 23) || (vcoIndex > 26 && vcoIndex <= 29) || (vcoIndex > 23 && vcoIndex <= 25) || vcoIndex == 35) ? + 12 : 13; + + loopFilterIcp = icp_76p8[vcoIndex-1]; + loopFilterC2C1 = (vcoIndex == 20 ) ? 0xF7 : (vcoIndex == 4 || vcoIndex == 6 || vcoIndex == 8 ) ? 0xE6: 0xF6; /*C2=0xF0, C1=6 or 7 */ + loopFilterR1C3 = (vcoIndex == 4 ) ? 0xE4 : 0xD5; + loopFilterR3 = 0x0E; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETRFPLL_INV_REFCLK, getMykonosErrorMessage(MYKONOS_ERR_SETRFPLL_INV_REFCLK)); + return MYKONOS_ERR_SETRFPLL_INV_REFCLK; /* invalid ref clk */ + } + + /* Hold CLKPLL digital logic in reset */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_4, 0x00); + + /* Set reference clock scaler + HSdiv + VCOdiv */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_2, clockControl2); + + /*Set VCO cal time */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_CAL_CONTROL, 0x02); + + /* Write Synth Setting regs */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_F_VCOTN_BYTE1, ((vcoCalOffset & 0x0F) << 3)); /* Set VCO Cal offset[3:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_BYTE1, (0xC0 | (vcoVaractor & 0x0F))); /* Init ALC[3:0], VCO varactor[3:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_BYTE2, (0x40 | (vcoOutLvl & 0x0F))); /* VCO output level */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_BYTE9, (((vcoBiasTcf & 0x03) << 3) | (vcoBiasRef & 0x07))); /* Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_VCO_CAL_REF, 0x30); /* Set VCO cal time (compare length) + Set VCO Cal Ref Tcf[2:0]=0 */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL1, 0x70); /* Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL2, (vcoVaractorRef & 0x0F)); /* Set VCO Varactor Reference[3:0] */ + + /* Write Loop filter */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_BYTE3, (0x80 | (loopFilterIcp & 0x03F))); /* Set Loop Filter Icp[5:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_BYTE6, loopFilterC2C1); /* Set Loop Filter C2[3:0] and C1[3:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_BYTE7, loopFilterR1C3); /* Set Loop Filter R1[3:0] and C3[3:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_LF_R3, (loopFilterR3 & 0x0F)); /*Set Loop Filter R3[3:0] */ + + /* Calculate PLL integer and fractional words with integer math */ + scaledRefClk_Hz = scaledRefClk_kHz * 1000; + hsDigClk_Hz = (((uint64_t)(device->clocks->clkPllVcoFreq_kHz) * 10000) / vcoDivTimes10) / hsDiv; + integerWord = (uint16_t)(hsDigClk_Hz / scaledRefClk_Hz); + fractionalRemainder = hsDigClk_Hz % scaledRefClk_Hz; + + /* +1 >> 1 is rounding (add .5) */ + fractionalWord = ((uint32_t)((((uint64_t)fractionalRemainder * 4177920) / (uint64_t)scaledRefClk_Hz) + 1) >> 1); + + /* if fractionalWord rounded up and == PLL modulus, fix it */ + if (fractionalWord == 2088960) + { + fractionalWord = 0; + integerWord = integerWord + 1; + } + + if (fractionalWord > 0) + { /* in normal case, the fractional word should be zero and SDM bypassed */ + CMB_writeToLog(ADIHAL_LOG_WARNING, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETCLKPLL_INV_FRACWORD, + getMykonosErrorMessage(MYKONOS_ERR_SETCLKPLL_INV_FRACWORD)); + /* down graded to warning, do not return error code */ + //return MYKONOS_ERR_SETCLKPLL_INV_FRACWORD; + sdmSettings = 0x20; + } + else + { + /* Bypass SDM */ + sdmSettings = 0xE0; + } + + /* Set PLL fractional word[22:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE0, (fractionalWord & 0xFF)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE1, ((fractionalWord >> 8) & 0xFF)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE2, ((fractionalWord >> 16) & 0x7F)); + + /* Write PLL integer word [7:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE1, (sdmSettings | ((integerWord >> 8) & 0x7))); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE0, (integerWord & 0xFF)); + + /* Release PLL from reset, and set start VCO cal bit to 0 */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_4, 0x80); + + /* Power up CLKPLL */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_0, 0x00); + CMB_wait_ms(200); /* Allow PLL time to power up */ + + /* Enable Charge pump cal after Charge Pump current set (Icp[5:0]) */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_BYTE5, 0x84); + + /* Start VCO Cal */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_4, 0x81); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets the RF PLL local oscillator frequency (RF carrier frequency). + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->spiSettings + * + * \param device is structure pointer to the MYKONOS data structure containing settings + * \param pllName Name of the PLL to configure + * \param rfPllLoFrequency_Hz Desired RF LO frequency + * + * \return MYKONOS_ERR_OK Function completed successfully + * \return MYKONOS_ERR_SETRFPLL_ARMERROR ARM Command to set RF PLL frequency failed + */ +mykonosErr_t MYKONOS_setRfPllFrequency(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint64_t rfPllLoFrequency_Hz) +{ + const uint8_t SETCMD_OPCODE = 0x0A; + const uint8_t SET_PLL_FREQUENCY = 0x63; + + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armData[8] = {0}; + uint8_t extData[2] = {0}; + uint32_t timeoutMs = 0; + uint8_t cmdStatusByte = 0; + + armData[0] = (uint8_t)(rfPllLoFrequency_Hz & 0xFF); + armData[1] = (uint8_t)((rfPllLoFrequency_Hz >> 8) & 0xFF); + armData[2] = (uint8_t)((rfPllLoFrequency_Hz >> 16) & 0xFF); + armData[3] = (uint8_t)((rfPllLoFrequency_Hz >> 24) & 0xFF); + armData[4] = (uint8_t)((rfPllLoFrequency_Hz >> 32) & 0xFF); + armData[5] = (uint8_t)((rfPllLoFrequency_Hz >> 40) & 0xFF); + armData[6] = (uint8_t)((rfPllLoFrequency_Hz >> 48) & 0xFF); + armData[7] = (uint8_t)((rfPllLoFrequency_Hz >> 56) & 0xFF); + + /* write 64-bit frequency to ARM memory */ + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &armData[0], 8); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + extData[0] = SET_PLL_FREQUENCY; + + switch (pllName) + { + case RX_PLL: + extData[1] = 0x00; + break; + case TX_PLL: + extData[1] = 0x01; + break; + case SNIFFER_PLL: + extData[1] = 0x02; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETRFPLL_INV_PLLNAME, + getMykonosErrorMessage(MYKONOS_ERR_SETRFPLL_INV_PLLNAME)); + return MYKONOS_ERR_SETRFPLL_INV_PLLNAME; + } + } + + retVal = MYKONOS_sendArmCommand(device, SETCMD_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, SETCMD_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETRFPLL_ARMERROR, getMykonosErrorMessage(MYKONOS_ERR_SETRFPLL_ARMERROR)); + return MYKONOS_ERR_SETRFPLL_ARMERROR; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETRFPLL_ARMERROR, getMykonosErrorMessage(MYKONOS_ERR_SETRFPLL_ARMERROR)); + return MYKONOS_ERR_SETRFPLL_ARMERROR; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Gets the RF PLL local oscillator frequency (RF carrier frequency). + * + * This function is used to get the RF PLL's frequency. It can get the RX PLL, TX PLL + * Sniffer PLL, and CLKPLL. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->spiSettings + * - device->clocks->deviceClock_kHz + * + * \param device is structure pointer to the MYKONOS data structure containing settings + * \param pllName Name of the PLL for which to read the frequency + * \param rfPllLoFrequency_Hz RF LO frequency currently set for the PLL specified + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GET_PLLFREQ_INV_REFCLKDIV Invalid CLKPLL reference clock divider read from Mykonos device + * \retval MYKONOS_ERR_GET_PLLFREQ_INV_HSDIV Invalid CLKPLL high speed clock divider read from Mykonos device + * \retval MYKONOS_ERR_GETRFPLL_INV_PLLNAME Invalid PLL name, can not get PLL frequency. Use PLL name ENUM. + * \retval MYKONOS_ERR_GETRFPLL_ARMERROR ARM Command to get RF PLL frequency failed + * \retval MYKONOS_ERR_GETRFPLL_NULLPARAM rfPllLoFrequency_Hz function parameter pointer is NULL + */ +mykonosErr_t MYKONOS_getRfPllFrequency(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint64_t *rfPllLoFrequency_Hz) +{ + const uint8_t RFPLL_LO_FREQUENCY = 0x63; + + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armData[8] = {0, 0, 0, 0, 0, 0, 0, 0}; + uint8_t extData[2] = {0, 0}; + uint32_t timeoutMs = 0; + uint8_t cmdStatusByte = 0; + uint8_t getClkPllFrequency = 0; + + uint32_t clkPllIntWord = 0; + uint32_t clkPllFracWord = 0; + uint8_t clkPllRefClkDiv = 0; + uint8_t hsDiv = 0; + uint8_t vcoDivTimes10 = 0; + uint8_t hsDivReg = 0; + uint8_t vcoDivReg = 0; + uint8_t clkPllIntWord7_0 = 0; + uint8_t clkPllIntWord10_8 = 0; + uint8_t clkPllFracWord7_0 = 0; + uint8_t clkPllFracWord15_8 = 0; + uint8_t clkPllFracWord22_16 = 0; + uint64_t refclk_Hz = 0; + + extData[0] = RFPLL_LO_FREQUENCY; + + switch (pllName) + { + case CLK_PLL: + getClkPllFrequency = 1; + break; + case RX_PLL: + extData[1] = 0x00; + break; + case TX_PLL: + extData[1] = 0x01; + break; + case SNIFFER_PLL: + extData[1] = 0x02; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRFPLL_INV_PLLNAME, + getMykonosErrorMessage(MYKONOS_ERR_GETRFPLL_INV_PLLNAME)); + return MYKONOS_ERR_GETRFPLL_INV_PLLNAME; + } + } + + if (getClkPllFrequency > 0) + { + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_2, &hsDivReg, 0x0C, 2); + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_2, &vcoDivReg, 0x03, 0); + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_2, &clkPllRefClkDiv, 0x70, 4); + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE0, &clkPllIntWord7_0); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE1, &clkPllIntWord10_8); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE0, &clkPllFracWord7_0); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE1, &clkPllFracWord15_8); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE2, &clkPllFracWord22_16); + + clkPllIntWord = (((uint32_t)(clkPllIntWord10_8 & 0x7) << 8) | clkPllIntWord7_0); + clkPllFracWord = (((uint32_t)(clkPllFracWord22_16 & 0x7F) << 16) | ((uint32_t)(clkPllFracWord15_8) << 8) | clkPllFracWord7_0); + + switch (clkPllRefClkDiv) + { + case 0: + refclk_Hz = ((uint64_t)device->clocks->deviceClock_kHz * 1000); + break; + case 1: + refclk_Hz = (((uint64_t)device->clocks->deviceClock_kHz * 1000) >> 1); + break; /* div 2 */ + case 2: + refclk_Hz = (((uint64_t)device->clocks->deviceClock_kHz * 1000) >> 2); + break; /* div 4 */ + case 3: + refclk_Hz = (((uint64_t)device->clocks->deviceClock_kHz * 1000) << 1); + break; /* times 2 */ + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_PLLFREQ_INV_REFCLKDIV, + getMykonosErrorMessage(MYKONOS_ERR_GET_PLLFREQ_INV_REFCLKDIV)); + return MYKONOS_ERR_GET_PLLFREQ_INV_REFCLKDIV; + } + } + + switch (vcoDivReg) + { + case 0: + vcoDivTimes10 = 10; + break; + case 1: + vcoDivTimes10 = 15; + break; + case 2: + vcoDivTimes10 = 20; + break; + case 3: + vcoDivTimes10 = 30; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_PLLFREQ_INV_VCODIV, + getMykonosErrorMessage(MYKONOS_ERR_GET_PLLFREQ_INV_VCODIV)); + return MYKONOS_ERR_GET_PLLFREQ_INV_VCODIV; + } + } + + switch (hsDivReg) + { + case 0: + hsDiv = 4; + break; + case 1: + hsDiv = 5; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_PLLFREQ_INV_HSDIV, + getMykonosErrorMessage(MYKONOS_ERR_GET_PLLFREQ_INV_HSDIV)); + return MYKONOS_ERR_GET_PLLFREQ_INV_HSDIV; + } + } + + /* round to nearest Hz for fractional word (fractional modulus = 2088960) */ + *rfPllLoFrequency_Hz = (uint64_t)(((refclk_Hz * clkPllIntWord) + (((refclk_Hz * clkPllFracWord / 1044480) + 1) >> 1)) * hsDiv * vcoDivTimes10 / 10); + } + else + { + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRFPLL_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_GETRFPLL_ARMERROR)); + return MYKONOS_ERR_GETRFPLL_ARMERROR; + } + + return retVal; + } + + /* read 64-bit frequency from ARM memory */ + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &armData[0], 8, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRFPLL_ARMERROR, getMykonosErrorMessage(MYKONOS_ERR_GETRFPLL_ARMERROR)); + return MYKONOS_ERR_GETRFPLL_ARMERROR; + } + + if (rfPllLoFrequency_Hz == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRFPLL_NULLPARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETRFPLL_NULLPARAM)); + return MYKONOS_ERR_GETRFPLL_NULLPARAM; + } + + *rfPllLoFrequency_Hz = (uint64_t)((uint64_t)(armData[0])) | ((uint64_t)(armData[1]) << 8) | ((uint64_t)(armData[2]) << 16) | ((uint64_t)(armData[3]) << 24) + | ((uint64_t)(armData[4]) << 32) | ((uint64_t)(armData[5]) << 40) | ((uint64_t)(armData[6]) << 48) | ((uint64_t)(armData[7]) << 56); + } + return MYKONOS_ERR_OK; +} + +/** + * \brief Checks if the PLLs are locked + * + * This function updates the pllLockStatus pointer with a lock status it per + * PLL. + * pllLockStatus[0] = CLKPLL Locked + * pllLockStatus[1] = RX_PLL Locked + * pllLockStatus[2] = TX_PLL Locked + * pllLockStatus[3] = SNIFFER_PLL Locked + * pllLockStatus[4] = CAL_PLL Locked + * + * \param device the Mykonos device data structure + * \param pllLockStatus Lock status bit per PLL + * + * \return Returns enum MYKONOS_ERR, MYKONOS_ERR_OK=pass, !MYKONOS_ERR_OK=fail + */ +mykonosErr_t MYKONOS_checkPllsLockStatus(mykonosDevice_t *device, uint8_t *pllLockStatus) +{ + uint8_t readData = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_checkPllsLockStatus()\n"); +#endif + + if (pllLockStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CHECK_PLL_LOCK_NULL_PARM, + getMykonosErrorMessage(MYKONOS_ERR_CHECK_PLL_LOCK_NULL_PARM)); + return MYKONOS_ERR_CHECK_PLL_LOCK_NULL_PARM; + } + + *pllLockStatus = 0; + + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_VCO_BAND_BYTE1, &readData, 0x01, 0); + *pllLockStatus = readData; + + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_RXSYNTH_VCO_BAND_BYTE1, &readData, 0x01, 0); + *pllLockStatus = *pllLockStatus | (uint8_t)(readData << 1); + + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_TXSYNTH_VCO_BAND_BYTE1, &readData, 0x01, 0); + *pllLockStatus = *pllLockStatus | (uint8_t)(readData << 2); + + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_SNIFF_RXSYNTH_VCO_BAND_BYTE1, &readData, 0x01, 0); + *pllLockStatus = *pllLockStatus | (uint8_t)(readData << 3); + + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_CALPLL_SDM_CONTROL, &readData, 0x80, 7); + *pllLockStatus = *pllLockStatus | (uint8_t)(readData << 4); + + return MYKONOS_ERR_OK; +} + +/* + ***************************************************************************** + * Shared Data path functions + ***************************************************************************** + */ + +/** + * \brief Sets the digital Tx PFIR SYNC clock divider. + * + * This function is a helper function. It is called automatically in + * MYKONOS_initialize() and should not need to be called by the BBIC. + * + * This function sets the digital clock divider that is used to synchronize the + * Tx PFIR each time the Tx channel power up. The Sync clock must + * be set equal to or slower than the FIR processing clock. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * - device->tx->txProfile->txFir + * - device->tx->txProfile->txFir->numFirCoefs + * - device->tx->txProfile->txFirInterpolation + * - device->tx->txProfile->iqRate_kHz + * + * \param device Pointer to the Mykonos data structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_TXFIR_INV_NUMTAPS_PARM: Invalid number of Tx FIR coefficients + * \retval MYKONOS_ERR_TXFIR_INV_NUMROWS Invalid number of PFIR coefficient rows + * \retval MYKONOS_ERR_TXFIR_TAPSEXCEEDED Too many Tx PFIR taps for the IQ sample rate. FIR processing clock can not run fast enough to handle the number of taps + */ +mykonosErr_t MYKONOS_setTxPfirSyncClk(mykonosDevice_t *device) +{ + const uint8_t numTapMultiple = 16; + const uint8_t maxNumTaps = 96; + uint8_t effectiveRows = 0; + uint8_t numRows = 0; + uint32_t dpClk_kHz = 0; + uint32_t syncClk_kHz = 0; + uint32_t hsDigClkDiv4or5_kHz = 0; + uint8_t syncDiv = 0; + mykonosErr_t retval = MYKONOS_ERR_OK; + + if (((device->profilesValid & TX_PROFILE_VALID) > 0) && (device->tx->txProfile->txFir != NULL)) + { + /* Calculate number of FIR rows for number of Taps */ + if ((device->tx->txProfile->txFir->numFirCoefs % numTapMultiple == 0) && (device->tx->txProfile->txFir->numFirCoefs > 0) + && (device->tx->txProfile->txFir->numFirCoefs <= maxNumTaps)) + { + numRows = (device->tx->txProfile->txFir->numFirCoefs / numTapMultiple); + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_TXFIR_INV_NUMTAPS_PARM, + getMykonosErrorMessage(MYKONOS_ERR_TXFIR_INV_NUMTAPS_PARM)); + return MYKONOS_ERR_TXFIR_INV_NUMTAPS_PARM; + } + + effectiveRows = ((numRows + (device->tx->txProfile->txFirInterpolation - 1)) / device->tx->txProfile->txFirInterpolation); + + /* round up to next power of 2 */ + switch (effectiveRows) + { + case 1: + effectiveRows = 1; + break; + case 2: + effectiveRows = 2; + break; + case 3: /* fall through */ + case 4: + effectiveRows = 4; + break; + case 5: /* fall through */ + case 6: /* fall through */ + case 7: /* fall through */ + case 8: + effectiveRows = 8; + break; + default: + { + /* invalid number of FIR taps */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_TXFIR_INV_NUMROWS, + getMykonosErrorMessage(MYKONOS_ERR_TXFIR_INV_NUMROWS)); + return MYKONOS_ERR_TXFIR_INV_NUMROWS; + } + } + + dpClk_kHz = (device->tx->txProfile->iqRate_kHz * device->tx->txProfile->txInputHbInterpolation * device->tx->txProfile->txFirInterpolation * effectiveRows); + + /* FIR DPCLK can only run at max of 500MHz */ + if (dpClk_kHz > 500000) + { + /* Max number of Tx PFIR taps exceeded for Tx Profile */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_TXFIR_TAPSEXCEEDED, + getMykonosErrorMessage(MYKONOS_ERR_TXFIR_TAPSEXCEEDED)); + return MYKONOS_ERR_TXFIR_TAPSEXCEEDED; + } + + /* SYNC CLOCK is the PFIR output rate / 2 */ + syncClk_kHz = device->tx->txProfile->iqRate_kHz * device->tx->txProfile->txFirInterpolation / 2; + if ((retval = MYKONOS_calculateDigitalClocks(device, NULL, &hsDigClkDiv4or5_kHz)) != MYKONOS_ERR_OK) + { + return retval; + } + + /* Select correct divider setting for SYNCCLK - must be == syncClk_kHz or slower */ + for (syncDiv = 0; syncDiv < 5; syncDiv++) + { + if ((hsDigClkDiv4or5_kHz / (uint32_t)(4 << syncDiv)) <= syncClk_kHz) + { + break; + } + } + + /* Write Tx PFIR SYNC Clock divider */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_5, syncDiv, 0x70, 4); + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets the digital Rx PFIR SYNC clock divider. + * + * This function is a helper function. It is called automatically in + * MYKONOS_initialize() and should not need to be called by the BBIC. + * + * This function sets the digital clock divider that is used to synchronize the + * Rx/ORx/Sniffer PFIRs each time the channels power up. The Sync clock must + * be set equal to or slower than the slowest Rx/ORx/Sniffer PFIR processing + * clock. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * - device->rx->rxProfile->rxFir + * - device->rx->rxProfile->rxFir->numFirCoefs + * - device->rx->rxProfile->iqRate_kHz + * - device->obsRx->orxProfile->rxFir + * - device->obsRx->orxProfile->rxFir->numFirCoefs + * - device->obsRx->orxProfile->iqRate_kHz + * - device->obsRx->snifferProfile->rxFir + * - device->obsRx->snifferProfile->rxFir->numFirCoefs + * - device->obsRx->snifferProfile->iqRate_kHz + * + * \param device Pointer to the Mykonos data structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_RXFIR_TAPSEXCEEDED ERROR: the number of Rx FIR taps exceeds the number of taps accommodated by the FIR processing clock + * \retval MYKONOS_ERR_ORXFIR_TAPSEXCEEDED ERROR: the number of ORx FIR Taps exceeds the number of taps accommodated by the FIR processing clock + * \retval MYKONOS_ERR_SNRXFIR_TAPSEXCEEDED ERROR: the number of sniffer FIR taps exceeds the number of taps accommodated by the FIR processing clock + */ +mykonosErr_t MYKONOS_setRxPfirSyncClk(mykonosDevice_t *device) +{ + uint32_t rxDpClk_kHz = 0; + uint32_t orxDpClk_kHz = 0; + uint32_t snRxDpClk_kHz = 0; + uint32_t slowestIqRate_kHz = 0; + uint32_t syncClk_kHz = 0; + uint8_t effectiveRxNumRows = 0; + uint8_t effectiveOrxNumRows = 0; + uint8_t effectiveSnrxNumRows = 0; + + uint32_t hsDigClkDiv4or5_kHz = 0; + uint8_t syncDiv = 0; + mykonosErr_t retval = MYKONOS_ERR_OK; + + /** + * Calculate Rx SYNC Clock divider for Rx PFIR. Same Rx SYNC Clock is used + * for Rx, ORx, and Sniffer PFIRs, and must be slow enough to handle the slowest + * PFIR rate. + **/ + + if (((device->profilesValid & RX_PROFILE_VALID) > 0) && (device->rx->rxProfile->rxFir != NULL)) + { + switch (device->rx->rxProfile->rxFir->numFirCoefs) + { + case 24: + effectiveRxNumRows = 1; + break; + case 48: + effectiveRxNumRows = 2; + break; + case 72: + effectiveRxNumRows = 4; + break; + default: + break; + } + + rxDpClk_kHz = device->rx->rxProfile->iqRate_kHz * effectiveRxNumRows; + + if (rxDpClk_kHz > 500000) + { + /* Max number of Rx PFIR taps exceeded for Profile */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RXFIR_TAPSEXCEEDED, + getMykonosErrorMessage(MYKONOS_ERR_RXFIR_TAPSEXCEEDED)); + return MYKONOS_ERR_RXFIR_TAPSEXCEEDED; + } + + slowestIqRate_kHz = device->rx->rxProfile->iqRate_kHz; + } + + if (((device->profilesValid & ORX_PROFILE_VALID) > 0) && (device->obsRx->orxProfile->rxFir != NULL)) + { + switch (device->obsRx->orxProfile->rxFir->numFirCoefs) + { + case 24: + effectiveOrxNumRows = 1; + break; + case 48: + effectiveOrxNumRows = 2; + break; + case 72: + effectiveOrxNumRows = 4; + break; + default: + break; + } + + orxDpClk_kHz = device->obsRx->orxProfile->iqRate_kHz * effectiveOrxNumRows; + + if (orxDpClk_kHz > 500000) + { + /* Max number of ORx PFIR taps exceeded for Profile */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ORXFIR_TAPSEXCEEDED, + getMykonosErrorMessage(MYKONOS_ERR_ORXFIR_TAPSEXCEEDED)); + return MYKONOS_ERR_ORXFIR_TAPSEXCEEDED; + } + + if ((slowestIqRate_kHz == 0) || (slowestIqRate_kHz > device->obsRx->orxProfile->iqRate_kHz)) + { + slowestIqRate_kHz = device->obsRx->orxProfile->iqRate_kHz; + + } + } + + if (((device->profilesValid & SNIFF_PROFILE_VALID) > 0) && (device->obsRx->snifferProfile->rxFir != NULL)) + { + switch (device->obsRx->snifferProfile->rxFir->numFirCoefs) + { + case 24: + effectiveSnrxNumRows = 1; + break; + case 48: + effectiveSnrxNumRows = 2; + break; + case 72: + effectiveSnrxNumRows = 4; + break; + default: + break; + } + + snRxDpClk_kHz = device->obsRx->snifferProfile->iqRate_kHz * effectiveSnrxNumRows; + + if (snRxDpClk_kHz > 500000) + { + /* Max number of ORx PFIR taps exceeded for Profile */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SNRXFIR_TAPSEXCEEDED, + getMykonosErrorMessage(MYKONOS_ERR_SNRXFIR_TAPSEXCEEDED)); + return MYKONOS_ERR_SNRXFIR_TAPSEXCEEDED; + } + + if ((slowestIqRate_kHz == 0) || (slowestIqRate_kHz > device->obsRx->snifferProfile->iqRate_kHz)) + { + slowestIqRate_kHz = device->obsRx->snifferProfile->iqRate_kHz; + } + } + + /* SYNC CLOCK should be FIR output rate / 2 */ + syncClk_kHz = (slowestIqRate_kHz / 2); + if ((retval = MYKONOS_calculateDigitalClocks(device, NULL, &hsDigClkDiv4or5_kHz)) != MYKONOS_ERR_OK) + { + return retval; + } + + /* Select correct divider setting for SYNCCLK - must be == syncClk_kHz or slower */ + for (syncDiv = 0; syncDiv < 5; syncDiv++) + { + if ((hsDigClkDiv4or5_kHz / (uint32_t)(4 << syncDiv)) <= syncClk_kHz) + { + break; + } + } + + /* Write Rx PFIR SYNC Clock divider */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_5, syncDiv, 0x07, 0); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Configures one or more FIR filters in the device + * + * The device stores up to 6 FIR filters (2Rx, 2Obs Rx/Sniffer, and 2Tx). + * Rx filters can have 24, 48, or 72 taps. Tx filters can have 16, 32, + * 48, 64, 80, or 96 taps. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos data structure + * \param filterToProgram Name of the desired filter to program + * \param firFilter Pointer to the filter to write into the device + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_PROGRAMFIR_NULL_PARM ERROR: firFilter parameter is a NULL pointer + * \retval MYKONOS_ERR_PROGRAMFIR_COEFS_NULL ERROR: firFilter->coefs is a NULL pointer + * \retval MYKONOS_ERR_PROGRAMFIR_INV_FIRNAME_PARM ERROR: Invalid FIR filter name in filterToProgram parameter + * \retval MYKONOS_ERR_PROGRAMFIR_INV_NUMTAPS_PARM ERROR: Invalid number of taps for the filter + * \retval MYKONOS_ERR_RXFIR_INV_GAIN_PARM ERROR: Rx FIR filter has invalid gain setting + * \retval MYKONOS_ERR_OBSRXFIR_INV_GAIN_PARM ERROR: OBSRX_A (ORX) FIR filter has invalid gain setting + * \retval MYKONOS_ERR_SRXFIR_INV_GAIN_PARM ERROR: OBSRX_B (Sniffer) FIR filter has invalid gain setting + * \retval MYKONOS_ERR_TXFIR_INV_GAIN_PARM ERROR: Tx FIR filter has invalid gain setting + */ +mykonosErr_t MYKONOS_programFir(mykonosDevice_t *device, mykonosfirName_t filterToProgram, mykonosFir_t *firFilter) +{ + uint8_t filterSelect = 0; + uint8_t i = 0; + uint8_t numTapsReg = 0; + uint8_t numTapMultiple = 24; /* Rx=24, Tx=16 */ + uint8_t maxNumTaps = 72; /* Rx=72, Tx=96 */ + uint8_t filterGain = 0; + +#if MYK_ENABLE_SPIWRITEARRAY == 1 + uint32_t addrIndex = 0; + uint32_t dataIndex = 0; + uint32_t spiBufferSize = ((MYK_SPIWRITEARRAY_BUFFERSIZE / 6) * 6); /* Make buffer size a multiple of 6 */ + uint16_t addrArray[MYK_SPIWRITEARRAY_BUFFERSIZE] = {0}; + uint8_t dataArray[MYK_SPIWRITEARRAY_BUFFERSIZE] = {0}; +#endif + + const uint8_t COEF_WRITE_EN = 0x40; + const uint8_t PROGRAM_CLK_EN = 0x80; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_programFir()\n"); +#endif + + if (firFilter == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_PROGRAMFIR_NULL_PARM, + getMykonosErrorMessage(MYKONOS_ERR_PROGRAMFIR_NULL_PARM)); + return MYKONOS_ERR_PROGRAMFIR_NULL_PARM; + } + + if (firFilter->coefs == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_PROGRAMFIR_COEFS_NULL, + getMykonosErrorMessage(MYKONOS_ERR_PROGRAMFIR_COEFS_NULL)); + return MYKONOS_ERR_PROGRAMFIR_COEFS_NULL; + } + + switch (filterToProgram) + { + case TX1_FIR: + filterSelect = 0x01; + numTapMultiple = 16; + maxNumTaps = 96; + break; + case TX2_FIR: + filterSelect = 0x02; + numTapMultiple = 16; + maxNumTaps = 96; + break; + case TX1TX2_FIR: + filterSelect = 0x03; + numTapMultiple = 16; + maxNumTaps = 96; + break; + case RX1_FIR: + filterSelect = 0x04; + numTapMultiple = 24; + maxNumTaps = 72; + break; + case RX2_FIR: + filterSelect = 0x08; + numTapMultiple = 24; + maxNumTaps = 72; + break; + case RX1RX2_FIR: + filterSelect = 0x0C; + numTapMultiple = 24; + maxNumTaps = 72; + break; + case OBSRX_A_FIR: + filterSelect = 0x10; + numTapMultiple = 24; + maxNumTaps = 72; + break; + case OBSRX_B_FIR: + filterSelect = 0x20; + numTapMultiple = 24; + maxNumTaps = 72; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_PROGRAMFIR_INV_FIRNAME_PARM, + getMykonosErrorMessage(MYKONOS_ERR_PROGRAMFIR_INV_FIRNAME_PARM)); + return MYKONOS_ERR_PROGRAMFIR_INV_FIRNAME_PARM; + } + + /* Calculate register value for number of Taps */ + if ((firFilter->numFirCoefs % numTapMultiple == 0) && (firFilter->numFirCoefs > 0) && (firFilter->numFirCoefs <= maxNumTaps)) + { + numTapsReg = (firFilter->numFirCoefs / numTapMultiple) - 1; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_PROGRAMFIR_INV_NUMTAPS_PARM, + getMykonosErrorMessage(MYKONOS_ERR_PROGRAMFIR_INV_NUMTAPS_PARM)); + return MYKONOS_ERR_PROGRAMFIR_INV_NUMTAPS_PARM; + } + + /* Select which FIR filter to program coeffs for */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_CTL, (PROGRAM_CLK_EN | filterSelect)); //select filter and enable the programming clock + +#if (MYK_ENABLE_SPIWRITEARRAY == 0) + + /* write filter coefficients */ + for (i = 0; i < firFilter->numFirCoefs; i++) + { + /* Write Low byte of 16bit coefficient */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_ADDR, (i * 2)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_DATA, (firFilter->coefs[i] & 0xFF)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_CTL, (PROGRAM_CLK_EN | COEF_WRITE_EN | filterSelect)); /* write enable (self clearing) */ + + /* Write High Byte of 16bit coefficient */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_ADDR, ((i * 2) + 1)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_DATA, ((firFilter->coefs[i] >> 8) & 0xFF)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_CTL, (PROGRAM_CLK_EN | COEF_WRITE_EN | filterSelect));/* write enable (self clearing) */ + } + +#elif (MYK_ENABLE_SPIWRITEARRAY == 1) + + addrIndex = 0; + dataIndex = 0; + for (i = 0; i < firFilter->numFirCoefs; i++) + { + addrArray[addrIndex++] = MYKONOS_ADDR_PFIR_COEFF_ADDR; + addrArray[addrIndex++] = MYKONOS_ADDR_PFIR_COEFF_DATA; + addrArray[addrIndex++] = MYKONOS_ADDR_PFIR_COEFF_CTL; + addrArray[addrIndex++] = MYKONOS_ADDR_PFIR_COEFF_ADDR; + addrArray[addrIndex++] = MYKONOS_ADDR_PFIR_COEFF_DATA; + addrArray[addrIndex++] = MYKONOS_ADDR_PFIR_COEFF_CTL; + + dataArray[dataIndex++] = (uint8_t)(i * 2); + dataArray[dataIndex++] = (firFilter->coefs[i] & 0xFF); + dataArray[dataIndex++] = (PROGRAM_CLK_EN | COEF_WRITE_EN | filterSelect); + dataArray[dataIndex++] = (uint8_t)((i * 2) + 1); + dataArray[dataIndex++] = (((uint16_t)firFilter->coefs[i] >> 8) & 0xFF); + dataArray[dataIndex++] = (PROGRAM_CLK_EN | COEF_WRITE_EN | filterSelect); + + /* Send full buffer size when possible */ + /* spiBufferSize set to multiple of 6 at top of function */ + if (addrIndex >= spiBufferSize) + { + CMB_SPIWriteBytes(device->spiSettings, &addrArray[0], &dataArray[0], addrIndex); + dataIndex = 0; + addrIndex = 0; + } + } + + if (addrIndex > 0) + { + CMB_SPIWriteBytes(device->spiSettings, &addrArray[0], &dataArray[0], addrIndex); + } + +#endif + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_CTL, filterSelect); /* clear Program clock enable */ + /* write filter gain and #taps */ + if (filterToProgram == RX1_FIR || filterToProgram == RX2_FIR || filterToProgram == RX1RX2_FIR) + { + /* Write Rx FIR #taps */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_RX_FILTER_CONFIGURATION, numTapsReg, 0x60, 5); + + /* Set Rx filter gain */ + switch (firFilter->gain_dB) + { + case -12: + filterGain = 0x00; + break; + case -6: + filterGain = 0x01; + break; + case 0: + filterGain = 0x02; + break; + case 6: + filterGain = 0x03; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RXFIR_INV_GAIN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_RXFIR_INV_GAIN_PARM)); + return MYKONOS_ERR_RXFIR_INV_GAIN_PARM; + } + + /* Write Rx filter gain */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_RX_FILTER_GAIN, filterGain, 0x03, 0); + } + else if (filterToProgram == OBSRX_A_FIR) + { + /* Write Obs Rx FIR A #taps */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_RX_FILTER_CONFIGURATION, numTapsReg, 0x06, 1); + + /* Set Rx filter gain */ + switch (firFilter->gain_dB) + { + case -12: + filterGain = 0x00; + break; + case -6: + filterGain = 0x01; + break; + case 0: + filterGain = 0x02; + break; + case 6: + filterGain = 0x03; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBSRXFIR_INV_GAIN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_OBSRXFIR_INV_GAIN_PARM)); + return MYKONOS_ERR_OBSRXFIR_INV_GAIN_PARM; + } + + /* Write Obs Rx filter gain */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_DPD_SNIFFER_RX_FILTER_GAIN, filterGain, 0x03, 0); + } + else if (filterToProgram == OBSRX_B_FIR) + { + /* Write Obs Rx FIR B #taps */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_RX_FILTER_CONFIGURATION, numTapsReg, 0x18, 3); + + /* Set Rx filter gain */ + switch (firFilter->gain_dB) + { + case -12: + filterGain = 0x00; + break; + case -6: + filterGain = 0x01; + break; + case 0: + filterGain = 0x02; + break; + case 6: + filterGain = 0x03; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SRXFIR_INV_GAIN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SRXFIR_INV_GAIN_PARM)); + return MYKONOS_ERR_SRXFIR_INV_GAIN_PARM; + } + + /* Write Obs Rx filter gain */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_DPD_SNIFFER_RX_FILTER_GAIN, filterGain, 0x60, 5); + } + else if (filterToProgram == TX1_FIR || filterToProgram == TX2_FIR || filterToProgram == TX1TX2_FIR) + { + /* Write number of Taps */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_FILTER_CONFIGURATION, numTapsReg, 0xE0, 5); + + switch (firFilter->gain_dB) + { + case 0: + filterGain = 0; + break; + case 6: + filterGain = 1; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_TXFIR_INV_GAIN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_TXFIR_INV_GAIN_PARM)); + return MYKONOS_ERR_TXFIR_INV_GAIN_PARM; + } + + /* Write Tx Filter gain */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_FILTER_CONFIGURATION, filterGain, 0x01, 0); + + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads the FIR filter programmed into the device + * + * The device stores up to 6 FIR filters (2Rx, 2Obs Rx/Sniffer, and 2Tx). + * Rx filters can have 24, 48, or 72 taps. Tx filters can have 16, 32, + * 48, 64, 80, or 96 taps. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos data structure + * \param filterToRead Name of the desired filter to be read + * \param firFilter Pointer to the filter to be read from the device + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_READFIR_NULL_PARM ERROR: firFilter parameter is a NULL pointer + * \retval MYKONOS_ERR_READFIR_COEFS_NULL ERROR: firFilter->coefs is a NULL pointer + * \retval MYKONOS_ERR_READFIR_INV_FIRNAME_PARM ERROR: Invalid FIR filter name in filterToRead parameter + * \retval MYKONOS_ERR_READFIR_INV_NUMTAPS_PARM ERROR: Invalid number of taps for the filter + * \retval MYKONOS_ERR_RXFIR_INV_GAIN_PARM ERROR: Rx FIR filter has invalid gain setting + * \retval MYKONOS_ERR_OBSRXFIR_INV_GAIN_PARM ERROR: OBSRX_A (ORX) FIR filter has invalid gain setting + * \retval MYKONOS_ERR_SRXFIR_INV_GAIN_PARM ERROR: OBSRX_B (Sniffer) FIR filter has invalid gain setting + * \retval MYKONOS_ERR_TXFIR_INV_GAIN_PARM ERROR: Tx FIR filter has invalid gain setting + */ +mykonosErr_t MYKONOS_readFir(mykonosDevice_t *device, mykonosfirName_t filterToRead, mykonosFir_t *firFilter) +{ + uint8_t filterSelect = 0; + uint8_t i = 0; + uint8_t numTapsReg = 0; + uint8_t numTapMultiple = 24; + uint8_t maxNumTaps = 72; + uint8_t filterGain = 0; + uint8_t msbRead = 0; + uint8_t lsbRead = 0; + + const uint8_t PROGRAM_CLK_EN = 0x80; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_readFir()\n"); +#endif + + if (firFilter == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READFIR_NULL_PARM, getMykonosErrorMessage(MYKONOS_ERR_READFIR_NULL_PARM)); + return MYKONOS_ERR_READFIR_NULL_PARM; + } + + if (firFilter->coefs == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READFIR_COEFS_NULL, getMykonosErrorMessage(MYKONOS_ERR_READFIR_COEFS_NULL)); + return MYKONOS_ERR_READFIR_COEFS_NULL; + } + + switch (filterToRead) + { + case TX1_FIR: + filterSelect = 0x01; + numTapMultiple = 16; + maxNumTaps = 96; + break; + case TX2_FIR: + filterSelect = 0x02; + numTapMultiple = 16; + maxNumTaps = 96; + break; + case TX1TX2_FIR: + filterSelect = 0x03; + numTapMultiple = 16; + maxNumTaps = 96; + break; + case RX1_FIR: + filterSelect = 0x04; + numTapMultiple = 24; + maxNumTaps = 72; + break; + case RX2_FIR: + filterSelect = 0x08; + numTapMultiple = 24; + maxNumTaps = 72; + break; + case RX1RX2_FIR: + filterSelect = 0x0C; + numTapMultiple = 24; + maxNumTaps = 72; + break; + case OBSRX_A_FIR: + filterSelect = 0x10; + numTapMultiple = 24; + maxNumTaps = 72; + break; + case OBSRX_B_FIR: + filterSelect = 0x20; + numTapMultiple = 24; + maxNumTaps = 72; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READFIR_INV_FIRNAME_PARM, + getMykonosErrorMessage(MYKONOS_ERR_READFIR_INV_FIRNAME_PARM)); + return MYKONOS_ERR_READFIR_INV_FIRNAME_PARM; + } + + /* clear Program clock enable */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_CTL, filterSelect); + + /* Read filter gain and #taps */ + if (filterToRead == RX1_FIR || filterToRead == RX2_FIR || filterToRead == RX1RX2_FIR) + { + /* Read Rx FIR #taps */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_RX_FILTER_CONFIGURATION, &numTapsReg, 0x60, 5); + + firFilter->numFirCoefs = (uint8_t)((numTapsReg + 1) * numTapMultiple); + + /* Read Rx filter gain */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_RX_FILTER_GAIN, &filterGain, 0x03, 0); + + switch (filterGain) + { + case 0x00: + firFilter->gain_dB = -12; + break; + case 0x01: + firFilter->gain_dB = -6; + break; + case 0x02: + firFilter->gain_dB = 0; + break; + case 0x03: + firFilter->gain_dB = 6; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RXFIR_INV_GAIN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_RXFIR_INV_GAIN_PARM)); + return MYKONOS_ERR_RXFIR_INV_GAIN_PARM; + } + } + else if (filterToRead == OBSRX_A_FIR) + { + /* Read Obs Rx FIR A #taps */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_RX_FILTER_CONFIGURATION, &numTapsReg, 0x60, 1); + + firFilter->numFirCoefs = (uint8_t)((numTapsReg + 1) * numTapMultiple); + + /* Read Obs Rx FIR A gain */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_DPD_SNIFFER_RX_FILTER_GAIN, &filterGain, 0x03, 0); + + switch (filterGain) + { + case 0x00: + firFilter->gain_dB = -12; + break; + case 0x01: + firFilter->gain_dB = -6; + break; + case 0x02: + firFilter->gain_dB = 0; + break; + case 0x03: + firFilter->gain_dB = 6; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBSRXFIR_INV_GAIN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_OBSRXFIR_INV_GAIN_PARM)); + return MYKONOS_ERR_OBSRXFIR_INV_GAIN_PARM; + } + } + else if (filterToRead == OBSRX_B_FIR) + { + /* Read Obs Rx FIR B #taps */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_RX_FILTER_CONFIGURATION, &numTapsReg, 0x18, 3); + + firFilter->numFirCoefs = (uint8_t)((numTapsReg + 1) * numTapMultiple); + + /* Read Obs Rx FIR B gain */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_DPD_SNIFFER_RX_FILTER_GAIN, &filterGain, 0x60, 5); + + switch (filterGain) + { + case 0x00: + firFilter->gain_dB = -12; + break; + case 0x01: + firFilter->gain_dB = -6; + break; + case 0x02: + firFilter->gain_dB = 0; + break; + case 0x03: + firFilter->gain_dB = 6; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SRXFIR_INV_GAIN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SRXFIR_INV_GAIN_PARM)); + return MYKONOS_ERR_SRXFIR_INV_GAIN_PARM; + } + } + else if (filterToRead == TX1_FIR || filterToRead == TX2_FIR || filterToRead == TX1TX2_FIR) + { + /* Read number of Taps */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_TX_FILTER_CONFIGURATION, &numTapsReg, 0xE0, 5); + + firFilter->numFirCoefs = (uint8_t)((numTapsReg + 1) * numTapMultiple); + + /* Read Tx Filter gain */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_TX_FILTER_CONFIGURATION, &filterGain, 0x01, 0); + + switch (filterGain) + { + case 0: + firFilter->gain_dB = 0; + break; + case 1: + firFilter->gain_dB = 6; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_TXFIR_INV_GAIN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_TXFIR_INV_GAIN_PARM)); + return MYKONOS_ERR_TXFIR_INV_GAIN_PARM; + } + } + + /* Select which FIR filter to read the coeffs for */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_CTL, (PROGRAM_CLK_EN | filterSelect)); //select filter and enable the programming clock + + if (firFilter->numFirCoefs > maxNumTaps) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READFIR_INV_NUMTAPS_PARM, + getMykonosErrorMessage(MYKONOS_ERR_READFIR_INV_NUMTAPS_PARM)); + return MYKONOS_ERR_READFIR_INV_NUMTAPS_PARM; + } + + /* write filter coefficients */ + for (i = 0; i < firFilter->numFirCoefs; i++) + { + /* Write Low byte of 16bit coefficient */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_ADDR, (uint8_t)(i * 2)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_CTL, (PROGRAM_CLK_EN | filterSelect)); /* write enable (self clearing) */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_DATA, &lsbRead); + + /* Write High Byte of 16bit coefficient */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_ADDR, (uint8_t)((i * 2) + 1)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_CTL, (PROGRAM_CLK_EN | filterSelect));/* write enable (self clearing) */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_PFIR_COEFF_DATA, &msbRead); + + firFilter->coefs[i] = (int16_t)((lsbRead & 0xFF) | ((msbRead << 8) & 0xFF00)); + } + + return MYKONOS_ERR_OK; +} + +/* + ***************************************************************************** + * Rx Data path functions + ***************************************************************************** + */ +/*! + * \brief Programs the gain table settings for either Rx1, Rx2, Rx1 + Rx2, ORx, or SnRx receiver types + * + * The gain table for a receiver type is set with the parameters passed by uint8_t gainTablePtr array. + * gainTablePtr is a 4 x n array, where there are four (4) elements per index, and the array + * length (n) is dependent upon receiver type. The (n) value is conveyed by numGainIndexesInTable. + * All gain tables have a maximum index of 255 when used with this function. The minimum gain index is + * application dependent. + * + * Where for Rx1, Rx2, and ObsRx: + * [A, B, C, D]: A = Front End Gain, B = External Control, C = Digital Attenuation/Gain, D = Attenuation/Gain select + * + * Where for SnRx: + * [A, B, C, D]: A = Front End Gain, B = LNA Bypass, C = Digital Attenuation/Gain, D = Attenuation/Gain select + * + * The gain table starting address changes with each receiver type. This function accounts for this change as well as the + * difference between byte [B] for {Rx1, Rx2, ObsRx} and SnRx receiver array values and programs the correct registers. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos data structure + * \param gainTablePtr Pointer to 4 x n array containing gain table program values + * \param numGainIndexesInTable The number of 'n' indices in 4 x n array. A range check is performed to ensure the maximum is not exceeded. + * \param rxChannel mykonosGainTable_t enum type to select either Rx1, Rx2, Rx1 + Rx2, ORx, or SnRx gain table for programming. A + * channel check is performed to ensure a valid selection. + * + * \return Returns enum MYKONOS_ERR, MYKONOS_ERR_OK if successful, MYKONOS_ERR_RXGAINTABLE_INV_CHANNEL if invalid channel is selected, MYKONOS_ERR_RXGAINTABLE_INV_GAIN_INDEX_RANGE + * if numGainIndexesInTable exceeds range for selected receiver gain table + */ +mykonosErr_t MYKONOS_programRxGainTable(mykonosDevice_t *device, uint8_t *gainTablePtr, uint8_t numGainIndexesInTable, mykonosGainTable_t rxChannel) +{ + uint8_t ctlReg = 0; + uint8_t ch3CtlReg = 0; + uint16_t rxFEGainAddr = 0; + uint16_t rxExtCtlLnaAddr = 0; + uint16_t rxDigGainAttenAddr = 0; + uint16_t rx2FEGainAddr = 0; + uint16_t rx2ExtCtlAddr = 0; + uint16_t rx2DigGainAttenAddr = 0; + uint8_t minGainIndex = 0; + uint8_t startIndex = 0; + int16_t i = 0; + uint16_t tableRowIndex = 0; + uint8_t retFlag = 0; + +#if MYK_ENABLE_SPIWRITEARRAY + uint32_t addrIndex = 0; + uint32_t dataIndex = 0; + uint32_t spiBufferSize = (((MYK_SPIWRITEARRAY_BUFFERSIZE / 9) - 1) * 9); + uint16_t addrArray[MYK_SPIWRITEARRAY_BUFFERSIZE] = {0}; + uint8_t dataArray[MYK_SPIWRITEARRAY_BUFFERSIZE] = {0}; +#endif + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_programRxGainTable()\n"); +#endif + + if (gainTablePtr == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_PROGRAM_RXGAIN_TABLE_NULL_PARM, + getMykonosErrorMessage(MYKONOS_ERR_PROGRAM_RXGAIN_TABLE_NULL_PARM)); + return MYKONOS_ERR_PROGRAM_RXGAIN_TABLE_NULL_PARM; + } + + /* checking range of numGainIndexesInTable against maximums and for valid rxChannel selection */ + switch (rxChannel) + { + case RX1_GT: + /* Rx1 max gain index = 255, check is out of range of uint8_t */ + break; + case RX2_GT: + /* Rx1 max gain index = 255, check is out of range of uint8_t */ + break; + case RX1_RX2_GT: + /* Rx1 max gain index = 255, check is out of range of uint8_t */ + break; + case ORX_GT: + if (numGainIndexesInTable > MAX_ORX_GAIN_TABLE_NUMINDEXES) + { + retFlag = 1; + } + break; + case SNRX_GT: + if (numGainIndexesInTable > MAX_SNRX_GAIN_TABLE_NUMINDEXES) + { + retFlag = 1; + } + break; + case LOOPBACK_GT: + if (numGainIndexesInTable > MAX_LOOPBACK_GAIN_TABLE_NUMINDEXES) + { + retFlag = 1; + } + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RXGAINTABLE_INV_CHANNEL, + getMykonosErrorMessage(MYKONOS_ERR_RXGAINTABLE_INV_CHANNEL)); + return MYKONOS_ERR_RXGAINTABLE_INV_CHANNEL; + } + + if (retFlag) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RXGAINTABLE_INV_GAIN_INDEX_RANGE, + getMykonosErrorMessage(MYKONOS_ERR_RXGAINTABLE_INV_GAIN_INDEX_RANGE)); + return MYKONOS_ERR_RXGAINTABLE_INV_GAIN_INDEX_RANGE; + } + else + { + /* calculating minimum gain index value */ + minGainIndex = MAX_GAIN_TABLE_INDEX - numGainIndexesInTable + 1; + } + + /* forming control register words based on channel select, assigning starting index, and register addressing, also updating max and min gain table indices in structure */ + switch (rxChannel) + { + case RX1_GT: + ctlReg = ((uint8_t)rxChannel << 3) | 0x05; + startIndex = START_RX_GAIN_INDEX; + rxFEGainAddr = MYKONOS_ADDR_GAIN_TABLE_RX1_FE_GAIN; + rxExtCtlLnaAddr = MYKONOS_ADDR_GAIN_TABLE_RX1_EXT_CTL; + rxDigGainAttenAddr = MYKONOS_ADDR_GAIN_TABLE_RX1_DIG_GAIN; + device->rx->rxGainCtrl->rx1MaxGainIndex = MAX_GAIN_TABLE_INDEX; + device->rx->rxGainCtrl->rx1MinGainIndex = minGainIndex; + break; + case RX2_GT: + ctlReg = ((uint8_t)rxChannel << 3) | 0x05; + startIndex = START_RX_GAIN_INDEX; + rxFEGainAddr = MYKONOS_ADDR_GAIN_TABLE_RX2_FE_GAIN; + rxExtCtlLnaAddr = MYKONOS_ADDR_GAIN_TABLE_RX2_EXT_CTL; + rxDigGainAttenAddr = MYKONOS_ADDR_GAIN_TABLE_RX2_DIG_GAIN; + device->rx->rxGainCtrl->rx2MaxGainIndex = MAX_GAIN_TABLE_INDEX; + device->rx->rxGainCtrl->rx2MinGainIndex = minGainIndex; + break; + case RX1_RX2_GT: + ctlReg = ((uint8_t)rxChannel << 3) | 0x05; + startIndex = START_RX_GAIN_INDEX; + rxFEGainAddr = MYKONOS_ADDR_GAIN_TABLE_RX1_FE_GAIN; + rx2FEGainAddr = MYKONOS_ADDR_GAIN_TABLE_RX2_FE_GAIN; + rxExtCtlLnaAddr = MYKONOS_ADDR_GAIN_TABLE_RX1_EXT_CTL; + rx2ExtCtlAddr = MYKONOS_ADDR_GAIN_TABLE_RX2_EXT_CTL; + rxDigGainAttenAddr = MYKONOS_ADDR_GAIN_TABLE_RX1_DIG_GAIN; + rx2DigGainAttenAddr = MYKONOS_ADDR_GAIN_TABLE_RX2_DIG_GAIN; + device->rx->rxGainCtrl->rx1MaxGainIndex = MAX_GAIN_TABLE_INDEX; + device->rx->rxGainCtrl->rx1MinGainIndex = minGainIndex; + device->rx->rxGainCtrl->rx2MaxGainIndex = MAX_GAIN_TABLE_INDEX; + device->rx->rxGainCtrl->rx2MinGainIndex = minGainIndex; + break; + case ORX_GT: + ctlReg = 0x05; + ch3CtlReg = 0x08; + startIndex = START_ORX_GAIN_INDEX; + rxFEGainAddr = MYKONOS_ADDR_GAIN_TABLE_RX3_FE_GAIN; + rxExtCtlLnaAddr = MYKONOS_ADDR_GAIN_TABLE_RX3_LNA_ENAB; + rxDigGainAttenAddr = MYKONOS_ADDR_GAIN_TABLE_RX3_DIG_GAIN; + device->obsRx->orxGainCtrl->maxGainIndex = MAX_GAIN_TABLE_INDEX; + device->obsRx->orxGainCtrl->minGainIndex = minGainIndex; + break; + case SNRX_GT: + ctlReg = 0x05; + ch3CtlReg = 0x00; + startIndex = START_SNRX_GAIN_INDEX; + rxFEGainAddr = MYKONOS_ADDR_GAIN_TABLE_RX3_FE_GAIN; + rxExtCtlLnaAddr = MYKONOS_ADDR_GAIN_TABLE_RX3_LNA_ENAB; + rxDigGainAttenAddr = MYKONOS_ADDR_GAIN_TABLE_RX3_DIG_GAIN; + device->obsRx->snifferGainCtrl->maxGainIndex = MAX_GAIN_TABLE_INDEX; + device->obsRx->snifferGainCtrl->minGainIndex = minGainIndex; + break; + /*case LOOPBACK_GT: Loopback is only for ARM calibrations */ + default: + ctlReg = 0x05; + ch3CtlReg = 0x10; + startIndex = START_LOOPBACK_GAIN_INDEX; + rxFEGainAddr = MYKONOS_ADDR_GAIN_TABLE_RX3_FE_GAIN; + rxExtCtlLnaAddr = MYKONOS_ADDR_GAIN_TABLE_RX3_LNA_ENAB; + rxDigGainAttenAddr = MYKONOS_ADDR_GAIN_TABLE_RX3_DIG_GAIN; + break; + } + + /* starting the gain table clock and read from gain table address bits */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION, ctlReg); + + /* if ORx or Sniffer are selected also writing channel 3 readback bits for ObsRx or Sniffer selection */ + if (rxChannel > RX1_RX2_GT) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION, ch3CtlReg); + } + + /* programming a table selected by rxChannel enum type */ + +#if MYK_ENABLE_SPIWRITEARRAY == 0 + + for(i = startIndex; i >= ((startIndex + 1) - numGainIndexesInTable); i--) + { + tableRowIndex = (uint16_t)(startIndex - i) << 2; + + /* set current gain table index (address) */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GAIN_TABLE_ADDR, i); + + /* Set Rx Front End gain[5:0] */ + CMB_SPIWriteByte(device->spiSettings, rxFEGainAddr, gainTablePtr[tableRowIndex]); + + /* Set external control [5:0] OR LNA bypass if rxChannel == SNRX_GT */ + if (rxChannel == SNRX_GT) + { + CMB_SPIWriteByte(device->spiSettings, rxExtCtlLnaAddr, gainTablePtr[tableRowIndex + 1] << 4); + } + else + { + CMB_SPIWriteByte(device->spiSettings, rxExtCtlLnaAddr, gainTablePtr[tableRowIndex + 1]); + } + + /* Set digital attenuation/gain[6:0] and set/clear attenuation bit */ + CMB_SPIWriteByte(device->spiSettings, rxDigGainAttenAddr, (gainTablePtr[tableRowIndex + 3] << 7) | gainTablePtr[tableRowIndex + 2]); + + /* repeating gain table settings if Rx1 and Rx2 are selected for Rx2 configuration */ + if (rxChannel == RX1_RX2_GT) + { + /* Set Rx Front End gain[5:0] */ + CMB_SPIWriteByte(device->spiSettings, rx2FEGainAddr, gainTablePtr[tableRowIndex]); + + /* Set external control [5:0] */ + CMB_SPIWriteByte(device->spiSettings, rx2ExtCtlAddr, gainTablePtr[tableRowIndex + 1]); + + /* Set digital attenuation/gain[6:0] */ + CMB_SPIWriteByte(device->spiSettings, rx2DigGainAttenAddr, (gainTablePtr[tableRowIndex + 3] << 7) | gainTablePtr[tableRowIndex + 2]); + } + + /* setting the write enable depending on rxChannel choice */ + if (rxChannel == ORX_GT) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION, ch3CtlReg | 0x02); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION, ctlReg | 0x02); + } + else if (rxChannel == SNRX_GT) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION, ch3CtlReg | 0x01); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION, ctlReg | 0x02); + } + else if (rxChannel == LOOPBACK_GT) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION, ch3CtlReg | 0x04); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION, ctlReg | 0x02); + } + else + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION, ctlReg | 0x02); + } + } + +#elif MYK_ENABLE_SPIWRITEARRAY == 1 +//#elif 0 + + addrIndex = 0; + dataIndex = 0; + for(i = startIndex; i >= ((startIndex + 1) - numGainIndexesInTable); i--) + { + tableRowIndex = (uint16_t)(startIndex - (uint8_t)i) << 2; + + /* set current gain table index (address) */ + addrArray[addrIndex++] = MYKONOS_ADDR_GAIN_TABLE_ADDR; + dataArray[dataIndex++] = (uint8_t)i; + + /* Set Rx Front End gain[5:0] */ + addrArray[addrIndex++] = rxFEGainAddr; + dataArray[dataIndex++] = gainTablePtr[tableRowIndex]; + + /* Set external control [5:0] OR LNA bypass if rxChannel == SNRX_GT */ + addrArray[addrIndex++] = rxExtCtlLnaAddr; + dataArray[dataIndex++] = (rxChannel == SNRX_GT) ? (uint8_t)(gainTablePtr[tableRowIndex + 1] << 4) : (gainTablePtr[tableRowIndex + 1]); + + /* Set digital attenuation/gain[6:0] and set/clear attenuation bit */ + addrArray[addrIndex++] = rxDigGainAttenAddr; + dataArray[dataIndex++] = ((uint8_t)(gainTablePtr[tableRowIndex + 3] << 7) | gainTablePtr[tableRowIndex + 2]); + + /* repeating gain table settings if Rx1 and Rx2 are selected for Rx2 configuration */ + if (rxChannel == RX1_RX2_GT) + { + /* Set Rx Front End gain[5:0] */ + addrArray[addrIndex++] = rx2FEGainAddr; + dataArray[dataIndex++] = gainTablePtr[tableRowIndex]; + + /* Set external control [5:0] */ + addrArray[addrIndex++] = rx2ExtCtlAddr; + dataArray[dataIndex++] = gainTablePtr[tableRowIndex + 1]; + + /* Set digital attenuation/gain[6:0] */ + addrArray[addrIndex++] = rx2DigGainAttenAddr; + dataArray[dataIndex++] = ((uint8_t)(gainTablePtr[tableRowIndex + 3] << 7) | gainTablePtr[tableRowIndex + 2]); + } + + /* setting the write enable depending on rxChannel choice */ + if (rxChannel == ORX_GT) + { + addrArray[addrIndex++] = MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION; + dataArray[dataIndex++] = (ch3CtlReg | 0x02); + addrArray[addrIndex++] = MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION; + dataArray[dataIndex++] = (ctlReg | 0x02); + } + else if (rxChannel == SNRX_GT) + { + addrArray[addrIndex++] = MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION; + dataArray[dataIndex++] = (ch3CtlReg | 0x01); + addrArray[addrIndex++] = MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION; + dataArray[dataIndex++] = (ctlReg | 0x02); + } + else if (rxChannel == LOOPBACK_GT) + { + addrArray[addrIndex++] = MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION; + dataArray[dataIndex++] = (ch3CtlReg | 0x04); + addrArray[addrIndex++] = MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION; + dataArray[dataIndex++] = (ctlReg | 0x02); + } + else + { + addrArray[addrIndex++] = MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION; + dataArray[dataIndex++] = (ctlReg | 0x02); + } + + if (addrIndex >= spiBufferSize) + { + CMB_SPIWriteBytes(device->spiSettings, &addrArray[0], &dataArray[0], addrIndex); + dataIndex = 0; + addrIndex = 0; + } + } + + if (addrIndex > 0) + { + CMB_SPIWriteBytes(device->spiSettings, &addrArray[0], &dataArray[0], addrIndex); + } + +#endif + + /* clearing the channel 3 gain table configuration register if selected and stopping the gain table clock */ + if (rxChannel > RX1_RX2_GT) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION, 0x00); + } + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION, 0x08); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets the Rx1 Manual Gain Index + * + * If the value passed in the gainIndex parameter is within range of the gain table minimum and + * maximum indexes, the Rx1 gain index will be updated in the device data structure + * and written to the transceiver. Else, an error will be returned. The maximum index is 255 + * and the minimum index is application specific. + * + * Dependencies + * - device->spiSettings + * - device->rxSettings->rxGainControl->rx1GainIndex + * - device->rxSettings->rxGainControl->rx1MaxGainIndex + * - device->rxSettings->rxGainControl->rx1MinGainIndex + * + * \param device Pointer to the Mykonos data structure + * \param gainIndex Desired Rx1 gain index + * + * \return Returns enum MYKONOS_ERR, MYKONOS_ERR_OK=pass, !MYKONOS_ERR_OK=fail + */ +mykonosErr_t MYKONOS_setRx1ManualGain(mykonosDevice_t *device, uint8_t gainIndex) +{ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setRx1ManualGain()\n"); +#endif + + if ((gainIndex < device->rx->rxGainCtrl->rx1MinGainIndex) || (gainIndex > device->rx->rxGainCtrl->rx1MaxGainIndex)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETRX1GAIN_INV_GAIN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SETRX1GAIN_INV_GAIN_PARM)); + return MYKONOS_ERR_SETRX1GAIN_INV_GAIN_PARM; + + } + else + { + /* If the desired gain index is in range of the gain table, update the + * value in the device data structure, and write to device. + */ + device->rx->rxGainCtrl->rx1GainIndex = gainIndex; + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_1, gainIndex); + + return MYKONOS_ERR_OK; + } +} + +/** + * \brief Sets the Rx2 Manual Gain index + * + * If the value passed in the gainIndex parameter is within range of the gain table minimum and + * maximum indexes, the Rx2 gain index will be updated in the device data structure + * and written to the transceiver. Else, an error will be returned. The maximum index is 255 + * and the minimum index is application specific. + * + * Dependencies + * - device->spiSettings + * - device->rxTxSettings->rxGainControl->rx2GainIndex + * - device->rxTxSettings->rxGainControl->rx2MaxGainIndex + * - device->rxTxSettings->rxGainControl->rx2MinGainIndex + * + * \param device Pointer to the Mykonos data structure + * \param gainIndex Desired Rx2 gain index + * + * \return Returns enum MYKONOS_ERR, MYKONOS_ERR_OK=pass, !MYKONOS_ERR_OK=fail + */ +mykonosErr_t MYKONOS_setRx2ManualGain(mykonosDevice_t *device, uint8_t gainIndex) +{ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setRx2ManualGain()\n"); +#endif + + if ((gainIndex < device->rx->rxGainCtrl->rx2MinGainIndex) || (gainIndex > device->rx->rxGainCtrl->rx2MaxGainIndex)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETRX2GAIN_INV_GAIN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SETRX2GAIN_INV_GAIN_PARM)); + return MYKONOS_ERR_SETRX2GAIN_INV_GAIN_PARM; + + } + else + { + /* If the desired gain index is in range of the gain table, update the + * value in the device data structure, and write to device. + */ + device->rx->rxGainCtrl->rx2GainIndex = gainIndex; + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_2, gainIndex); + + return MYKONOS_ERR_OK; + } +} + +/** + * \brief Reads the Rx1 Gain Index for Manual or AGC gain control mode + * + * This function reads the Rx1 gain index for manual or AGC modes. If the + * *rx1GainIndex pointer is nonzero, the read back gain index will + * be returned in the parameter. If the *rx1GainIndex pointer + * is NULL, the device data structure will be updated with the new read back value + * + * Dependencies + * - device->spiSettings + * - device->rxTxSettings->rxGainControl->rx1GainIndex + * + * \param device Pointer to the Mykonos data structure + * \param rx1GainIndex uint8_t Pointer to the Rx1 gain index value + * + * \return Returns enum MYKONOS_ERR, MYKONOS_ERR_OK=pass, !MYKONOS_ERR_OK=fail + */ +mykonosErr_t MYKONOS_getRx1Gain(mykonosDevice_t *device, uint8_t *rx1GainIndex) +{ + uint8_t readData = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getRx1Gain()\n"); +#endif + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GAIN_CTL_CHANNEL_1, &readData); + + /* + * If rx1GainIndex address is not NULL, return the Rx1 gain index in the + * rx1GainIndex function parameter + */ + if (rx1GainIndex != NULL) + { + *rx1GainIndex = readData; + } + + /* + * set the current Rx1 gain in the device data structure + */ + if (device->profilesValid & RX_PROFILE_VALID) + { + device->rx->rxGainCtrl->rx1GainIndex = readData; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads the Rx2 Gain Index for Manual or AGC gain control mode + * + * This function reads the Rx2 gain index for manual or AGC modes. If the + * *rx1GainIndex pointer is nonzero, the read back gain index will + * be returned in the parameter. If the *rx1GainIndex pointer + * is NULL, the device data structure will be updated with the new read back value + * + * Dependencies + * - device->spiSettings + * - device->rxTxSettings->rxGainControl->rx2GainIndex + * + * \param device Pointer to the Mykonos data structure + * \param rx2GainIndex Desired Rx2 gain index + * + * \return Returns enum MYKONOS_ERR, MYKONOS_ERR_OK=pass, !MYKONOS_ERR_OK=fail + */ +mykonosErr_t MYKONOS_getRx2Gain(mykonosDevice_t *device, uint8_t *rx2GainIndex) +{ + uint8_t readData = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getRx2Gain()\n"); +#endif + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GAIN_CTL_CHANNEL_2, &readData); + + /* + * If rx1GainIndex address is not NULL, return the Rx1 gain index in the + * rx1GainIndex function parameter + */ + if (rx2GainIndex != NULL) + { + *rx2GainIndex = readData; + } + + /* + * set the current Rx2 gain in the device data structure + */ + if (device->profilesValid & RX_PROFILE_VALID) + { + device->rx->rxGainCtrl->rx2GainIndex = readData; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets up the device Rx Automatic Gain Control (AGC) registers. + * + * Three data structures (mykonosAgcCfg_t, mykonosPeakDetAgcCfg_t, mykonosPowerMeasAgcCfg_t) + * must be instantiated prior to calling this function. Valid ranges for data structure members + * must also be provided. + * + * + * Dependencies: + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * - device->rx->rxAgcCtrl->agcRx1MaxGainIndex + * - device->rx->rxAgcCtrl->agcRx1MinGainIndex + * - device->rx->rxAgcCtrl->agcRx2MaxGainIndex + * - device->rx->rxAgcCtrl->agcRx2MinGainIndex + * - device->rx->rxAgcCtrl->agcObsRxMaxGainIndex + * - device->rx->rxAgcCtrl->agcObsRxMinGainIndex + * - device->rx->rxAgcCtrl->agcObsRxSelect + * - device->rx->rxAgcCtrl->agcPeakThresholdMode + * - device->rx->rxAgcCtrl->agcLowThsPreventGainIncrease + * - device->rx->rxAgcCtrl->agcGainUpdateCounter + * - device->rx->rxAgcCtrl->agcSlowLoopSettlingDelay + * - device->rx->rxAgcCtrl->agcPeakWaitTime + * - device->rx->rxAgcCtrl->agcResetOnRxEnable + * - device->rx->rxAgcCtrl->agcEnableSyncPulseForGainCounter + * - device->rx->rxAgcCtrl->peakAgc->apdHighThresh + * - device->rx->rxAgcCtrl->peakAgc->apdLowThresh + * - device->rx->rxAgcCtrl->peakAgc->hb2HighThresh + * - device->rx->rxAgcCtrl->peakAgc->hb2LowThresh + * - device->rx->rxAgcCtrl->peakAgc->hb2VeryLowThresh + * - device->rx->rxAgcCtrl->peakAgc->apdHighThreshExceededCnt + * - device->rx->rxAgcCtrl->peakAgc->apdLowThreshExceededCnt + * - device->rx->rxAgcCtrl->peakAgc->hb2HighThreshExceededCnt + * - device->rx->rxAgcCtrl->peakAgc->hb2LowThreshExceededCnt + * - device->rx->rxAgcCtrl->peakAgc->hb2VeryLowThreshExceededCnt + * - device->rx->rxAgcCtrl->peakAgc->apdHighGainStepAttack + * - device->rx->rxAgcCtrl->peakAgc->apdLowGainStepRecovery + * - device->rx->rxAgcCtrl->peakAgc->hb2HighGainStepAttack + * - device->rx->rxAgcCtrl->peakAgc->hb2LowGainStepRecovery + * - device->rx->rxAgcCtrl->peakAgc->hb2VeryLowGainStepRecovery + * - device->rx->rxAgcCtrl->peakAgc->apdFastAttack + * - device->rx->rxAgcCtrl->peakAgc->hb2FastAttack + * - device->rx->rxAgcCtrl->peakAgc->hb2OverloadDetectEnable + * - device->rx->rxAgcCtrl->peakAgc->hb2OverloadDurationCnt + * - device->rx->rxAgcCtrl->peakAgc->hb2OverloadThreshCnt + * - device->rx->rxAgcCtrl->powerAgc->pmdUpperHighThresh + * - device->rx->rxAgcCtrl->powerAgc->pmdUpperLowThresh + * - device->rx->rxAgcCtrl->powerAgc->pmdLowerHighThresh + * - device->rx->rxAgcCtrl->powerAgc->pmdLowerLowThresh + * - device->rx->rxAgcCtrl->powerAgc->pmdUpperHighGainStepAttack + * - device->rx->rxAgcCtrl->powerAgc->pmdUpperLowGainStepAttack + * - device->rx->rxAgcCtrl->powerAgc->pmdLowerHighGainStepRecovery + * - device->rx->rxAgcCtrl->powerAgc->pmdLowerLowGainStepRecovery + * - device->rx->rxAgcCtrl->powerAgc->pmdMeasDuration + * - device->rx->rxAgcCtrl->powerAgc->pmdMeasConfig + * + * \param device is structure pointer to the Mykonos data structure containing settings + * The pointer to the Mykonos AGC data structure containing settings is checked for a null pointer + * to ensure it has been initialized. If not an error is thrown. + * + * \retval Returns MYKONOS_ERR=pass, !MYKONOS_ERR=fail + * \retval MYKONOS_ERR_INV_AGC_RX_STRUCT_INIT + * \retval MYKONOS_ERR_INV_AGC_RX_PEAK_STRUCT_INIT + * \retval MYKONOS_ERR_INV_AGC_RX_PWR_STRUCT_INIT + * \retval MYKONOS_ERR_INV_AGC_RX1_MAX_GAIN_INDEX + * \retval MYKONOS_ERR_INV_AGC_RX1_MIN_GAIN_INDEX + * \retval MYKONOS_ERR_INV_AGC_RX2_MAX_GAIN_INDEX + * \retval MYKONOS_ERR_INV_AGC_RX2_MIN_GAIN_INDEX + * \retval MYKONOS_ERR_INV_AGC_RX_GAIN_UPDATE_TIME_PARM + * \retval MYKONOS_ERR_INV_AGC_RX_PEAK_WAIT_TIME_PARM + * \retval MYKONOS_ERR_INV_AGC_RX_SLOW_LOOP_SETTLING_DELAY + * \retval MYKONOS_ERR_INV_AGC_PMD_MEAS_DURATION + * \retval MYKONOS_ERR_INV_AGC_PMD_MEAS_CONFIG + * \retval MYKONOS_ERR_INV_AGC_RX_LOW_THS_PREV_GAIN_INC + * \retval MYKONOS_ERR_INV_AGC_RX_PEAK_THRESH_MODE + * \retval MYKONOS_ERR_INV_AGC_RX_RESET_ON_RX_ENABLE + * \retval MYKONOS_ERR_INV_AGC_RX_ENABLE_SYNC_PULSE_GAIN_COUNTER + * \retval MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_HIGH_THRESH + * \retval MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_THRESH + * \retval MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_THRESH + * \retval MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_THRESH + * \retval MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_GAIN_STEP + * \retval MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_GAIN_STEP + * \retval MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_GAIN_STEP + * \retval MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_GAIN_STEP + * \retval MYKONOS_ERR_INV_AGC_RX_PKDET_FAST_ATTACK_VALUE + * \retval MYKONOS_ERR_INV_AGC_RX_APD_HIGH_THRESH_PARM + * \retval MYKONOS_ERR_INV_AGC_RX_APD_LOW_THRESH_PARM + * \retval MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_THRESH_PARM + * \retval MYKONOS_ERR_INV_AGC_RX_HB2_LOW_THRESH_PARM + * \retval MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_THRESH_PARM + * \retval MYKONOS_ERR_INV_AGC_RX_APD_HIGH_GAIN_STEP_PARM + * \retval MYKONOS_ERR_INV_AGC_RX_APD_LOW_GAIN_STEP_PARM + * \retval MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_GAIN_STEP_PARM + * \retval MYKONOS_ERR_INV_AGC_RX_HB2_LOW_GAIN_STEP_PARM + * \retval MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_GAIN_STEP_PARM + * \retval MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_ENABLE + * \retval MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_DUR_CNT + * \retval MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_THRESH_CNT + */ +mykonosErr_t MYKONOS_setupRxAgc(mykonosDevice_t *device) +{ + uint8_t decPowerConfig = 0; + uint8_t lower1ThreshGainStepRegValue = 0; + uint8_t powerThresholdsRegValue = 0; + uint8_t hb2OvldCfgRegValue = 0; + uint8_t agcGainUpdateCtr[3] = {0}; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setRxAgc()\n"); +#endif + + /* Check mykonosAgcCfg_t device->rx->rxAgcCtrl pointer for initialization */ + if (device->rx->rxAgcCtrl == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_STRUCT_INIT, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_STRUCT_INIT)); + return MYKONOS_ERR_INV_AGC_RX_STRUCT_INIT; + } + + /* Check mykonosPeakDetAgcCfg_t device->rx->rxAgcCtrl->peakAgc pointer for initialization */ + if (device->rx->rxAgcCtrl->peakAgc == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_PEAK_STRUCT_INIT, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_PEAK_STRUCT_INIT)); + return MYKONOS_ERR_INV_AGC_RX_PEAK_STRUCT_INIT; + } + + /* Check mykonosPowerMeasAgcCfg_t device->rx->rxAgcCtrl->powerAgc pointer for initialization */ + if (device->rx->rxAgcCtrl->powerAgc == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_PWR_STRUCT_INIT, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_PWR_STRUCT_INIT)); + return MYKONOS_ERR_INV_AGC_RX_PWR_STRUCT_INIT; + } + + /* Range check agcRx1MaxGainIndex versus gain table limits */ + if ((device->rx->rxAgcCtrl->agcRx1MaxGainIndex > device->rx->rxGainCtrl->rx1MaxGainIndex) + || (device->rx->rxAgcCtrl->agcRx1MaxGainIndex < device->rx->rxAgcCtrl->agcRx1MinGainIndex)) + + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX1_MAX_GAIN_INDEX, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX1_MAX_GAIN_INDEX)); + return MYKONOS_ERR_INV_AGC_RX1_MAX_GAIN_INDEX; + } + else + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_RX1_MAX_GAIN_INDEX, device->rx->rxAgcCtrl->agcRx1MaxGainIndex); + } + + /* Range check agcRx1MinGainIndex versus gain table limits */ + if ((device->rx->rxAgcCtrl->agcRx1MinGainIndex < device->rx->rxGainCtrl->rx1MinGainIndex) + || (device->rx->rxAgcCtrl->agcRx1MaxGainIndex < device->rx->rxAgcCtrl->agcRx1MinGainIndex)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX1_MIN_GAIN_INDEX, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX1_MIN_GAIN_INDEX)); + return MYKONOS_ERR_INV_AGC_RX1_MIN_GAIN_INDEX; + } + else + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_RX1_MIN_GAIN_INDEX, device->rx->rxAgcCtrl->agcRx1MinGainIndex); + } + + /* Range check agcRx2MaxGainIndex versus gain table limits */ + if ((device->rx->rxAgcCtrl->agcRx2MaxGainIndex > device->rx->rxGainCtrl->rx2MaxGainIndex) + || (device->rx->rxAgcCtrl->agcRx2MaxGainIndex < device->rx->rxAgcCtrl->agcRx2MinGainIndex)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX2_MAX_GAIN_INDEX, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX2_MAX_GAIN_INDEX)); + return MYKONOS_ERR_INV_AGC_RX2_MAX_GAIN_INDEX; + } + else + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_RX2_MAX_GAIN_INDEX, device->rx->rxAgcCtrl->agcRx2MaxGainIndex); + } + + /* Range check agcRx2MinGainIndex versus gain table limits */ + if ((device->rx->rxAgcCtrl->agcRx2MinGainIndex < device->rx->rxGainCtrl->rx2MinGainIndex) + || (device->rx->rxAgcCtrl->agcRx2MaxGainIndex < device->rx->rxAgcCtrl->agcRx2MinGainIndex)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX2_MIN_GAIN_INDEX, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX2_MIN_GAIN_INDEX)); + return MYKONOS_ERR_INV_AGC_RX2_MIN_GAIN_INDEX; + } + else + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_RX2_MIN_GAIN_INDEX, device->rx->rxAgcCtrl->agcRx2MinGainIndex); + } + + /* Range check for agcGainUpdateCounter (22-bit) */ + if ((device->rx->rxAgcCtrl->agcGainUpdateCounter > 0x3FFFFF) || (device->rx->rxAgcCtrl->agcGainUpdateCounter < 1)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_GAIN_UPDATE_TIME_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_GAIN_UPDATE_TIME_PARM)); + return MYKONOS_ERR_INV_AGC_RX_GAIN_UPDATE_TIME_PARM; + } + else + { + /* Split agcGainUpdateCounter into three values */ + agcGainUpdateCtr[0] = (uint8_t)(device->rx->rxAgcCtrl->agcGainUpdateCounter); + agcGainUpdateCtr[1] = (uint8_t)(device->rx->rxAgcCtrl->agcGainUpdateCounter >> 8); + agcGainUpdateCtr[2] = (uint8_t)(device->rx->rxAgcCtrl->agcGainUpdateCounter >> 16); + + /* Write two bytes directly due. Third word has its upper two bits masked off. */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_1, agcGainUpdateCtr[0]); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_2, agcGainUpdateCtr[1]); + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_3, agcGainUpdateCtr[2], 0x3F, 0); + } + + /* Range check on agcPeakWaitTime (5-bit) */ + if (device->rx->rxAgcCtrl->agcPeakWaitTime > 0x1F || device->rx->rxAgcCtrl->agcPeakWaitTime < 0x02) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_PEAK_WAIT_TIME_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_PEAK_WAIT_TIME_PARM)); + return MYKONOS_ERR_INV_AGC_RX_PEAK_WAIT_TIME_PARM; + } + else + { + /* Write agcPeakWaitTime */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_CFG_2, device->rx->rxAgcCtrl->agcPeakWaitTime, 0x1F, 0); + } + + /* Set MYKONOS_ADDR_AGC_CFG_2 bits [6:5] = b11 to enable AGC counters for MGC mode - needed for ARM cals to work correctly */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_CFG_2, 3, 0x60, 5); + + /* Range check for agcSlowLoopSettlingDelay (7-bit) */ + if (device->rx->rxAgcCtrl->agcSlowLoopSettlingDelay > 0x7F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_SLOW_LOOP_SETTLING_DELAY, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_SLOW_LOOP_SETTLING_DELAY)); + return MYKONOS_ERR_INV_AGC_RX_SLOW_LOOP_SETTLING_DELAY; + } + else + { + /* Write agcSlowLoopSettlingDelay */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_LOOP_CFG, device->rx->rxAgcCtrl->agcSlowLoopSettlingDelay, 0x7F, 0); + } + + /* Range check for pmdMeasDuration */ + if ((uint32_t)(1 << (3 + device->rx->rxAgcCtrl->powerAgc->pmdMeasDuration)) >= (device->rx->rxAgcCtrl->agcGainUpdateCounter)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_PMD_MEAS_DURATION, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_PMD_MEAS_DURATION)); + return MYKONOS_ERR_INV_AGC_PMD_MEAS_DURATION; + } + else + { + /* Write pmdMeasDuration */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_DEC_POWER_CONFIG_2, device->rx->rxAgcCtrl->powerAgc->pmdMeasDuration, 0x0F, 0); + } + + /* Range check for pmdMeasConfig */ + if (device->rx->rxAgcCtrl->powerAgc->pmdMeasConfig > 0x3) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_PMD_MEAS_CONFIG, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_PMD_MEAS_CONFIG)); + return MYKONOS_ERR_INV_AGC_PMD_MEAS_CONFIG; + } + else + { + if (device->rx->rxAgcCtrl->powerAgc->pmdMeasConfig == 0) + { + decPowerConfig = 0x0; /* Dec Pwr measurement disable */ + } + else if (device->rx->rxAgcCtrl->powerAgc->pmdMeasConfig == 1) + { + decPowerConfig = 0x3; /* Dec Pwr measurement enable, HB2 for decPwr measurement */ + } + else if (device->rx->rxAgcCtrl->powerAgc->pmdMeasConfig == 2) + { + decPowerConfig = 0x5; /* Dec Pwr measurement enable, RFIR for decPwr measurement */ + } + else if (device->rx->rxAgcCtrl->powerAgc->pmdMeasConfig == 3) + { + decPowerConfig = 0x11; /* Dec Pwr measurement enable, BBDC2 for decPwr measurement */ + } + /* Write pmdMeasConfig */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_DEC_POWER_CONFIG_1, decPowerConfig); + } + + /* Range check agcLowThsPreventGainIncrease (1-bit) */ + if (device->rx->rxAgcCtrl->agcLowThsPreventGainIncrease > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_LOW_THS_PREV_GAIN_INC, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_LOW_THS_PREV_GAIN_INC)); + return MYKONOS_ERR_INV_AGC_RX_LOW_THS_PREV_GAIN_INC; + } + else + { + /* Write agcLowThsPreventGainIncrease */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_LOCK_LEV_THRSH, device->rx->rxAgcCtrl->agcLowThsPreventGainIncrease, 0x80, 7); + } + + /* Range check agcPeakThresholdMode (1-bit), */ + if (device->rx->rxAgcCtrl->agcPeakThresholdMode > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_PEAK_THRESH_MODE, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_PEAK_THRESH_MODE)); + return MYKONOS_ERR_INV_AGC_RX_PEAK_THRESH_MODE; + } + else + { + /* Save to lower1ThreshGainStepRegValue register variable */ + lower1ThreshGainStepRegValue |= (uint8_t)(device->rx->rxAgcCtrl->agcPeakThresholdMode << 5); + } + + /* Range check agcResetOnRxEnable (1-bit) */ + if (device->rx->rxAgcCtrl->agcResetOnRxEnable > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_LOW_THS_PREV_GAIN_INC, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_LOW_THS_PREV_GAIN_INC)); + return MYKONOS_ERR_INV_AGC_RX_RESET_ON_RX_ENABLE; + } + else + { + /* Write agcResetOnRxEnable */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_3, (uint8_t)(device->rx->rxAgcCtrl->agcResetOnRxEnable << 7), 0x80, 0); + } + + /* Range check agcEnableSyncPulseForGainCounter (1-bit) */ + if (device->rx->rxAgcCtrl->agcEnableSyncPulseForGainCounter > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_ENABLE_SYNC_PULSE_GAIN_COUNTER, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_ENABLE_SYNC_PULSE_GAIN_COUNTER)); + return MYKONOS_ERR_INV_AGC_RX_ENABLE_SYNC_PULSE_GAIN_COUNTER; + } + else + { + /* Write agcEnableSyncPulseForGainCounter */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_LOOP_CFG, (uint8_t)(device->rx->rxAgcCtrl->agcEnableSyncPulseForGainCounter << 7), 0x80, 0); + } + + /* WRITE REGISTERS FOR THE AGC POWER MEASUREMENT DETECTOR (PMD) STRUCTURE */ + + /* Range check pmdLowerHighThresh (7-bit) vs 0x7F and pmdUpperLowThresh */ + if ((device->rx->rxAgcCtrl->powerAgc->pmdLowerHighThresh <= device->rx->rxAgcCtrl->powerAgc->pmdUpperLowThresh) + || device->rx->rxAgcCtrl->powerAgc->pmdLowerHighThresh > 0x7F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_HIGH_THRESH, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_HIGH_THRESH)); + return MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_HIGH_THRESH; + } + else + { + /* Write pmdLowerHighThresh */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_LOCK_LEV_THRSH, device->rx->rxAgcCtrl->powerAgc->pmdLowerHighThresh, 0x7F, 0); + } + + /* Range check pmdUpperLowThresh (7-bit): Comparison to pmdLowerHigh done earlier */ + if (device->rx->rxAgcCtrl->powerAgc->pmdUpperLowThresh > 0x7F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_THRESH, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_THRESH)); + return MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_THRESH; + } + else + { + /* Write pmdUpperLowThresh */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_LOCK_LEVEL, device->rx->rxAgcCtrl->powerAgc->pmdUpperLowThresh); + } + + /* Range check pmdLowerLowThresh (4-bit) */ + if (device->rx->rxAgcCtrl->powerAgc->pmdLowerLowThresh > 0xF) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_THRESH, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_THRESH)); + return MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_THRESH; + } + else + { + /* Write pmdUpperLowThresh to temp variable */ + powerThresholdsRegValue |= device->rx->rxAgcCtrl->powerAgc->pmdLowerLowThresh; + } + + /* Range check pmdUpperHighThresh (4-bit) */ + if (device->rx->rxAgcCtrl->powerAgc->pmdUpperHighThresh > 0xF) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_THRESH, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_THRESH)); + return MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_THRESH; + } + else + { + /* Write pmdUpperHighThresh to temp var, then to register */ + powerThresholdsRegValue |= (uint8_t)(device->rx->rxAgcCtrl->powerAgc->pmdUpperHighThresh << 4); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_POWER_THRSH, powerThresholdsRegValue); + } + + /* Range check pmdUpperHighGainStepAttack (5-bit) */ + if (device->rx->rxAgcCtrl->powerAgc->pmdUpperHighGainStepAttack > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_GAIN_STEP, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_GAIN_STEP)); + return MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_GAIN_STEP; + } + else + { + /* Write pmdUpperHighGainStepAttack */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_UPPER1_THRSH_GAIN_STEP, device->rx->rxAgcCtrl->powerAgc->pmdUpperHighGainStepAttack, 0x1F, 0); + } + + /* Range check pmdLowerLowGainStepRecovery (5-bit) */ + if (device->rx->rxAgcCtrl->powerAgc->pmdLowerLowGainStepRecovery > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_GAIN_STEP, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_GAIN_STEP)); + return MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_GAIN_STEP; + } + else + { + /* Write pmdLowerLowGainStepRecovery to temp var, then to register */ + lower1ThreshGainStepRegValue |= (device->rx->rxAgcCtrl->powerAgc->pmdLowerLowGainStepRecovery); + } + + /* Range check pmdUpperLowGainStepRecovery (5-bit) */ + if (device->rx->rxAgcCtrl->powerAgc->pmdUpperLowGainStepAttack > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_GAIN_STEP, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_GAIN_STEP)); + return MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_GAIN_STEP; + } + else + { + /* Write pmdLowerLowGainStepRecovery to temp var, then to register */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_UPPER0_THRSH_GAIN_STEP, device->rx->rxAgcCtrl->powerAgc->pmdUpperLowGainStepAttack); + } + + /* Range check pmdLowerHighGainStepRecovery (5-bit) */ + if (device->rx->rxAgcCtrl->powerAgc->pmdLowerHighGainStepRecovery > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_HIGH_GAIN_STEP, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_HIGH_GAIN_STEP)); + return MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_HIGH_GAIN_STEP; + } + else + { + /* Write pmdLowerLowGainStepRecovery to temp var, then to register */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_LOWER0_THRSH_GAIN_STEP, device->rx->rxAgcCtrl->powerAgc->pmdLowerHighGainStepRecovery); + } + + /* WRITE REGISTERS FOR THE AGC PEAK DETECTOR (APD/HB2) STRUCTURE */ + + /* Range check apdFastAttack and hb2FastAttack (1-bit) */ + if (device->rx->rxAgcCtrl->peakAgc->apdFastAttack > 0x1 || device->rx->rxAgcCtrl->peakAgc->hb2FastAttack > 0x1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_PKDET_FAST_ATTACK_VALUE, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_PKDET_FAST_ATTACK_VALUE)); + return MYKONOS_ERR_INV_AGC_RX_PKDET_FAST_ATTACK_VALUE; + } + else + { + /* Write pmdLowerLowGainStepRecovery to temp var, then to register */ + lower1ThreshGainStepRegValue |= (uint8_t)(device->rx->rxAgcCtrl->peakAgc->apdFastAttack << 7); + lower1ThreshGainStepRegValue |= (uint8_t)(device->rx->rxAgcCtrl->peakAgc->hb2FastAttack << 6); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_LOWER1_THRSH_GAIN_STEP, lower1ThreshGainStepRegValue); + } + + /* Range check apdHighThresh */ + if ((device->rx->rxAgcCtrl->peakAgc->apdHighThresh > 0x3F) || (device->rx->rxAgcCtrl->peakAgc->apdHighThresh <= device->rx->rxAgcCtrl->peakAgc->apdLowThresh)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_APD_HIGH_THRESH_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_APD_HIGH_THRESH_PARM)); + return MYKONOS_ERR_INV_AGC_RX_APD_HIGH_THRESH_PARM; + } + else + { + /* Write apdHighThresh */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_ULB_THRSH, device->rx->rxAgcCtrl->peakAgc->apdHighThresh, 0X3F, 0); + } + + /* Range check apdLowThresh */ + if ((device->rx->rxAgcCtrl->peakAgc->apdLowThresh > 0x3F) || (device->rx->rxAgcCtrl->peakAgc->apdHighThresh < device->rx->rxAgcCtrl->peakAgc->apdLowThresh)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_APD_LOW_THRESH_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_APD_LOW_THRESH_PARM)); + return MYKONOS_ERR_INV_AGC_RX_APD_LOW_THRESH_PARM; + } + else + { + /* write apdLowThresh */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_LLB_THRSH, device->rx->rxAgcCtrl->peakAgc->apdLowThresh, 0x3F, 0); + } + + /* Range check hb2HighThresh */ + if (device->rx->rxAgcCtrl->peakAgc->hb2HighThresh < device->rx->rxAgcCtrl->peakAgc->hb2LowThresh) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_THRESH_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_THRESH_PARM)); + return MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_THRESH_PARM; + } + else + { + /* write hb2HighThresh */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_UPPER_THRSH, device->rx->rxAgcCtrl->peakAgc->hb2HighThresh); + } + + /* Range check hb2LowThresh */ + if (device->rx->rxAgcCtrl->peakAgc->hb2LowThresh > device->rx->rxAgcCtrl->peakAgc->hb2HighThresh) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_HB2_LOW_THRESH_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_HB2_LOW_THRESH_PARM)); + return MYKONOS_ERR_INV_AGC_RX_HB2_LOW_THRESH_PARM; + } + else + { + /* write hb2LowThresh */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_LOWER_THRSH, device->rx->rxAgcCtrl->peakAgc->hb2LowThresh); + } + + /* Range check hb2VeryLowThresh */ + if (device->rx->rxAgcCtrl->peakAgc->hb2VeryLowThresh > device->rx->rxAgcCtrl->peakAgc->hb2LowThresh) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_THRESH_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_THRESH_PARM)); + return MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_THRESH_PARM; + } + else + { + /* write hb2VeryLowThresh */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OVRLD_PD_DEC_VERYLOW_THRSH, device->rx->rxAgcCtrl->peakAgc->hb2VeryLowThresh); + } + + /* Write threshold counter values for apdHigh/apdLow/hb2High/hb2Low/hb2VeryLow */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ULB_CNT_THRSH, device->rx->rxAgcCtrl->peakAgc->apdHighThreshExceededCnt); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_LLB_CNT_THRSH, device->rx->rxAgcCtrl->peakAgc->apdLowThreshExceededCnt); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_HIGH_OVRG_CNT_THRSH, device->rx->rxAgcCtrl->peakAgc->hb2HighThreshExceededCnt); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_LOW_OVRG_CNT_THRSH, device->rx->rxAgcCtrl->peakAgc->hb2LowThreshExceededCnt); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_VERYLOW_OVRG_CNT_THRSH, device->rx->rxAgcCtrl->peakAgc->hb2VeryLowThreshExceededCnt); + + /* Range check on apdHighGainStepAttack (5-bit) */ + if (device->rx->rxAgcCtrl->peakAgc->apdHighGainStepAttack > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_APD_HIGH_GAIN_STEP_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_APD_HIGH_GAIN_STEP_PARM)); + return MYKONOS_ERR_INV_AGC_RX_APD_HIGH_GAIN_STEP_PARM; + } + else + { + /* Write apdHighGainStepAttack */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_1, device->rx->rxAgcCtrl->peakAgc->apdHighGainStepAttack); + } + + /* Range check on apdLowGainStepRecovery (5-bit) */ + if (device->rx->rxAgcCtrl->peakAgc->apdLowGainStepRecovery > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_APD_LOW_GAIN_STEP_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_APD_LOW_GAIN_STEP_PARM)); + return MYKONOS_ERR_INV_AGC_RX_APD_LOW_GAIN_STEP_PARM; + } + else + { + /* Write apdLowGainStepRecovery */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_4, device->rx->rxAgcCtrl->peakAgc->apdLowGainStepRecovery); + } + + /* Range check on hb2HighGainStepAttack (5-bit) */ + if (device->rx->rxAgcCtrl->peakAgc->hb2HighGainStepAttack > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_GAIN_STEP_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_GAIN_STEP_PARM)); + return MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_GAIN_STEP_PARM; + } + else + { + /* Write hb2HighGainStepAttack */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_2, device->rx->rxAgcCtrl->peakAgc->hb2HighGainStepAttack); + } + + /* Range check on hb2LowGainStepRecovery (5-bit) */ + if (device->rx->rxAgcCtrl->peakAgc->hb2LowGainStepRecovery > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_HB2_LOW_GAIN_STEP_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_HB2_LOW_GAIN_STEP_PARM)); + return MYKONOS_ERR_INV_AGC_RX_HB2_LOW_GAIN_STEP_PARM; + } + else + { + /* Write hb2LowGainStepRecovery */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_5, device->rx->rxAgcCtrl->peakAgc->hb2LowGainStepRecovery); + } + + /* Range check on hb2VeryLowGainStepRecovery (5-bit) */ + if (device->rx->rxAgcCtrl->peakAgc->hb2VeryLowGainStepRecovery > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_GAIN_STEP_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_GAIN_STEP_PARM)); + return MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_GAIN_STEP_PARM; + } + else + { + /* Write hb2VeryLowGainStepRecovery */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_6, device->rx->rxAgcCtrl->peakAgc->hb2VeryLowGainStepRecovery); + } + + /* Range Check on hb2OverloadDetectEnable */ + if (device->rx->rxAgcCtrl->peakAgc->hb2OverloadDetectEnable > 0x1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_ENABLE, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_ENABLE)); + return MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_ENABLE; + } + + /* Range Check on hb2OverloadDetectEnable */ + if (device->rx->rxAgcCtrl->peakAgc->hb2OverloadDurationCnt > 0x7) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_DUR_CNT, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_DUR_CNT)); + return MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_DUR_CNT; + } + + /* Range Check on hb2OverloadDetectEnable */ + if (device->rx->rxAgcCtrl->peakAgc->hb2OverloadThreshCnt > 0xF) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_THRESH_CNT, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_THRESH_CNT)); + return MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_THRESH_CNT; + } + else + { + /* Write the hb2OvldCfgRegValue, the combination of hb2OverloadThreshCnt, hb2OverloadDurationCnt, and hb2OverloadDetectEnable */ + hb2OvldCfgRegValue = (device->rx->rxAgcCtrl->peakAgc->hb2OverloadThreshCnt) |(uint8_t)(device->rx->rxAgcCtrl->peakAgc->hb2OverloadDurationCnt << 4) + | (uint8_t)(device->rx->rxAgcCtrl->peakAgc->hb2OverloadDetectEnable << 7); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_CFG, hb2OvldCfgRegValue); + } + + /* Hard-coded value for the ADC overload configuration. Sets the HB2 offset to -6dB.*/ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OVRLD_ADC_OVRLD_CFG, 0x18); + /* Hard-coded value for APD decay setting. Setting allows for the quickest settling time of peak detector */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_RX_BLOCK_DET_DECAY, 0x0); + + /* performing a soft reset */ + return MYKONOS_resetRxAgc(device); +} + +/** + * \brief This function resets the AGC state machine + * + * Calling this function resets all state machines within the gain control and maximum gain. + * + * Dependencies: + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing the device SPI settings + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_resetRxAgc(mykonosDevice_t *device) +{ + const uint8_t AGC_RESET = 0x80; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_resetRxAgc()\n"); +#endif + + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_CFG_2, 1, AGC_RESET, 7); + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_CFG_2, 0, AGC_RESET, 7); + + return MYKONOS_ERR_OK; + +} + +/** + * \brief This function sets the min/max gain indexes for AGC in the main RX channel + * + * Allows to change min/max gain index on runtime. + * If RX1_RX2 selected, then the maxGainIndex/minGainIndex value will be applied to both channels. + * If only Rx1 selected, then only Rx1 min/max gain indices will be updated, along with their device data structure values. + * If only Rx2 selected, then only Rx2 min/max gain indices will be updated, along with their device data structure values. + * + * Dependencies: + * - device->spiSettings + * - device->rx->rxAgcCtrl + * + * \param device is structure pointer to the Mykonos data structure containing the device SPI settings + * \param rxChannelSelect RX channel for setting the max and min gain index settings + * \param maxGainIndex Max gain index setting + * \param minGainIndex Min gain index setting + * + * \retval MYKONOS_ERR_SET_RX_MAX_GAIN_INDEX Max gain index bigger than max gain index loaded table. + * \retval MYKONOS_ERR_SET_RX_MIN_GAIN_INDEX Min gain index lower than min gain index loaded table. + * \retval MYKONOS_ERR_AGC_MIN_MAX_CHANNEL Wrong RX channel selected + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setRxAgcMinMaxGainIndex(mykonosDevice_t *device, mykonosRxChannels_t rxChannelSelect, uint8_t maxGainIndex, uint8_t minGainIndex) +{ + const uint8_t MIN_GAIN_INDEX = 1 + MAX_GAIN_TABLE_INDEX - (sizeof(RxGainTable) / sizeof(RxGainTable[0])); + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setRxAgcMinMaxGainIndex()\n"); +#endif + + /* Check for maxGainIndex */ + if (maxGainIndex > MAX_GAIN_TABLE_INDEX) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_RX_MAX_GAIN_INDEX, + getMykonosErrorMessage(MYKONOS_ERR_SET_RX_MAX_GAIN_INDEX)); + return MYKONOS_ERR_SET_RX_MAX_GAIN_INDEX; + } + + /* Check for minGainIndex */ + if (minGainIndex < MIN_GAIN_INDEX) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_RX_MIN_GAIN_INDEX, + getMykonosErrorMessage(MYKONOS_ERR_SET_RX_MIN_GAIN_INDEX)); + return MYKONOS_ERR_SET_RX_MIN_GAIN_INDEX; + } + + if ((uint32_t)rxChannelSelect & (uint32_t)RX1) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_RX1_MAX_GAIN_INDEX, maxGainIndex); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_RX1_MIN_GAIN_INDEX, minGainIndex); + device->rx->rxAgcCtrl->agcRx1MaxGainIndex = maxGainIndex; + device->rx->rxAgcCtrl->agcRx1MinGainIndex = minGainIndex; + } + + if ((uint32_t)rxChannelSelect & (uint32_t)RX2) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_RX2_MAX_GAIN_INDEX, maxGainIndex); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_RX2_MIN_GAIN_INDEX, minGainIndex); + device->rx->rxAgcCtrl->agcRx2MaxGainIndex = maxGainIndex; + device->rx->rxAgcCtrl->agcRx2MinGainIndex = minGainIndex; + } + + /* Check for invalid Rx channel */ + if (!((uint32_t)rxChannelSelect & (uint32_t)RX1_RX2)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_AGC_MIN_MAX_RX_CHANNEL, + getMykonosErrorMessage(MYKONOS_ERR_AGC_MIN_MAX_RX_CHANNEL)); + return MYKONOS_ERR_AGC_MIN_MAX_RX_CHANNEL; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function sets the min/max gain indexes for AGC in the observation channel + * + * Allows to change min/max gain index on runtime. + * + * Dependencies: + * - device->spiSettings + * - device->rx->rxAgcCtrl + * + * \param device is structure pointer to the Mykonos data structure containing the device SPI settings + * \param obsRxChannelSelect Observation channel for setting the max and min gain index settings + * \param maxGainIndex Max gain index setting + * \param minGainIndex Min gain index setting + * + * \retval MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX_CHANNEL Wrong read back channel. + * \retval MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX Max gain index bigger than max gain index loaded table. + * \retval MYKONOS_ERR_SET_ORX_MIN_GAIN_INDEX Min gain index lower than min gain index loaded table. + * \retval MYKONOS_ERR_AGC_MIN_MAX_ORX_CHANNEL Wrong observation channel selected + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setObsRxAgcMinMaxGainIndex(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxChannelSelect, uint8_t maxGainIndex, uint8_t minGainIndex) +{ + uint8_t rdObsActive = 0x00; + uint8_t obsActive = 0x00; + uint8_t obsCheck = 0x00; + uint8_t minGainIndexCheck = 0x00; + uint8_t maxGainIndexCheck = 0x00; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setObsRxAgcMinMaxGainIndex()\n"); +#endif + + /* Read active channel */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_ACTIVE, &rdObsActive, 0x03, 0); + + /* Check active channel and set min/max checks */ + switch (rdObsActive) + { + case 0x00: + case 0x01: + /*sniffer*/ + maxGainIndexCheck = MAX_GAIN_TABLE_INDEX; + minGainIndexCheck = MAX_GAIN_TABLE_INDEX - (sizeof(SnRxGainTable) / sizeof(SnRxGainTable[0])); + obsActive = (uint32_t)OBS_SNIFFER | (uint32_t)OBS_SNIFFER_A | (uint32_t)OBS_SNIFFER_B | (uint32_t)OBS_SNIFFER_C; + break; + case 0x02: + case 0x03: + /*observation 1*/ + maxGainIndexCheck = MAX_GAIN_TABLE_INDEX; + minGainIndexCheck = MAX_GAIN_TABLE_INDEX - (sizeof(ORxGainTable) / sizeof(ORxGainTable[0])); + obsActive = (uint32_t)OBS_RX1_TXLO | (uint32_t)OBS_RX1_SNIFFERLO | (uint32_t)OBS_RX2_TXLO | (uint32_t)OBS_RX2_SNIFFERLO; + break; + + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX_CHANNEL, + getMykonosErrorMessage(MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX_CHANNEL)); + return MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX_CHANNEL; + } + + /* Check for maxGainIndex */ + if ((maxGainIndex > maxGainIndexCheck) || (maxGainIndex < minGainIndexCheck)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX, + getMykonosErrorMessage(MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX)); + return MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX; + } + + /* Check for minGainIndex */ + if ((minGainIndex < minGainIndexCheck) || (minGainIndex > maxGainIndexCheck)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_ORX_MIN_GAIN_INDEX, + getMykonosErrorMessage(MYKONOS_ERR_SET_ORX_MIN_GAIN_INDEX)); + return MYKONOS_ERR_SET_ORX_MIN_GAIN_INDEX; + } + + device->obsRx->orxAgcCtrl->agcObsRxMaxGainIndex = maxGainIndex; + device->obsRx->orxAgcCtrl->agcObsRxMinGainIndex = minGainIndex; + + switch (obsRxChannelSelect) + { + case OBS_SNIFFER: + case OBS_SNIFFER_A: + case OBS_SNIFFER_B: + case OBS_SNIFFER_C: + obsCheck = (uint32_t)OBS_SNIFFER | (uint32_t)OBS_SNIFFER_A | (uint32_t)OBS_SNIFFER_B | (uint32_t)OBS_SNIFFER_C; + maxGainIndex = maxGainIndex - MAX_SNRX_GAIN_TABLE_NUMINDEXES; + minGainIndex = minGainIndex - MAX_SNRX_GAIN_TABLE_NUMINDEXES; + break; + + case OBS_RX1_TXLO: + case OBS_RX2_TXLO: + case OBS_RX1_SNIFFERLO: + case OBS_RX2_SNIFFERLO: + obsCheck = (uint32_t)OBS_RX1_TXLO | (uint32_t)OBS_RX1_SNIFFERLO | (uint32_t)OBS_RX2_TXLO | (uint32_t)OBS_RX2_SNIFFERLO; + maxGainIndex = maxGainIndex - MAX_ORX_GAIN_TABLE_NUMINDEXES; + minGainIndex = minGainIndex - MAX_ORX_GAIN_TABLE_NUMINDEXES; + break; + + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_AGC_MIN_MAX_ORX_CHANNEL, + getMykonosErrorMessage(MYKONOS_ERR_AGC_MIN_MAX_ORX_CHANNEL)); + return MYKONOS_ERR_AGC_MIN_MAX_ORX_CHANNEL; + } + + if (obsCheck == obsActive) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_MAX_GAIN_INDEX, maxGainIndex); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_MIN_GAIN_INDEX, minGainIndex); + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_AGC_MIN_MAX_ORX_CHANNEL, + getMykonosErrorMessage(MYKONOS_ERR_AGC_MIN_MAX_ORX_CHANNEL)); + return MYKONOS_ERR_AGC_MIN_MAX_ORX_CHANNEL; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function sets the Temperature gain compensation for Rx1 channel + * + * The temperature gain compensation control allow for a +3000mdB to -3000mdB digital gain + * in the data path. + * The resolution of the temperature compensation gain is 250mdB. + * + * Dependencies: + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing the device SPI settings + * \param rx1TempCompGain_mdB gain compensation for Rx1, the range is from -3000mdB to +3000mdB in steps of 250mdB + * + * \retval MYKONOS_ERR_RX1_TEMP_GAIN_COMP_RANGE The temp gain compensation is outside range (-3000mdB to 3000mdB) + * \retval MYKONOS_ERR_RX1_TEMP_GAIN_COMP_STEP Not valid temp gain compensation, step size is 250mdB + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setRx1TempGainComp(mykonosDevice_t *device, int16_t rx1TempCompGain_mdB) +{ + int8_t tempGainComp = 0x00; + + const int16_t LOW_LIMIT_GAIN_COMP = -3000; + const int16_t HIGH_LIMIT_GAIN_COMP = 3000; + const int16_t GAIN_COMP_STEP = 250; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setRx1TempGainComp()\n"); +#endif + + /* Check for Gain compensation range */ + if ((rx1TempCompGain_mdB > HIGH_LIMIT_GAIN_COMP) || (rx1TempCompGain_mdB < LOW_LIMIT_GAIN_COMP)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RX1_TEMP_GAIN_COMP_RANGE, + getMykonosErrorMessage(MYKONOS_ERR_RX1_TEMP_GAIN_COMP_RANGE)); + return MYKONOS_ERR_RX1_TEMP_GAIN_COMP_RANGE; + } + + /* Check for Gain compensation steps */ + if (rx1TempCompGain_mdB % GAIN_COMP_STEP) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RX1_TEMP_GAIN_COMP_STEP, + getMykonosErrorMessage(MYKONOS_ERR_RX1_TEMP_GAIN_COMP_STEP)); + return MYKONOS_ERR_RX1_TEMP_GAIN_COMP_STEP; + } + + /* Prepare register write */ + tempGainComp = (rx1TempCompGain_mdB / GAIN_COMP_STEP) & 0x1F; + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX1_TEMP_GAIN_COMP, (uint8_t)tempGainComp); + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function gets the Temperature gain compensation for Rx1 + * + * Dependencies: + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing the device SPI settings + * \param rx1TempCompGain_mdB Which will be populated with the Temperature Gain Compensation in mdB value for Rx1 channel. + * + * \retval MYKONOS_ERR_RX1_TEMP_GAIN_COMP_NULL rx1TempCompGain_mdB pointer is null. + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getRx1TempGainComp(mykonosDevice_t *device, int16_t *rx1TempCompGain_mdB) +{ + uint8_t tempGainComp = 0x00; + int8_t tempGainCompDB = 0x00; + + const int16_t GAIN_COMP_STEP = 250; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getRx1TempGainComp()\n"); +#endif + + /* Check for null passed parameter */ + if (rx1TempCompGain_mdB == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RX1_TEMP_GAIN_COMP_NULL, + getMykonosErrorMessage(MYKONOS_ERR_RX1_TEMP_GAIN_COMP_NULL)); + return MYKONOS_ERR_RX1_TEMP_GAIN_COMP_NULL; + } + + /* Read Temperature Gain Compensation */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_RX1_TEMP_GAIN_COMP, &tempGainComp); + + /* Convert to dB and prepare the signed return */ + tempGainCompDB = tempGainComp & 0x1F; + if (tempGainCompDB & 0x10) + { + tempGainCompDB = ((((~((uint8_t)tempGainCompDB)) & 0x0F) + 1) * (-1)); + } + + /* Assign value to the passed pointer */ + *rx1TempCompGain_mdB = tempGainCompDB * GAIN_COMP_STEP; + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function sets the Temperature gain compensation for Rx2 channel + * + * The temperature gain compensation control allow for a +3000mdB to -3000mdB digital gain + * in the data path. + * The resolution of the temperature compensation gain is 250mdB. + * + * Dependencies: + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing the device SPI settings + * \param rx2TempCompGain_mdB gain compensation for Rx1, + * the range is from -3000mdB to +3000mdB in steps of 250mdB + * + * \retval MYKONOS_ERR_RX2_TEMP_GAIN_COMP_RANGE The temp gain compensation is outside range (-3000mdB to 3000mdB) + * \retval MYKONOS_ERR_RX2_TEMP_GAIN_COMP_STEP Not valid temp gain compensation, step size is 250mdB + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setRx2TempGainComp(mykonosDevice_t *device, int16_t rx2TempCompGain_mdB) +{ + int8_t tempGainComp = 0x00; + + const int16_t LOW_LIMIT_GAIN_COMP = -3000; + const int16_t HIGH_LIMIT_GAIN_COMP = 3000; + const int16_t GAIN_COMP_STEP = 250; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setRx2TempGainComp()\n"); +#endif + + /* Check for Gain compensation range */ + if ((rx2TempCompGain_mdB > HIGH_LIMIT_GAIN_COMP) || (rx2TempCompGain_mdB < LOW_LIMIT_GAIN_COMP)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RX2_TEMP_GAIN_COMP_RANGE, + getMykonosErrorMessage(MYKONOS_ERR_RX2_TEMP_GAIN_COMP_RANGE)); + return MYKONOS_ERR_RX2_TEMP_GAIN_COMP_RANGE; + } + + /* Check for Gain compensation range */ + if (rx2TempCompGain_mdB % GAIN_COMP_STEP) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RX2_TEMP_GAIN_COMP_STEP, + getMykonosErrorMessage(MYKONOS_ERR_RX2_TEMP_GAIN_COMP_STEP)); + return MYKONOS_ERR_RX2_TEMP_GAIN_COMP_STEP; + } + + /* Prepare register write */ + tempGainComp = (rx2TempCompGain_mdB / GAIN_COMP_STEP) & 0x1F; + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX2_TEMP_GAIN_COMP, (uint8_t)tempGainComp); + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function gets the Temperature gain compensation for Rx2 + * + * Dependencies: + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing the device SPI settings + * \param rx2TempCompGain_mdB Which will be populated with the Temperature Gain Compensation in mdB value for Rx2 channel. + * + * \retval MYKONOS_ERR_RX2_TEMP_GAIN_COMP_NULL rx2TempCompGain_mdB pointer is null. + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getRx2TempGainComp(mykonosDevice_t *device, int16_t *rx2TempCompGain_mdB) +{ + uint8_t tempGainComp = 0x00; + int8_t tempGainCompDB = 0x00; + + const int16_t GAIN_COMP_STEP = 250; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getRx2TempGainComp()\n"); +#endif + + /* Check for null passed parameter */ + if (rx2TempCompGain_mdB == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RX2_TEMP_GAIN_COMP_NULL, + getMykonosErrorMessage(MYKONOS_ERR_RX2_TEMP_GAIN_COMP_NULL)); + return MYKONOS_ERR_RX2_TEMP_GAIN_COMP_NULL; + } + + /* Read programmed Temperature Gain Compensation */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_RX2_TEMP_GAIN_COMP, &tempGainComp); + + /* Convert to dB and prepare the signed return */ + tempGainCompDB = tempGainComp & 0x1F; + if (tempGainCompDB & 0x10) + { + tempGainCompDB = (((~((uint8_t)tempGainCompDB)) & 0x0F) + 1) * (-1); + } + + /* Assign value to the passed pointer */ + *rx2TempCompGain_mdB = tempGainCompDB * GAIN_COMP_STEP; + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function sets the Temperature gain compensation for the observation channel + * + * The temperature gain compensation control allow for a +3000mdB to -3000mdB digital gain + * in the data path. + * The resolution of the temperature compensation gain is 250mdB. + * + * Dependencies: + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing the device SPI settings + * \param obsRxTempCompGain_mdB gain compensation for observation channel, + * the range is from -3000mdB to +3000mdB in steps of 250mdB + * + * \retval MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_RANGE The temp gain compensation is outside range (-3000mdB to 3000mdB) + * \retval MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_STEP Not valid temp gain compensation, step size is 250mdB + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setObsRxTempGainComp(mykonosDevice_t *device, int16_t obsRxTempCompGain_mdB) +{ + int8_t tempGainComp = 0x00; + + const int16_t LOW_LIMIT_GAIN_COMP = -3000; + const int16_t HIGH_LIMIT_GAIN_COMP = 3000; + const int16_t GAIN_COMP_STEP = 250; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setObsRxTempGainComp()\n"); +#endif + + /* Check for Gain compensation range */ + if ((obsRxTempCompGain_mdB > HIGH_LIMIT_GAIN_COMP) || (obsRxTempCompGain_mdB < LOW_LIMIT_GAIN_COMP)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_RANGE, + getMykonosErrorMessage(MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_RANGE)); + return MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_RANGE; + } + + /* Check for Gain compensation range */ + if (obsRxTempCompGain_mdB % GAIN_COMP_STEP) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_STEP, + getMykonosErrorMessage(MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_STEP)); + return MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_STEP; + } + + /* Prepare register write */ + tempGainComp = (obsRxTempCompGain_mdB / GAIN_COMP_STEP) & 0x1F; + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_TEMP_GAIN_COMP, (uint8_t)tempGainComp); + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function gets the Temperature gain compensation for the observation channel + * + * + * Dependencies: + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing the device SPI settings + * \param obsRxTempCompGain_mdB Which will be populated with the Temperature Gain Compensation in mdB value for the observation channel. + * + * \retval MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_NULL obsRxTempCompGain_mdB pointer is null. + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getObsRxTempGainComp(mykonosDevice_t *device, int16_t *obsRxTempCompGain_mdB) +{ + uint8_t tempGainComp = 0x00; + int8_t tempGainCompDB = 0x00; + + const int16_t GAIN_COMP_STEP = 250; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getObsRxTempGainComp()\n"); +#endif + + /* Check for null passed parameter */ + if (obsRxTempCompGain_mdB == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_NULL, + getMykonosErrorMessage(MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_NULL)); + return MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_NULL; + } + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_OBS_TEMP_GAIN_COMP, &tempGainComp); + + /* Convert to dB and prepare the signed return */ + tempGainCompDB = tempGainComp & 0x1F; + if (tempGainCompDB & 0x10) + { + tempGainCompDB = (((~((uint8_t)tempGainCompDB)) & 0x0F) + 1) * (-1); + } + + /* Assign value to the passed pointer */ + *obsRxTempCompGain_mdB = tempGainCompDB * GAIN_COMP_STEP; + + return MYKONOS_ERR_OK; +} + +/** + * \brief Enables or disables the Rx slow loop gain counter to use the sync pulse + * + * Dependencies: + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing the device SPI settings + * \param enable is a uint8_t data type where '0' = disable Rx gain counter from using sync pulse, '1' = enable Rx gain. All other values will throw an error. + * counter to use the sync pulse. This value is written back to the device data structure for storage. + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_enableRxGainCtrSyncPulse(mykonosDevice_t *device, uint8_t enable) +{ + const uint8_t syncPulseBitMask = 0x80; + uint8_t enableBit = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setRxGainCtrSyncPulse()\n"); +#endif + + /* read, modify, write Rx gain counter sync pulse enable bit */ + enableBit = (enable > 0) ? 1 : 0; + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_LOOP_CFG, enableBit, syncPulseBitMask, 7); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Configures the Rx gain control mode + * + * Dependencies: + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * - device->rx->rxGainCtrl->gainMode + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param mode is a mykonosGainMode_t enumerated gain control mode type where: + * Manual Gain = MGC, Automatic Gain Control = AGC, and hybrid mode = HYBRID + * + * When the mode enumerated type is passed, the Rx1 and Rx2 gain mode is set to this value and the + * Rx gainMode structure member is updated with the new value + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_INV_RX_GAIN_MODE_PARM Invalid AGC mode pass in function mode paramter + */ +mykonosErr_t MYKONOS_setRxGainControlMode(mykonosDevice_t *device, mykonosGainMode_t mode) +{ + uint8_t rxGainCfgReg = 0; + + const uint8_t RX_GAIN_TYPE_MASK = 0x1F; + const uint8_t RX_GAIN_HYBRID_MASK = 0x10; + const uint8_t RX_GAIN_TYPE_SHIFT = 0x02; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setRxGainControlMode()\n"); +#endif + + /* read AGC type for Rx1 and Rx2 for modify, write */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_AGC_CFG_1, &rxGainCfgReg); + rxGainCfgReg &= ~RX_GAIN_TYPE_MASK; + + /* performing AGC type check */ + switch (mode) + { + case MGC: + rxGainCfgReg &= ~RX_GAIN_HYBRID_MASK; + break; + case AGC: + rxGainCfgReg &= ~RX_GAIN_HYBRID_MASK; + break; + case HYBRID: + rxGainCfgReg |= RX_GAIN_HYBRID_MASK; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_RX_GAIN_MODE_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_RX_GAIN_MODE_PARM)); + return MYKONOS_ERR_INV_RX_GAIN_MODE_PARM; + } + + /* modify, write AGC type for Rx1 and Rx2 */ + rxGainCfgReg |= (uint8_t)mode; + rxGainCfgReg |= (uint8_t)((uint8_t)mode << RX_GAIN_TYPE_SHIFT); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_CFG_1, rxGainCfgReg); + + /* writing mode setting to data structure */ + if ((device->profilesValid & RX_PROFILE_VALID) > 0) + { + device->rx->rxGainCtrl->gainMode = mode; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Performs a power measurement in the Rx1 digital data path. + * + * Due to interdependencies between the AGC and power measurement the power measurement duration and + * where the measurement is taken is variable. + * The location of the power measurement is given by device->rx->rxAgcCtrl->rxPwrAgc->pmdMeasConfig + * The number of samples the power measurement uses is given by 8*2^(device->rx->rxAgcCtrl->rxPwrAgc->pmdMeasDuration) at the IQ rate, + * if measured at RFIR output. This number of samples must be less than the agcGainUpdateCounter. + * If the receiver is disabled during the power measurement, this function returns a 0 value for rx1DecPower_mdBFS + * + * The resolution of this function is 0.25dB. + * The dynamic range of this function is 40dB. Signals lower than 40dBFS may not be measured accurately. + * + * Dependencies + * - device->spiSettings + * - device->rx->rxAgcCtrl->rxPwrAgc->pmdMeasConfig + * - device->rx->rxAgcCtrl->rxPwrAgc->pmdMeasDuration + * + * \param device Pointer to the Mykonos data structure + * \param rx1DecPower_mdBFS Pointer to store the Rx1 decimated power return. Value returned in mdBFS + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getRx1DecPower(mykonosDevice_t *device, uint16_t *rx1DecPower_mdBFS) +{ + uint8_t rx1DecPower_dBFS = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getRx1DecPower()\n"); +#endif + + /* read Rx1 Dec Power Measurement */ + if (rx1DecPower_mdBFS != NULL) + { + CMB_SPIReadByte(device->spiSettings, MYKONOS_CH1_DECIMATED_PWR, &rx1DecPower_dBFS); + *rx1DecPower_mdBFS = (uint16_t)(rx1DecPower_dBFS * 250); /* 250 = 1000 * 0.25dB */ + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_RX1_DEC_POWER_NULL_PARM, + getMykonosErrorMessage(MYKONOS_ERR_GET_RX1_DEC_POWER_NULL_PARM)); + return MYKONOS_ERR_GET_RX1_DEC_POWER_NULL_PARM; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Performs a power measurement in the Rx2 digital data path. + * + * Due to interdependencies between the AGC and power measurement the power measurement duration and + * where the measurement is taken is variable. + * The location of the power measurement is given by device->rx->rxAgcCtrl->rxPwrAgc->pmdMeasConfig + * The number of samples the power measurement uses is given by 8*2^(device->rx->rxAgcCtrl->rxPwrAgc->pmdMeasDuration) at the IQ rate, + * if measured at RFIR output. This number of samples must be less than the agcGainUpdateCounter. + * If the receiver is disabled during the power measurement, this function returns a 0 value for rx2DecPower_mdBFS + * + * The resolution of this function is 0.25dB. + * The dynamic range of this function is 40dB. Signals lower than 40dBFS may not be measured accurately. + * + * Dependencies + * - device->spiSettings + * + * \param device Pointer to the Mykonos data structure + * \param rx2DecPower_mdBFS Pointer to store the Rx1 decimated power return. Value returned in mdBFS + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getRx2DecPower(mykonosDevice_t *device, uint16_t *rx2DecPower_mdBFS) +{ + uint8_t rx2DecPower_dBFS = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getRx2DecPower()\n"); +#endif + + /* read Rx2 Dec Power Measurement */ + if (rx2DecPower_mdBFS != NULL) + { + CMB_SPIReadByte(device->spiSettings, MYKONOS_CH2_DECIMATED_PWR, &rx2DecPower_dBFS); + *rx2DecPower_mdBFS = (uint16_t)(rx2DecPower_dBFS * 250); /* 250 = 1000 * 0.25dB */ + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_RX2_DEC_POWER_NULL_PARM, + getMykonosErrorMessage(MYKONOS_ERR_GET_RX2_DEC_POWER_NULL_PARM)); + return MYKONOS_ERR_GET_RX2_DEC_POWER_NULL_PARM; + } + + return MYKONOS_ERR_OK; +} + +/* + ***************************************************************************** + * Observation Rx Data path functions + ***************************************************************************** + */ + +/** + * \brief Sets the default Obs Rx channel to enter when device moves from + * radioOff to radioOn + * + * By default, the observation receiver remains powered down when the device + * moves into the radioOn state. If the BBIC prefers a particular ObsRx + * channel to be enabled, this function can be called in radioOff to set + * the default channel to power up when the device moves to radioOn. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->obsRx->defaultObsRxChannel + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param defaultObsRxCh is mykonosObsRxChannels_t enum type which selects the desired observation receive path to power up + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_SETDEFOBSRXPATH_NULL_OBSRX_STRUCT Observation profile not valid, device->obsRx structure is NULL + * \retval MYKONOS_ERR_SETDEFOBSRXPATH_NULL_DEF_OBSRX_STRUCT Invalid defaultObsRxCh function parameter + */ +mykonosErr_t MYKONOS_setDefaultObsRxPath(mykonosDevice_t *device, mykonosObsRxChannels_t defaultObsRxCh) +{ + uint8_t orxEntryMode[1] = {0}; + uint16_t byteOffset = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setDefaultObsRxPath()\n"); +#endif + + if (device->obsRx == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETDEFOBSRXPATH_NULL_DEF_OBSRX_STRUCT, + getMykonosErrorMessage(MYKONOS_ERR_SETDEFOBSRXPATH_NULL_DEF_OBSRX_STRUCT)); + return MYKONOS_ERR_SETDEFOBSRXPATH_NULL_DEF_OBSRX_STRUCT; + } + + if (((defaultObsRxCh > OBS_RX2_SNIFFERLO) && (defaultObsRxCh != OBS_SNIFFER_A) && (defaultObsRxCh != OBS_SNIFFER_B) && (defaultObsRxCh != OBS_SNIFFER_C))) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_PU_OBSRXPATH_INV_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_PU_OBSRXPATH_INV_PARAM)); + return MYKONOS_ERR_PU_OBSRXPATH_INV_PARAM; + } + + device->obsRx->defaultObsRxChannel = defaultObsRxCh; + orxEntryMode[0] = ((uint8_t)device->obsRx->defaultObsRxChannel & 0xFF); + + byteOffset = 6; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_RADIO_CONTROL, byteOffset, &orxEntryMode[0], 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Powers up or down the Observation Rx signal chain in the radioOn state + * + * When the ARM radio control is in ARM command mode, this + * function allows the user to selectively power up or down the desired ObsRx + * data path. If this function is called when the ARM is expecting GPIO pin + * control of the ObsRx path source, an error will be returned. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param obsRxCh is mykonosObsRxChannels_t enum type which selects the desired observation receive path to power up + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_PU_OBSRXPATH_INV_PARAM Invalid obsRxCh function parameter + * \retval MYKONOS_ERR_PU_OBSRXPATH_ARMERROR ARM returned an error while trying to set the ObsRx Path source + */ +mykonosErr_t MYKONOS_setObsRxPathSource(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxCh) +{ + uint8_t cmdStatByte = 0; + uint32_t timeoutMs = 0; + uint8_t payload[2] = {0, 0}; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setObsRxPathSource()\n"); +#endif + + if (((obsRxCh > OBS_RX2_SNIFFERLO) && (obsRxCh != OBS_SNIFFER_A) && (obsRxCh != OBS_SNIFFER_B) && (obsRxCh != OBS_SNIFFER_C))) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_PU_OBSRXPATH_INV_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_PU_OBSRXPATH_INV_PARAM)); + return MYKONOS_ERR_PU_OBSRXPATH_INV_PARAM; + } + + payload[0] = MYKONOS_ARM_OBJECTID_ORX_MODE; + payload[1] = (uint8_t)(obsRxCh); + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_SET_OPCODE, &payload[0], sizeof(payload)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; /* wait max of 1sec for command to complete */ + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_SET_OPCODE, timeoutMs, &cmdStatByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_PU_OBSRXPATH_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_PU_OBSRXPATH_ARMERROR)); + return MYKONOS_ERR_PU_OBSRXPATH_ARMERROR; + } + + return retVal; + } + + /* Verify ARM command did not return an error */ + if (cmdStatByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_PU_OBSRXPATH_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_PU_OBSRXPATH_ARMERROR)); + return MYKONOS_ERR_PU_OBSRXPATH_ARMERROR; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads back the currently enabled Observation Rx channel in the + * radioOn state + * + * In pin mode, the pin could change asynchronous to reading back the + * current enable ObsRx path. Calling this function while in radioOff will + * return OBS_RXOFF since all radio channels are powered down. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param obsRxCh Parameter to return enum of the current observation receive + * path powered up + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_PU_GETOBSRXPATH_ARMERROR ARM returned an error while trying to get the ObsRx Path source + */ +mykonosErr_t MYKONOS_getObsRxPathSource(mykonosDevice_t *device, mykonosObsRxChannels_t *obsRxCh) +{ + uint8_t extData[1] = {MYKONOS_ARM_OBJECTID_ORX_MODE}; + uint8_t cmdStatusByte = 0; + uint8_t armData[1] = {0}; + uint32_t timeoutMs = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getObsRxPathSource()\n"); +#endif + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_PU_GETOBSRXPATH_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_PU_GETOBSRXPATH_ARMERROR)); + return MYKONOS_ERR_PU_GETOBSRXPATH_ARMERROR; + } + + return retVal; + } + + /* read 64-bit frequency from ARM memory */ + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &armData[0], 1, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_PU_GETOBSRXPATH_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_PU_GETOBSRXPATH_ARMERROR)); + return MYKONOS_ERR_PU_GETOBSRXPATH_ARMERROR; + } + + *obsRxCh = (mykonosObsRxChannels_t)(armData[0]); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets the Rx gain of the ObsRx channel + * + * The ObsRx channel can have different RF inputs (ORx1/ORx2/SnRx A,B,C) + * This function sets the ObsRx gain index independently for ORx1/ORx2, or SnRx. + * SnRx A, B, and C share the same gain index. Please note that ORx1/ORx2 share a gain + * table, as does SnRx A, B, and C. The maximum index is 255 + * and the minimum index is application specific. + * + * Dependencies + * - device->spiSettings + * - device->obsRx->orxGainCtrl->maxGainIndex + * - device->obsRx->orxGainCtrl->minGainIndex + * - device->obsRx->orxGainCtrl->orx1GainIndex + * - device->obsRx->orxGainCtrl->orx2GainIndex + * - device->obsRx->snifferGainCtrl->maxGainIndex + * - device->obsRx->snifferGainCtrl->minGainIndex + * - device->obsRx->snifferGainCtrl->gainIndex + * + * \param device Pointer to the Mykonos device data structure + * \param obsRxCh is an enum type mykonosObsRxChannels_t to identify the desired RF input for gain change + * \param gainIndex Desired manual gain table index to set + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_SETORXGAIN_INV_ORX1GAIN Invalid gain requested for ORx1: outside gain table min/max index + * \retval MYKONOS_ERR_SETORXGAIN_INV_ORX2GAIN Invalid gain requested for ORx2: outside gain table min/max index + * \retval MYKONOS_ERR_SETORXGAIN_INV_SNRXGAIN Invalid gain requested for Sniffer: outside gain table min/max index + * \retval MYKONOS_ERR_SETORXGAIN_INV_CHANNEL Function parameter obsRxCh has an invalid enum value + */ +mykonosErr_t MYKONOS_setObsRxManualGain(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxCh, uint8_t gainIndex) +{ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setObsRxManualGain()\n"); +#endif + + if ((obsRxCh == OBS_RX1_TXLO) || (obsRxCh == OBS_RX1_SNIFFERLO)) + { + if (gainIndex <= device->obsRx->orxGainCtrl->maxGainIndex && gainIndex >= device->obsRx->orxGainCtrl->minGainIndex) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX1_MANUAL_GAIN_INDEX, (gainIndex - MIN_ORX_GAIN_TABLE_INDEX)); + device->obsRx->orxGainCtrl->orx1GainIndex = gainIndex; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETORXGAIN_INV_ORX1GAIN, + getMykonosErrorMessage(MYKONOS_ERR_SETORXGAIN_INV_ORX1GAIN)); + return MYKONOS_ERR_SETORXGAIN_INV_ORX1GAIN; + } + } + else if ((obsRxCh == OBS_RX2_TXLO) || (obsRxCh == OBS_RX2_SNIFFERLO)) + { + if (gainIndex <= device->obsRx->orxGainCtrl->maxGainIndex && gainIndex >= device->obsRx->orxGainCtrl->minGainIndex) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX2_MANUAL_GAIN_INDEX, (gainIndex - MIN_ORX_GAIN_TABLE_INDEX)); + device->obsRx->orxGainCtrl->orx2GainIndex = gainIndex; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETORXGAIN_INV_ORX2GAIN, + getMykonosErrorMessage(MYKONOS_ERR_SETORXGAIN_INV_ORX2GAIN)); + return MYKONOS_ERR_SETORXGAIN_INV_ORX2GAIN; + } + + } + else if (obsRxCh == OBS_SNIFFER_A || obsRxCh == OBS_SNIFFER_B || obsRxCh == OBS_SNIFFER_C || obsRxCh == OBS_SNIFFER) + { + if (gainIndex <= device->obsRx->snifferGainCtrl->maxGainIndex && gainIndex >= device->obsRx->snifferGainCtrl->minGainIndex) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SNRX_MANUAL_GAIN_INDEX, (gainIndex - MIN_SNRX_GAIN_TABLE_INDEX)); + device->obsRx->snifferGainCtrl->gainIndex = gainIndex; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETORXGAIN_INV_SNRXGAIN, + getMykonosErrorMessage(MYKONOS_ERR_SETORXGAIN_INV_SNRXGAIN)); + return MYKONOS_ERR_SETORXGAIN_INV_SNRXGAIN; + } + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETORXGAIN_INV_CHANNEL, + getMykonosErrorMessage(MYKONOS_ERR_SETORXGAIN_INV_CHANNEL)); + return MYKONOS_ERR_SETORXGAIN_INV_CHANNEL; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Gets the gain index of the currently enabled ObsRx channel + * + * The ObsRx data path can have multiple RF sources. This function will + * read back the gain index of the currently enabled RF source. If the ObsRx + * data path is disabled, an error is returned. If the functions uint8_t *gainIndex + * parameter is a valid pointer, the gain index is returned at the pointers + * address. Else, if the uint8_t *gainIndex pointer is NULL, the gainIndex read back + * is stored in the device data structure. + * + * NOTE: if the observation source is chosen by ORX_MODE pins, it is possible that + * the readback value will be incorrect if the obsRx channel changes while this function + * reads the gain. + * + * Dependencies + * - device->spiSettings + * - device->profilesValid + * - device->obsRx->orxGainCtrl->orx1GainIndex + * - device->obsRx->orxGainCtrl->orx2GainIndex + * - device->obsRx->snifferGainCtrl->gainIndex + * + * \param device Pointer to the Mykonos device data structure + * \param gainIndex Return value of the current gain index for the currently enabled ObsRx channel. + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETORX1GAIN_INV_POINTER The ObsRx profile is not valid in the device data structure + * \retval MYKONOS_ERR_GETORX2GAIN_INV_POINTER The ObsRx profile is not valid in the device data structure + * \retval MYKONOS_ERR_GETSNIFFGAIN_INV_POINTER The sniffer profile is not valid in the device data structure + * \retval MYKONOS_ERR_GETOBSRXGAIN_CH_DISABLED The observation receiver is currently disabled, can not read back gain index. + */ +mykonosErr_t MYKONOS_getObsRxGain(mykonosDevice_t *device, uint8_t *gainIndex) +{ + /* Potential issue, if ARM is using loopback path when this function is called, it will likely readback loopback gain */ + uint8_t readObsRxPathEnabled = 0; + uint8_t readObsRxGain = 0; + + const uint8_t ORX1_EN = 0x01; + const uint8_t ORX2_EN = 0x02; + const uint8_t SNRX_EN = 0x04; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getObsRxGain()\n"); +#endif + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_1, &readObsRxPathEnabled); + + /* If obsRx channel enabled, then read gain index */ + if (readObsRxPathEnabled > 0) + { + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_GAIN, &readObsRxGain); + + switch (readObsRxPathEnabled) + { + case 0x01: + readObsRxGain += MIN_ORX_GAIN_TABLE_INDEX; + break; + case 0x02: + readObsRxGain += MIN_ORX_GAIN_TABLE_INDEX; + break; + case 0x04: + readObsRxGain += MIN_SNRX_GAIN_TABLE_INDEX; + break; + default: + break; + } + + if (gainIndex != NULL) + { + *gainIndex = readObsRxGain; + } + + /* Store the gain index in the device's gain control data structure. */ + + if (readObsRxPathEnabled == ORX1_EN) + { + /* verify valid data structure pointers */ + if (device->profilesValid & ORX_PROFILE_VALID) + { + device->obsRx->orxGainCtrl->orx1GainIndex = readObsRxGain; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETORX1GAIN_INV_POINTER, + getMykonosErrorMessage(MYKONOS_ERR_GETORX1GAIN_INV_POINTER)); + return MYKONOS_ERR_GETORX1GAIN_INV_POINTER; + } + + } + else if (readObsRxPathEnabled == ORX2_EN) + { + /* verify valid pointers */ + if (device->profilesValid & ORX_PROFILE_VALID) + { + device->obsRx->orxGainCtrl->orx2GainIndex = readObsRxGain; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETORX2GAIN_INV_POINTER, + getMykonosErrorMessage(MYKONOS_ERR_GETORX2GAIN_INV_POINTER)); + return MYKONOS_ERR_GETORX2GAIN_INV_POINTER; + } + + } + else if (readObsRxPathEnabled == SNRX_EN) + { + /* verify valid pointers */ + if (device->profilesValid & SNIFF_PROFILE_VALID) + { + device->obsRx->snifferGainCtrl->gainIndex = readObsRxGain; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETSNIFFGAIN_INV_POINTER, + getMykonosErrorMessage(MYKONOS_ERR_GETSNIFFGAIN_INV_POINTER)); + return MYKONOS_ERR_GETSNIFFGAIN_INV_POINTER; + } + } + else + { + /* ignore gain index for Tx loopback input into obsRx channel */ + } + } + else + { + CMB_writeToLog(ADIHAL_LOG_WARNING, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETOBSRXGAIN_CH_DISABLED, + getMykonosErrorMessage(MYKONOS_ERR_GETOBSRXGAIN_CH_DISABLED)); + return MYKONOS_ERR_GETOBSRXGAIN_CH_DISABLED; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets up the device ObsRx Automatic Gain Control (AGC) registers. + * + * Three data structures (of types mykonosAgcCfg_t, mykonosPeakDetAgcCfg_t, mykonosPowerMeasAgcCfg_t) + * must be instantiated prior to calling this function. Valid ranges for data structure members + * must also be provided. + * + * + * Dependencies: + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * - device->obsRx->orxAgcCtrl->agcRx1MaxGainIndex + * - device->obsRx->orxAgcCtrl->agcRx1MinGainIndex + * - device->obsRx->orxAgcCtrl->agcRx2MaxGainIndex + * - device->obsRx->orxAgcCtrl->agcRx2MinGainIndex + * - device->obsRx->orxAgcCtrl->agcObsRxMaxGainIndex + * - device->obsRx->orxAgcCtrl->agcObsRxMinGainIndex + * - device->obsRx->orxAgcCtrl->agcObsRxSelect + * - device->obsRx->orxAgcCtrl->agcPeakThresholdMode + * - device->obsRx->orxAgcCtrl->agcLowThsPreventGainIncrease + * - device->obsRx->orxAgcCtrl->agcGainUpdateCounter + * - device->obsRx->orxAgcCtrl->agcSlowLoopSettlingDelay + * - device->obsRx->orxAgcCtrl->agcPeakWaitTime + * - device->obsRx->orxAgcCtrl->agcResetOnRxEnable + * - device->obsRx->orxAgcCtrl->agcEnableSyncPulseForGainCounter + * - device->obsRx->orxAgcCtrl->peakAgc->apdHighThresh + * - device->obsRx->orxAgcCtrl->peakAgc->apdLowThresh + * - device->obsRx->orxAgcCtrl->peakAgc->hb2HighThresh + * - device->obsRx->orxAgcCtrl->peakAgc->hb2LowThresh + * - device->obsRx->orxAgcCtrl->peakAgc->hb2VeryLowThresh + * - device->obsRx->orxAgcCtrl->peakAgc->apdHighThreshExceededCnt + * - device->obsRx->orxAgcCtrl->peakAgc->apdLowThreshExceededCnt + * - device->obsRx->orxAgcCtrl->peakAgc->hb2HighThreshExceededCnt + * - device->obsRx->orxAgcCtrl->peakAgc->hb2LowThreshExceededCnt + * - device->obsRx->orxAgcCtrl->peakAgc->hb2VeryLowThreshExceededCnt + * - device->obsRx->orxAgcCtrl->peakAgc->apdHighGainStepAttack + * - device->obsRx->orxAgcCtrl->peakAgc->apdLowGainStepRecovery + * - device->obsRx->orxAgcCtrl->peakAgc->hb2HighGainStepAttack + * - device->obsRx->orxAgcCtrl->peakAgc->hb2LowGainStepRecovery + * - device->obsRx->orxAgcCtrl->peakAgc->hb2VeryLowGainStepRecovery + * - device->obsRx->orxAgcCtrl->peakAgc->apdFastAttack + * - device->obsRx->orxAgcCtrl->peakAgc->hb2FastAttack + * - device->obsRx->orxAgcCtrl->peakAgc->hb2OverloadDetectEnable + * - device->obsRx->orxAgcCtrl->peakAgc->hb2OverloadDurationCnt + * - device->obsRx->orxAgcCtrl->peakAgc->hb2OverloadThreshCnt + * - device->obsRx->orxAgcCtrl->powerAgc->pmdUpperHighThresh + * - device->obsRx->orxAgcCtrl->powerAgc->pmdUpperLowThresh + * - device->obsRx->orxAgcCtrl->powerAgc->pmdLowerHighThresh + * - device->obsRx->orxAgcCtrl->powerAgc->pmdLowerLowThresh + * - device->obsRx->orxAgcCtrl->powerAgc->pmdUpperHighGainStepAttack + * - device->obsRx->orxAgcCtrl->powerAgc->pmdUpperLowGainStepAttack + * - device->obsRx->orxAgcCtrl->powerAgc->pmdLowerHighGainStepRecovery + * - device->obsRx->orxAgcCtrl->powerAgc->pmdLowerLowGainStepRecovery + * - device->obsRx->orxAgcCtrl->powerAgc->pmdMeasDuration + * - device->obsRx->orxAgcCtrl->powerAgc->pmdMeasConfig + * + * \param device is structure pointer to the Mykonos data structure containing settings + * The pointer to the Mykonos AGC data structure containing settings is checked for a null pointer + * to ensure it has been initialized. If not an error is thrown. + * + * \retval Returns MYKONOS_ERR=pass, !MYKONOS_ERR=fail + * \retval MYKONOS_ERR_INV_AGC_OBSRX_STRUCT_INIT + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PEAK_STRUCT_INIT + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PWR_STRUCT_INIT + * \retval MYKONOS_ERR_INV_AGC_OBSRX_MAX_GAIN_INDEX + * \retval MYKONOS_ERR_INV_AGC_OBSRX_MIN_GAIN_INDEX + * \retval MYKONOS_ERR_INV_AGC_OBSRX_SELECT + * \retval MYKONOS_ERR_INV_AGC_OBSRX_GAIN_UPDATE_TIME_PARM + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PEAK_WAIT_TIME_PARM + * \retval MYKONOS_ERR_INV_AGC_OBSRX_SLOW_LOOP_SETTLING_DELAY + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_DURATION + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_CONFIG + * \retval MYKONOS_ERR_INV_AGC_OBSRX_LOW_THS_PREV_GAIN_INC + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PEAK_THRESH_MODE + * \retval MYKONOS_ERR_INV_AGC_OBSRX_RESET_ON_RX_ENABLE + * \retval MYKONOS_ERR_INV_AGC_OBSRX_ENABLE_SYNC_PULSE_GAIN_COUNTER + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_THRESH + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_THRESH + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_THRESH + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_THRESH + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_GAIN_STEP + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_GAIN_STEP + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_GAIN_STEP + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_GAIN_STEP + * \retval MYKONOS_ERR_INV_AGC_OBSRX_PKDET_FAST_ATTACK_VALUE + * \retval MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_THRESH_PARM + * \retval MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_THRESH_PARM + * \retval MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_THRESH_PARM + * \retval MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_THRESH_PARM + * \retval MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_THRESH_PARM + * \retval MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_GAIN_STEP_PARM + * \retval MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_GAIN_STEP_PARM + * \retval MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_GAIN_STEP_PARM + * \retval MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_GAIN_STEP_PARM + * \retval MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_GAIN_STEP_PARM + * \retval MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_ENABLE + * \retval MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_DUR_CNT + * \retval MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_THRESH_CNT + */ +mykonosErr_t MYKONOS_setupObsRxAgc(mykonosDevice_t *device) +{ + /* Current configuration does not support AGC on ORx channel */ + uint8_t decPowerConfig = 0; + uint8_t lower1ThreshGainStepRegValue = 0; + uint8_t powerThresholdsRegValue = 0; + uint8_t hb2OvldCfgRegValue = 0; + uint8_t agcGainUpdateCtr[3] = {0}; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setupObsRxAgc()\n"); +#endif + + /* Check mykonosAgcCfg_t device->obsRx->orxAgcCtrl pointer for initialization */ + if (device->obsRx->orxAgcCtrl == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_STRUCT_INIT, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_STRUCT_INIT)); + return MYKONOS_ERR_INV_AGC_OBSRX_STRUCT_INIT; + } + + /* Check mykonosPeakDetAgcCfg_t device->orx->orxAgcCtrl->peakAgc pointer for initialization */ + if (device->obsRx->orxAgcCtrl->peakAgc == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PEAK_STRUCT_INIT, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PEAK_STRUCT_INIT)); + return MYKONOS_ERR_INV_AGC_OBSRX_PEAK_STRUCT_INIT; + } + + /* Check mykonosPowerMeasAgcCfg_t device->obsRx->orxAgcCtrl->powerAgc pointer for initialization */ + if (device->obsRx->orxAgcCtrl->powerAgc == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PWR_STRUCT_INIT, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PWR_STRUCT_INIT)); + return MYKONOS_ERR_INV_AGC_OBSRX_PWR_STRUCT_INIT; + } + + /* Range check agcObsRxMaxGainIndex versus gain table limits and agcObsRxMinGainIndex */ + if ((device->obsRx->orxAgcCtrl->agcObsRxMaxGainIndex > device->obsRx->snifferGainCtrl->maxGainIndex) || + (device->obsRx->orxAgcCtrl->agcObsRxMaxGainIndex < device->obsRx->orxAgcCtrl->agcObsRxMinGainIndex)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_MAX_GAIN_INDEX, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_MAX_GAIN_INDEX)); + return MYKONOS_ERR_INV_AGC_OBSRX_MAX_GAIN_INDEX; + } + else + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_MAX_GAIN_INDEX, + (device->obsRx->orxAgcCtrl->agcObsRxMaxGainIndex - MAX_SNRX_GAIN_TABLE_NUMINDEXES)); + } + + /* Range check agcObsRxMinGainIndex versus gain table limits and agcObsRxMaxGainIndex */ + if ((device->obsRx->orxAgcCtrl->agcObsRxMinGainIndex < device->obsRx->snifferGainCtrl->minGainIndex) || + (device->obsRx->orxAgcCtrl->agcObsRxMaxGainIndex < device->obsRx->orxAgcCtrl->agcObsRxMinGainIndex)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_MIN_GAIN_INDEX, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_MIN_GAIN_INDEX)); + return MYKONOS_ERR_INV_AGC_OBSRX_MIN_GAIN_INDEX; + } + else + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_MIN_GAIN_INDEX, + (device->obsRx->orxAgcCtrl->agcObsRxMinGainIndex - MAX_SNRX_GAIN_TABLE_NUMINDEXES)); + } + + /* Range check agcObsRxSelect. Sniffer only support. Sniffer is selected if value is 0 or 1. 2 or 3 select ORx1/ORx2 respectively */ + if (device->obsRx->orxAgcCtrl->agcObsRxSelect > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_SELECT, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_SELECT)); + return MYKONOS_ERR_INV_AGC_OBSRX_SELECT; + } + else + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_ACTIVE, device->obsRx->orxAgcCtrl->agcObsRxSelect); + } + + /* Range check for agcGainUpdateCounter (22-bit) */ + if ((device->obsRx->orxAgcCtrl->agcGainUpdateCounter > 0x3FFFFF) || + (device->obsRx->orxAgcCtrl->agcGainUpdateCounter < 1)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_GAIN_UPDATE_TIME_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_GAIN_UPDATE_TIME_PARM)); + return MYKONOS_ERR_INV_AGC_OBSRX_GAIN_UPDATE_TIME_PARM; + } + else + { + /* Split agcGainUpdateCounter into three values */ + agcGainUpdateCtr[0] = (uint8_t)(device->obsRx->orxAgcCtrl->agcGainUpdateCounter); + agcGainUpdateCtr[1] = (uint8_t)(device->obsRx->orxAgcCtrl->agcGainUpdateCounter >> 8); + agcGainUpdateCtr[2] = (uint8_t)(device->obsRx->orxAgcCtrl->agcGainUpdateCounter >> 16); + + /* Write two bytes directly due. Third word has its upper two bits masked off. */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_1, agcGainUpdateCtr[0]); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_2, agcGainUpdateCtr[1]); + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_3, agcGainUpdateCtr[2], 0x3F, 0); + } + + /* Range check on agcPeakWaitTime (5-bit) */ + if ((device->obsRx->orxAgcCtrl->agcPeakWaitTime > 0x1F) || + (device->obsRx->orxAgcCtrl->agcPeakWaitTime < 0x02)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PEAK_WAIT_TIME_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PEAK_WAIT_TIME_PARM)); + return MYKONOS_ERR_INV_AGC_OBSRX_PEAK_WAIT_TIME_PARM; + } + else + { + /* Write agcPeakWaitTime */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_CFG_2, device->obsRx->orxAgcCtrl->agcPeakWaitTime, 0x1F, 0); + } + + /* Range check for agcSlowLoopSettlingDelay (7-bit) */ + if (device->obsRx->orxAgcCtrl->agcSlowLoopSettlingDelay > 0x7F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_SLOW_LOOP_SETTLING_DELAY, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_SLOW_LOOP_SETTLING_DELAY)); + return MYKONOS_ERR_INV_AGC_OBSRX_SLOW_LOOP_SETTLING_DELAY; + } + else + { + /* Write agcSlowLoopSettlingDelay */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOOP_CFG, device->obsRx->orxAgcCtrl->agcSlowLoopSettlingDelay, 0x7F, 0); + } + + /* Range check for pmdMeasDuration */ + if ((uint32_t)(1 << (3 + device->obsRx->orxAgcCtrl->powerAgc->pmdMeasDuration)) >= (device->obsRx->orxAgcCtrl->agcGainUpdateCounter)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_DURATION, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_DURATION)); + return MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_DURATION; + } + else + { + /* Write pmdMeasDuration */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_SNIFFER_DEC_POWER_CONFIG_2, device->obsRx->orxAgcCtrl->powerAgc->pmdMeasDuration, 0x0F, 0); + } + + /* Range check for pmdMeasConfig */ + if (device->obsRx->orxAgcCtrl->powerAgc->pmdMeasConfig > 0x3) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_CONFIG, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_CONFIG)); + return MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_CONFIG; + } + else + { + if (device->obsRx->orxAgcCtrl->powerAgc->pmdMeasConfig == 0) + { + decPowerConfig = 0x0; /* Dec Pwr measurement disable */ + } + else if (device->obsRx->orxAgcCtrl->powerAgc->pmdMeasConfig == 1) + { + decPowerConfig = 0x3; /* Dec Pwr measurement enable, HB2 for decPwr measurement */ + } + else if (device->obsRx->orxAgcCtrl->powerAgc->pmdMeasConfig == 2) + { + decPowerConfig = 0x5; /* Dec Pwr measurement enable, RFIR for decPwr measurement */ + } + else if (device->obsRx->orxAgcCtrl->powerAgc->pmdMeasConfig == 3) + { + decPowerConfig = 0x11; /* Dec Pwr measurement enable, BBDC2 for decPwr measurement */ + } + /* Write pmdMeasConfig */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_SNIFFER_DEC_POWER_CONFIG_1, decPowerConfig); + } + + /* Range check agcLowThsPreventGainIncrease (1-bit) */ + if (device->obsRx->orxAgcCtrl->agcLowThsPreventGainIncrease > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_LOW_THS_PREV_GAIN_INC, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_LOW_THS_PREV_GAIN_INC)); + return MYKONOS_ERR_INV_AGC_OBSRX_LOW_THS_PREV_GAIN_INC; + } + else + { + /* Write agcLowThsPreventGainIncrease */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOCK_LEV_THRSH, device->obsRx->orxAgcCtrl->agcLowThsPreventGainIncrease, 0x80, 7); + } + + /* Range check agcPeakThresholdMode (1-bit), */ + if (device->obsRx->orxAgcCtrl->agcPeakThresholdMode > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PEAK_THRESH_MODE, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PEAK_THRESH_MODE)); + return MYKONOS_ERR_INV_AGC_OBSRX_PEAK_THRESH_MODE; + } + else + { + /* Save to lower1ThreshGainStepRegValue register variable */ + lower1ThreshGainStepRegValue |= (uint8_t)(device->obsRx->orxAgcCtrl->agcPeakThresholdMode << 5); + } + + /* Range check agcResetOnRxEnable (1-bit) */ + if (device->obsRx->orxAgcCtrl->agcResetOnRxEnable > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_RESET_ON_RX_ENABLE, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_RESET_ON_RX_ENABLE)); + return MYKONOS_ERR_INV_AGC_OBSRX_RESET_ON_RX_ENABLE; + } + else + { + /* Write agcResetOnRxEnable */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_3, (uint8_t)(device->obsRx->orxAgcCtrl->agcResetOnRxEnable << 7), 0x80, 0); + } + + /* Range check agcEnableSyncPulseForGainCounter (1-bit) */ + if (device->obsRx->orxAgcCtrl->agcEnableSyncPulseForGainCounter > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_ENABLE_SYNC_PULSE_GAIN_COUNTER, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_ENABLE_SYNC_PULSE_GAIN_COUNTER)); + return MYKONOS_ERR_INV_AGC_OBSRX_ENABLE_SYNC_PULSE_GAIN_COUNTER; + } + else + { + /* Write agcEnableSyncPulseForGainCounter */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOOP_CFG, (uint8_t)(device->obsRx->orxAgcCtrl->agcEnableSyncPulseForGainCounter << 7), 0x80, 0); + } + + /* WRITE REGISTERS FOR THE AGC POWER MEASUREMENT DETECTOR (PMD) STRUCTURE */ + + /* Range check pmdLowerHighThresh (7-bit) vs 0x7F and pmdUpperLowThresh */ + if ((device->obsRx->orxAgcCtrl->powerAgc->pmdLowerHighThresh <= device->obsRx->orxAgcCtrl->powerAgc->pmdUpperLowThresh) || + device->obsRx->orxAgcCtrl->powerAgc->pmdLowerHighThresh > 0x7F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_THRESH, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_THRESH)); + return MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_THRESH; + } + else + { + /* Write pmdLowerHighThresh */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOCK_LEV_THRSH, device->obsRx->orxAgcCtrl->powerAgc->pmdLowerHighThresh, 0x7F, 0); + } + + /* Range check pmdUpperLowThresh (7-bit): Comparison to pmdLowerHigh done earlier */ + if (device->obsRx->orxAgcCtrl->powerAgc->pmdUpperLowThresh > 0x7F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_THRESH, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_THRESH)); + return MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_THRESH; + } + else + { + /* Write pmdUpperLowThresh */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_LOCK_LEVEL, device->obsRx->orxAgcCtrl->powerAgc->pmdUpperLowThresh); + } + + /* Range check pmdLowerLowThresh (4-bit) */ + if (device->obsRx->orxAgcCtrl->powerAgc->pmdLowerLowThresh > 0xF) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_THRESH, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_THRESH)); + return MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_THRESH; + } + else + { + /* Write pmdUpperLowThresh to temp variable */ + powerThresholdsRegValue |= device->obsRx->orxAgcCtrl->powerAgc->pmdLowerLowThresh; + } + + /* Range check pmdUpperHighThresh (4-bit) */ + if (device->obsRx->orxAgcCtrl->powerAgc->pmdUpperHighThresh > 0xF) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_THRESH, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_THRESH)); + return MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_THRESH; + } + else + { + /* Write pmdUpperHighThresh to temp var, then to register */ + powerThresholdsRegValue |= (uint8_t)(device->obsRx->orxAgcCtrl->powerAgc->pmdUpperHighThresh << 4); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_POWER_THRSH, powerThresholdsRegValue); + } + + /* Range check pmdUpperHighGainStepAttack (5-bit) */ + if (device->obsRx->orxAgcCtrl->powerAgc->pmdUpperHighGainStepAttack > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_GAIN_STEP, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_GAIN_STEP)); + return MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_GAIN_STEP; + } + else + { + /* Write pmdUpperHighGainStepAttack */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER1_THRSH_GAIN_STEP, device->obsRx->orxAgcCtrl->powerAgc->pmdUpperHighGainStepAttack, 0x1F, 0); + } + + /* Range check pmdLowerLowGainStepRecovery (5-bit) */ + if (device->obsRx->orxAgcCtrl->powerAgc->pmdLowerLowGainStepRecovery > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_GAIN_STEP, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_GAIN_STEP)); + return MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_GAIN_STEP; + } + else + { + /* Write pmdLowerLowGainStepRecovery to temp var, then to register */ + lower1ThreshGainStepRegValue |= (uint8_t)(device->obsRx->orxAgcCtrl->powerAgc->pmdLowerLowGainStepRecovery); + } + + /* Range check pmdUpperLowGainStepRecovery (5-bit) */ + if (device->obsRx->orxAgcCtrl->powerAgc->pmdUpperLowGainStepAttack > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_GAIN_STEP, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_GAIN_STEP)); + return MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_GAIN_STEP; + } + else + { + /* Write pmdUpperLowGainStepRecovery to register */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER0_THRSH_GAIN_STEP, device->obsRx->orxAgcCtrl->powerAgc->pmdUpperLowGainStepAttack); + } + + /* Range check pmdLowerHighGainStepRecovery (5-bit) */ + if (device->obsRx->orxAgcCtrl->powerAgc->pmdLowerHighGainStepRecovery > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_GAIN_STEP, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_GAIN_STEP)); + return MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_GAIN_STEP; + } + else + { + /* Write pmdLowerLowGainStepRecovery to temp var, then to register */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER0_THRSH_GAIN_STEP, device->obsRx->orxAgcCtrl->powerAgc->pmdLowerHighGainStepRecovery); + } + + /* WRITE REGISTERS FOR THE AGC PEAK DETECTOR (APD/HB2) STRUCTURE */ + + /* Range check apdFastAttack and hb2FastAttack (1-bit) */ + if ((device->obsRx->orxAgcCtrl->peakAgc->apdFastAttack > 0x1) || + (device->obsRx->orxAgcCtrl->peakAgc->hb2FastAttack > 0x1)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_PKDET_FAST_ATTACK_VALUE, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_PKDET_FAST_ATTACK_VALUE)); + return MYKONOS_ERR_INV_AGC_OBSRX_PKDET_FAST_ATTACK_VALUE; + } + else + { + /* Write pmdLowerLowGainStepRecovery to temp var, then to register */ + lower1ThreshGainStepRegValue |= (uint8_t)(device->obsRx->orxAgcCtrl->peakAgc->apdFastAttack << 7); + lower1ThreshGainStepRegValue |= (uint8_t)(device->obsRx->orxAgcCtrl->peakAgc->hb2FastAttack << 6); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER1_THRSH_GAIN_STEP, lower1ThreshGainStepRegValue); + } + + /* Range check apdHighThresh */ + if ((device->obsRx->orxAgcCtrl->peakAgc->apdHighThresh > 0x3F) || + (device->obsRx->orxAgcCtrl->peakAgc->apdHighThresh <= device->obsRx->orxAgcCtrl->peakAgc->apdLowThresh)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_THRESH_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_THRESH_PARM)); + return MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_THRESH_PARM; + } + else + { + /* Write apdHighThresh */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_ULB_THRSH, device->obsRx->orxAgcCtrl->peakAgc->apdHighThresh, 0X3F, 0); + } + + /* Range check apdLowThresh */ + if ((device->obsRx->orxAgcCtrl->peakAgc->apdLowThresh > 0x3F) || + (device->obsRx->orxAgcCtrl->peakAgc->apdHighThresh < device->obsRx->orxAgcCtrl->peakAgc->apdLowThresh)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_THRESH_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_THRESH_PARM)); + return MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_THRESH_PARM; + } + else + { + /* write apdLowThresh */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_LLB_THRSH, device->obsRx->orxAgcCtrl->peakAgc->apdLowThresh, 0x3F, 0); + } + + /* Range check hb2HighThresh */ + if (device->obsRx->orxAgcCtrl->peakAgc->hb2HighThresh < device->obsRx->orxAgcCtrl->peakAgc->hb2LowThresh) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_THRESH_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_THRESH_PARM)); + return MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_THRESH_PARM; + } + else + { + /* write hb2HighThresh */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_UPPER_THRSH, device->obsRx->orxAgcCtrl->peakAgc->hb2HighThresh); + } + + /* Range check hb2LowThresh */ + if (device->obsRx->orxAgcCtrl->peakAgc->hb2LowThresh > device->obsRx->orxAgcCtrl->peakAgc->hb2HighThresh) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_THRESH_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_THRESH_PARM)); + return MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_THRESH_PARM; + } + else + { + /* write hb2LowThresh */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_LOWER_THRSH, device->obsRx->orxAgcCtrl->peakAgc->hb2LowThresh); + } + + /* Range check hb2VeryLowThresh */ + if (device->obsRx->orxAgcCtrl->peakAgc->hb2VeryLowThresh > device->obsRx->orxAgcCtrl->peakAgc->hb2LowThresh) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_THRESH_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_THRESH_PARM)); + return MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_THRESH_PARM; + } + else + { + /* write hb2VeryLowThresh */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_VERYLOW_THRSH, device->obsRx->orxAgcCtrl->peakAgc->hb2VeryLowThresh); + } + + /* Write threshold counter values for apdHigh/apdLow/hb2High/hb2Low/hb2VeryLow */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ULB_CNT_THRSH, device->obsRx->orxAgcCtrl->peakAgc->apdHighThreshExceededCnt); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LLB_CNT_THRSH, device->obsRx->orxAgcCtrl->peakAgc->apdLowThreshExceededCnt); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_HIGH_OVRG_CNT_THRSH, device->obsRx->orxAgcCtrl->peakAgc->hb2HighThreshExceededCnt); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_LOW_OVRG_CNT_THRSH, device->obsRx->orxAgcCtrl->peakAgc->hb2LowThreshExceededCnt); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_VERYLOW_OVRG_CNT_THRSH, device->obsRx->orxAgcCtrl->peakAgc->hb2VeryLowThreshExceededCnt); + + /* Range check on apdHighGainStepAttack (5-bit) */ + if (device->obsRx->orxAgcCtrl->peakAgc->apdHighGainStepAttack > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_GAIN_STEP_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_GAIN_STEP_PARM)); + return MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_GAIN_STEP_PARM; + } + else + { + /* Write apdHighGainStepAttack */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_1, device->obsRx->orxAgcCtrl->peakAgc->apdHighGainStepAttack); + } + + /* Range check on apdLowGainStepRecovery (5-bit) */ + if (device->obsRx->orxAgcCtrl->peakAgc->apdLowGainStepRecovery > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_GAIN_STEP_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_GAIN_STEP_PARM)); + return MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_GAIN_STEP_PARM; + } + else + { + /* Write apdLowGainStepRecovery */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_4, device->obsRx->orxAgcCtrl->peakAgc->apdLowGainStepRecovery); + } + + /* Range check on hb2HighGainStepAttack (5-bit) */ + if (device->obsRx->orxAgcCtrl->peakAgc->hb2HighGainStepAttack > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_GAIN_STEP_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_GAIN_STEP_PARM)); + return MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_GAIN_STEP_PARM; + } + else + { + /* Write hb2HighGainStepAttack */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_2, device->obsRx->orxAgcCtrl->peakAgc->hb2HighGainStepAttack); + } + + /* Range check on hb2LowGainStepRecovery (5-bit) */ + if (device->obsRx->orxAgcCtrl->peakAgc->hb2LowGainStepRecovery > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_GAIN_STEP_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_GAIN_STEP_PARM)); + return MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_GAIN_STEP_PARM; + } + else + { + /* Write hb2LowGainStepRecovery */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_5, device->obsRx->orxAgcCtrl->peakAgc->hb2LowGainStepRecovery); + } + + /* Range check on hb2VeryLowGainStepRecovery (5-bit) */ + if (device->obsRx->orxAgcCtrl->peakAgc->hb2VeryLowGainStepRecovery > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_GAIN_STEP_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_GAIN_STEP_PARM)); + return MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_GAIN_STEP_PARM; + } + else + { + /* Write hb2VeryLowGainStepRecovery */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_6, device->obsRx->orxAgcCtrl->peakAgc->hb2VeryLowGainStepRecovery); + } + + /* Range Check on hb2OverloadDetectEnable */ + if (device->obsRx->orxAgcCtrl->peakAgc->hb2OverloadDetectEnable > 0x1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_ENABLE, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_ENABLE)); + return MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_ENABLE; + } + + /* Range Check on hb2OverloadDetectEnable */ + if (device->obsRx->orxAgcCtrl->peakAgc->hb2OverloadDurationCnt > 0x7) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_DUR_CNT, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_DUR_CNT)); + return MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_DUR_CNT; + } + + /* Range Check on hb2OverloadDetectEnable */ + if (device->obsRx->orxAgcCtrl->peakAgc->hb2OverloadThreshCnt > 0xF) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_THRESH_CNT, + getMykonosErrorMessage(MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_THRESH_CNT)); + return MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_THRESH_CNT; + } + else + { + /* Write the hb2OvldCfgRegValue, the combination of hb2OverloadThreshCnt, hb2OverloadDurationCnt, and hb2OverloadDetectEnable */ + hb2OvldCfgRegValue = (device->obsRx->orxAgcCtrl->peakAgc->hb2OverloadThreshCnt) | + (uint8_t)(device->obsRx->orxAgcCtrl->peakAgc->hb2OverloadDurationCnt << 4) | + (uint8_t)(device->obsRx->orxAgcCtrl->peakAgc->hb2OverloadDetectEnable << 7); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_CFG, hb2OvldCfgRegValue); + } + + /* Hard-coded value for the ADC overload configuration. Sets the HB2 offset to -6dB.*/ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ORX_SNRX_OVRLD_ADC_OVRLD_CFG, 0x18); + /* Hard-coded value for APD decay setting. Setting allows for the quickest settling time of peak detector */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_BLOCK_DET_DECAY, 0x0); + + /* performing a soft reset */ + return MYKONOS_resetRxAgc(device); +} + +/** + * \brief Enables or disables the ObsRx slow loop gain counter to use the sync pulse + * + * Dependencies: + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing the device SPI settings + * \param enable is a uint8_t data type where '0' = disable ObsRx gain counter from using sync pulse, '1' = enable ObsRx gain. All other values will throw an error. + * counter to use the sync pulse. This value is written back to the device data structure for storage. + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_enableObsRxGainCtrSyncPulse(mykonosDevice_t *device, uint8_t enable) +{ + const uint8_t syncPulseBitMask = 0x80; + uint8_t enableBit = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableObsRxGainCtrSyncPulse()\n"); +#endif + + enableBit = (enable > 0) ? 1 : 0; + + /* read, modify, write ObsRx gain counter sync pulse enable bit */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOOP_CFG, enableBit, syncPulseBitMask, 7); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Configures the ObsRx gain control mode + * + * Dependencies: + * - device->spiSettings + * - device->obsRx->orxGainCtrl->gainMode + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param mode is a mykonosGainMode_t enumerated gain control mode type + * + * When the mode enumerated type is passed, the ObsRx gain mode is set to this value and the + * ObsRX agcType mykonosAgcCfg_t structure member is updated with the new value + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_INV_ORX_GAIN_MODE_PARM Invalid Observation Rx Gain control mode selected (use mykonosGainMode_t ENUM values) + */ +mykonosErr_t MYKONOS_setObsRxGainControlMode(mykonosDevice_t *device, mykonosGainMode_t mode) +{ + const uint8_t ORX_GAIN_TYPE_MASK = 0x3; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setObsRxGainControlMode()\n"); +#endif + + /* performing gain type check */ + switch (mode) + { + case MGC: + break; + case AGC: + break; + case HYBRID: + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_ORX_GAIN_MODE_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_ORX_GAIN_MODE_PARM)); + return MYKONOS_ERR_INV_ORX_GAIN_MODE_PARM; + } + + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_CFG_1, mode, ORX_GAIN_TYPE_MASK, 0); + + /* writing mode setting to data structure */ + if ((device->profilesValid & ORX_PROFILE_VALID) > 0) + { + device->obsRx->orxGainCtrl->gainMode = mode; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Performs a power measurement in the ObsRx digital data path. + * + * Due to interdependencies between the AGC and power measurement the power measurement duration and + * where the measurement is taken is variable. + * The location of the power measurement is given by device->obsRx->obsRxAgcCtrl->obsRxPwrAgc->pmdMeasConfig + * The number of samples the power measurement uses is given by 8*2^(device->obsRx->obsRxAgcCtrl->obsRxPwrAgc->pmdMeasConfig) at the IQ rate, + * if measured at RFIR output. This number of samples must be less than the agcGainUpdateCounter. + * If the receiver is disabled during the power measurement, this function returns a 0 value for rx2DecPower_mdBFS + * + * The resolution of this function is 0.25dB. + * The dynamic range of this function is 40dB. Signals lower than 40dBFS may not be measured accurately. + * + * Dependencies + * - device->spiSettings + * - device->obsRx->obsRxAgcCtrl->obsRxPwrAgc->pmdMeasConfig + * - device->obsRx->obsRxAgcCtrl->obsRxPwrAgc->pmdMeasConfig + * + * \param device Pointer to the Mykonos data structure + * \param obsRxDecPower_mdBFS Pointer to store the Rx1 decimated power return. Value returned in mdBFS + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getObsRxDecPower(mykonosDevice_t *device, uint16_t *obsRxDecPower_mdBFS) +{ + uint8_t obsRxDecPower_dBFS = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getObsRxDecPower()\n"); +#endif + + /* read ObsRx Dec Power Measurement */ + if (obsRxDecPower_mdBFS != NULL) + { + CMB_SPIReadByte(device->spiSettings, MYKONOS_SNIFFER_DECIMATED_PWR, &obsRxDecPower_dBFS); + *obsRxDecPower_mdBFS = (uint16_t)(obsRxDecPower_dBFS * 250); /* 250 = 1000 * 0.25dB */ + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_OBSRX_DEC_POWER_NULL_PARM, + getMykonosErrorMessage(MYKONOS_ERR_GET_OBSRX_DEC_POWER_NULL_PARM)); + return MYKONOS_ERR_GET_OBSRX_DEC_POWER_NULL_PARM; + } + + return MYKONOS_ERR_OK; +} + +/* + ***************************************************************************** + * Tx Data path functions + ***************************************************************************** + */ + +/** + * \brief Sets the Tx1 RF output Attenuation + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * - device->tx->txAttenStepSize + * + * \param device Pointer to the Mykonos device's data structure + * \param tx1Attenuation_mdB The desired TxAttenuation in milli-dB (Range: 0 to 41950 mdB) + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_SETTX1ATTEN_INV_PARM tx1Attenuation_mdB parameter is out of range (0 - 41950) + * \retval MYKONOS_ERR_SETTX1ATTEN_INV_STEPSIZE_PARM device->tx->txAttenStepSize is not a valid enum value + */ +mykonosErr_t MYKONOS_setTx1Attenuation(mykonosDevice_t *device, uint16_t tx1Attenuation_mdB) +{ + uint16_t data = 0; + uint16_t attenStepSizeDiv = 50; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setTx1Attenuation()\n"); +#endif + + /* check input parameter is in valid range */ + if (tx1Attenuation_mdB > 41950) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETTX1ATTEN_INV_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SETTX1ATTEN_INV_PARM)); + return MYKONOS_ERR_SETTX1ATTEN_INV_PARM; + } + + switch (device->tx->txAttenStepSize) + { + case TXATTEN_0P05_DB: + attenStepSizeDiv = 50; + break; + case TXATTEN_0P1_DB: + attenStepSizeDiv = 100; + break; + case TXATTEN_0P2_DB: + attenStepSizeDiv = 200; + break; + case TXATTEN_0P4_DB: + attenStepSizeDiv = 400; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETTX1ATTEN_INV_STEPSIZE_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SETTX1ATTEN_INV_STEPSIZE_PARM)); + return MYKONOS_ERR_SETTX1ATTEN_INV_STEPSIZE_PARM; + + } + + data = (tx1Attenuation_mdB / attenStepSizeDiv); + + /* Write MSB bits followed by LSB bits, TxAtten updates when [7:0] written */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX1_ATTENUATION_1, ((data >> 8) & 0x03)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX1_ATTENUATION_0, (data & 0xFF)); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets the Tx2 RF output Attenuation (Step size is 0.05dB.) + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * - device->tx->txAttenStepSize + * + * \param device Pointer to the Mykonos device's data structure + * \param tx2Attenuation_mdB The desired TxAttenuation in milli-dB + * (Range: 0 to 41950 mdB) + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_SETTX2ATTEN_INV_PARM tx2Attenuation_mdB parameter is out of range (0 - 41950) + * \retval MYKONOS_ERR_SETTX2ATTEN_INV_STEPSIZE_PARM device->tx->txAttenStepSize is not a valid enum value + */ +mykonosErr_t MYKONOS_setTx2Attenuation(mykonosDevice_t *device, uint16_t tx2Attenuation_mdB) +{ + uint16_t attenStepSizeDiv = 50; + uint16_t data = 0; + //const uint8_t SPI_TXATTEN_MODE = 0x01; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setTx2Attenuation()\n"); +#endif + + /* check input parameter is in valid range */ + if (tx2Attenuation_mdB > 41950) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETTX2ATTEN_INV_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SETTX2ATTEN_INV_PARM)); + return MYKONOS_ERR_SETTX2ATTEN_INV_PARM; + } + + switch (device->tx->txAttenStepSize) + { + case TXATTEN_0P05_DB: + attenStepSizeDiv = 50; + break; + case TXATTEN_0P1_DB: + attenStepSizeDiv = 100; + break; + case TXATTEN_0P2_DB: + attenStepSizeDiv = 200; + break; + case TXATTEN_0P4_DB: + attenStepSizeDiv = 400; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETTX2ATTEN_INV_STEPSIZE_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SETTX2ATTEN_INV_STEPSIZE_PARM)); + return MYKONOS_ERR_SETTX2ATTEN_INV_STEPSIZE_PARM; + } + + data = (tx2Attenuation_mdB / attenStepSizeDiv); + + /* Write MSB bits followed by LSB bits, TxAtten updates when [7:0] written */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX2_ATTENUATION_1, ((data >> 8) & 0x03)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX2_ATTENUATION_0, (data & 0xFF)); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads back the Tx1 RF output Attenuation + * + * This function reads back the TxAttenuation setting currently applied to the transmit chain. + * The function will work with SPI mode or pin controlled TxAtten mode using the increment/decrement GPIO + * pins. For the readback value to be valid the Tx data path must be powered up. If the Tx data path + * is powered down or radioOff state, the last TxAtten setting while the Tx was powered up will be + * read back. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device's data structure + * \param tx1Attenuation_mdB The readback value of the Tx1 Attenuation in milli-dB (Range: 0 to 41950 mdB) + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETTX1ATTEN_NULL_PARM tx1Attenuation_mdB return parameter has NULL pointer + */ +mykonosErr_t MYKONOS_getTx1Attenuation(mykonosDevice_t *device, uint16_t *tx1Attenuation_mdB) +{ + uint8_t txAttenLsb = 0; + uint8_t txAttenMsb = 0; + uint16_t attenStepSizeDiv = 50; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getTx1Attenuation()\n"); +#endif + + /* check return parameter pointer is not NULL pointer */ + if (tx1Attenuation_mdB == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTX1ATTEN_NULL_PARM, + getMykonosErrorMessage(MYKONOS_ERR_GETTX1ATTEN_NULL_PARM)); + return MYKONOS_ERR_GETTX1ATTEN_NULL_PARM; + } + + /* Write TxAtten read back reg to update readback values, then read Tx1Atten */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX1_ATTENUATION_1_READBACK, 0x00); + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_TX1_ATTENUATION_0_READBACK, &txAttenLsb, 0xFF, 0); + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_TX1_ATTENUATION_1_READBACK, &txAttenMsb, 0x03, 0); + + /* Readback word always reads back with 0.05dB resolution */ + *tx1Attenuation_mdB = (uint16_t)(((uint16_t)(txAttenLsb) | ((uint16_t)(txAttenMsb) << 8)) * attenStepSizeDiv); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads back the Tx2 RF output Attenuation + * + * This function reads back the TxAttenuation setting currently applied to the transmit chain. + * The function will work with SPI mode or pin controlled TxAtten mode using the increment/decrement GPIO + * pins. For the readback value to be valid the Tx data path must be powered up. If the Tx data path + * is powered down or radioOff state, the last TxAtten setting while the Tx was powered up will be + * read back. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device's data structure + * \param tx2Attenuation_mdB The readback value of the Tx2 Attenuation in milli-dB (Range: 0 to 41950 mdB) + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETTX2ATTEN_NULL_PARM tx2Attenuation_mdB return parameter pointer is NULL + */ +mykonosErr_t MYKONOS_getTx2Attenuation(mykonosDevice_t *device, uint16_t *tx2Attenuation_mdB) +{ + uint8_t txAttenLsb = 0; + uint8_t txAttenMsb = 0; + uint16_t attenStepSizeDiv = 50; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getTx2Attenuation()\n"); +#endif + + /* check return parameter pointer is not NULL pointer */ + if (tx2Attenuation_mdB == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTX2ATTEN_NULL_PARM, + getMykonosErrorMessage(MYKONOS_ERR_GETTX2ATTEN_NULL_PARM)); + return MYKONOS_ERR_GETTX2ATTEN_NULL_PARM; + } + + /* Write TxAtten read back reg to update readback values, then read Tx1Atten */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX2_ATTENUATION_1_READBACK, 0x00); + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_TX2_ATTENUATION_0_READBACK, &txAttenLsb, 0xFF, 0); + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_TX2_ATTENUATION_1_READBACK, &txAttenMsb, 0x03, 0); + + /* Readback word always reads back with 0.05dB resolution */ + *tx2Attenuation_mdB = (uint16_t)(((uint16_t)(txAttenLsb) | ((uint16_t)(txAttenMsb) << 8)) * attenStepSizeDiv); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Checks the Tx Filter over-range bit assignments for digital clipping in the Tx data path + * + * Dependencies + * - device->spiSettings + * + * txFilterStatus bit-field assignments are: + * txFilterStatus[0] = TFIR Ch1 Overflow + * txFilterStatus[1] = HB1 Ch1 Overflow + * txFilterStatus[2] = HB2 Ch1 Overflow + * txFilterStatus[3] = QEC Ch1 Overflow + * txFilterStatus[4] = TFIR Ch2 Overflow + * txFilterStatus[5] = HB1 Ch2 Overflow + * txFilterStatus[6] = HB2 Ch2 Overflow + * txFilterStatus[7] = QEC Ch2 Overflow + * + * \param device Pointer to the Mykonos device's data structure + * \param txFilterStatus is an 8-bit Tx filter over-range status bit-field + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GET_TXFILTEROVRG_NULL_PARM Function txFilterStatus parameter pointer is NULL + */ +mykonosErr_t MYKONOS_getTxFilterOverRangeStatus(mykonosDevice_t *device, uint8_t *txFilterStatus) +{ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getTxFilterOverRangeStatus()\n"); +#endif + + if (txFilterStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_TXFILTEROVRG_NULL_PARM, + getMykonosErrorMessage(MYKONOS_ERR_GET_TXFILTEROVRG_NULL_PARM)); + return MYKONOS_ERR_GET_TXFILTEROVRG_NULL_PARM; + } + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_TX_FILTER_OVERFLOW, txFilterStatus); + return MYKONOS_ERR_OK; +} + +/** + * \brief Enables/Disables the Tx NCO test tone + * + * This function enables/disables a digital numerically controlled oscillator + * in the Mykonos Digital to create a test CW tone on Tx1 and Tx2 RF outputs. + * + * The TxAttenuation is forced in this function to max analog output power, but + * the digital attenuation is backed off 6dB to make sure the digital filter + * does not clip and cause spurs in the tx spectrum. + * + * Dependencies + * - device->spiSettings + * - device->profilesValid + * - device->tx->txProfile->iqRate_kHz + * + * \param device Pointer to the Mykonos device's data structure + * \param enable 0 = Disable Tx NCO, 1 = Enable Tx NCO on both transmitters + * \param tx1ToneFreq_kHz Signed frequency in kHz of the desired Tx1 tone + * \param tx2ToneFreq_kHz Signed frequency in kHz of the desired Tx2 tone + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_ENTXNCO_TXPROFILE_INVALID Can not enable Tx NCO when Tx Profile is not enabled/valid + * \retval MYKONOS_ERR_ENTXNCO_TX1_FREQ_INVALID Tx1 NCO Tone frequency out of range (-IQrate/2 to IQrate/2) + * \retval MYKONOS_ERR_ENTXNCO_TX2_FREQ_INVALID Tx2 NCO Tone frequency out of range (-IQrate/2 to IQrate/2) + */ +mykonosErr_t MYKONOS_enableTxNco(mykonosDevice_t *device, uint8_t enable, int32_t tx1ToneFreq_kHz, int32_t tx2ToneFreq_kHz) +{ + int16_t tx1NcoTuneWord = 0; + int16_t tx2NcoTuneWord = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableTxNco()\n"); +#endif + + if (enable > 0) + { + if ((device->profilesValid & TX_PROFILE_VALID) == 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ENTXNCO_TXPROFILE_INVALID, + getMykonosErrorMessage(MYKONOS_ERR_ENTXNCO_TXPROFILE_INVALID)); + return MYKONOS_ERR_ENTXNCO_TXPROFILE_INVALID; + } + + if ((tx1ToneFreq_kHz > ((int32_t)(device->tx->txProfile->iqRate_kHz) / 2)) || (tx1ToneFreq_kHz < ((int32_t)(device->tx->txProfile->iqRate_kHz) * -1 / 2))) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ENTXNCO_TX1_FREQ_INVALID, + getMykonosErrorMessage(MYKONOS_ERR_ENTXNCO_TX1_FREQ_INVALID)); + return MYKONOS_ERR_ENTXNCO_TX1_FREQ_INVALID; + } + + if ((tx2ToneFreq_kHz > ((int32_t)(device->tx->txProfile->iqRate_kHz) / 2)) || (tx2ToneFreq_kHz < ((int32_t)(device->tx->txProfile->iqRate_kHz) * -1 / 2))) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ENTXNCO_TX2_FREQ_INVALID, + getMykonosErrorMessage(MYKONOS_ERR_ENTXNCO_TX2_FREQ_INVALID)); + return MYKONOS_ERR_ENTXNCO_TX2_FREQ_INVALID; + } + + /* Force Tx output power to max analog output power, but 6dB digital */ + /* backoff to prevent the NCO from clipping the Tx PFIR filter */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX1_GAIN_0, 0x78); + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX1_GAIN_1, 0x00, 0x3F, 0); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX1_GAIN_2, 0x0); + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX2_GAIN_0, 0x78); + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX2_GAIN_1, 0x00, 0x3F, 0); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX2_GAIN_2, 0x0); + + /* Enable manual Tx output power mode */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_TPC_CONFIG, 0x0A, 0x0F, 0); + + /* Set Tx NCO tuning words */ + tx1NcoTuneWord = (int16_t)(((int64_t)(tx1ToneFreq_kHz) << 16) / device->tx->txProfile->iqRate_kHz * -1); + tx2NcoTuneWord = (int16_t)(((int64_t)(tx2ToneFreq_kHz) << 16) / device->tx->txProfile->iqRate_kHz * -1); + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_MSB, (uint8_t)((uint16_t)tx1NcoTuneWord >> 8)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_LSB, (tx1NcoTuneWord & 0xFF)); + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_MSB, (uint8_t)((uint16_t)tx2NcoTuneWord >> 8)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_LSB, (tx2NcoTuneWord & 0xFF)); + + /* Enable Tx NCO - set [7] = 1 */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_DIGITAL_TEST_BYTE_0, 1, 0x80, 7); + } + else + { + /* Disable Tx NCO - set [7] = 0 */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_DIGITAL_TEST_BYTE_0, 0, 0x80, 7); + + /* Enable normal Tx Atten table mode */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_TPC_CONFIG, 0x05, 0x0F, 0); + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Writes Mykonos device registers with settings for the PA Protection block. + * + * This function writes register settings for the Mykonos PA Protection Block. + * This function does not enable the PA Protection functionality. + * Note that independent control of PA protection for both Tx channels is not possible. + * The PA Protection block allows for error flags to go high if the accumulated TX power in the data path + * exceeds a programmable threshold level based on samples taken in a programmable duration. + * + * \post After calling this function the user will need to call MYKONOS_enablePaProtection(...) + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device's data structure + * \param powerThreshold PA Protection Threshold sets the power level that, if detected in the TX data path, raises the PA error flags. The range is 0 to 4096. + * To calculate the required setting for the power threshold: + * powerThreshold = MAX_DAC_CODE * (10^((txPowerThresh_dBFS/10))) + * For example: If the required dBFS for the threshold is -10 dBFS, then the powerThreshold passed should be 409. + * + * \param attenStepSize Attenuation Step Size sets the size of the attenuation step when Tx Atten Control is Enabled. The range is 0 to 128 with a resolution is 0.2dB/LSB. + * \param avgDuration Averaging Duration for the TX data path power measurement. The range is 0 to 14 specified in number of cycles of the TX IQ Rate. + * \param stickyFlagEnable "1" Enables the PA Error Flags to stay high after being triggered, even if the power decreases below threshold. "0" disables this functionality. + * \param txAttenControlEnable "1" Enables autonomous attenuation changes in response to PA error flags. "0" disables this functionality. + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_SETUP_PA_PROT_INV_AVG_DURATION avgDuration parameter invalid (valid 0-15) + * \retval MYKONOS_ERR_SETUP_PA_PROT_INV_ATTEN_STEP attenStepSize function parameter invalid (valid 0-127) + */ +mykonosErr_t MYKONOS_setupPaProtection(mykonosDevice_t *device, uint16_t powerThreshold, uint8_t attenStepSize, uint8_t avgDuration, uint8_t stickyFlagEnable, uint8_t txAttenControlEnable) +{ + uint8_t paProtectConfig = 0; + uint8_t paProtectAttenCntl = 0; + + const uint8_t PROTECT_AVG_DUR_MASK = 0x1E; + const uint8_t STICKY_FLAG_EN_MASK = 0x40; + const uint8_t ATT_STEP_MASK = 0xFE; + const uint8_t PROTECT_ATT_EN_MASK = 0x01; + const uint8_t AVG_DUR_MASK = 0x0F; + const uint8_t ATT_STEP_SIZE = 0x7F; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setupPaProtection()\n"); +#endif + + /* Overwrite PA Protection Config register data with averaging duration and sticky flag. Also performing range check on stickyFlagEnable and avgDuration */ + if (avgDuration > AVG_DUR_MASK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETUP_PA_PROT_INV_AVG_DURATION, + getMykonosErrorMessage(MYKONOS_ERR_SETUP_PA_PROT_INV_AVG_DURATION)); + return MYKONOS_ERR_SETUP_PA_PROT_INV_AVG_DURATION; + } + + if (attenStepSize > ATT_STEP_SIZE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETUP_PA_PROT_INV_ATTEN_STEP, + getMykonosErrorMessage(MYKONOS_ERR_SETUP_PA_PROT_INV_ATTEN_STEP)); + return MYKONOS_ERR_SETUP_PA_PROT_INV_ATTEN_STEP; + } + + paProtectConfig = (PROTECT_AVG_DUR_MASK & (avgDuration << 1)); + + if (stickyFlagEnable > 0) + { + paProtectConfig |= (STICKY_FLAG_EN_MASK); + } + + paProtectAttenCntl = ATT_STEP_MASK & (attenStepSize << 1); + + if (txAttenControlEnable > 0) + { + paProtectAttenCntl |= (PROTECT_ATT_EN_MASK); + } + + /* Clear and write all PA Protection setup registers */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_ATTEN_CONTROL, 0x00); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_CONFIGURATION, 0x00); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_LSB, 0x00); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_MSB, 0x00); + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_ATTEN_CONTROL, paProtectAttenCntl); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_CONFIGURATION, paProtectConfig); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_LSB, (powerThreshold & 0xFF)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_MSB, ((powerThreshold >> 8) & 0x0F)); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Enables the Mykonos PA Protection block according to the parameters passed in MYKONOS_setupPaProtection(...). + * + * This function enables the PA Protection block according to the parameters passed in MYKONOS_setupPaProtection(...) + * The paProtectEnable signal enables the PA Protection block, allowing usage of the PA protection functions. + * + * \pre Before calling this function the user needs to setup the PA protection by calling MYKONOS_setupPaProtection(...) + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device's data structure + * \param paProtectEnable "1" Enables the PA Protection block. "0" Disables the PA Protection block + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_enablePaProtection(mykonosDevice_t *device, uint8_t paProtectEnable) +{ + uint8_t paProtectEnableReg = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enablePaProtection()\n"); +#endif + + paProtectEnableReg = (paProtectEnable > 0) ? 1 : 0; + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_CONFIGURATION, paProtectEnableReg, 0x01, 0); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Obtains an estimate of a TX channel's accumulated power over the sample duration provided in MYKONOS_setupPaProtection(...) + * + * This function uses the 'avgDuration' parameter provided in MYKONOS_setupPaProtection to set the number of samples to accumulate + * to obtain an estimate for a TX channel specified by the 'channel' parameter. + * A 12-bit field estimating the channel power is returned in the '*channelPower' pointer. + * To obtain the dBFS value of the reading: + * dBFS value = 10*log10(channelPower/MAX_DAC_CODE) + * where MAX_DAC_CODE = 2^12 = 4096 + * For example: If channelPower is reading 409 then the channel power in dBFS is -10dBFS. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device Point to the Mykonos device's data structure + * \param channel Select the channel of interest. Only use TX1 (1) or TX2 (2) of mykonosTxChannels_t + * \param *channelPower A pointer that stores the selected channels power. Read back is provided as a 12 bit value. + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GET_DAC_PWR_INV_POINTER Function channelPower parameter is a NULL pointer + * \retval MYKONOS_ERR_SETUP_PA_PROT_INV_TX_CHANNEL Invalid Tx Channel passed in function channel parameter (TX1 or TX2) + */ +mykonosErr_t MYKONOS_getDacPower(mykonosDevice_t *device, mykonosTxChannels_t channel, uint16_t *channelPower) +{ + uint8_t channelPowerLsb = 0; + uint8_t channelPowerMsb = 0; + + const uint8_t CHAN_POWER_MSB_MASK = 0xF; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getDacPower()\n"); +#endif + + if (channelPower == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_DAC_PWR_INV_POINTER, + getMykonosErrorMessage(MYKONOS_ERR_GET_DAC_PWR_INV_POINTER)); + return MYKONOS_ERR_GET_DAC_PWR_INV_POINTER; + } + + /* Set bit D5 to read the appropriate channel power */ + switch (channel) + { + case TX1: + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_CONFIGURATION, 0, 0x20, 5); + break; + case TX2: + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_CONFIGURATION, 1, 0x20, 5); + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETUP_PA_PROT_INV_TX_CHANNEL, + getMykonosErrorMessage(MYKONOS_ERR_SETUP_PA_PROT_INV_TX_CHANNEL)); + return MYKONOS_ERR_SETUP_PA_PROT_INV_TX_CHANNEL; + } + + /* SPI Write to register PA Protection power readback registers (write strobe) */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_LSB, 0x00); + + /* SPI Read of the PA Protection power readback registers */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_LSB, &channelPowerLsb); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_MSB, &channelPowerMsb); + + *channelPower = (channelPowerLsb | (((uint16_t)(channelPowerMsb & CHAN_POWER_MSB_MASK)) << 8)); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Returns PA Protection Error Flag Status + * + * This function provides a readback of the PA protection Error Flag Status through the '*errorFlagStatus' pointer + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device Point to the Mykonos device's data structure + * \param errorFlagStatus Pointer to store the error flag status. + * errorFlagStatus | error + * -----------------|------------ + * 0 | indicates no PA Error Flags are high + * 1 | indicates TX1 Error Flag + * 2 | indicates TX2 Error Flag + * 3 | indicates TX1 and TX2 Error Flags are high + * + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GET_PA_FLAG_STATUS_INV_POINTER Function errorFlagStatus parameter has NULL pointer + */ +mykonosErr_t MYKONOS_getPaProtectErrorFlagStatus(mykonosDevice_t *device, uint8_t *errorFlagStatus) +{ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getPaProtectErrorFlagStatus()\n"); +#endif + + if (errorFlagStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_PA_FLAG_STATUS_INV_POINTER, + getMykonosErrorMessage(MYKONOS_ERR_GET_PA_FLAG_STATUS_INV_POINTER)); + return MYKONOS_ERR_GET_PA_FLAG_STATUS_INV_POINTER; + } + + /* SPI Write to register PA Protection power readback registers (write strobe) */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_LSB, 0x00); + + /* SPI Read of the PA Protection power readback registers */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_MSB, errorFlagStatus, 0x60, 5); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Manually clears the PA Protection Error Flags. + * + * This function manually clears the PA Error Flags. The user must setup the PA Protection block to enable + * sticky error flags. Sticky error flags require the user to clear the bit manually even if the accumulated power is + * below the power threshold for the PA protection block. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device's data structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_clearPaErrorFlag(mykonosDevice_t *device) +{ + uint8_t paProtectConfig = 0; + + const uint8_t PA_ERROR_CLEAR_MASK = 0x80; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_clearPaErrorFlag()\n"); +#endif + + /* SPI Read of the PA Protection power readback registers */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_CONFIGURATION, &paProtectConfig); + + /* SPI Write to self clear the PA Error Flags */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PA_PROTECTION_CONFIGURATION, (paProtectConfig | PA_ERROR_CLEAR_MASK)); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Helper function for return of character string based on 32-bit mykonosErr_t enum value + * + * To save codespace, these error strings are ifdef'd out unless the user + * adds a define MYKONOS_VERBOSE to their workspace. This function can be + * useful for debug. Each function also returns unique error codes to + * make it easier to determine where the code broke. + * + * \param errorCode is enumerated error code value + * + * \return Returns character string based on enumerated value + */ +const char* getMykonosErrorMessage(mykonosErr_t errorCode) +{ +#ifndef MYKONOS_VERBOSE + return ""; + +#else + + switch (errorCode) + { + case MYKONOS_ERR_OK: + return ""; + case MYKONOS_ERR_INV_PARM: + return "Mykonos: Invalid parameter\n"; + case MYKONOS_ERR_FAILED: + return "Mykonos: General Failure\n"; + case MYKONOS_ERR_WAITFOREVENT_INV_PARM: + return "waitForEvent had invalid parameter.\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT: + return "waitForEvent timed out.\n"; + case MYKONOS_ERR_SETENSM_INVALID_NEWSTATE_WAIT: + return "Requested new ENSM state is invalid from the WAIT state.\n"; + case MYKONOS_ERR_SETENSM_INVALID_NEWSTATE_ALERT: + return "Requested new ENSM state is invalid from the ALERT state.\n"; + case MYKONOS_ERR_SETENSM_INVALID_NEWSTATE_TXRX: + return "Requested new ENSM state is invalid from the TXRX state.\n"; + case MYKONOS_ERR_SETENSM_INVALIDSTATE: + return "Current ENSM state is an invalid state or calibration state.\n"; + case MYKONOS_ERR_PU_RXPATH_INV_PARAM: + return "Invalid Rx channel was requested to be powered up.\n"; + case MYKONOS_ERR_PU_TXPATH_INV_PARAM: + return "Invalid Tx channel was requested to be powered up.\n"; + case MYKONOS_ERR_PU_OBSRXPATH_INV_PARAM: + return "Invalid ObsRx channel was requested to be powered up.\n"; + case MYKONOS_ERR_SETDEFOBSRXPATH_NULL_DEF_OBSRX_STRUCT: + return "Invalid default ObsRx channel was requested to be powered up.\n"; + case MYKONOS_ERR_INIT_INV_ORXCHAN: + return "Invalid ObsRx channel requested during initialize().\n"; + case MYKONOS_ERR_INIT_INV_RXSYNCB_ORXSYNCB_MODE: + return "Invalid combination for rxsyncb and orxsyncb, if shared syncb they should have the CMOS/LVDS mode\n"; + case MYKONOS_ERR_INIT_INV_TXFIR_INTERPOLATION: + return "Invalid TxFIR interpolation value.(Valid: 1,2,4)\n"; + case MYKONOS_ERR_INIT_INV_TXHB2_INTERPOLATION: + return "Invalid TXHB2 interpolation value.(Valid: 1 or 2)\n"; + case MYKONOS_ERR_INIT_INV_TXHB1_INTERPOLATION: + return "Invalid TXHB1 interpolation value.(Valid: 1 or 2)\n"; + case MYKONOS_ERR_INIT_INV_RXFIR_DECIMATION: + return "Invalid RxFIR decimation value.(Valid: 1,2,4)\n"; + case MYKONOS_ERR_INIT_INV_RXDEC5_DECIMATION: + return "Invalid Rx DEC5 decimation value.(Valid: 4 or 5)\n"; + case MYKONOS_ERR_INIT_INV_RXHB1_DECIMATION: + return "Invalid RxHB1 decimation value.(Valid: 1 or 2)\n"; + case MYKONOS_ERR_INIT_INV_SNIFFER_RHB1: + return "Invalid Sniffer HB1 decimation value (Valid 1 or 2)\n"; + case MYKONOS_ERR_INIT_INV_SNIFFER_RFIR_DEC: + return "Invalid Sniffer RFIR decimation value (Valid 1,2,4)\n"; + case MYKONOS_ERR_INIT_INV_ORX_RHB1: + return "Invalid ORx HB1 decimation value (Valid 1 or 2)\n"; + case MYKONOS_ERR_INIT_INV_ORX_RFIR_DEC: + return "Invalid ORx RFIR decimation value. (Valid 1,2,4)\n"; + case MYKONOS_ERR_INIT_INV_ADCDIV: + return "Invalid Rx ADC divider. (Valid 1 or 2)\n"; + case MYKONOS_ERR_INIT_INV_DACDIV: + return "Invalid Tx DAC divider. Use enum DACDIV_2, DACDIV_2p5 or DACDIV_4.\n"; + case MYKONOS_ERR_INIT_INV_OBSRX_ADCDIV: + return "Invalid ObsRx ADC div. (Valid 1 or 2)\n"; + case MYKONOS_ERR_CLKPLL_INV_HSDIV: + return "Invalid CLKPLL HSDIV. (Valid 4 or 5)\n"; + case MYKONOS_ERR_CLKPLL_INV_VCODIV: + return "Invalid CLKPLL VCODIV. Use enum VCODIV_1, VCODIV_1p5, VCODIV_2, VCODIV_3\n"; + case MYKONOS_ERR_CLKPLL_INV_RXTXPROFILES: + return "No Rx or Tx profile is specified.\n"; + case MYKONOS_ERR_SETCLKPLL_INV_VCOINDEX: + return "CLKPLL VCO frequency out of range.\n"; + case MYKONOS_ERR_SETCLKPLL_INV_FRACWORD: + return "CLKPLL fractional word is non zero.\n"; + case MYKONOS_ERR_SETRFPLL_INV_PLLNAME: + return "Invalid pllName requested in setRfPllFreuquency()\n"; + case MYKONOS_ERR_SETRFPLL_INV_LO_PARM: + return "RF PLL frequency out of range\n"; + case MYKONOS_ERR_GETRFPLL_INV_PLLNAME: + return "Invalid pllName requested in getRfPllFrequency()\n"; + case MYKONOS_ERR_GETRFPLL_ARMERROR: + return "ARM Command Error in MYKONOS_getRfPllFrequency()\n"; + case MYKONOS_ERR_GETRFPLL_NULLPARAM: + return "NULL pointer in function parameter for MYKONOS_setRfPllFrequency()\n"; + case MYKONOS_ERR_INV_SCALEDDEVCLK_PARAM: + return "Could not scale device clock into range 40MHz to 80Mhz.\n"; + case MYKONOS_ERR_SETRFPLL_INV_VCOINDEX: + return "RFPLL VCO frequency out of range.\n"; + case MYKONOS_ERR_SETRFPLL_INV_REFCLK: + return "Unsupported PLL reference clock or refclk out of range.\n"; + case MYKONOS_ERR_SETORXGAIN_INV_CHANNEL: + return "Invalid ObsRx channel in setObsRxManualGain().\n"; + case MYKONOS_ERR_SETORXGAIN_INV_ORX1GAIN: + return "Invalid gain requested in setObsRxManualGain() for ORX1\n"; + case MYKONOS_ERR_SETORXGAIN_INV_ORX2GAIN: + return "Invalid gain requested in setObsRxManualGain() for ORX2\n"; + case MYKONOS_ERR_SETORXGAIN_INV_SNRXGAIN: + return "Invalid gain requested in setObsRxManualGain() for Sniffer\n"; + case MYKONOS_ERR_GETORX1GAIN_INV_POINTER: + return "Cannot return ORx1 gain to gain control data structure (invalid pointer).\n"; + case MYKONOS_ERR_GETORX2GAIN_INV_POINTER: + return "Cannot return ORx2 gain to gain control data structure (invalid pointer).\n"; + case MYKONOS_ERR_GETSNIFFGAIN_INV_POINTER: + return "Cannot return Sniffer gain to gain control data structure (invalid pointer).\n"; + case MYKONOS_ERR_GETOBSRXGAIN_CH_DISABLED: + return "Cannot read ObsRx gain index. ObsRx Channel is disabled.\n"; + case MYKONOS_ERR_SETTX1ATTEN_INV_PARM: + return "Tx1 attenuation is out of range (0 - 41950 mdB).\n"; + case MYKONOS_ERR_SETTX1ATTEN_INV_STEPSIZE_PARM: + return "Invalid Tx1Atten stepsize. Use enum mykonosTxAttenStepSize_t\n"; + case MYKONOS_ERR_SETTX2ATTEN_INV_PARM: + return "Tx2 attenuation is out of range (0 - 41950 mdB).\n"; + case MYKONOS_ERR_SETTX2ATTEN_INV_STEPSIZE_PARM: + return "Invalid Tx2Atten stepsize. Use enum mykonosTxAttenStepSize_t\n"; + case MYKONOS_ERR_PROGRAMFIR_INV_NUMTAPS_PARM: + return "Invalid number of FIR taps\n"; + case MYKONOS_ERR_READFIR_INV_NUMTAPS_PARM: + return "Invalid number of FIR taps read for the selected Filter\n"; + case MYKONOS_ERR_PROGRAMFIR_INV_FIRNAME_PARM: + return "Invalid FIR filter name requested. use enum mykonosfirName_t\n"; + case MYKONOS_ERR_RXFIR_INV_GAIN_PARM: + return "Rx FIR filter has invalid gain setting\n"; + case MYKONOS_ERR_OBSRXFIR_INV_GAIN_PARM: + return "ObsRx FIR filter A (ORx) has invalid gain setting\n"; + case MYKONOS_ERR_SRXFIR_INV_GAIN_PARM: + return "ObsRx FIR filter B (Sniffer) has invalid gain setting\n"; + case MYKONOS_ERR_TXFIR_INV_GAIN_PARM: + return "Tx FIR filter has invalid gain setting\n"; + case MYKONOS_ERR_READFIR_NULL_PARM: + return "MYKONOS_readFir() has a null *firFilter parameter\n"; + case MYKONOS_ERR_READFIR_COEFS_NULL: + return "MYKONOS_readFir() has a null coef array in *firFilter structure\n"; + case MYKONOS_ERR_READFIR_INV_FIRNAME_PARM: + return "Invalid FIR filter name requested. use enum mykonosfirName_t\n"; + case MYKONOS_ERR_SETRX1GAIN_INV_GAIN_PARM: + return "Rx1 manual gain index out of range of gain table\n"; + case MYKONOS_ERR_SETRX2GAIN_INV_GAIN_PARM: + return "Rx2 manual gain index out of range of gain table\n"; + case MYKONOS_ERR_INITSER_INV_VCODIV_PARM: + return "Found invalid VCO divider value during setupSerializers()\n"; + case MYKONOS_ERR_INITSER_INV_VCODIV1_HSCLK_PARM: + return "CLKPLL VCO frequency exceeded max(8Ghz) in VCO divider /1 case ()\n"; + case MYKONOS_ERR_INITSER_INV_VCODIV1P5_HSCLK_PARM: + return "CLKPLL VCO frequency exceeded max(9.216Ghz) in VCO divider /1.5 case ()\n"; + case MYKONOS_ERR_INITDES_INV_VCODIV_PARM: + return "Found invalid VCO divider value during setupDeserializers()\n"; + case MYKONOS_ERR_SER_INV_M_PARM: + return "Invalid JESD Framer M parameter during setupSerializers()\n"; + case MYKONOS_ERR_SER_INV_L_PARM: + return "Invalid JESD Framer L parameter during setupSerializers()\n"; + case MYKONOS_ERR_SER_INV_LANERATE_PARM: + return "Invalid Lanerate frequency in setupSerializer()\n"; + case MYKONOS_ERR_SER_INV_LANEEN_PARM: + return "Invalid number of JESD204 lanes enabled.\n"; + case MYKONOS_ERR_SER_INV_AMP_PARM: + return "Invalid JESD204 serializer amplitude\n"; + case MYKONOS_ERR_SER_INV_PREEMP_PARM: + return "Invalid JESD204 serializer preemphasis setting\n"; + case MYKONOS_ERR_SER_INV_LANEPN_PARM: + return "Invald JESD204 serializer PN invert setting\n"; + case MYKONOS_ERR_SER_LANE_CONFLICT_PARM: + return "Rx framer and ObsRx framer are attempting to use the same physical lanes\n"; + case MYKONOS_ERR_SER_INV_TXSER_DIV_PARM: + return "Invalid serializer lane clock divider\n"; + case MYKONOS_ERR_SER_LANE_RATE_CONFLICT_PARM: + return "Rx lane and ObsRx lane rate must match\n"; + case MYKONOS_ERR_SER_INV_REAL_IF_DATA_PARM: + return "Framer M can only =1 if Real IF data option is enabled\n"; + case MYKONOS_ERR_HS_AND_LANE_RATE_NOT_INTEGER_MULT: + return "Serializer HSCLK and lane clock are not integer multiples\n"; + case MYKONOS_ERR_DES_HS_AND_LANE_RATE_NOT_INTEGER_MULT: + return "Deserializer HSCLK and lane clock are not integer multiples\n"; + case MYKONOS_ERR_DESER_INV_M_PARM: + return "Invalid deserializer M value. (Valid 2 or 4)\n"; + case MYKONOS_ERR_DESER_INV_L_PARM: + return "Invalid deserializer L value. (Valid 1,2,4)\n"; + case MYKONOS_ERR_DESER_INV_HSCLK_PARM: + return "Invalid HSCLK in setupDeserializer()\n"; + case MYKONOS_ERR_DESER_INV_LANERATE_PARM: + return "Invalid deserializer lane rate\n"; + case MYKONOS_ERR_DESER_INV_LANEEN_PARM: + return "Invalid number of deserializer lanes enabled\n"; + case MYKONOS_ERR_DESER_INV_EQ_PARM: + return "Invalid deserializer EQ setting"; + case MYKONOS_ERR_DESER_INV_LANEPN_PARM: + return "Invalid deserializer invert Lane PN setting\n"; + case MYKONOS_ERR_FRAMER_INV_M_PARM: + return "Invalid Rx framer M setting\n"; + case MYKONOS_ERR_FRAMER_INV_BANKID_PARM: + return "Invalid Rx framer Bank ID\n"; + case MYKONOS_ERR_FRAMER_INV_LANEID_PARM: + return "Invalid Rx framer Lane ID\n"; + case MYKONOS_ERR_FRAMER_INV_K_OFFSET_PARAM: + return "Invalid Rx framer LMFC offset\n"; + case MYKONOS_ERR_FRAMER_INV_REAL_IF_DATA_PARM: + return "Invalid Rx framer Real IF setting\n"; + case MYKONOS_ERR_OBSRX_FRAMER_INV_M_PARM: + return "Invalid ObsRx Framer M value\n"; + case MYKONOS_ERR_OBSRX_FRAMER_INV_BANKID_PARM: + return "Invalid ObsRx Framer Bank ID\n"; + case MYKONOS_ERR_OBSRX_FRAMER_INV_LANEID_PARM: + return "Invalid ObsRx framer Lane ID\n"; + case MYKONOS_ERR_OBSRX_FRAMER_INV_K_OFFSET_PARAM: + return "Invalid ObsRx framer LMFC offset\n"; + case MYKONOS_ERR_OBSRX_FRAMER_INV_REAL_IF_DATA_PARM: + return "Invalid ObsRx framer Real IF setting, M must =1\n"; + case MYKONOS_ERR_DEFRAMER_INV_M_PARM: + return "Invalid Deframer M setting\n"; + case MYKONOS_ERR_DEFRAMER_INV_BANKID_PARM: + return "Invalid Deframer Bank ID\n"; + case MYKONOS_ERR_ERR_DEFRAMER_INV_LANEID_PARM: + return "Invalid Deframer Lane ID\n"; + case MYKONOS_ERR_DEFRAMER_INV_K_OFFSET_PARAM: + return "Invalid Deframer LMFC offset"; + case MYKONOS_ERR_DEFRAMER_INV_K_PARAM: + return "Invalid Deframer K setting\n"; + case MYKONOS_ERR_DEFRAMER_INV_FK_PARAM: + return "Invalid Deframer F*K value\n"; + case MYKONOS_ERR_RX_FRAMER_INV_PRBS_POLYORDER_PARAM: + return "Invalid polyOrder parameter in enableRxFramerPrbs()\n"; + case MYKONOS_ERR_OBSRX_FRAMER_INV_PRBS_POLYORDER_PARAM: + return "Invalid polyOrder parameter in enableObsRxFramerPrbs()\n"; + case MYKONOS_ERR_DEFRAMER_INV_PRBS_ENABLE_PARAM: + return "Invalid enable parameter value in enableDeframerPrbsChecker()\n"; + case MYKONOS_ERR_DEFRAMER_INV_PRBS_POLYORDER_PARAM: + return "Invalid polyOrder parameter in enableDeframerPrbsChecker()\n"; + case MYKONOS_ERR_DEFRAMER_INV_PRBS_CNTR_SEL_PARAM: + return "Invalid lane counter select in readDeframerPrbsCounters()\n"; + case MYKONOS_ERR_INITARM_INV_DATARATE_PARM: + return 0; + case MYKONOS_ERR_INITARM_INV_VCODIV: + return "Invalid ARM VCO divider\n"; + case MYKONOS_ERR_INITARM_INV_REGCLK: + return "Invalid ARM SPI register clock rate\n"; + case MYKONOS_ERR_INITARM_INV_ARMCLK_PARAM: + return "Invalid ARM clock rate\n"; + case MYKONOS_ERR_LOADHEX_INV_CHARCOUNT: + return "LoadHex() char count = 0\n"; + case MYKONOS_ERR_LOADHEX_INVALID_FIRSTCHAR: + return "LoadHex() First char is not :\n"; + case MYKONOS_ERR_LOADHEX_INVALID_CHKSUM: + return "LoadHex() line checksum is invalid\n"; + case MYKONOS_ERR_LOADBIN_INVALID_BYTECOUNT: + return "Invalid byte count passed to function MYKONOS_loadArmFromBinary()"; + case MYKONOS_ERR_LOADARMCON_INVALID_BYTECOUNT: + return "Invalid byte count passed to function MYKONOS_loadArmConcurrent()"; + case MYKONOS_ERR_ARM_INVALID_BUILDCHKSUM: + return "Verify ARM checksum failed\n"; + case MYKONOS_ERR_READARMMEM_INV_ADDR_PARM: + return "ReadArmMem() was given an invalid memory address\n"; + case MYKONOS_ERR_WRITEARMMEM_INV_ADDR_PARM: + return "WriteArmMem() was given an invalid memory address\n"; + case MYKONOS_ERR_ARM_INV_ADDR_PARM: + return "Invalid memory address in MYKONOS_loadArmConcurrent()"; + case MYKONOS_ERR_ARMCMD_INV_OPCODE_PARM: + return "Invalid ARM opcode given to sendArmCommand()\n"; + case MYKONOS_ERR_ARMCMD_INV_NUMBYTES_PARM: + return "Invalid number of extended data in sendArmCommand()\n"; + case MYKONOS_ERR_ARMCMDSTATUS_INV_OPCODE_PARM: + return "Invalid opcode given to waitArmCmdStatus()\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_NULLDEVPOINTER: + return "Pointer to Mykonos device data structure is NULL\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_SPI: + return "Invalid spiSettings pointer in device data structure\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_RX: + return "Invalid device->rx pointer in device data structure\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_RXSUB: + return "Invalid pointer within device->rx data structure\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_RXFIR: + return "Invalid RXFIR pointer in device data structure\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_TX: + return "Invalid device->tx pointer in device data structure\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_TXSUB: + return "Invalid pointer within device->tx data structure\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_TXFIR: + return "Invalid TXFIR pointer in device data structure\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_OBSRX: + return "Invalid device->obsRx pointer in device data structure\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_OBSRXSUB: + return "Invalid pointer within device->obsRx data structure\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_SNIFFERFIR: + return "Invalid Sniffer FIR pointer in device data structure\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_ORXFIR: + return "Invalid ORX FIR pointer in device data structure\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_ORXGAINCTRL: + return "Invalid Orx gain control pointer in device data structure\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_SNIFFERGAINCTRL: + return "Invalid Sniffer gain control pointer in device data structure\n"; + case MYKONOS_ERR_CHECKDEVSTRUCT_OBSRXFRAMER: + return "Invalid obsRx framer pointer in device data structure\n"; + case MYKONOS_ERR_INITSER_INV_PROFILE: + return "Invalid RX profile within device data structure detected in MYKONOS_setupSerializers()\n"; + case MYKONOS_ERR_INITDES_INV_TXPROFILE: + return "Invalid TX profile within device data structure detected in MYKONOS_setupDeserializers()\n"; + case MYKONOS_ERR_JESD204B_ILAS_MISMATCH: + return "Mismatch detected in MYKONOS_jesd204bIlasCheck()\n"; + case MYKONOS_ERR_RXGAINTABLE_INV_CHANNEL: + return "Invalid channel specified in MYKONOS_programRxGainTable()\n"; + case MYKONOS_ERR_RXGAINTABLE_INV_GAIN_INDEX_RANGE: + return "Invalid numGainIndicesinTable greater than possible number of gain indices for channel. \n"; + case MYKONOS_ERR_WRITE_CFG_MEMORY_FAILED: + return "Failed write to ARM memory in MYKONOS_writeArmProfile()\n"; + case MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM: + return "Invalid PCLKDIV parameter detected in MYKONOS_setupSerializers()\n"; + case MYKONOS_ERR_RXFRAMER_INV_FK_PARAM: + return "Invalid FK parameter detected in MYKONOS_setupJesd204bFramer()\n"; + case MYKONOS_ERR_OBSRXFRAMER_INV_FK_PARAM: + return "Invalid FK paramter detected in MYKONOS_setupJesd204bObsRxFramer()\n"; + case MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM: + return "Invalid PCLKDIV paramter detected in MYKONOS_setupSerializers()\n"; + case MYKONOS_ERR_PU_OBSRXPATH_INV_LOSOURCE_PARAM: + return "Invalid LO Source for OBSRX data path \n"; + case MYKONOS_ERR_ARM_RADIOON_FAILED: + return "ARM command to move to radioOn state failed. \n"; + case MYKONOS_ERR_ARM_RADIOOFF_FAILED: + return "ARM command to move to radioOff state failed. \n"; + case MYKONOS_ERR_INV_RX_GAIN_MODE_PARM: + return "Invalid gain control mode detected in MYKONOS_setRxGainControlMode()\n"; + case MYKONOS_ERR_INV_ORX_GAIN_MODE_PARM: + return "Invalid gain control mode detected in MYKONOS_setObsRxGainControlMode()\n"; + case MYKONOS_ERR_INV_AGC_RX_STRUCT_INIT: + return "Invalid RX AGC structure detected at &device->rx->rxAgcCtrl in MYKONOS_setupRxAgc()\n"; + case MYKONOS_ERR_INV_AGC_RX_PEAK_WAIT_TIME_PARM: + return "device->rx->rxAgcCtrl->agcPeakWaitTime out of range in MYKONOS_setupRxAgc()\n"; + case MYKONOS_ERR_INV_AGC_RX_GAIN_UPDATE_TIME_PARM: + return "device->rx->rxAgcCtrl->agcGainUpdateTime_us out of range in MYKONOS_setupRxAgc()\n"; + case MYKONOS_ERR_INV_AGC_RX_APD_HIGH_THRESH_PARM: + return "device->rx->rxAgcCtrl->apdHighThresh out of range in MYKONOS_setupRxAgc()\n"; + case MYKONOS_ERR_INV_AGC_RX_APD_LOW_THRESH_PARM: + return "device->rx->rxAgcCtrl->apdLowThresh out of range in MYKONOS_setupRxAgc()\n"; + case MYKONOS_ERR_INV_AGC_RX_BLOCK_DET_DECAY_PARM: + return "device->rx->rxAgcCtrl->apdDecay out of range in MYKONOS_setupRxAgc()\n"; + case MYKONOS_ERR_INV_AGC_RX_PEAK_STRUCT_INIT: + return "Data structure for peakAgc not initialized when used in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_PWR_STRUCT_INIT: + return "Data structure for powerAgc not initialized when used in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX1_MAX_GAIN_INDEX: + return "device->rx->rxAgcCtrl->agcRx1MaxGainIndex out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX1_MIN_GAIN_INDEX: + return "device->rx->rxAgcCtrl->agcRx1MinGainIndex out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX2_MAX_GAIN_INDEX: + return "device->rx->rxAgcCtrl->agcRx2MaxGainIndex out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX2_MIN_GAIN_INDEX: + return "device->rx->rxAgcCtrl->agcRx2MinGainIndex out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_SLOW_LOOP_SETTLING_DELAY: + return "device->rx->rxAgcCtrl->agcSlowLoopSettlingDelay out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_PMD_MEAS_DURATION: + return "device->rx->rxAgcCtrl->powerAgc->pmdMeasDuration out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_PMD_MEAS_CONFIG: + return "device->rx->rxAgcCtrl->powerAgc->pmdMeasConfig out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_LOW_THS_PREV_GAIN_INC: + return "device->rx->rxAgcCtrl->agcLowThsPreventGainIncrease out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_PEAK_THRESH_MODE: + return "device->rx->rxAgcCtrl->agcPeakThresholdMode out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_RESET_ON_RX_ENABLE: + return "device->rx->rxAgcCtrl->agcResetOnRxEnable out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_ENABLE_SYNC_PULSE_GAIN_COUNTER: + return "device->rx->rxAgcCtrl->agcEnableSyncPulseForGainCounter out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_HIGH_THRESH: + return "device->rx->rxAgcCtrl->powerAgc->pmdLowerHighThresh out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_THRESH: + return "device->rx->rxAgcCtrl->powerAgc->pmdUpperLowThresh out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_THRESH: + return "device->rx->rxAgcCtrl->powerAgc->pmdLowerLowThresh out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_THRESH: + return "device->rx->rxAgcCtrl->powerAgc->pmdUpperHighThresh out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_GAIN_STEP: + return "device->rx->rxAgcCtrl->powerAgc->pmdUpperHighGainStepAttack out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_GAIN_STEP: + return "device->rx->rxAgcCtrl->powerAgc->pmdLowerLowGainStepRecovery out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_HIGH_GAIN_STEP: + return "device->rx->rxAgcCtrl->powerAgc->pmdLowerHighGainStepRecovery out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_GAIN_STEP: + return "device->rx->rxAgcCtrl->powerAgc->pmdUpperLowGainStepAttack out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_PKDET_FAST_ATTACK_VALUE: + return "device->rx->rxAgcCtrl->peakAgc->apdFastAttack or hb2FastAttack out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_THRESH_PARM: + return "device->rx->rxAgcCtrl->peakAgc->hb2HighThresh out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_HB2_LOW_THRESH_PARM: + return "device->rx->rxAgcCtrl->peakAgc->hb2LowThresh out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_THRESH_PARM: + return "device->rx->rxAgcCtrl->peakAgc->hb2VeryLowThresh out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_APD_HIGH_GAIN_STEP_PARM: + return "device->rx->rxAgcCtrl->peakAgc->apdHighGainStepAttack out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_APD_LOW_GAIN_STEP_PARM: + return "device->rx->rxAgcCtrl->peakAgc->apdLowGainStepRecovery out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_GAIN_STEP_PARM: + return "device->rx->rxAgcCtrl->peakAgc->hb2HighGainStepAttack out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_HB2_LOW_GAIN_STEP_PARM: + return "device->rx->rxAgcCtrl->peakAgc->hb2LowGainStepRecovery out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_GAIN_STEP_PARM: + return "device->rx->rxAgcCtrl->peakAgc->hb2VeryLowGainStepRecovery out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_ENABLE: + return "device->rx->rxAgcCtrl->peakAgc->hb2OverloadEnable out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_THRESH_CNT: + return "device->rx->rxAgcCtrl->peakAgc->hb2OverloadThreshCnt out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_DUR_CNT: + return "device->rx->rxAgcCtrl->peakAgc->hb2OverloadDurationCnt out of range in MYKONOS_setupRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_STRUCT_INIT: + return "Invalid OBSRX AGC structure detected at &device->obsRx->orxAgcCtrl in MYKONOS_setupObsRxAgc()\n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PEAK_STRUCT_INIT: + return "Data structure for obsRx->orxAgcCtrl->peakAgc not initialized when used in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PWR_STRUCT_INIT: + return "Data structure for obsRx->orxAgcCtrl->powerAgc not initialized when used in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_MAX_GAIN_INDEX: + return "device->obsRx->orxAgcCtrl->agcObsRxMaxGainIndex out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_MIN_GAIN_INDEX: + return "device->obsRx->orxAgcCtrl->agcObsRxMinGainIndex out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_SELECT: + return "device->obsRx->orxAgcCtrl->agcObsRxSelect out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_GAIN_UPDATE_TIME_PARM: + return "device->obsRx->orxAgcCtrl->agcGainUpdateTime_us out of range in MYKONOS_setupObsRxAgc()\n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PEAK_WAIT_TIME_PARM: + return "device->obsRx->orxAgcCtrl->agcPeakWaitTime out of range in MYKONOS_setupObsRxAgc()\n"; + case MYKONOS_ERR_INV_AGC_OBSRX_SLOW_LOOP_SETTLING_DELAY: + return "device->obsRx->orxAgcCtrl->agcSlowLoopSettlingDelay out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_DURATION: + return "device->obsRx->orxAgcCtrl->powerAgc->pmdMeasDuration out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_CONFIG: + return "device->obsRx->orxAgcCtrl->powerAgc->pmdMeasConfig out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_LOW_THS_PREV_GAIN_INC: + return "device->obsRx->orxAgcCtrl->agcLowThsPreventGainIncrease out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PEAK_THRESH_MODE: + return "device->obsRx->orxAgcCtrl->agcPeakThresholdMode out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_RESET_ON_RX_ENABLE: + return "device->obsRx->orxAgcCtrl->agcResetOnRxEnable out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_ENABLE_SYNC_PULSE_GAIN_COUNTER: + return "device->obsRx->orxAgcCtrl->agcEnableSyncPulseForGainCounter out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_THRESH: + return "device->obsRx->orxAgcCtrl->powerAgc->pmdLowerHighThresh out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_THRESH: + return "device->obsRx->orxAgcCtrl->powerAgc->pmdUpperLowThresh out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_THRESH: + return "device->obsRx->orxAgcCtrl->powerAgc->pmdLowerLowThresh out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_THRESH: + return "device->obsRx->orxAgcCtrl->powerAgc->pmdUpperHighThresh out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_GAIN_STEP: + return "device->obsRx->orxAgcCtrl->powerAgc->pmdUpperHighGainStepAttack out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_GAIN_STEP: + return "device->obsRx->orxAgcCtrl->powerAgc->pmdLowerLowGainStepRecovery out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_GAIN_STEP: + return "device->obsRx->orxAgcCtrl->powerAgc->pmdUpperLowGainStepAttack out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PKDET_FAST_ATTACK_VALUE: + return "device->obsRx->orxAgcCtrl->peakAgc->apdFastAttack or hb2FastAttack out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_THRESH_PARM: + return "device->obsRx->orxAgcCtrl->apdHighThresh out of range in MYKONOS_setupObsRxAgc()\n"; + case MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_THRESH_PARM: + return "device->obsRx->orxAgcCtrl->apdLowThresh out of range in MYKONOS_setupObsRxAgc()\n"; + case MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_THRESH_PARM: + return "device->obsRx->orxAgcCtrl->peakAgc->hb2HighThresh out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_THRESH_PARM: + return "device->obsRx->orxAgcCtrl->peakAgc->hb2LowThresh out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_THRESH_PARM: + return "device->obsRx->orxAgcCtrl->peakAgc->hb2VeryLowThresh out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_GAIN_STEP_PARM: + return "device->obsRx->orxAgcCtrl->peakAgc->apdHighGainStepAttack out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_GAIN_STEP_PARM: + return "device->obsRx->orxAgcCtrl->peakAgc->apdLowGainStepRecovery out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_GAIN_STEP_PARM: + return "device->obsRx->orxAgcCtrl->peakAgc->hb2HighGainStepAttack out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_GAIN_STEP_PARM: + return "device->obsRx->orxAgcCtrl->peakAgc->hb2LowGainStepRecovery out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_GAIN_STEP_PARM: + return "device->obsRx->orxAgcCtrl->peakAgc->hb2VeryLowGainStepRecovery out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_ENABLE: + return "device->obsRx->orxAgcCtrl->peakAgc->hb2OverloadEnable out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_DUR_CNT: + return "device->obsRx->orxAgcCtrl->peakAgc->hb2OverloadDurationCnt out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_THRESH_CNT: + return "device->obsRx->orxAgcCtrl->peakAgc->hb2OverloadThresholdCnt out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_GAIN_STEP: + return "device->obsRx->orxAgcCtrl->powerAgc->pmdLowerHighGainStepRecovery out of range in MYKONOS_setupObsRxAgc() \n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_CALPLL_LOCK: + return "CAL PLL Lock event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_CLKPLLCP: + return "Clock PLL Charge Pump Cal event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_CLKPLL_LOCK: + return "Clock PLL Lock event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RXPLLCP: + return "RX PLL Charge Pump Cal event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RXPLL_LOCK: + return "RX PLL Lock event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_TXPLLCP: + return "TX PLL Charge Pump Cal event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_TXPLL_LOCK: + return "TX PLL Lock event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_SNIFFPLLCP: + return "Sniffer PLL Charge Pump Cal event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_SNIFFPLL_LOCK: + return "Sniffer PLL Lock event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RXBBFCALDONE: + return "RX Baseband Filter Cal event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_TXBBFCALDONE: + return "TX Baseband Filter Cal timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RFDCCALDONE: + return "RF DC Offset Cal event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_ADCTUNECALDONE: + return "ADC Tuner Cal event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RX1ADCPROFILE: + return "Rx1 ADC Profile Loading event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RX2ADCPROFILE: + return "Rx2 ADC Profile Loading event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_ORXADCPROFILE: + return "ObsRx ADC Profile Loading event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RCALDONE: + return "Resistor Cal event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_ARMBUSY: + return "ARM Busy event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_INITARMDONE: + return "Initialize ARM event timed out in MYKONOS_waitForEvent()\n"; + case MYKONOS_ERR_TIMEDOUT_ARMMAILBOXBUSY: + return "ARM Mailbox Busy. Command not executed in MYKONOS_sendArmCommand()\n"; + case MYKONOS_ERR_PU_OBSRXPATH_ARMERROR: + return "ARM Command Error in MYKONOS_setObsRxPathSource()\n"; + case MYKONOS_ERR_EN_TRACKING_CALS_ARMSTATE_ERROR: + return "Device not in radioOff/IDLE state. Error in MYKONOS_enableTrackingCals()\n"; + case MYKONOS_ERR_SET_RADIOCTRL_PINS_ARMERROR: + return "ARM command Error in MYKONOS_setRadioControlPinMode()\n"; + case MYKONOS_ERR_EN_TRACKING_CALS_ARMERROR: + return "ARM Command Error in MYKONOS_enableTrackingCals()\n"; + case MYKONOS_ERR_SETRFPLL_ARMERROR: + return "ARM Command Error in MYKONOS_setRfPllFrequency()\n"; + case MYKONOS_ERR_INIT_INV_TXINPUTHB_PARM: + return "device->tx->txProfile->txInputHbInterpolation out of range in MYKONOS_initialize(): valid = 1,2 or 4\n"; + case MYKONOS_ERR_LOAD_ADCPROFILE_INV_VCODIV: + return "device->clocks->clkPllVcoDiv value not supported in MYKONOS_loadAdcProfiles\n"; + case MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_RXREQUIRED: + return "Custom RX ADC Profile required\n"; + case MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_ORXREQUIRED: + return "Custom ORX ADC Profile required\n"; + case MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_SNRXREQUIRED: + return "Custom SNRX ADC Profile required\n"; + case MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_LBREQUIRED: + return "Custom Loopback ADC profile required\n"; + case MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED: + return "WriteArmMemory call failed while writing the Loopback ADC profile into ARM memory\n"; + case MYKONOS_ERR_LOAD_SNRXADCPROFILE_ARMMEM_FAILED: + return "WriteArmMemory call failed while writing the Sniffer ADC profile into ARM memory\n"; + case MYKONOS_ERR_LOAD_ORXADCPROFILE_ARMMEM_FAILED: + return "WriteArmMemory call failed while writing the ObsRx ADC profile into ARM memory\n"; + case MYKONOS_ERR_LOAD_RXADCPROFILE_ARMMEM_FAILED: + return "WriteArmMemory call failed while writing the RX ADC profile into ARM memory\n"; + case MYKONOS_ERR_LOAD_ADCPROFILE_SNRX_ADCDIV_ZERO: + return "SnRx profile has invalid ADC divider of 0, causing a divide by zero\n"; + case MYKONOS_ERR_LOAD_ADCPROFILE_ORXADCDIV_ZERO: + return "ORx profile has invalid ADC divider of 0, causing a divide by zero\n"; + case MYKONOS_ERR_LOAD_ADCPROFILE_RXADCDIV_ZERO: + return "Rx profile has invalid ADC divider of 0, causing a divide by zero\n"; + case MYKONOS_ERR_LOAD_ADCPROFILE_MISSING_ORX_PROFILE: + return "If Tx Profile is valid, a matching ORx profile must be provided to set ADC divider and digital filtering for loopback calibrations\n"; + case MYKONOS_ERR_SETUP_PA_PROT_INV_AVG_DURATION: + return "Invalid setting for avgDuration in MYKONOS_setupPaProtection(...)\n"; + case MYKONOS_ERR_SETUP_PA_PROT_INV_ATTEN_STEP: + return "Invalid setting for attenStepSize in MYKONOS_setupPaProtection(...)\n"; + case MYKONOS_ERR_SETUP_PA_PROT_INV_ATTEN_ENABLE: + return "Invalid setting for txAttenControlEnable in MYKONOS_setupPaProtection(...)\n"; + case MYKONOS_ERR_SETUP_PA_PROT_INV_POWER_THRESH: + return "Invalid setting for powerThreshold in MYKONOS_setupPaProtection(...)\n"; + case MYKONOS_ERR_SETUP_PA_PROT_INV_TX_CHANNEL: + return "Invalid TX channel selected for MYKONOS_getDacPower(...)\n"; + case MYKONOS_ERR_GET_DAC_PWR_INV_POINTER: + return "Cannot return DAC Power information (invalid pointer)\n"; + case MYKONOS_ERR_GET_PA_FLAG_STATUS_INV_POINTER: + return "Cannot return PA Protection Flag Status information (invalid pointer)\n"; + case MYKONOS_ERR_GET_OBSRX_OVERLOADS_NULL_PARM: + return "MYKONOS_getObsRxPathOverloads() has null *obsRxOverloads parameter\n"; + case MYKONOS_ERR_GET_RX1_OVERLOADS_NULL_PARM: + return "MYKONOS_getRxPathOverloads() has null *rx1Overloads parameter\n"; + case MYKONOS_ERR_GET_RX2_OVERLOADS_NULL_PARM: + return "MYKONOS_getRxPathOverloads() has null *rx2Overloads parameter\n"; + case MYKONOS_ERR_GETRADIOSTATE_NULL_PARAM: + return "MYKONOS_getRadioState() has null *radioStatus parameter\n"; + case MYKONOS_ERR_ABORT_INITCALS_NULL_PARAM: + return "MYKONOS_abortInitCals() has null *calsCompleted parameter\n"; + case MYKONOS_ERR_WAIT_INITCALS_ARMERROR: + return "MYKONOS_waitInitCals() returned an ARM error\n"; + case MYKONOS_ERR_WAIT_INITCALS_NULL_PARAM: + return "MYKONOS_waitInitCals() has one or more null parameters\n"; + case MYKONOS_ERR_CHECK_PLL_LOCK_NULL_PARM: + return "MYKONOS_checkPllsLockStatus() has a null *pllLockStatus parameter\n"; + case MYKONOS_ERR_GET_TXFILTEROVRG_NULL_PARM: + return "MYKONOS_getTxFilterOverRangeStatus() has a null *txFilterStatus parameter\n"; + case MYKONOS_ERR_PROGRAM_RXGAIN_TABLE_NULL_PARM: + return "MYKONOS_programRxGainTable() has a null *gainTablePtr parameter\n"; + case MYKONOS_ERR_PROGRAMFIR_NULL_PARM: + return "MYKONOS_programFir() has a null *firFilter parameter\n"; + case MYKONOS_ERR_PROGRAMFIR_COEFS_NULL: + return "MYKONOS_programFir() has a null coef array in *firFilter structure\n"; + case MYKONOS_ERR_READ_DEFRAMERSTATUS_NULL_PARAM: + return "MYKONOS_readDeframerStatus() has a null *deframerStatus parameter\n"; + case MYKONOS_ERR_READ_DEFRAMERPRBS_NULL_PARAM: + return "MYKONOS_readDeframerPrbscounters() has a null *prbsErrorCount parameter\n"; + case MYKONOS_ERR_READ_ORXFRAMERSTATUS_NULL_PARAM: + return "MYKONOS_readOrxFramerStatus() has a null *obsFramerStatus parameter\n"; + case MYKONOS_ERR_READ_RXFRAMERSTATUS_NULL_PARAM: + return "MYKONOS_readRxFramerStatus() has a null *framerStatus parameter\n"; + case MYKONOS_ERR_ARMCMDSTATUS_NULL_PARM: + return "MYKONOS_waitArmCmdStatus() has a null *cmdStatByte parameter\n"; + case MYKONOS_ERR_READARMCMDSTATUS_NULL_PARM: + return "MYKONOS_readArmCmdStatus() has one or more null pointer parameters\n"; + case MYKONOS_ERR_READARMCMDSTATUS_INV_OPCODE_PARM: + return "MYKONOS_readArmCmdStatusByte() has an invalid opcode parameter\n"; + case MYKONOS_ERR_READARMCMDSTATUSBYTE_NULL_PARM: + return "MYKONOS_readArmCmdStatusByte() has a null *cmdStatByte parameter\n"; + case MYKONOS_ERR_ARMCMD_NULL_PARM: + return "MYKONOS_sendArmCommand() has a null *extendedData parameter\n"; + case MYKONOS_ERR_WRITEARMMEM_NULL_PARM: + return "MYKONOS_writeArmMem() has a null *data parameter\n"; + case MYKONOS_ERR_LOADBIN_NULL_PARAM: + return "MYKONOS_loadArmFromBinary() has a null *binary parameter\n"; + case MYKONOS_ERR_LOADARMCON_NULL_PARAM: + return "MYKONOS_loadArmConcurrent() has a null *binary parameter\n"; + case MYKONOS_ERR_GETTX1ATTEN_NULL_PARM: + return "MYKONOS_getTx1Attenuation() has NULL tx1Attenuation_mdB parameter\n"; + case MYKONOS_ERR_GETTX2ATTEN_NULL_PARM: + return "MYKONOS_getTx2Attenuation() has NULL tx2Attenuation_mdB parameter\n"; + case MYKONOS_ERR_ENFRAMERLINK_INV_LANESEN_PARM: + return "Invalid serializer Lanes Enable parameter in Rx framer structure\n"; + case MYKONOS_ERR_ENOBSFRAMERLINK_INV_LANESEN_PARM: + return "Invalid serializer Lanes Enable parameter in ObsRx framer structure\n"; + case MYKONOS_ERR_ENTXNCO_TXPROFILE_INVALID: + return "Can not enable Tx NCO when Tx Profile is invalid\n"; + case MYKONOS_ERR_ENTXNCO_TX1_FREQ_INVALID: + return "Invalid Tx1 NCO frequency\n"; + case MYKONOS_ERR_ENTXNCO_TX2_FREQ_INVALID: + return "Invalid Tx2 NCO frequency\n"; + case MYKONOS_ERR_JESD204B_ILAS_MISMATCH_NULLPARAM: + return "Function parameter has NULL pointer in MYKONOS_jesd204bIlasCheck()\n"; + case MYKONOS_ERR_GET_PLLFREQ_INV_REFCLKDIV: + return "CLKPLL refclk divider was read back as an invalid setting in MYKONOS_getRfPllFrequency()\n"; + case MYKONOS_ERR_GET_PLLFREQ_INV_HSDIV: + return "CLKPLL HSDIV divider was read back as an invalid setting in MYKONOS_getRfPllFrequency()\n"; + case MYKONOS_ERR_GET_PLLFREQ_INV_VCODIV: + return "CLKPLL VCODIV divider was read back as an invalid setting in MYKONOS_getRfPllFrequency()\n"; + case MYKONOS_ERR_GET_RX1_DEC_POWER_NULL_PARM: + return "MYKONOS_getRx1DecPower() has a null *rx1DecPower_mdBFS parameter\n"; + case MYKONOS_ERR_GET_RX1_DEC_POWER_NUM_SAMPLES: + return "MYKONOS_getRx1DecPower() numSamples greater than agcGainUpdateCounter\n"; + case MYKONOS_ERR_GET_RX2_DEC_POWER_NULL_PARM: + return "MYKONOS_getRx2DecPower() has a null *rx2DecPower_mdBFS parameter\n"; + case MYKONOS_ERR_GET_RX2_DEC_POWER_NUM_SAMPLES: + return "MYKONOS_getRx2DecPower() numSamples greater than agcGainUpdateCounter\n"; + case MYKONOS_ERR_GET_OBSRX_DEC_POWER_NULL_PARM: + return "MYKONOS_getObsRxDecPower() has a null *obsRxDecPower_mdBFS parameter\n"; + case MYKONOS_ERR_GET_OBSRX_DEC_POWER_NUM_SAMPLES: + return "MYKONOS_getObsRxDecPower() numSamples greater than agcGainUpdateCounter\n"; + case MYKONOS_ERR_GETARMVER_NULL_PARM: + return "MYKONOS_getArmVersion() has a NULL pointer in one of the function parameters\n"; + case MYKONOS_ERR_EN_DPDTRACKING_ARMSTATE_ERROR: + return "ARM is not in the RadioOff state before MYKONOS_enableDpdTracking(), call MYKONOS_radioOff()\n"; + case MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE: + return "MYKONOS_restoreDpdModel() supplied DPD Model Data Buffer is incorrect size\n"; + case MYKONOS_ERR_RESTDPDMOD_ARMERRFLAG: + return "The ARM reported a error while in MYKONOS_restoreDpdModel().\n"; + case MYKONOS_ERR_RESTDPDMOD_INVALID_TXCHANNEL: + return "MYKONOS_restoreDpdModel() invalid txChannel specified\n"; + case MYKONOS_ERR_SAVDPDMOD_WRONGBUFFERSIZE: + return "MYKONOS_saveDpdModel() supplied DPD Model Data Buffer is incorrect size\n"; + case MYKONOS_ERR_SAVDPDMOD_ARMSTATE: + return "ARM is not in the RadioOff state before MYKONOS_saveDpdModel(), call MYKONOS_radioOff()\n"; + case MYKONOS_ERR_SAVDPDMOD_INVALID_TXCHANNEL: + return "MYKONOS_saveDpdModel() invalid txChannel specified\n"; + case MYKONOS_ERR_EN_CLGCTRACKING_ARMSTATE_ERROR: + return "ARM is not in the RadioOff state before MYKONOS_enableClgcTracking(), call MYKONOS_radioOff()\n"; + case MYKONOS_ERR_CFGDPD_TXORX_PROFILE_INV: + return "Tx or ORx profile is not valid, both are necessary for DPD features in MYKONOS_configDpd()\n"; + case MYKONOS_ERR_CFGDPD_NULL_DPDCFGSTRUCT: + return "device->tx->dpdConfig structure has NULL pointer in MYKONOS_configDpd()\n"; + case MYKONOS_ERR_WRITEARMCFG_ARMERRFLAG: + return "The ARM reported a error while writing to an ARM config structure in MYKONOS_writeArmCfgStruct()\n"; + case MYKONOS_ERR_CFGDPD_INV_DPDDAMPING: + return "ERROR: device->tx->dpdConfig->damping parameter is out of range (0-15)\n"; + case MYKONOS_ERR_CFGDPD_INV_DPDSAMPLES: + return "ERROR: device->tx->dpdConfig->samples parameter is out of range (64 - 32768)\n"; + case MYKONOS_ERR_CFGDPD_INV_NUMWEIGHTS: + return "ERROR: device->tx->dpdConfig->numWeights parameter is out of range (0-3)\n"; + case MYKONOS_ERR_CFGDPD_INV_DPDOUTLIERTHRESH: + return "ERROR: device->tx->dpdConfig->outlierThreshold parameter is out of range\n"; + case MYKONOS_ERR_CFGDPD_INV_DPDPRIORWEIGHT: + return "ERROR: device->tx->dpdConfig->modelPriorWeight parameter is out of range (Valid 0-32)\n"; + case MYKONOS_ERR_CFGCLGC_INV_DESIREDGAIN: + return "ERROR: device->tx->clgcConfig->tx1DesiredGain or tx2DesiredGain parameter is out of range\n"; + case MYKONOS_ERR_CFGCLGC_INV_TXATTENLIMIT: + return "ERROR: device->tx->clgcConfig->tx1AttenLimit or tx2AttenLimit parameter is out of range\n"; + case MYKONOS_ERR_CFGCLGC_INV_CLGC_CTRLRATIO: + return "ERROR: device->tx->clgcConfig->tx1ControlRatio or tx2ControlRatio parameter is out of range\n"; + case MYKONOS_ERR_CFGDPD_INV_DPD_ADDDELAY: + return "ERROR: device->tx->dpdConfig->additionalDelayOffset parameter is out of range\n"; + case MYKONOS_ERR_CFGDPD_INV_PNSEQLEVEL: + return "ERROR: device->tx->dpdConfig->pathDelayPnSeqLevel parameter is out of range\n"; + case MYKONOS_ERR_CFGDPD_INV_MODELVERSION: + return "ERROR: device->tx->dpdConfig->modelVersion parameter is out of range\n"; + case MYKONOS_ERR_READARMCFG_ARMERRFLAG: + return "ERROR: MYKONOS_readArmConfig failed due to an ARM error\n"; + case MYKONOS_ERR_GETPENDTRKCALS_NULL_PARAM: + return "MYKONOS_getPendingTrackingCals() has NULL function parameter\n"; + case MYKONOS_ERR_ARMCMDSTATUS_ARMERROR: + return "MYKONOS_waitArmCmdStatus() exited due to ARM error for the desired ARM opcode\n"; + case MYKONOS_ERR_WAITARMCMDSTATUS_TIMEOUT: + return "MYKONOS_waitArmCmdStatus() timed out waiting for the ARM to complete the requested command\n"; + case MYKONOS_ERR_PU_GETOBSRXPATH_ARMERROR: + return "ARM returned an error while trying to get the ObsRx Path source in MYKONOS_getObsRxPathSource()\n"; + case MYKONOS_ERR_GETDPDCFG_NULL_DPDCFGSTRUCT: + return "MYKONOS_getDpdConfig() could not complete due to a NULL pointer to device->tx->dpdConfig structure\n"; + case MYKONOS_ERR_GETDPDCFG_TXORX_PROFILE_INV: + return "The Tx and ORx profiles must be valid for DPD related functions\n"; + case MYKONOS_ERR_GETDPDSTATUS_ARMERRFLAG: + return "MYKONOS_getDpdStatus() reported an ARM error with the ARM Get command\n"; + case MYKONOS_ERR_GETDPDSTATUS_NULLPARAM: + return "MYKONOS_getDpdStatus() has NULL pointer in the function parameter\n"; + case MYKONOS_ERR_SETDEFOBSRXPATH_NULL_OBSRX_STRUCT: + return "Observation profile not valid, device->obsRx structure is NULL in MYKONOS_setDefaultObsRxPath()\n"; + case MYKONOS_ERR_GETCLGCSTATUS_NULLPARAM: + return "MYKONOS_getClgcStatus() has NULL clgcStatus parameter\n"; + case MYKONOS_ERR_GETCLGCSTATUS_ARMERRFLAG: + return "ARM reported an error with the ARM GET command during MYKONOS_getClgcStatus()\n"; + case MYKONOS_ERR_READ_DEFFIFODEPTH_NULL_PARAM: + return "MYKONOS_getDeframerFifoDepth() function parameter fifoDepth is a NULL pointer\n"; + case MYKONOS_ERR_READ_DEFFIFODEPTH_LMFCCOUNT_NULL_PARAM: + return "MYKONOS_getDeframerFifoDepth() function parameter readEnLmfcCount is a NULL pointer\n"; + case MYKONOS_ERR_GETDPDSTATUS_INV_CH: + return "MYKONOS_getDpdStatus() txChannel parameter is not valid (TX1 and TX2 are the only valid options)\n"; + case MYKONOS_ERR_GETCLGCSTATUS_INV_CH: + return "MYKONOS_getClgcStatus() txChannel parameter is not valid (TX1 and TX2 are the only valid options)\n"; + case MYKONOS_ERR_INIT_INV_TXINPUTHB_INV_RATE: + return "Invalid Tx profile: When using Tx Input halfband, IQ rate must not exceed 160MSPS\n"; + case MYKONOS_ERR_INIT_INV_TXINPUTHB0_INV_RATE: + return "Invalid Tx profile: When using Tx Input halfband 0, IQ rate must not exceed 80MSPS\n"; + case MYKONOS_ERR_RXFIR_TAPSEXCEEDED: + return "Rx PFIR can not be clocked fast enough to handle the number of FIR coefficents provided\n"; + case MYKONOS_ERR_ORXFIR_TAPSEXCEEDED: + return "ORx PFIR can not be clocked fast enough to handle the number of FIR coefficents provided\n"; + case MYKONOS_ERR_SNRXFIR_TAPSEXCEEDED: + return "Sniffer Rx PFIR can not be clocked fast enough to handle the number of FIR coefficents provided\n"; + case MYKONOS_ERR_TXFIR_INV_NUMTAPS_PARM: + return "Invalid number of Tx FIR coefficients\n"; + case MYKONOS_ERR_TXFIR_INV_NUMROWS: + return "Invalid number of PFIR coefficient rows\n"; + case MYKONOS_ERR_TXFIR_TAPSEXCEEDED: + return "Too many Tx PFIR taps for the IQ sample rate. FIR processing clock can not run fast enough to handle the number of taps\n"; + case MYKONOS_ERR_GETINITCALSTATUS_NULL_PARAM: + return "MYKONOS_getInitCalStatus() has a null pointer in parameter list\n"; + case MYKONOS_ERR_GETINITCALSTATUS_ARMERROR: + return "MYKONOS_getInitCalStatus() returned an ARM error while getting the init cal status information"; + case MYKONOS_ERR_CFGCLGC_TXORX_PROFILE_INV: + return "Tx and ObsRx profiles must be valid to use the CLGC feature in MYKONOS_configClgc()\n"; + case MYKONOS_ERR_CFGCLGC_NULL_CLGCCFGSTRUCT: + return "CLGC config structure is NULL in device->tx->clgcConfig in MYKONOS_configClgc()\n"; + case MYKONOS_ERR_GETCLGCCFG_TXORX_PROFILE_INV: + return "Could not read back CLGC status because Tx and ORx profiles are not valid\n"; + case MYKONOS_ERR_GETCLGCCFG_NULL_CFGSTRUCT: + return "Could not read back CLGC status because return structure device->tx->clgcConfig pointer is NULL\n"; + case MYKONOS_ERR_CALCDIGCLK_NULLDEV_PARAM: + return "device structure pointer is NULL in MYKONOS_calculateDigitalClocks()\n"; + case MYKONOS_ERR_CALCDIGCLK_NULL_CLKSTRUCT: + return "device->clocks structure pointer is NULL in MYKONOS_calculateDigitalClocks()\n"; + case MYKONOS_ERR_NULL_DEVICE_PARAM: + return "The device pointer in the calling function's parameter list is a NULL pointer\n"; + case MYKONOS_ERR_CALCDEVCLK_NULLPARAM: + return "MYKONOS_calculateScaledDeviceClk_kHz() has a NULL pointer in one of the function parameters\n"; + case MYKONOS_ERR_CFGCLGC_INV_CLGC_ADDDELAY: + return "CLGC Additional Delay parameter is out of range in MYKONOS_configClgc\n"; + case MYKONOS_ERR_CFGCLGC_INV_PNSEQLEVEL: + return "CLGC PN Sequence level parameter is out of range in MYKONOS_configClgc\n"; + case MYKONOS_ERR_CFGVSWR_TXORX_PROFILE_INV: + return "The Tx and ORx profiles must be valid to use the VSWR feature in MYKONOS_configVswr()\n"; + case MYKONOS_ERR_CFGVSWR_ARMSTATE_ERROR: + return "ARM must be in radioOff state to configure the VSWR config parameters in MYKONOS_configVswr()\n"; + case MYKONOS_ERR_CFGVSWR_INV_3P3GPIOPIN: + return "VSWR 3.3v GPIO pin selection is out of range (0-11) in MYKONOS_configVswr()\n"; + case MYKONOS_ERR_CFGVSWR_INV_PNSEQLEVEL: + return "VSWR init PN sequence level is out of range in MYKONOS_configVswr()\n"; + case MYKONOS_ERR_CFGVSWR_INV_VSWR_ADDDELAY: + return "VSWR additionalDelay member is out of range in MYKONOS_configVswr()\n"; + case MYKONOS_ERR_CFGVSWR_NULL_VSWRCFGSTRUCT: + return "device->tx->vswrConfig pointer is null in MYKONOS_confgiVswr()\n"; + case MYKONOS_ERR_GETVSWRCFG_NULL_CFGSTRUCT: + return "device->tx->vswrConfig pointer is null in MYKONOS_getVswrConfig()\n"; + case MYKONOS_ERR_GETVSWRCFG_TXORX_PROFILE_INV: + return "Tx and ORx profiles must be valid in MYKONOS_getVswrConfig()\n"; + case MYKONOS_ERR_GETVSWRSTATUS_ARMERRFLAG: + return "ARM returned an error while attempting to read the VSWR status structure\n"; + case MYKONOS_ERR_GETVSWRSTATUS_INV_CH: + return "Invalid Tx channel parameter passed to MYKONOS_getVswrStatus()\n"; + case MYKONOS_ERR_GETVSWRSTATUS_NULLPARAM: + return "vswrStatus function parameter is null in MYKONOS_getVswrStatus\n"; + case MYKONOS_ERR_SET_RX_MAX_GAIN_INDEX: + return "Max gain index bigger than max gain index loaded table in MYKONOS_setRxAgcMinMaxGainIndex().\n"; + case MYKONOS_ERR_SET_RX_MIN_GAIN_INDEX: + return "Min gain index lower than min gain index loaded table in MYKONOS_setRxAgcMinMaxGainIndex().\n"; + case MYKONOS_ERR_AGC_MIN_MAX_RX_CHANNEL: + return "Wrong RX channel selected in MYKONOS_setRxAgcMinMaxGainIndex().\n"; + case MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX_CHANNEL: + return "Wrong read back channel in MYKONOS_setObsRxAgcMinMaxGainIndex().\n"; + case MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX: + return "Max gain index bigger than max gain index loaded table in MYKONOS_setObsRxAgcMinMaxGainIndex().\n"; + case MYKONOS_ERR_SET_ORX_MIN_GAIN_INDEX: + return "Min gain index lower than min gain index loaded table in MYKONOS_setObsRxAgcMinMaxGainIndex().\n"; + case MYKONOS_ERR_AGC_MIN_MAX_ORX_CHANNEL: + return "Wrong observation channel selected in MYKONOS_setObsRxAgcMinMaxGainIndex().\n"; + case MYKONOS_ERR_RX1_TEMP_GAIN_COMP_RANGE: + return "The temp gain compensation is outside range (-3000mdB to 3000mdB) in MYKONOS_setRx1TempGainComp().\n"; + case MYKONOS_ERR_RX1_TEMP_GAIN_COMP_STEP: + return "Not valid temp gain compensation, step size is 250mdB in MYKONOS_setRx1TempGainComp().\n"; + case MYKONOS_ERR_RX2_TEMP_GAIN_COMP_RANGE: + return "The temp gain compensation is outside range (-3000mdB to 3000mdB) in MYKONOS_setRx2TempGainComp().\n"; + case MYKONOS_ERR_RX2_TEMP_GAIN_COMP_STEP: + return "Not valid temp gain compensation, step size is 250mdB in MYKONOS_setRx2TempGainComp().\n"; + case MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_RANGE: + return "The temp gain compensation is outside range (-3000mdB to 3000mdB) in MYKONOS_setObsRxTempGainComp().\n"; + case MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_STEP: + return "Not valid temp gain compensation, step size is 250mdB in MYKONOS_setObsRxTempGainComp().\n"; + case MYKONOS_ERR_RX1_TEMP_GAIN_COMP_NULL: + return "rx1TempCompGain_mdB pointer is null MYKONOS_getRx1TempGainComp().\n"; + case MYKONOS_ERR_RX2_TEMP_GAIN_COMP_NULL: + return "rx2TempCompGain_mdB pointer is null MYKONOS_getRx2TempGainComp().\n"; + case MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_NULL: + return "obsRxTempCompGain_mdB pointer is null MYKONOS_getObsRxTempGainComp().\n"; + case MYKONOS_ERR_GETORXQECSTATUS_NULLPARAM: + return "Function parameter mykonosOrxQecStatus_t is a NULL pointer in MYKONOS_getOrxQecStatus().\n"; + case MYKONOS_ERR_GETORXQECSTATUS_INV_CH: + return "Channel selection not valid in MYKONOS_getOrxQecStatus().\n"; + case MYKONOS_ERR_GETORXQECSTATUS_ARMERRFLAG: + return "ARM command error in MYKONOS_getOrxQecStatus().\n"; + case MYKONOS_ERR_GETRXQECSTATUS_NULLPARAM: + return "Function parameter mykonosRxQecStatus_t is a NULL pointer in MYKONOS_getRxQecStatus().\n"; + case MYKONOS_ERR_GETRXQECSTATUS_INV_CH: + return "Channel selection not valid in MYKONOS_getRxQecStatus().\n"; + case MYKONOS_ERR_GETRXQECSTATUS_ARMERRFLAG: + return "ARM command error in MYKONOS_getRxQecStatus().\n"; + case MYKONOS_ERR_GETTXQECSTATUS_NULLPARAM: + return "Function parameter mykonosTxQecStatus_t is a NULL pointer in MYKONOS_getRxQecStatus().\n"; + case MYKONOS_ERR_GETTXQECSTATUS_INV_CH: + return "Channel selection not valid in MYKONOS_getTxQecStatus().\n"; + case MYKONOS_ERR_GETTXQECSTATUS_ARMERRFLAG: + return "ARM command error in MYKONOS_getTxQecStatus().\n"; + case MYKONOS_ERR_GETTXLOLSTATUS_NULLPARAM: + return "Function parameter mykonosTxLolStatus_t is a NULL pointer in MYKONOS_getTLolStatus().\n"; + case MYKONOS_ERR_GETTXLOLSTATUS_INV_CH: + return "Channel selection not valid in MYKONOS_getTLolStatus().\n"; + case MYKONOS_ERR_GETTXLOLSTATUS_ARMERRFLAG: + return "ARM command error in MYKONOS_getTLolStatus().\n"; + case MYKONOS_ERR_RESCHEDULE_TRACK_CAL_INV: + return "Not valid calibration passed to MYKONOS_rescheduleTrackingCal().\n"; + case MYKONOS_ERR_RESCHEDULE_TRACK_ARMERRFLAG: + return "ARM error in MYKONOS_rescheduleTrackingCal().\n"; + case MYKONOS_ERR_ARMSTATE_EXCEPTION: + return "ARM system problem has been detected.\n"; + case MYKONOS_ERR_ARMSTATE_CAL_ERROR: + return "ARM has detected an error in the tracking calibrations.\n"; + case MYKONOS_ERR_ARMSTATE_PROFILE_ERROR: + return "ARM has detected an illegal profile.\n"; + case MYKONOS_ERR_WAITARMCSTATE_TIMEOUT: + return "Timeout occurred in MYKONOS_checkArmState().\n"; + case MYKONOS_ERR_GET_API_VERSION_NULL_PARAM: + return "Null parameter passed to the function MYKONOS_getApiVersion().\n"; + case MYKONOS_ERR_GETPRODUCTID_NULL_PARAM: + return "Null parameter passed to the function MYKONOS_getProductId().\n"; + case MYKONOS_ERR_TXPROFILE_IQRATE: + return "Tx Profile IQ rate out of range.\n"; + case MYKONOS_ERR_TXPROFILE_RFBW: + return "Tx Profile RF bandwidth out of range.\n"; + case MYKONOS_ERR_TXPROFILE_FILTER_INTERPOLATION: + return "Tx Filter interpolation not valid.\n"; + case MYKONOS_ERR_TXPROFILE_FIR_COEFS: + return "Tx FIR filter not valid.\n"; + case MYKONOS_ERR_RXPROFILE_RXCHANNEL: + return " Rx channel is not valid.\n"; + case MYKONOS_ERR_RXPROFILE_IQRATE: + return "Receiver profile out of range IQ rate.\n"; + case MYKONOS_ERR_RXPROFILE_RFBW: + return "Receiver profile out of range RF bandwidth.\n"; + case MYKONOS_ERR_RXPROFILE_FILTER_DECIMATION: + return "Receiver profile not valid filter decimation setting.\n"; + case MYKONOS_ERR_RXPROFILE_FIR_COEFS: + return "Receiver profile FIR filter not valid.\n"; + case MYKONOS_ERR_RXPROFILE_ADCDIV: + return "Receiver profile not valid ADC divider.\n"; + case MYKONOS_ERR_PROFILES_HSDIGCLK: + return "Profile combinations loaded are not valid.\n"; + case MYKONOS_ERR_RESET_TXLOL_INV_PARAM: + return "Selected channel is not valid.\n"; + case MYKONOS_ERR_RESET_TXLOL_ARMERROR: + return "ARM command error in MYKONOS_resetExtTxLolChannel().\n"; + case MYKONOS_ERR_SETSTATEALL_TRACK_CAL_INV: + return "Not valid calibration mask passed for trackCals.\n"; + case MYKONOS_ERR_SETSTATEALL_TRACK_ARMERRFLAG: + return "ARM error flag set.\n"; + case MYKONOS_ERR_GETSTATEALL_TRACK_ARMERRFLAG: + return "ARM error flag set.\n"; + case MYKONOS_ERR_GETSTATEALL_TRACK_ARMERROR: + return "ARM command error.\n"; + case MYKONOS_ERR_GETSTATEALL_TRACK_NULL_PARAM: + return "Null parameter passed for trackCals.\n"; + case MYKONOS_ERR_SETSTATE_TRACK_CAL_INV: + return "Not valid calibration passed.\n"; + case MYKONOS_ERR_SETSTATE_TRACK_ARMERRFLAG: + return "ARM command error.\n"; + case MYKONOS_ERR_GETSTATE_TRACK_NULL_PARAM: + return "Null parameter passed to trackCalState.\n"; + case MYKONOS_ERR_GETSTATE_TRACK_ARMERRFLAG: + return "ARM command error flag set.\n"; + case MYKONOS_ERR_GETSTATE_TRACK_ARMERROR: + return "ARM command error.\n"; + case MYKONOS_ERR_SETCLGCGAIN_INV_TXCHANNEL: + return "Tx channel is not valid (Valid ENUM values: TX1 or TX2 only).\n"; + case MYKONOS_ERR_SETCLGCGAIN_TRACK_ARMERRFLAG: + return "ARM command flag error set.\n"; + case MYKONOS_ERR_SETCLGCGAIN_INV_DESIREDGAIN: + return "CLGC gain parameter is out of range, valid range is from -10000 to 10000.\n"; + case MYKONOS_ERR_SETDPDACT_INV_TXCHANNEL: + return "Tx channel is not valid (Valid ENUM values: TX1, TX2 or TX1_TX2).\n"; + case MYKONOS_ERR_SETDPDACT_INV_STATE: + return "Invalid Actuator state, valid states are 0-disable and 1-enable.\n"; + case MYKONOS_ERR_SETDPDACT_ARMERRFLAG: + return "ARM command flag error set.\n"; + case MYKONOS_ERR_SETRFPLL_LF_PLLNAME: + return "Invalid pllName requested in MYKONOS_setRfPllLoopFilter()\n"; + case MYKONOS_ERR_SETRFPLL_LF_INV_STABILITY: + return "Invalid stability value requested in MYKONOS_setRfPllLoopFilter()\n"; + case MYKONOS_ERR_SETRFPLL_LF_ARMERROR: + return "ARM Command Error in MYKONOS_setRfPllLoopFilter()\n"; + case MYKONOS_ERR_SETRFPLL_LF_INV_TXRX_LOOPBANDWIDTH: + return "Invalid Tx/Rx value bandwith requested in MYKONOS_setRfPllLoopFilter()\n"; + case MYKONOS_ERR_SETRFPLL_LF_INV_SNF_LOOPBANDWIDTH: + return "Invalid Sniffer value bandwith in MYKONOS_setRfPllLoopFilter()\n"; + case MYKONOS_ERR_GETRFPLL_LF_INV_PLLNAME: + return "Invalid pllName requested in MYKONOS_getRfPllLoopFilter()\n"; + case MYKONOS_ERR_GETRFPLL_LF_ARMERROR: + return "ARM Command Error in MYKONOS_getRfPllLoopFilter()\n"; + case MYKONOS_ERR_GETRFPLL_LF_NULLPARAM: + return "NULL pointer in function parameter for MYKONOS_getRfPllLoopFilter()\n"; + case MYKONOS_ERR_SET_RF_DC_OFFSET_INV_MEASURECNT: + return "Invalid value passed as parameter for measureCount to function MYKONOS_setRfDcOffsetCnt().\n"; + case MYKONOS_ERR_SET_RF_DC_OFFSET_MEASURECNT_MIN_LIMIT: + return "The measureCount value passed to function MYKONOS_setRfDcOffsetCnt() is less than the minimum limit allowed.\n"; + case MYKONOS_ERR_DC_OFFSET_INV_CHAN: + return "Invalid channel passed as parameter, for valid channel refer mykonosDcOffsetChannels_t enum.\n"; + case MYKONOS_ERR_GET_RF_DC_OFFSET_NULL_MEASURECNT: + return "Null parameter passed for measureCount MYKONOS_getRfDcOffsetCnt().\n"; + case MYKONOS_ERR_SET_DIG_DC_OFFSET_INV_MSHIFT: + return "Invalid MShift value passed as parameter to function MYKONOS_setDigDcOffsetMShift().\n"; + case MYKONOS_ERR_GET_DIG_DC_OFFSET_NULL_MSHIFT: + return "MShift passed to the function MYKONOS_getDigDcOffsetMShift() is NULL.\n"; + case MYKONOS_ERR_DIG_DC_OFFSET_INV_ENABLE_MASK: + return "Invalid enable mask passed to the function MYKONOS_setDigDcOffsetEn().\n"; + case MYKONOS_ERR_DIG_DC_OFFSET_NULL_ENABLE_MASK: + return "Enable mask passed to the function MYKONOS_getDigDcOffsetEn() is NULL.\n"; + case MYKONOS_ERR_RESETDPD_WRONG_PARAM: + return "reset parameter passed to function MYKONOS_resetDpd() is not valid, possible values are: MYK_DPD_RESET_FULL, MYK_DPD_RESET_PRIOR or MYK_DPD_RESET_CORRELATOR \n"; + case MYKONOS_ERR_RESETDPD_ARMERRFLAG: + return "ARM command flag error set in function MYKONOS_resetDpd().\n"; + case MYKONOS_ERR_CFGCLGC_INV_THRESHOLD: + return "tx1RelThreshold or tx2RelThreshold parameter is out of range in function MYKONOS_configClgc().\n"; + case MYKONOS_ERR_RESETDPD_INV_TXCHANNEL: + return "Tx channel is not valid (Valid ENUM values: TX1, TX2 or TX1_TX2 in function MYKONOS_resetDpd().\n"; + case MYKONOS_ERR_SET_PATH_DELAY_NULL_PARAM: + return "pathDelay structure is null in function MYKONOS_setPathDelay().\n"; + case MYKONOS_ERR_SET_PATH_DELAY_PARAM_OUT_OF_RANGE: + return "path delay not valid range in MYKONOS_setPathDelay(), valid ranges are from 0 to 4095 at 1/16 sample resolution of ORx sample rate.\n"; + case MYKONOS_ERR_GET_PATH_DELAY_NULL_PARAM: + return "pathDelay structure is null in function MYKONOS_getPathDelay().\n"; + case MYKONOS_ERR_GET_PATH_DELAY_INVALID_SELECTION: + return "invalid selection for getting the path delay, valid selections are given by mykonosPathDelaySel_t.\n"; + case MYKONOS_ERR_GET_PATH_DELAY_ARMERRFLAG: + return "Arm error while reading path delay for the selected calibration status.\n"; + case MYKONOS_ERR_GETDPD_ERROR_CNT_NULLPARAM: + return "dpdErrCnt is null in function MYKONOS_getDpdErrorCounters().\n"; + case MYKONOS_ERR_GETDPD_ERROR_CNT_INV_CH: + return "invalid selection for getting the error counters tx channel in MYKONOS_getDpdErrorCounters().\n"; + case MYKONOS_ERR_GETDPD_ERROR_CNT_ARMERRFLAG: + return "Arm error while reading the error counters for the DPD status MYKONOS_getDpdErrorCounters().\n"; + case MYKONOS_ERR_SETDPDACT_NULL_ACTSTRUCT: + return "Passed structure is null in MYKONOS_setDpdBypassConfig().\n"; + case MYKONOS_ERR_SETDPDACT_INV_ACTMODE: + return "Invalid mode passed detected in MYKONOS_setDpdBypassConfig(), actConfig->bypassActuatorMode for valid modes mykonosDpdResetMode_t.\n"; + case MYKONOS_ERR_SETDPDACT_INV_LEVEL: + return "Passed actConfig->bypassActuatorLevel outside the range in MYKONOS_setDpdBypassConfig().\n"; + case MYKONOS_ERR_GETDPDACT_NULL_ACTSTRUCT: + return "Passed structure is null in MYKONOS_getDpdBypassConfig().\n"; + case MYKONOS_ERR_SETDPDACTCHECK_NULL_ACTSTRUCT: + return "Passed structure is null in MYKONOS_setDpdActuatorCheck().\n"; + case MYKONOS_ERR_SETDPDACTCHECK_INV_ACTMODE: + return "Invalid mode detected in MYKONOS_setDpdActuatorCheck(), actCheck->actuatorGainCheckMode for valid modes mykonosDpdResetMode_t.\n"; + case MYKONOS_ERR_SETDPDACTCHECK_INV_LEVEL: + return "Passed actCheck->actuatorGainCheckLevel outside the range in MYKONOS_setDpdActuatorCheck().\n"; + case MYKONOS_ERR_GETDPDACTCHECK_NULL_ACTSTRUCT: + return "Passed structure is null in MYKONOS_getDpdActuatorCheck().\n"; + case MYKONOS_ERR_CLGCATTENTUNCFG_NULL_ATTRANGECFGSTRUCT: + return "Passed structure is null in MYKONOS_setClgcAttenTuningConfig().\n"; + case MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_MODE: + return "Invalid mode detected for attRangeCfg member in MYKONOS_getClgcAttenTuningConfig(), for valid modes ::mykonosClgcAttenTuningMode_t.\n"; + case MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_PRESET: + return "Invalid AttenTuningPreset detected for attRangeCfg member in MYKONOS_getClgcAttenTuningConfig(), valid range is from 0 to 839 (0 to 41.95dB).\n"; + case MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_RANGE: + return "Invalid AttenTuningRange detected for attRangeCfg member in MYKONOS_getClgcAttenTuningConfig(), valid range is from 0 to 420 (0 to 21dB).\n"; + case MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX1_SETTINGS: + return "Invalid Tx1 AttenTuningRange and AttenTuningPreset combination in MYKONOS_getClgcAttenTuningConfig().\n"; + case MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX2_SETTINGS: + return "Invalid Tx2 AttenTuningRange and AttenTuningPreset combination in MYKONOS_getClgcAttenTuningConfig().\n"; + case MYKONOS_ERR_CLGCATTENTUNCFGGET_NULL_ATTRANGECFGSTRUCT: + return "Passed structure is null in MYKONOS_getClgcAttenTuningConfig().\n"; + + default: + return "Unknown error was encountered.\n"; + } + +#endif +} + +/** + * \brief Calculates the scaled device clock frequency at the input of the + * CLKPLL or RFPLL + * + * Use this helper function any time the scaled device clock frequency is needed. + * + * Dependencies + * - device->clocks->deviceClock_kHz + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param scaledRefClk_kHz Output: The returned scaled reference clock for the device's PLLs + * \param deviceClkDiv Output: The device clock divider setting that gets set in the devices SPI register. + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_NULL_DEVICE_PARAM Function parameter device pointer is NULL + * \retval MYKONOS_ERR_INV_SCALEDDEVCLK_PARAM The scaled PLL refclk frequency is out of range (40MHz to 80MHz) + * \retval MYKONOS_ERR_CALCDEVCLK_NULLPARAM Function parameter scaledRefClk_kHz or deviceClkDiv has a NULL pointer + */ +static mykonosErr_t MYKONOS_calculateScaledDeviceClk_kHz(mykonosDevice_t *device, uint32_t *scaledRefClk_kHz, uint8_t *deviceClkDiv) +{ + uint32_t deviceClock_kHz = 0; + + if ((device == NULL) || (device->clocks == NULL)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, 0, MYKONOS_ERR_NULL_DEVICE_PARAM, getMykonosErrorMessage(MYKONOS_ERR_NULL_DEVICE_PARAM)); + return MYKONOS_ERR_NULL_DEVICE_PARAM; + } + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_calculateScaledDeviceClk_kHz()\n"); +#endif + + deviceClock_kHz = device->clocks->deviceClock_kHz; + + if ((scaledRefClk_kHz == NULL) || (deviceClkDiv == NULL)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CALCDEVCLK_NULLPARAM, + getMykonosErrorMessage(MYKONOS_ERR_CALCDEVCLK_NULLPARAM)); + return MYKONOS_ERR_CALCDEVCLK_NULLPARAM; + } + + /* scaled Ref Clock at input to CLKPLL must be in range 40-80MHz. */ + if (deviceClock_kHz > 20000 && deviceClock_kHz <= 40000) + { + *scaledRefClk_kHz = deviceClock_kHz << 1; + *deviceClkDiv = 3; + } /* x2 */ + else if (deviceClock_kHz > 40000 && deviceClock_kHz <= 80000) + { + *scaledRefClk_kHz = deviceClock_kHz; + *deviceClkDiv = 0; + } /* x1 */ + else if (deviceClock_kHz > 80000 && deviceClock_kHz <= 160000) + { + *scaledRefClk_kHz = deviceClock_kHz >> 1; + *deviceClkDiv = 1; + } /* div2 */ + else if (deviceClock_kHz > 160000 && deviceClock_kHz <= 320000) + { + *scaledRefClk_kHz = deviceClock_kHz >> 2; + *deviceClkDiv = 2; + } /* div4 */ + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_SCALEDDEVCLK_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_INV_SCALEDDEVCLK_PARAM)); + return MYKONOS_ERR_INV_SCALEDDEVCLK_PARAM; + } + return MYKONOS_ERR_OK; +} + +/** + * \brief Resets the JESD204B Deframer + * + * Dependencies + * - device->spiSettings + * + * \param device is a pointer to the device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_resetDeframer(mykonosDevice_t *device) +{ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_resetDeframer()\n"); +#endif + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_RESET, 0x03); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_RESET, 0x00); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets up the JESD204B Serializers + * + * This function uses the Rx framer and ObsRx framer structures to setup the 4 + * serializer lanes that are shared between the two framers. If the Rx profile is valid + * the serializer amplitude and preEmphasis are used from the Rx framer. If only the ObsRx + * profile is valid, the obsRx framer settings are used. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * - device->rx->framer->M + * - device->rx->framer->serializerAmplitude + * - device->rx->framer->preEmphasis + * - device->rx->framer->serializerLanesEnabled + * - device->rx->framer->invertLanePolarity + * - device->obsRx->framer->serializerLanesEnabled + * - device->obsRx->framer->invertLanePolarity + * - device->obsRx->framer->M + * - device->obsRx->framer->serializerLanesEnabled + * - device->obsRx->framer->serializerAmplitude + * - device->obsRx->framer->preEmphasis + * + * \param device Pointer to the device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_INITSER_INV_VCODIV_PARM Mykonos CLKPLL has invalid VCO divider, verify CLKPLL config + * \retval MYKONOS_ERR_SER_LANE_CONFLICT_PARM When both Rx and ObsRx framers are enabled, framers can not share the same physical lane. + * \retval MYKONOS_ERR_SER_INV_REAL_IF_DATA_PARM Rx Framer M can only = 1 when Real IF mode is enabled + * \retval MYKONOS_ERR_SER_INV_M_PARM Invalid Rx Framer M (valid 1,2,4) + * \retval MYKONOS_ERR_SER_INV_LANEEN_PARM Invalid Rx framer serializerLanesEnabled (valid 0-15) + * \retval MYKONOS_ERR_SER_INV_AMP_PARM Invalid Rx serializer amplitude (valid 0-31) + * \retval MYKONOS_ERR_SER_INV_PREEMP_PARM Invalid Rx serializer pre-emphesis (valid 0-7) + * \retval MYKONOS_ERR_SER_INV_LANEPN_PARM Invalid Rx serializer PN invert setting (valid 0-15) + * \retval MYKONOS_ERR_SER_INV_L_PARM Invalid Rx serializer lanes enabled (must use 1, 2 or 4 lanes) + * \retval MYKONOS_ERR_SER_INV_LANERATE_PARM Invalid Rx serializer lane rate (valid 614.4Mbps - 6144Mbps) + * + * \retval MYKONOS_ERR_SER_INV_REAL_IF_DATA_PARM + * \retval MYKONOS_ERR_SER_INV_LANEEN_PARM + * \retval MYKONOS_ERR_SER_INV_AMP_PARM + * \retval MYKONOS_ERR_SER_INV_PREEMP_PARM + * \retval MYKONOS_ERR_SER_INV_LANEPN_PARM + * \retval MYKONOS_ERR_SER_INV_L_PARM + * \retval MYKONOS_ERR_SER_INV_LANERATE_PARM + * + * \retval MYKONOS_ERR_SER_LANE_RATE_CONFLICT_PARM Necessary lane rates for Rx and ObsRx framer can not be obtained with possible divider settings + * \retval MYKONOS_ERR_HS_AND_LANE_RATE_NOT_INTEGER_MULT HSCLK is not an integer multiple of the lane clock rate + * \retval MYKONOS_ERR_SER_INV_TXSER_DIV_PARM No valid Tx serializer divider to obtain desired lane rates + * \retval MYKONOS_ERR_INITSER_INV_PROFILE Rx/ObsRx and sniffer profiles are not valid - can not config serializers + * \retval MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM Invalid Rx framer PCLK divider + * \retval MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM Invalid ORx/Sniffer framer PCLK divider + * + */ +mykonosErr_t MYKONOS_setupSerializers(mykonosDevice_t *device) +{ + uint8_t serializerHalfRateReg = 0; + uint8_t txser_div = 0; + uint8_t txser_div_reg = 0; + uint32_t clkPllVcoFrequency_kHz = 0; + uint32_t hsclkRate_kHz = 0; + uint32_t rxLaneRate_kHz = 0; + uint32_t obsRxLaneRate_kHz = 0; + uint32_t fasterLaneRate_kHz = 0; + uint32_t slowerLaneRate_kHz = 0; + uint8_t modHsLaneRate = 0; + uint8_t rxL = 0; + uint8_t obsRxL = 0; + uint8_t i = 0; + uint8_t amplitudeEmphasis = 0; + uint8_t lanePowerDown = 0x00; + mykonosVcoDiv_t vcoDiv = VCODIV_1; + uint8_t rxLanePn = 0; + uint8_t obsRxLanePn = 0; + + uint32_t hsDigClkdiv4_5_kHz = 0; + uint32_t rxPclkDiv = 0; + uint32_t obsRxPclkDiv = 0; + uint32_t tempPclkDiv = 0; + uint32_t rxFramerPclk_kHz = 0; + uint32_t obsRxFramerPclk_kHz = 0; + uint8_t rxSyncbSelect = 0; + uint8_t obsRxSyncbSelect = 0; + + static const uint32_t MAX_HSCLK_KHZ_IF_VCODIV1P5 = 6144000; /* max VCO /1.5 output is 6144Mhz. This limits VCO to 9216MHz */ + static const uint32_t MAX_HSCLK_KHZ_IF_VCODIV1 = 8000000; /* max VCO div1 output is 8000Mhz. This limits VCO to 8000MHz */ + static const uint32_t MIN_SERIALIZER_RATE_KHZ = 614400; /* max serializer lane rate = 0.6144 Gbps */ + static const uint32_t MAX_SERIALIZER_RATE_KHZ = 6144000; /* max serializer lane rate = 6.144 Gbps */ +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setupSerializers()\n"); +#endif + + vcoDiv = device->clocks->clkPllVcoDiv; + clkPllVcoFrequency_kHz = device->clocks->clkPllVcoFreq_kHz; + + switch (vcoDiv) + { + case VCODIV_1: + hsclkRate_kHz = clkPllVcoFrequency_kHz; + + /* max VCO /1 output is 8000Mhz. This limits VCO to 8000MHz */ + if (hsclkRate_kHz > MAX_HSCLK_KHZ_IF_VCODIV1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INITSER_INV_VCODIV1_HSCLK_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INITSER_INV_VCODIV1_HSCLK_PARM)); + return MYKONOS_ERR_INITSER_INV_VCODIV1_HSCLK_PARM; + } + + break; + + case VCODIV_1p5: + hsclkRate_kHz = (clkPllVcoFrequency_kHz / 15) * 10; + + /* max VCO /1.5 output is 6144Mhz. This limits VCO to 9216MHz */ + if (hsclkRate_kHz > MAX_HSCLK_KHZ_IF_VCODIV1P5) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INITSER_INV_VCODIV1P5_HSCLK_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INITSER_INV_VCODIV1P5_HSCLK_PARM)); + return MYKONOS_ERR_INITSER_INV_VCODIV1P5_HSCLK_PARM; + } + + break; + + case VCODIV_2: + hsclkRate_kHz = clkPllVcoFrequency_kHz >> 1; + break; + + case VCODIV_3: + hsclkRate_kHz = (clkPllVcoFrequency_kHz / 30) * 10; + break; + + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INITSER_INV_VCODIV_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INITSER_INV_VCODIV_PARM)); + return MYKONOS_ERR_INITSER_INV_VCODIV_PARM; + } + } + + if ((device->profilesValid & RX_PROFILE_VALID) && (device->profilesValid & (ORX_PROFILE_VALID | SNIFF_PROFILE_VALID))) + { + if (device->rx->framer->serializerLanesEnabled & device->obsRx->framer->serializerLanesEnabled) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_LANE_CONFLICT_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_LANE_CONFLICT_PARM)); + return MYKONOS_ERR_SER_LANE_CONFLICT_PARM; + } + } + + lanePowerDown = 0x9F; + if (device->profilesValid & RX_PROFILE_VALID) + { + if (device->rx->framer->M == 1 && !(device->rx->realIfData)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_REAL_IF_DATA_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_INV_REAL_IF_DATA_PARM)); + return MYKONOS_ERR_SER_INV_REAL_IF_DATA_PARM; + } + + if (device->rx->framer->M != 1 && device->rx->framer->M != 2 && device->rx->framer->M != 4) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_M_PARM, getMykonosErrorMessage(MYKONOS_ERR_SER_INV_M_PARM)); + return MYKONOS_ERR_SER_INV_M_PARM; + } + + for (i = 0; i < 4; i++) + { + rxL += ((device->rx->framer->serializerLanesEnabled >> i) & 0x01); + } + + if (device->rx->framer->serializerLanesEnabled > 15) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_LANEEN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_INV_LANEEN_PARM)); + return MYKONOS_ERR_SER_INV_LANEEN_PARM; + } + + if (device->rx->framer->serializerAmplitude > 31) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_AMP_PARM, getMykonosErrorMessage(MYKONOS_ERR_SER_INV_AMP_PARM)); + return MYKONOS_ERR_SER_INV_AMP_PARM; + } + + if (device->rx->framer->preEmphasis > 7) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_PREEMP_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_INV_PREEMP_PARM)); + return MYKONOS_ERR_SER_INV_PREEMP_PARM; + } + + if (device->rx->framer->invertLanePolarity > 15) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_LANEPN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_INV_LANEPN_PARM)); + return MYKONOS_ERR_SER_INV_LANEPN_PARM; + } + if ((rxL != 1) && (rxL != 2) && (rxL != 4)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_L_PARM, getMykonosErrorMessage(MYKONOS_ERR_SER_INV_L_PARM)); + return MYKONOS_ERR_SER_INV_L_PARM; + } + + rxLaneRate_kHz = device->rx->rxProfile->iqRate_kHz * 20 * device->rx->framer->M / rxL; + lanePowerDown &= (~(device->rx->framer->serializerLanesEnabled)); + + if ((rxLaneRate_kHz < MIN_SERIALIZER_RATE_KHZ) || (rxLaneRate_kHz > MAX_SERIALIZER_RATE_KHZ)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_LANERATE_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_INV_LANERATE_PARM)); + return MYKONOS_ERR_SER_INV_LANERATE_PARM; + } + } + + if ((device->obsRx->framer != NULL) && (device->profilesValid & (ORX_PROFILE_VALID | SNIFF_PROFILE_VALID))) + { + if ((device->obsRx->framer->M == 1) && !(device->obsRx->realIfData)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_REAL_IF_DATA_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_INV_REAL_IF_DATA_PARM)); + return MYKONOS_ERR_SER_INV_REAL_IF_DATA_PARM; + } + + for (i = 0; i < 4; i++) + { + obsRxL += ((device->obsRx->framer->serializerLanesEnabled >> i) & 0x01); + } + + if (device->obsRx->framer->serializerLanesEnabled > 15) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_LANEEN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_INV_LANEEN_PARM)); + return MYKONOS_ERR_SER_INV_LANEEN_PARM; + } + + if (device->obsRx->framer->serializerAmplitude > 31) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_AMP_PARM, getMykonosErrorMessage(MYKONOS_ERR_SER_INV_AMP_PARM)); + return MYKONOS_ERR_SER_INV_AMP_PARM; + } + + if (device->obsRx->framer->preEmphasis > 7) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_PREEMP_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_INV_PREEMP_PARM)); + return MYKONOS_ERR_SER_INV_PREEMP_PARM; + } + + if (device->obsRx->framer->invertLanePolarity > 15) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_LANEPN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_INV_LANEPN_PARM)); + return MYKONOS_ERR_SER_INV_LANEPN_PARM; + } + + if ((obsRxL != 0) && (obsRxL != 1) && (obsRxL != 2) && (obsRxL != 4)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_L_PARM, getMykonosErrorMessage(MYKONOS_ERR_SER_INV_L_PARM)); + return MYKONOS_ERR_SER_INV_L_PARM; + } + + /* check for valid pointer */ + if (obsRxL == 0) + { + /* Allow ORx receiver to work but disable Obs Rx framer link - valid on a DPD-enabled transceiver */ + obsRxLaneRate_kHz = 0; + } + else if (device->profilesValid & ORX_PROFILE_VALID) + { + obsRxLaneRate_kHz = device->obsRx->orxProfile->iqRate_kHz * 20 * device->obsRx->framer->M / obsRxL; + } + else if (device->profilesValid & SNIFF_PROFILE_VALID) + { + obsRxLaneRate_kHz = device->obsRx->snifferProfile->iqRate_kHz * 20 * device->obsRx->framer->M / obsRxL; + } + + lanePowerDown &= (~(device->obsRx->framer->serializerLanesEnabled)); + + if ((obsRxLaneRate_kHz != 0) && ((obsRxLaneRate_kHz < MIN_SERIALIZER_RATE_KHZ) || (obsRxLaneRate_kHz > MAX_SERIALIZER_RATE_KHZ))) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_LANERATE_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_INV_LANERATE_PARM)); + return MYKONOS_ERR_SER_INV_LANERATE_PARM; + } + } + + /* checking for RX and OBSRX effective lane rates match */ + /* Need to account for oversampling, verify that the 2 lane rate are integer related */ + + if ((rxLaneRate_kHz > 0) && (obsRxLaneRate_kHz > 0)) + { + fasterLaneRate_kHz = (rxLaneRate_kHz >= obsRxLaneRate_kHz) ? (rxLaneRate_kHz) : (obsRxLaneRate_kHz); + slowerLaneRate_kHz = (rxLaneRate_kHz >= obsRxLaneRate_kHz) ? (obsRxLaneRate_kHz) : (rxLaneRate_kHz); + + /* Verify that lane rates are integer multiples of each other */ + if ((fasterLaneRate_kHz % slowerLaneRate_kHz) != 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_LANE_RATE_CONFLICT_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_LANE_RATE_CONFLICT_PARM)); + return MYKONOS_ERR_SER_LANE_RATE_CONFLICT_PARM; + } + } + else + { + fasterLaneRate_kHz = (rxLaneRate_kHz >= obsRxLaneRate_kHz) ? (rxLaneRate_kHz) : (obsRxLaneRate_kHz); + } + + /* performing integer multiple check on HS clock and lane rate clock */ + if (fasterLaneRate_kHz == 0) + { + /* All serializer lanes are disabled */ + txser_div = 1; + txser_div_reg = 0; + serializerHalfRateReg = 0; + } + else + { + if ((fasterLaneRate_kHz > hsclkRate_kHz) || + (fasterLaneRate_kHz > MAX_SERIALIZER_RATE_KHZ)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_LANERATE_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_INV_LANERATE_PARM)); + return MYKONOS_ERR_SER_INV_LANERATE_PARM; + } + + modHsLaneRate = (uint8_t)(hsclkRate_kHz % fasterLaneRate_kHz); + if (modHsLaneRate != 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_HS_AND_LANE_RATE_NOT_INTEGER_MULT, + getMykonosErrorMessage(MYKONOS_ERR_HS_AND_LANE_RATE_NOT_INTEGER_MULT)); + return MYKONOS_ERR_HS_AND_LANE_RATE_NOT_INTEGER_MULT; + } + + txser_div = (uint8_t)(hsclkRate_kHz / fasterLaneRate_kHz); /* Total serializer Divider (1,2,4,8) */ + switch (txser_div) + { + case 1: + txser_div_reg = 0; /* Divide hsclk by 1 */ + serializerHalfRateReg = 0; /* 0 = divide serializer clock by 1 */ + break; + case 2: + txser_div_reg = 1; /* Divide hsclk by 2 */ + serializerHalfRateReg = 0; /* 0 = divide serializer clock by 1 */ + break; + case 4: + txser_div_reg = 2; /* Divide hsclk by 4 */ + serializerHalfRateReg = 0; /* 0 = divide serializer clock by 1 */ + break; + case 8: + txser_div_reg = 2; /* Divide hsclk by 4 */ + serializerHalfRateReg = 1; /* 1 = divide serializer clock by 2 */ + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SER_INV_TXSER_DIV_PARM, + getMykonosErrorMessage(MYKONOS_ERR_SER_INV_TXSER_DIV_PARM)); + return MYKONOS_ERR_SER_INV_TXSER_DIV_PARM; + } + } + + if (device->profilesValid & RX_PROFILE_VALID) + { + amplitudeEmphasis = ((device->rx->framer->serializerAmplitude & 0x1f) << 3) | (device->rx->framer->preEmphasis & 0x07); + } + else if (device->profilesValid & (ORX_PROFILE_VALID | SNIFF_PROFILE_VALID)) + { + amplitudeEmphasis = ((device->obsRx->framer->serializerAmplitude & 0x1f) << 3) | (device->obsRx->framer->preEmphasis & 0x07); + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INITSER_INV_PROFILE, getMykonosErrorMessage(MYKONOS_ERR_INITSER_INV_PROFILE)); + return MYKONOS_ERR_INITSER_INV_PROFILE; + } + + if (device->profilesValid & RX_PROFILE_VALID) + { + rxSyncbSelect = (device->rx->framer->obsRxSyncbSelect > 0) ? 1 : 0; + rxLanePn = (uint8_t)(rxSyncbSelect << 7) | (device->rx->framer->invertLanePolarity & 0xF); + } + + if (device->profilesValid & (ORX_PROFILE_VALID | SNIFF_PROFILE_VALID)) + { + obsRxSyncbSelect = (device->obsRx->framer->obsRxSyncbSelect > 0) ? 1 : 0; + obsRxLanePn = (uint8_t)(obsRxSyncbSelect << 7) | (device->obsRx->framer->invertLanePolarity & 0xF); + } + + /* Serializer lane clock frequency */ + /* serLaneClock_kHz = fasterLaneRate_kHz / txser_div / 20; */ + if (device->profilesValid & RX_PROFILE_VALID) + { + /* calculate manual PCLK frequency for Rx framer = Rx IQrate * F, where F = (2*M/L) or PCLK = lanerate /10 */ + if (device->rx->framer->overSample) + { + rxFramerPclk_kHz = fasterLaneRate_kHz / 10; + } + else + { + rxFramerPclk_kHz = rxLaneRate_kHz / 10; + } + + hsDigClkdiv4_5_kHz = hsclkRate_kHz / device->clocks->clkPllHsDiv / device->rx->rxProfile->rxDec5Decimation; + + /* PCLKDiv: 0=4x, 1=2x, 2=1x, 3=/2, 4=/4, 5=/8, 6=/16 */ + if (hsDigClkdiv4_5_kHz == rxFramerPclk_kHz) + { + rxPclkDiv = 2; + } + else if (hsDigClkdiv4_5_kHz > rxFramerPclk_kHz) + { + if (rxFramerPclk_kHz == 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM)); + return MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM; + } + + tempPclkDiv = hsDigClkdiv4_5_kHz / rxFramerPclk_kHz; + switch (tempPclkDiv) + { + case 2: + rxPclkDiv = 3; + break; + case 4: + rxPclkDiv = 4; + break; + case 8: + rxPclkDiv = 5; + break; + case 16: + rxPclkDiv = 6; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM)); + return MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM; + } + } + } + else if (hsDigClkdiv4_5_kHz < rxFramerPclk_kHz) + { + tempPclkDiv = rxFramerPclk_kHz / hsDigClkdiv4_5_kHz; + switch (tempPclkDiv) + { + case 2: + rxPclkDiv = 1; + break; + case 4: + rxPclkDiv = 0; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM)); + return MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM; + } + } + } + } + + if (obsRxL == 0) + { + /* Make sure PCLK is set as low as possible because it interacts with Rx Framer logic, */ + /* even though ObsRx Framer disabled */ + obsRxPclkDiv = 6; + } + else if (device->profilesValid & (ORX_PROFILE_VALID | SNIFF_PROFILE_VALID)) + { + /* calculate manual PCLK frequency for obsRx framer = obsRx IQrate * F, where F = (2*M/L) */ + if (device->profilesValid & ORX_PROFILE_VALID) + { + if (device->obsRx->framer->overSample) + { + obsRxFramerPclk_kHz = fasterLaneRate_kHz / 10; + } + else + { + obsRxFramerPclk_kHz = obsRxLaneRate_kHz / 10; + } + + hsDigClkdiv4_5_kHz = hsclkRate_kHz / device->clocks->clkPllHsDiv / device->obsRx->orxProfile->rxDec5Decimation; + } + else if (device->profilesValid & SNIFF_PROFILE_VALID) + { + if (device->obsRx->framer->overSample) + { + obsRxFramerPclk_kHz = fasterLaneRate_kHz / 10; + } + else + { + obsRxFramerPclk_kHz = obsRxLaneRate_kHz / 10; + } + + hsDigClkdiv4_5_kHz = hsclkRate_kHz / device->clocks->clkPllHsDiv / device->obsRx->snifferProfile->rxDec5Decimation; + } + + /* PCLKDiv: 0=4x, 1=2x, 2=1x, 3=/2, 4=/4, 5=/8, 6=/16 */ + if (hsDigClkdiv4_5_kHz == obsRxFramerPclk_kHz) + { + obsRxPclkDiv = 2; + } + else if ((hsDigClkdiv4_5_kHz > obsRxFramerPclk_kHz) && (obsRxFramerPclk_kHz != 0)) + { + tempPclkDiv = hsDigClkdiv4_5_kHz / obsRxFramerPclk_kHz; + switch (tempPclkDiv) + { + case 2: + obsRxPclkDiv = 3; + break; + case 4: + obsRxPclkDiv = 4; + break; + case 8: + obsRxPclkDiv = 5; + break; + case 16: + obsRxPclkDiv = 6; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM)); + return MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM; + } + } + } + else if (hsDigClkdiv4_5_kHz < obsRxFramerPclk_kHz) + { + if (hsDigClkdiv4_5_kHz == 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM)); + return MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM; + } + + tempPclkDiv = obsRxFramerPclk_kHz / hsDigClkdiv4_5_kHz; + switch (tempPclkDiv) + { + case 2: + obsRxPclkDiv = 1; + break; + case 4: + obsRxPclkDiv = 0; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM)); + return MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM; + } + } + } + } + + /* set lane rate divide setting */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_3, txser_div_reg, 0x03, 0); + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SERIALIZER_CTL_2, amplitudeEmphasis); + + /* Serializer: Release Reset */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SERIALIZER_SPECIAL, 0x03); + + /* Serializer: txser clk enable */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SERIALIZER_HS_DIV_TXSER_CLK_EN, 0x01); + + /* Serializer: Enable 2 to 1 serializer */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SERIALIZER_CTL_3, 0x20 | serializerHalfRateReg); + + /* power up desired serializer lanes */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SERIALIZER_CTL_1, lanePowerDown); + + /* apply desired lane PN inversions to the TX and OBSRX framers */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_LANE_DATA_CTL, rxLanePn); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_LANE_DATA_CTL, obsRxLanePn); + + /* set Rx framer manual PCLK frequency based on lane rate of the serializers */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_FRAMER_CLK_EN, (uint8_t)rxPclkDiv, 0x70, 4); + + /* enable bit repeat mode in Rx framer - since manual PCLK, oversample will still work */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_FRAMER_CLK_EN, 0, 0x80, 7); + + /* enable manual PCLK mode in Rx framer */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_FRAMER_CLK_EN, 1, 0x04, 2); + + /* set obsRx framer manual PCLK frequency based on lane rate of the serializers */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_CLK_EN, (uint8_t)obsRxPclkDiv, 0x70, 4); + + /* enable bit repeat mode in ObsRx framer - since manual PCLK, oversample will still work */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_CLK_EN, 0, 0x80, 7); + + /* enable manual PCLK mode in ObsRx framer */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_CLK_EN, 1, 0x04, 2); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets up the JESD204B Deserializers + * + * This function enables the necessary deserializer lanes, sets the deserializer clocks + * PN inversion settings, and EQ settings based on the info found in the device data structure. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * - device->tx->txProfile->clkPllVcoDiv + * - device->tx->txProfile->vcoFreq_kHz + * - device->tx->txProfile->txIqRate_kHz + * - device->tx->deframer->M + * - device->tx->deframer->deserializerLanesEnabled + * - device->tx->deframer->invertLanePolarity + * - device->tx->deframer->EQSetting + * + * \param device Pointer to the device settings structure + + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_INITDES_INV_TXPROFILE Tx Profile is not valid in data structure - can not setup deserializer + * \retval MYKONOS_ERR_INITDES_INV_VCODIV_PARM Mykonos CLKPLL VCO divider is invalid + * \retval MYKONOS_ERR_DESER_INV_M_PARM Invalid M (valid 2 or 4) + * \retval MYKONOS_ERR_DESER_INV_L_PARM Invalid L (valid 1,2,4) + * \retval MYKONOS_ERR_DESER_INV_HSCLK_PARM Invalid HSCLK, must be 6.144G or less after CLKPLL VCO divider - verify CLKPLL config + * \retval MYKONOS_ERR_DESER_INV_LANERATE_PARM Invalid lanerate, must be between 614.4 Mbps to 6144 Mbps + * \retval MYKONOS_ERR_DESER_INV_LANEEN_PARM Invalid deserializerLanesEnabled (valid 0-15 in 1,2,4 lane combinations) + * \retval MYKONOS_ERR_DESER_INV_EQ_PARM Invalid EQ parameter (valid 0-4) + * \retval MYKONOS_ERR_DESER_INV_LANEPN_PARM Invalid PN invert setting, (valid 0-15, invert bit per lane) + * \retval MYKONOS_ERR_DES_HS_AND_LANE_RATE_NOT_INTEGER_MULT Invalid clock settings, HSCLK is not an integer multiple of lane rate + * + */ +mykonosErr_t MYKONOS_setupDeserializers(mykonosDevice_t *device) +{ + uint8_t lanePowerDown = 0xF; + uint8_t des_div = 0; + uint8_t des_div_bitfield = 0; + uint8_t rxcdr_div = 0; + uint8_t rxcdr_div_bitfield = 0; + uint32_t hsclkRate_kHz = 0; + uint8_t i = 0; + uint8_t L = 0; + uint32_t laneRate_kHz = 0; + uint8_t invertLanePolarity = 0; + uint8_t modHsLaneRate = 0; + + const uint32_t MAX_HSCLKRATE_KHZ = 12288000; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setupDeserializers()\n"); +#endif + + if ((device->profilesValid & TX_PROFILE_VALID) == 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INITDES_INV_TXPROFILE, + getMykonosErrorMessage(MYKONOS_ERR_INITDES_INV_TXPROFILE)); + return MYKONOS_ERR_INITDES_INV_TXPROFILE; + } + + if (device->tx->deframer->M != 2 && device->tx->deframer->M != 4) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DESER_INV_M_PARM, getMykonosErrorMessage(MYKONOS_ERR_DESER_INV_M_PARM)); + return MYKONOS_ERR_DESER_INV_M_PARM; + } + + for (i = 0; i < 4; i++) + { + L += ((device->tx->deframer->deserializerLanesEnabled >> i) & 0x01); + } + + if ((L == 0) || (L == 3) || (L > 4)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DESER_INV_L_PARM, getMykonosErrorMessage(MYKONOS_ERR_DESER_INV_L_PARM)); + return MYKONOS_ERR_DESER_INV_L_PARM; + } + + //laneRate_kHz calculation and checks + laneRate_kHz = device->tx->txProfile->iqRate_kHz * 20 * device->tx->deframer->M / L; + + if ((laneRate_kHz < 614400) || (laneRate_kHz > 6144000)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DESER_INV_LANERATE_PARM, + getMykonosErrorMessage(MYKONOS_ERR_DESER_INV_LANERATE_PARM)); + return MYKONOS_ERR_DESER_INV_LANERATE_PARM; + } + + if (device->tx->deframer->deserializerLanesEnabled > 15) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DESER_INV_LANEEN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_DESER_INV_LANEEN_PARM)); + return MYKONOS_ERR_DESER_INV_LANEEN_PARM; + } + + if ((device->tx->deframer->deserializerLanesEnabled == 0x7) || (device->tx->deframer->deserializerLanesEnabled == 0xB) + || (device->tx->deframer->deserializerLanesEnabled == 0xD) || (device->tx->deframer->deserializerLanesEnabled == 0xE)) + { + /* 3 lanes not valid, only 1,2, or 4 lanes */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DESER_INV_LANEEN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_DESER_INV_LANEEN_PARM)); + return MYKONOS_ERR_DESER_INV_LANEEN_PARM; + } + + if (device->tx->deframer->EQSetting > 4) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DESER_INV_EQ_PARM, getMykonosErrorMessage(MYKONOS_ERR_DESER_INV_EQ_PARM)); + return MYKONOS_ERR_DESER_INV_EQ_PARM; + } + + if (device->tx->deframer->invertLanePolarity > 15) + { + /* only lower 4 bits of parameter are valid */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DESER_INV_LANEPN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_DESER_INV_LANEPN_PARM)); + return MYKONOS_ERR_DESER_INV_LANEPN_PARM; + } + + //hsclkRate_kHz calculations + switch (device->clocks->clkPllVcoDiv) + { + case VCODIV_1: + hsclkRate_kHz = device->clocks->clkPllVcoFreq_kHz; + break; + case VCODIV_1p5: + hsclkRate_kHz = (device->clocks->clkPllVcoFreq_kHz / 15) * 10; + break; + case VCODIV_2: + hsclkRate_kHz = device->clocks->clkPllVcoFreq_kHz >> 1; + break; + case VCODIV_3: + hsclkRate_kHz = (device->clocks->clkPllVcoFreq_kHz / 30) * 10; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INITDES_INV_VCODIV_PARM, + getMykonosErrorMessage(MYKONOS_ERR_INITDES_INV_VCODIV_PARM)); + return MYKONOS_ERR_INITDES_INV_VCODIV_PARM; + } + + /* The deserializer clock needs to be in the range 3.8GHz to 6.144 GHz in reg x107. The rest of the division is in xDD */ + if (hsclkRate_kHz <= 6144000) + { + rxcdr_div = 1; + } + else if ((hsclkRate_kHz > 6144000) && (hsclkRate_kHz <= MAX_HSCLKRATE_KHZ)) + { + rxcdr_div = 2; + } + else if ((hsclkRate_kHz > MAX_HSCLKRATE_KHZ) && (hsclkRate_kHz < 24576000)) + { + rxcdr_div = 4; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DESER_INV_HSCLK_PARM, + getMykonosErrorMessage(MYKONOS_ERR_DESER_INV_HSCLK_PARM)); + return MYKONOS_ERR_DESER_INV_HSCLK_PARM; + } + + switch (rxcdr_div) + { + case 1: + rxcdr_div_bitfield = 0; + break; + case 2: + rxcdr_div_bitfield = 1; + break; + + default: + /* Default case is when rxcdr_div == 4 */ + rxcdr_div_bitfield = 2; + break; + } + + /* performing integer multiple check on HS clock and lane rate clock */ + modHsLaneRate = (uint8_t)(hsclkRate_kHz % laneRate_kHz); + if (modHsLaneRate) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DES_HS_AND_LANE_RATE_NOT_INTEGER_MULT, + getMykonosErrorMessage(MYKONOS_ERR_DES_HS_AND_LANE_RATE_NOT_INTEGER_MULT)); + return MYKONOS_ERR_DES_HS_AND_LANE_RATE_NOT_INTEGER_MULT; + } + + des_div = (uint8_t)(hsclkRate_kHz / laneRate_kHz / rxcdr_div); + + switch (des_div) + { + case 1: + des_div_bitfield = 0; + break; + case 2: + des_div_bitfield = 1; + break; + case 4: + des_div_bitfield = 2; + break; + case 8: + des_div_bitfield = 3; + break; + default: + des_div_bitfield = 0; + break; + } + + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_3, rxcdr_div_bitfield, 0x0C, 0x02); + + invertLanePolarity = (device->tx->deframer->invertLanePolarity & 0xF); + + lanePowerDown = (~(device->tx->deframer->deserializerLanesEnabled)) & 0xF; + + /* Deserializer: PLL clock enable */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DESERIALIZER_HS_DIV_RXCDR_CLK_EN, 0x01); + + /* Deserializer: Set Pdet control */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DESERIALIZER_PDET_CTL, 0x09); + + /* Deserializer: Set Power down control */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DESERIALIZER_CTL_0, (0x80U | lanePowerDown | (uint8_t)(des_div_bitfield << 4))); + + /* Deserializer: Set Sine Shape */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_0, 0x00); + + /* Deserializer: Set ss gain and vga */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_1, 0x00); + + /* Deserializer: Enable EQ, AC coupled JESD204B lanes */ + /* TODO: add ability to set this for AC coupling or DC coupling */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1, 0x07); + + /* Deserializer: Clear Data present at negedge, disable peak adjust */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DESERIALIZER_MISC_CTL, 0x04); + + /* Deserializer: Set Equalizer for lanes 1 and 0 */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1_TO_0, ((uint8_t)(device->tx->deframer->EQSetting << 3) | device->tx->deframer->EQSetting)); + + /* Deserializer: Set Equalizer for lanes 2 and 3 */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DESERIALIZER_EQ_CTL_3_TO_2, ((uint8_t)(device->tx->deframer->EQSetting << 3) | device->tx->deframer->EQSetting)); + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_LANE_DATA_CTL, invertLanePolarity); + + /* Reset Deserializers - toggle resetb bit in [0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DESERIALIZER_SPECIAL, 0x00); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DESERIALIZER_SPECIAL, 0x01); + + /* Start ALC cal */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DESERIALIZER_CDR_CAL_CTL, 0x02); + + /* Deframer: Enable clocks and lane clocks */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_CLK_EN, 0x03); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets up the JESD204B Framer + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * - device->rx->framer->M + * - device->rx->realIfData + * - device->rx->framer->bankId + * - device->rx->framer->lane0Id + * - device->rx->framer->serializerLanesEnabled + * - device->rx->framer->obsRxSyncbSelect + * - device->rx->framer->K + * - device->rx->framer->externalSysref + * - device->rx->rxChannels + * - device->rx->framer->newSysrefOnRelink + * - device->rx->framer->enableAutoChanXbar + * - device->rx->framer->lmfcOffset + * - device->rx->framer->scramble + * + * \param device Pointer to the device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_FRAMER_INV_REAL_IF_DATA_PARM Invalid framer M, M can only = 1 in real IF mode + * \retval MYKONOS_ERR_FRAMER_INV_M_PARM Invalid framer M (valid 1,2,4) + * \retval MYKONOS_ERR_FRAMER_INV_BANKID_PARM Invalid BankId (valid 0-15) + * \retval MYKONOS_ERR_FRAMER_INV_LANEID_PARM Invalid Lane0Id (valid 0-31) + * \retval MYKONOS_ERR_RXFRAMER_INV_FK_PARAM + * \retval MYKONOS_ERR_FRAMER_INV_K_OFFSET_PARAM + */ +mykonosErr_t MYKONOS_setupJesd204bFramer(mykonosDevice_t *device) +{ + uint8_t i = 0; + uint8_t fifoLaneEnable = 0; + uint8_t L = 0; + uint8_t ML = 0; + uint8_t framerConfigF = 0; + + uint8_t subaddr[29] = {0}; /* holds address to framer sub register map */ + uint8_t subdata[29] = {0}; /* holds data for framer sub register map */ + + /* Setup submap registers */ + uint8_t SUBCLASSV = 1; /* JESD subclass 1 */ + uint8_t JESDV = 1; /* Version: JESD204B */ + uint8_t DID = 0; + uint8_t BID = 0; + uint8_t LID0 = 0; + uint8_t LID1 = 1; + uint8_t LID2 = 2; + uint8_t LID3 = 3; + uint8_t CS = 0; + uint8_t N = 0x0F; + uint8_t Np = 0x0F; + uint8_t S = 0; + uint8_t CF = 0; + uint8_t K = 31; + uint8_t HD = 0; + uint8_t FramerL = 1; + uint8_t FramerM = 2; + uint8_t FramerF = 1; + uint8_t framerADC_XBar = 0xE4; + uint16_t FK = 0; + + uint8_t regE0 = 0; + uint8_t regE2 = 0; + uint8_t framerLaneXbar = 0xE4; + uint16_t CheckSum = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setupJesd204bFramer()\n"); +#endif + + if (device->rx->framer->M == 1 && !(device->rx->realIfData)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FRAMER_INV_REAL_IF_DATA_PARM, + getMykonosErrorMessage(MYKONOS_ERR_FRAMER_INV_REAL_IF_DATA_PARM)); + return MYKONOS_ERR_FRAMER_INV_REAL_IF_DATA_PARM; + } + + if (device->rx->framer->M != 1 && device->rx->framer->M != 2 && device->rx->framer->M != 4) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FRAMER_INV_M_PARM, getMykonosErrorMessage(MYKONOS_ERR_FRAMER_INV_M_PARM)); + return MYKONOS_ERR_FRAMER_INV_M_PARM; + } + + if (device->rx->framer->bankId > 15) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FRAMER_INV_BANKID_PARM, + getMykonosErrorMessage(MYKONOS_ERR_FRAMER_INV_BANKID_PARM)); + return MYKONOS_ERR_FRAMER_INV_BANKID_PARM; + } + + /* no need to check deviceId, its range is full uint8_t range */ + if (device->rx->framer->lane0Id > 31) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FRAMER_INV_LANEID_PARM, + getMykonosErrorMessage(MYKONOS_ERR_FRAMER_INV_LANEID_PARM)); + return MYKONOS_ERR_FRAMER_INV_LANEID_PARM; + } + + //count number of lanes + L = 0; + ML = 0; + + for (i = 0; i < 4; i++) + { + L += ((device->rx->framer->serializerLanesEnabled >> i) & 0x01); + } + ML = (uint8_t)(device->rx->framer->M * 10) + L; + + FK = (uint16_t)(device->rx->framer->K * 2 * device->rx->framer->M / L); + + if (FK < 20 || FK > 256 || FK % 4 != 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RXFRAMER_INV_FK_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_RXFRAMER_INV_FK_PARAM)); + return MYKONOS_ERR_RXFRAMER_INV_FK_PARAM; + } + + if (device->rx->framer->externalSysref == 0) + { + /* Framer: Generate SYSREF internally */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_TEST_CNTR_CTL, 0x20); + } + + framerADC_XBar = 0xB1; + if (ML == 24) + { + if (device->rx->rxChannels == RX1) + { + /* adc 0 and 2 used */ + framerADC_XBar = ((framerADC_XBar & 0x0C) << 2) | (framerADC_XBar & 0x03); + } + else if (device->rx->rxChannels == RX2) + { + /* swap ADC xbar for Rx1 and Rx2 */ + framerADC_XBar = ((framerADC_XBar & 0xF) << 4) | ((framerADC_XBar & 0xF0) >> 4); + /* adc 0 and 2 used */ + framerADC_XBar = ((framerADC_XBar & 0x0C) << 2) | (framerADC_XBar & 0x03); + } + + /* Framer: Set ADC Crossbar */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_ADC_XBAR_SEL, framerADC_XBar); + } + else + { + /* Framer: Set ADC Crossbar */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_ADC_XBAR_SEL, framerADC_XBar); + } + + if (device->rx->framer->enableManualLaneXbar == 1) + { + framerLaneXbar = device->rx->framer->serializerLaneCrossbar; + } + else + { + if (ML == 42) + { + /* uses framer outputs 0 and 2 instead of 0 and 1...fix framer lane XBar */ + /* only 2 lane cases here */ + switch ((device->rx->framer->serializerLanesEnabled & 0x0F)) + { + case 3: + framerLaneXbar = 0x08; + break; + case 5: + framerLaneXbar = 0x20; + break; + case 6: + framerLaneXbar = 0x20; + break; + case 9: + framerLaneXbar = 0x80; + break; + case 10: + framerLaneXbar = 0x80; + break; + case 12: + framerLaneXbar = 0x80; + break; + default: + /* default to valid setting for Lane 0 */ + framerLaneXbar = 0x08; + break; + } + } + else + { + switch ((device->rx->framer->serializerLanesEnabled & 0x0F)) + { + /* all 4 lanes get framer 0 output */ + case 1: + framerLaneXbar = 0x00; + break; + case 2: + framerLaneXbar = 0x00; + break; + case 3: + framerLaneXbar = 0x04; + break; + case 4: + framerLaneXbar = 0x00; + break; + case 5: + framerLaneXbar = 0x10; + break; + case 6: + framerLaneXbar = 0x10; + break; + case 8: + framerLaneXbar = 0x00; + break; + case 9: + framerLaneXbar = 0x40; + break; + case 10: + framerLaneXbar = 0x40; + break; + case 12: + framerLaneXbar = 0x40; + break; + case 15: + framerLaneXbar = 0xE4; + break; + default: + /* default to valid setting for all Lanes */ + framerLaneXbar = 0xE4; + break; + } + } + } + + /* Framer: Set Lane Crossbar */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_LANE_XBAR_SEL, framerLaneXbar); + + if (ML == 24) + { + /* Framer: Clear ADC Xbar channel auto switch */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_CONFIG_LOOPBACK_XBAR_REV, 0x00); + } + else + { + /* Framer: Set ADC Xbar channel auto switch */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_CONFIG_LOOPBACK_XBAR_REV, 0x04); + } + + /* enabling the SYSREF for relink if newSysrefOnRelink is set */ + if (device->rx->framer->newSysrefOnRelink) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_FRAMER_SYSREF_FIFO_EN, 0x01, 0x40, 6); + } + + /* enabling auto channel if the enableAutoChanXbar structure member is set */ + if (device->rx->framer->enableAutoChanXbar) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_FRAMER_CONFIG_LOOPBACK_XBAR_REV, 0x01, 0x04, 2); + } + + /* determining F octets per frame based on 2*M/L */ + framerConfigF = (uint8_t)(2 * (device->rx->framer->M / L)); + + /* Framer: Soft Reset */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_RESET, 0x03); + + /* Framer: Clear Soft Reset */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_RESET, 0x00); + + /* Framer: Set F (Octets in Frame) */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_CONFIG_F, framerConfigF); + + /* Framer: Enable framer clock and lane clocks */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_FRAMER_CLK_EN, 0x03, 0x03, 0); + + /* Set Framer lane FIFO enable for each lane enabled */ + fifoLaneEnable = (((device->rx->framer->serializerLanesEnabled & 0x0F) << 4) | 0x01); + + /* Framer: Enable Lane FIFOs */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_LANE_CTL, fifoLaneEnable); + + /* Setup submap registers */ + SUBCLASSV = 1; /* JESD subclass 1 */ + JESDV = 1; /* Version: JESD204B */ + DID = device->rx->framer->deviceId; + BID = device->rx->framer->bankId; + LID0 = device->rx->framer->lane0Id; + LID1 = device->rx->framer->lane0Id + 1; + LID2 = device->rx->framer->lane0Id + 2; + LID3 = device->rx->framer->lane0Id + 3; + + CS = 0; + N = 0x0F; + Np = 0x0F; + S = 0; + CF = 0; + HD = 0; + K = device->rx->framer->K - 1; + FramerL = L - 1; + FramerM = device->rx->framer->M - 1; + FramerF = (uint8_t)(2 * device->rx->framer->M / L) - 1; + + if (ML == 11) + { + regE0 = 0x01; + regE2 = 0x01; + } + else if (ML == 12) + { + regE0 = 0x01; + regE2 = 0x03; + HD = 0x01; + } + else if (ML == 21) + { + regE0 = 0x03; + regE2 = 0x01; + } + else if (ML == 22) + { + regE0 = 0x03; + regE2 = 0x03; + } + else if (ML == 24) + { + regE0 = 0x05; + regE2 = 0x0F; + HD = 0x01; + } + else if (ML == 41) + { + regE0 = 0x0F; + regE2 = 0x01; + } + else if (ML == 42) + { + regE0 = 0x0F; + regE2 = 0x05; + } + else if (ML == 44) + { + regE0 = 0x0F; + regE2 = 0x0F; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FRAMER_INV_M_PARM, getMykonosErrorMessage(MYKONOS_ERR_FRAMER_INV_M_PARM)); + return MYKONOS_ERR_FRAMER_INV_M_PARM; + } + + /* setting K offset for framer */ + if (device->rx->framer->lmfcOffset < device->rx->framer->K) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_LMFC_K_OFFSET, device->rx->framer->lmfcOffset); + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FRAMER_INV_K_OFFSET_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_FRAMER_INV_K_OFFSET_PARAM)); + return MYKONOS_ERR_FRAMER_INV_K_OFFSET_PARAM; + } + + subaddr[0] = 0x00; + subdata[0] = (DID & 0xFF); /* Device ID */ + subaddr[1] = 0x01; + subdata[1] = (BID & 0x0F); /* Bank ID */ + subaddr[2] = 0x02; + subdata[2] = (LID0 & 0x1F); /* Lane 0 ID */ + subaddr[3] = 0x03; + subdata[3] = (uint8_t)(device->rx->framer->scramble << 7) | (FramerL & 0x1F); /* [7] Scramble, #Lanes[4:0]-1 */ + subaddr[4] = 0x04; + subdata[4] = (FramerF & 0xFF); /* F[7:0]-1 */ + subaddr[5] = 0x05; + subdata[5] = (K & 0x1F); /* K[4:0]-1 */ + subaddr[6] = 0x06; + subdata[6] = (FramerM & 0xFF); /* M[7:0]-1 */ + subaddr[7] = 0x07; + subdata[7] = ((CS & 0x3) << 6) | (N & 0x1F); /* [7:6] = CS[1:0], N[4:0]-1 */ + subaddr[8] = 0x08; + subdata[8] = ((SUBCLASSV & 7) << 5) | (Np & 0x1F); /* NP[4:0] -1 */ + subaddr[9] = 0x09; + subdata[9] = ((JESDV & 7) << 5) | (S & 0x1F); /* S[4:0]-1 */ + subaddr[10] = 0x0A; + subdata[10] = ((HD & 1) << 7) | (CF & 0x1F); /* [7] = HD, CF[4:0] */ + subaddr[11] = 0x0B; + subdata[11] = 0x00; /* reserved */ + subaddr[12] = 0x0C; + subdata[12] = 0x00; /* reserved */ + + CheckSum = (DID & 0xFF) + (BID & 0xF) + (LID0 & 0x1F) + (device->rx->framer->scramble) + (FramerL & 0x1F) + (FramerF & 0xFF) + (K & 0x1F) + (FramerM & 0xFF) + + (CS & 0x3) + (N & 0x1F) + (Np & 0x1F) + (S & 0x1F) + (HD & 1) + (CF & 0x1F) + (SUBCLASSV & 7) + (JESDV & 7); + + /* Checksum Lane 0 */ + subaddr[13] = 0x0D; + subdata[13] = CheckSum & 0xFF; + + /* in JESD204B ML=42 case, framer ip lanes 0 and 2 are used, write lane 1 id and checksum to ip lane 2 regs */ + if (ML == 42) + { + /* Lane 1 ID */ + subaddr[14] = 0x1A; + subdata[14] = LID1; + + CheckSum = (DID & 0xFF) + (BID & 0xF) + (LID1 & 0x1F) + (device->rx->framer->scramble) + (FramerL & 0x1F) + (FramerF & 0xFF) + (K & 0x1F) + (FramerM & 0xFF) + + (CS & 0x3) + (N & 0x1F) + (Np & 0x1F) + (S & 0x1F) + (HD & 1) + (CF & 0x1F) + (SUBCLASSV & 7) + (JESDV & 7); + + /* Checksum Lane 1 */ + subaddr[15] = 0x1D; + subdata[15] = CheckSum & 0xFF; + } + else + { + /* Lane 1 ID */ + subaddr[14] = 0x12; + subdata[14] = LID1; + + CheckSum = (DID & 0xFF) + (BID & 0xF) + (LID1 & 0x1F) + (device->rx->framer->scramble) + (FramerL & 0x1F) + (FramerF & 0xFF) + (K & 0x1F) + (FramerM & 0xFF) + + (CS & 0x3) + (N & 0x1F) + (Np & 0x1F) + (S & 0x1F) + (HD & 1) + (CF & 0x1F) + (SUBCLASSV & 7) + (JESDV & 7); + + /* Checksum Lane 1 */ + subaddr[15] = 0x15; + subdata[15] = CheckSum & 0xFF; + + /* Lane 2 ID */ + subaddr[16] = 0x1A; + subdata[16] = LID2; + + CheckSum = (DID & 0xFF) + (BID & 0xF) + (LID2 & 0x1F) + (device->rx->framer->scramble) + (FramerL & 0x1F) + (FramerF & 0xFF) + (K & 0x1F) + (FramerM & 0xFF) + + (CS & 0x3) + (N & 0x1F) + (Np & 0x1F) + (S & 0x1F) + (HD & 1) + (CF & 0x1F) + (SUBCLASSV & 7) + (JESDV & 7); + + /* Checksum Lane 2 */ + subaddr[17] = 0x1D; + subdata[17] = CheckSum & 0xFF; + + /* Lane 3 ID */ + subaddr[18] = 0x22; + subdata[18] = LID3; + + CheckSum = (DID & 0xFF) + (BID & 0xF) + (LID3 & 0x1F) + (device->rx->framer->scramble) + (FramerL & 0x1F) + (FramerF & 0xFF) + (K & 0x1F) + (FramerM & 0xFF) + + (CS & 0x3) + (N & 0x1F) + (Np & 0x1F) + (S & 0x1F) + (HD & 1) + (CF & 0x1F) + (SUBCLASSV & 7) + (JESDV & 7); + + subaddr[19] = 0x25; + subdata[19] = CheckSum & 0xFF; + } + + subaddr[20] = 0xE0; + subdata[20] = regE0; /* Enable converter n logic */ + subaddr[21] = 0xE2; + subdata[21] = regE2; /* Enable Lane n logic */ + subaddr[22] = 0xE4; + subdata[22] = 0x00; + subaddr[23] = 0xE6; + subdata[23] = 0x00; + subaddr[24] = 0xF0; + subdata[24] = 0x00; /* #multiframes in ILAS */ + subaddr[25] = 0xF2; + subdata[25] = 0x00; + subaddr[26] = 0xF3; + subdata[26] = 0x00; + subaddr[27] = 0xF4; + subdata[27] = 0x00; + subaddr[28] = 0xC0; + subdata[28] = 0x03; /* Framer enable, both sides perform lane sync */ + + for (i = 0; i <= 28; i++) + { + /* Set framer sub register map address */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_ADDR, subaddr[i]); + + /* Set framer sub register map data word */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_DATA, subdata[i]); + + /* Write enable */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_WRITE_EN, 0x01); + } + + if (device->rx->framer->externalSysref > 0) + { + /* Framer: Enable lane FIFO sync (Enable CGS) */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_SYSREF_FIFO_EN, 0x30); + } + else + { + /* Framer: Enable lane FIFO sync (Enable CGS) */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_SYSREF_FIFO_EN, 0x10); + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets up the JESD204B OBSRX Framer + * + * Dependencies + * - device->rxChannels + * - device->spiSettings->chipSelectIndex + * - device->obsRx->framer->bankId + * - device->obsRx->framer->M + * - device->obsRx->framer->serializerLanesEnabled + * - device->obsRx->framer->externalSysref + * - device->spiSettings + * - device->obsRx->framer->deviceId + * - device->obsRx->framer->lane0Id + * - device->obsRx->framer->K + * - device->obsRx->framer->lmfcOffset + * - device->obsRx->framer->scramble + * - device->obsRx->framer->obsRxSyncbSelect + * + * \param device Pointer to the device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_OBSRX_FRAMER_INV_REAL_IF_DATA_PARM M parameter can only be 1 when real IF data mode is enabled + * \retval MYKONOS_ERR_OBSRX_FRAMER_INV_M_PARM ObsRx Framer M parameter can only be 1 or 2 + * \retval MYKONOS_ERR_OBSRX_FRAMER_INV_BANKID_PARM Invalid BankId (0-15) + * \retval MYKONOS_ERR_OBSRX_FRAMER_INV_LANEID_PARM Invalid lane0Id (0-31) + * \retval MYKONOS_ERR_OBSRXFRAMER_INV_FK_PARAM Invalid F*K value (F * K must be > 20 and divisible by 4) + * \retval MYKONOS_ERR_OBSRX_FRAMER_INV_K_OFFSET_PARAM Invalid K offset, must be less than K + */ +mykonosErr_t MYKONOS_setupJesd204bObsRxFramer(mykonosDevice_t *device) +{ + uint8_t i = 0; + uint8_t laneFifoEnable = 0; + uint8_t L = 1; + uint8_t ML = 2; + uint8_t framerConfigF = 0; + + uint8_t subaddr[29] = {0}; /* holds address to framer sub register map */ + uint8_t subdata[29] = {0}; /* holds data for framer sub register map */ + + /* Setup submap registers */ + uint8_t SUBCLASSV = 1; /* JESD subclass 1 */ + uint8_t JESDV = 1; /* Version: JESD204B */ + uint8_t DID = 0; + uint8_t BID = 0; + uint8_t LID0 = 0; + uint8_t LID1 = 1; + uint8_t LID2 = 2; + uint8_t LID3 = 3; + uint8_t CS = 0; + uint8_t N = 0x0F; + uint8_t Np = 0x0F; + uint8_t S = 0; + uint8_t CF = 0; + uint8_t K = 31; + uint8_t HD = 0; + uint8_t FramerL = 1; + uint8_t FramerM = 2; + uint8_t FramerF = 1; + uint8_t framerADC_XBar = 0xE4; + uint8_t regE0 = 0; + uint8_t regE2 = 0; + uint8_t framerLaneXbar = 0xE4; + uint16_t CheckSum = 0; + uint16_t FK = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setupJesd204bObsRxFramer()\n"); +#endif + + if (device->obsRx->framer->M == 1 && !(device->obsRx->realIfData)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBSRX_FRAMER_INV_REAL_IF_DATA_PARM, + getMykonosErrorMessage(MYKONOS_ERR_OBSRX_FRAMER_INV_REAL_IF_DATA_PARM)); + return MYKONOS_ERR_OBSRX_FRAMER_INV_REAL_IF_DATA_PARM; + } + + if (device->obsRx->framer->M != 1 && device->obsRx->framer->M != 2) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBSRX_FRAMER_INV_M_PARM, + getMykonosErrorMessage(MYKONOS_ERR_OBSRX_FRAMER_INV_M_PARM)); + return MYKONOS_ERR_OBSRX_FRAMER_INV_M_PARM; + } + + if (device->obsRx->framer->bankId > 15) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBSRX_FRAMER_INV_BANKID_PARM, + getMykonosErrorMessage(MYKONOS_ERR_OBSRX_FRAMER_INV_BANKID_PARM)); + return MYKONOS_ERR_OBSRX_FRAMER_INV_BANKID_PARM; + } + + /* no need to check deviceId, its range is full uint8_t range */ + if (device->obsRx->framer->lane0Id > 31) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBSRX_FRAMER_INV_LANEID_PARM, + getMykonosErrorMessage(MYKONOS_ERR_OBSRX_FRAMER_INV_LANEID_PARM)); + return MYKONOS_ERR_OBSRX_FRAMER_INV_LANEID_PARM; + } + + //count number of lanes + L = 0; + ML = 0; + + for (i = 0; i < 4; i++) + { + L += ((device->obsRx->framer->serializerLanesEnabled >> i) & 0x01); + } + + ML = (uint8_t)(device->obsRx->framer->M * 10 + L); + + if (L == 0) + { + /* Disable framer and return successfully */ + /* Disable framer clock and lane clocks */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_CLK_EN, 0, 0x03, 0); + + /* Disable lane FIFO enables */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_LANE_CTL, 0, 0xF0, 4); + return MYKONOS_ERR_OK; + } + + FK = (uint16_t)(device->obsRx->framer->K * 2 * device->obsRx->framer->M / L); + if (FK < 20 || FK > 256 || FK % 4 != 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBSRXFRAMER_INV_FK_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_OBSRXFRAMER_INV_FK_PARAM)); + return MYKONOS_ERR_OBSRXFRAMER_INV_FK_PARAM; + } + + if (device->obsRx->framer->externalSysref == 0) + { + /* Framer: Generate SYSREF internally */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_TEST_CNTR_CTL, 0x20); + } + + /* Framer: Set ADC Crossbar */ + framerADC_XBar = 0xB1; + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_ADC_XBAR_SEL, framerADC_XBar); + + if (device->obsRx->framer->enableManualLaneXbar == 1) + { + framerLaneXbar = device->obsRx->framer->serializerLaneCrossbar; + } + else + { + if (ML == 42) + { + /* uses framer outputs 0 and 2 instead of 0 and 1...fix framer lane XBar */ + /* only 2 lane cases here */ + switch ((device->obsRx->framer->serializerLanesEnabled & 0x0F)) + { + case 3: + framerLaneXbar = 0x08; + break; + case 5: + framerLaneXbar = 0x20; + break; + case 6: + framerLaneXbar = 0x20; + break; + case 9: + framerLaneXbar = 0x80; + break; + case 10: + framerLaneXbar = 0x80; + break; + case 12: + framerLaneXbar = 0x80; + break; + default: + /* default to valid setting for Lane 0 */ + framerLaneXbar = 0x08; + break; + } + } + else + { + switch ((device->obsRx->framer->serializerLanesEnabled & 0x0F)) + { + /* all 4 lanes get framer 0 output */ + case 1: + framerLaneXbar = 0x00; + break; + case 2: + framerLaneXbar = 0x00; + break; + case 3: + framerLaneXbar = 0x04; + break; + case 4: + framerLaneXbar = 0x00; + break; + case 5: + framerLaneXbar = 0x10; + break; + case 6: + framerLaneXbar = 0x10; + break; + case 8: + framerLaneXbar = 0x00; + break; + case 9: + framerLaneXbar = 0x40; + break; + case 10: + framerLaneXbar = 0x40; + break; + case 12: + framerLaneXbar = 0x40; + break; + case 15: + framerLaneXbar = 0xE4; + break; + default: + /* default to valid setting for all Lanes */ + framerLaneXbar = 0xE4; + break; + } + } + } + + /* Framer: set Lane Crossbar */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_LANE_XBAR_SEL, framerLaneXbar); + + /* Framer: determine the framerConfigF value (2*M/L) */ + framerConfigF = (uint8_t)(2 * (device->obsRx->framer->M/L)); + + /* Framer: Soft Reset */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_RESET, 0x03); + + /* Framer: Clear Soft Reset */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_RESET, 0x00); + + /* Framer: Set F (Octets in Frame) */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_CONFIG_F, framerConfigF); + + /* Framer: Enable framer clock and lane clocks */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_CLK_EN, 0x03, 0x03, 0); + + /* Set Framer lane FIFO enable for each lane enabled */ + laneFifoEnable = (uint8_t)(((device->obsRx->framer->serializerLanesEnabled & 0x0F) << 4) | 0x01); + + /* Framer: Enable Lane FIFOs */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_LANE_CTL, laneFifoEnable); + + /* enabling the SYSREF for relink if newSysrefOnRelink is set */ + if (device->obsRx->framer->newSysrefOnRelink) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_SYSREF_FIFO_EN, 0x01, 0x40, 6); + } + + /* enabling auto channel if the enableAutoChanXbar structure member is set */ + if (device->obsRx->framer->enableAutoChanXbar) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_CONFIG_LOOPBACK_XBAR_REV, 0x01, 0x04, 2); + } + + /* Setup submap registers */ + SUBCLASSV = 1; /* JESD subclass 1 */ + JESDV = 1; /* Version: JESD204B */ + DID = device->obsRx->framer->deviceId; + BID = device->obsRx->framer->bankId; + LID0 = device->obsRx->framer->lane0Id; + LID1 = device->obsRx->framer->lane0Id + 1; + LID2 = device->obsRx->framer->lane0Id + 2; + LID3 = device->obsRx->framer->lane0Id + 3; + + CS = 0; + N = 0x0F; + Np = 0x0F; + S = 0; + CF = 0; + K = device->obsRx->framer->K - 1; + HD = 0; + FramerL = L - 1; + FramerM = device->obsRx->framer->M - 1; + FramerF = (uint8_t)((2*device->obsRx->framer->M/L) - 1); + + if (ML == 11) + { + regE0 = 0x1; + regE2 = 0x1; + } + else if (ML == 12) + { + regE0 = 0x1; + regE2 = 0x3; + HD = 1; + } + else if (ML == 21) + { + regE0 = 0x3; + regE2 = 0x1; + } + else if (ML == 22) + { + regE0 = 0x3; + regE2 = 0x3; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBSRX_FRAMER_INV_M_PARM, + getMykonosErrorMessage(MYKONOS_ERR_OBSRX_FRAMER_INV_M_PARM)); + return MYKONOS_ERR_OBSRX_FRAMER_INV_M_PARM; + } + + /* setting K offset for framer */ + if (device->obsRx->framer->lmfcOffset < device->rx->framer->K) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_LMFC_K_OFFSET, device->obsRx->framer->lmfcOffset); + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBSRX_FRAMER_INV_K_OFFSET_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_OBSRX_FRAMER_INV_K_OFFSET_PARAM)); + return MYKONOS_ERR_OBSRX_FRAMER_INV_K_OFFSET_PARAM; + } + + subaddr[0] = 0x00; + subdata[0] = (DID & 0xFF); /* Device ID */ + subaddr[1] = 0x01; + subdata[1] = (BID & 0x0F); /* Bank ID */ + subaddr[2] = 0x02; + subdata[2] = (LID0 & 0x1F); /* Lane 0 ID */ + subaddr[3] = 0x03; + subdata[3] = (uint8_t)(device->obsRx->framer->scramble << 7) | (FramerL & 0x1F); /* [7] Scramble, #Lanes[4:0]-1 */ + subaddr[4] = 0x04; + subdata[4] = (FramerF & 0xFF); /* F[7:0]-1 */ + subaddr[5] = 0x05; + subdata[5] = (K & 0x1F); /* K[4:0]-1 */ + subaddr[6] = 0x06; + subdata[6] = (FramerM & 0xFF); /* M[7:0]-1 */ + subaddr[7] = 0x07; + subdata[7] = ((CS & 0x3) << 6) | (N & 0x1F); /* [7:6] = CS[1:0], N[4:0]-1 */ + subaddr[8] = 0x08; + subdata[8] = ((SUBCLASSV & 7) << 5) | (Np & 0x1F); /* NP[4:0] -1 */ + subaddr[9] = 0x09; + subdata[9] = ((JESDV & 7) << 5) | (S & 0x1F); /* S[4:0]-1 */ + subaddr[10] = 0x0a; + subdata[10] = ((HD & 1) << 7) | (CF & 0x1F); /* [7] = HD, CF[4:0] */ + subaddr[11] = 0x0b; + subdata[11] = 0x00; /* reserved */ + subaddr[12] = 0x0c; + subdata[12] = 0x00; /* reserved */ + + CheckSum = (DID & 0xFF) + (BID & 0xF) + (LID0 & 0x1F) + (device->obsRx->framer->scramble) + (FramerL & 0x1F) + (FramerF & 0xFF) + (K & 0x1F) + (FramerM & 0xFF) + + (CS & 0x3) + (N & 0x1F) + (Np & 0x1F) + (S & 0x1F) + (HD & 1) + (CF & 0x1F) + (SUBCLASSV & 7) + (JESDV & 7); + + /* Checksum Lane 0 */ + subaddr[13] = 0x0d; + subdata[13] = CheckSum & 0xFF; + + /* Lane 1 ID */ + subaddr[14] = 0x12; + subdata[14] = LID1; + + CheckSum = (DID & 0xFF) + (BID & 0xF) + (LID1 & 0x1F) + (device->obsRx->framer->scramble) + (FramerL & 0x1F) + (FramerF & 0xFF) + (K & 0x1F) + (FramerM & 0xFF) + + (CS & 0x3) + (N & 0x1F) + (Np & 0x1F) + (S & 0x1F) + (HD & 1) + (CF & 0x1F) + (SUBCLASSV & 7) + (JESDV & 7); + + /* Checksum Lane 1 */ + subaddr[15] = 0x15; + subdata[15] = CheckSum & 0xFF; + + /* Lane 2 ID */ + subaddr[16] = 0x1a; + subdata[16] = LID2; + + CheckSum = (DID & 0xFF) + (BID & 0xF) + (LID2 & 0x1F) + (device->obsRx->framer->scramble) + (FramerL & 0x1F) + (FramerF & 0xFF) + (K & 0x1F) + (FramerM & 0xFF) + + (CS & 0x3) + (N & 0x1F) + (Np & 0x1F) + (S & 0x1F) + (HD & 1) + (CF & 0x1F) + (SUBCLASSV & 7) + (JESDV & 7); + + /* Checksum Lane 2 */ + subaddr[17] = 0x1d; + subdata[17] = CheckSum & 0xFF; + + /* Lane 3 ID */ + subaddr[18] = 0x22; + subdata[18] = LID3; + + CheckSum = (DID & 0xFF) + (BID & 0xF) + (LID3 & 0x1F) + (device->obsRx->framer->scramble) + (FramerL & 0x1F) + (FramerF & 0xFF) + (K & 0x1F) + (FramerM & 0xFF) + + (CS & 0x3) + (N & 0x1F) + (Np & 0x1F) + (S & 0x1F) + (HD & 1) + (CF & 0x1F) + (SUBCLASSV & 7) + (JESDV & 7); + + subaddr[19] = 0x25; + subdata[19] = CheckSum & 0xFF; + + subaddr[20] = 0xe0; + subdata[20] = regE0; /* Enable converter n logic */ + subaddr[21] = 0xe2; + subdata[21] = regE2; /* Enable Lane n logic */ + subaddr[22] = 0xe4; + subdata[22] = 0x00; + subaddr[23] = 0xe6; + subdata[23] = 0x00; + subaddr[24] = 0xf0; + subdata[24] = 0x00; /* #multiframes in ILAS */ + subaddr[25] = 0xf2; + subdata[25] = 0x00; + subaddr[26] = 0xf3; + subdata[26] = 0x00; + subaddr[27] = 0xf4; + subdata[27] = 0x00; + subaddr[28] = 0xc0; + subdata[28] = 0x03; /* Framer enable, both sides perform lane sync */ + + for (i = 0; i <= 28; i++) + { + /* Set framer sub register map address */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_ADDR, subaddr[i]); + + /* Set framer sub register map data word */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_DATA, subdata[i]); + + /* Write enable */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_WRITE_EN, 0x01); + } + + if (device->obsRx->framer->externalSysref > 0) + { + /* Framer: Enable lane FIFO sync (Enable CGS) */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_SYSREF_FIFO_EN, 0x30); + } + else + { + /* Framer: Enable lane FIFO sync (Enable CGS) */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_SYSREF_FIFO_EN, 0x10); + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Enables/Disables the JESD204B Rx Framer + * + * This function is normally not necessary. In the event that the link needs to be reset, this + * function allows the Rx framer to be disabled and re-enabled. + * + * Dependencies + * - device->spiSettings + * - device->rx->framer->serializerLanesEnabled + * + * \param device is a pointer to the device settings structure + * \param enable 0 = Disable the selected framer, 1 = enable the selected framer link + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_ENFRAMERLINK_INV_LANESEN_PARM Invalid serializerLanesEnabled parameter in device data structure + */ +mykonosErr_t MYKONOS_enableRxFramerLink(mykonosDevice_t *device, uint8_t enable) +{ + uint8_t enableLink = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableFramerLink()\n"); +#endif + + enableLink = (enable > 0) ? 1 : 0; + + if (enableLink) + { + /* Power Up serializer lanes */ + if (device->rx->framer->serializerLanesEnabled > 15) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ENFRAMERLINK_INV_LANESEN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_ENFRAMERLINK_INV_LANESEN_PARM)); + return MYKONOS_ERR_ENFRAMERLINK_INV_LANESEN_PARM; + } + + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_SERIALIZER_CTL_1, ((~device->rx->framer->serializerLanesEnabled) & 0x0F), + device->rx->framer->serializerLanesEnabled, 0); + + /* Enable Clocks to Framer */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_FRAMER_CLK_EN, 3, 0x03, 0); + + /* Release reset to framer and lane FIFOs */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_RESET, 0x00); + } + else + { + /* Disable Link */ + /* Hold Rx framer in reset */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_RESET, 0x03); + + /* Disable Clocks to Framer */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_FRAMER_CLK_EN, 0, 0x03, 0); + + /* Power down serializer lanes */ + if (device->rx->framer->serializerLanesEnabled > 15) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ENFRAMERLINK_INV_LANESEN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_ENFRAMERLINK_INV_LANESEN_PARM)); + return MYKONOS_ERR_ENFRAMERLINK_INV_LANESEN_PARM; + } + + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_SERIALIZER_CTL_1, device->rx->framer->serializerLanesEnabled, device->rx->framer->serializerLanesEnabled, 0); + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Enables/Disables the JESD204B ObsRx Framer + * + * This function is normally not necessary. In the event that the link needs to be reset, this + * function allows the ObsRx framer to be disabled and re-enabled. + * + * Dependencies + * - device->spiSettings + * - device->obsRx->framer->serializerLanesEnabled + * + * \param device is a pointer to the device settings structure + * \param enable 0 = Disable the selected framer, 1 = enable the selected framer link + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_ENFRAMERLINK_INV_LANESEN_PARM Invalid serializerLanesEnabled parameter in device data structure (Valid 0-15) + */ +mykonosErr_t MYKONOS_enableObsRxFramerLink(mykonosDevice_t *device, uint8_t enable) +{ + uint8_t enableLink = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableObsRxFramerLink()\n"); +#endif + + enableLink = (enable > 0) ? 1 : 0; + + if (enableLink) + { + /* Power Up serializer lanes */ + if (device->rx->framer->serializerLanesEnabled > 15) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ENOBSFRAMERLINK_INV_LANESEN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_ENOBSFRAMERLINK_INV_LANESEN_PARM)); + return MYKONOS_ERR_ENOBSFRAMERLINK_INV_LANESEN_PARM; + } + + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_SERIALIZER_CTL_1, ((~device->obsRx->framer->serializerLanesEnabled) & 0x0F), + device->obsRx->framer->serializerLanesEnabled, 0); + + /* Enable Clocks to Framer */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_CLK_EN, 3, 0x03, 0); + + /* Release reset to framer and lane FIFOs */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_RESET, 0x00); + } + else + { + /* Disable Link */ + /* Hold Rx framer in reset */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_RESET, 0x03); + + /* Disable Clocks to Framer */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_CLK_EN, 0, 0x03, 0); + + /* Power down serializer lanes */ + if (device->obsRx->framer->serializerLanesEnabled > 15) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ENOBSFRAMERLINK_INV_LANESEN_PARM, + getMykonosErrorMessage(MYKONOS_ERR_ENOBSFRAMERLINK_INV_LANESEN_PARM)); + return MYKONOS_ERR_ENOBSFRAMERLINK_INV_LANESEN_PARM; + } + + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_SERIALIZER_CTL_1, device->obsRx->framer->serializerLanesEnabled, + device->obsRx->framer->serializerLanesEnabled, 0); + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets up the JESD204B Deframer + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->tx->deframer->M + * - device->tx->deframer->bankId + * - device->tx->deframer->lane0Id + * - device->tx->deframer->K + * - device->tx->deframer->deserializerLanesEnabled + * - device->tx->deframer->externalSysref + * - device->tx->deframer->newSysrefOnRelink + * - device->tx->deframer->enableAutoChanXbar + * - device->tx->deframer->lmfcOffset + * - device->tx->deframer->scramble + * + * \param device Pointer to device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_DEFRAMER_INV_M_PARM Invalid M parameter in deframer structure + * \retval MYKONOS_ERR_DEFRAMER_INV_BANKID_PARM Invalid BankId parameter in deframer structure (Valid 0-15) + * \retval MYKONOS_ERR_ERR_DEFRAMER_INV_LANEID_PARM Invalid Lane0Id parameter in deframer structure (Valid 0-31) + * \retval MYKONOS_ERR_DEFRAMER_INV_K_PARAM Invalid K parameter in deframer structure (valid 1-32 with other constraints) + * \retval MYKONOS_ERR_DEFRAMER_INV_FK_PARAM Invalid F*K parameter (Valid F*K > 20, F*K must be divisible by 4), K must be <= 32 + * \retval MYKONOS_ERR_DEFRAMER_INV_K_OFFSET_PARAM Invalid K offset parameter in deframer structure (must be less than K) + */ +mykonosErr_t MYKONOS_setupJesd204bDeframer(mykonosDevice_t *device) +{ + uint8_t i = 0; + uint8_t temp = 0; + uint8_t reg080 = 0; + uint8_t laneXbar = 0; + uint8_t L = 0; + uint8_t ML = 0; + + /* Setup submap registers */ + uint8_t SUBCLASSV = 1; + uint8_t JESDV = 1; + uint8_t DID = 0; + uint8_t BID = 0; + uint8_t LID0 = 0; + uint8_t CS = 2; /* 2 control bits */ + uint8_t N = 0x0D; /* 14 bits */ + uint8_t Np = 0x0F; /* 16 bits */ + uint8_t S = 0; + uint8_t CF = 0; + uint8_t K = 0x1F; + uint16_t FK = 0; + uint8_t HD = 0; /* only one case has HD == 1 */ + uint8_t CTRLREG0 = 0; + uint8_t DeframerL = 1; + uint8_t DeframerM = 2; + uint8_t DeframerF = 0; + uint8_t CTRLREG1 = 0; + uint8_t CTRLREG2 = 0; + uint8_t DeframerLaneEnable = 0x00; + uint16_t CheckSum = 0; + uint8_t subaddr[25] = {0}; + uint8_t subdata[25] = {0}; + + uint8_t deframerInput = 0; + uint8_t lane = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setupJesd204bDeframer()\n"); +#endif + + if (device->tx->deframer->M != 0 && device->tx->deframer->M != 2 && device->tx->deframer->M != 4) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DEFRAMER_INV_M_PARM, getMykonosErrorMessage(MYKONOS_ERR_DEFRAMER_INV_M_PARM)); + return MYKONOS_ERR_DEFRAMER_INV_M_PARM; + } + + if (device->tx->deframer->bankId > 15) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DEFRAMER_INV_BANKID_PARM, + getMykonosErrorMessage(MYKONOS_ERR_DEFRAMER_INV_BANKID_PARM)); + return MYKONOS_ERR_DEFRAMER_INV_BANKID_PARM; + } + + if (device->tx->deframer->lane0Id > 31) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ERR_DEFRAMER_INV_LANEID_PARM, + getMykonosErrorMessage(MYKONOS_ERR_ERR_DEFRAMER_INV_LANEID_PARM)); + return MYKONOS_ERR_ERR_DEFRAMER_INV_LANEID_PARM; + } + + //count number of lanes + L = 0; + ML = 0; + + for (i = 0; i < 4; i++) + { + L += ((device->tx->deframer->deserializerLanesEnabled >> i) & 0x01); + } + + ML = (uint8_t)(device->tx->deframer->M * 10 + L); + + if (device->tx->deframer->K > 32) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DEFRAMER_INV_K_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_DEFRAMER_INV_K_PARAM)); + return MYKONOS_ERR_DEFRAMER_INV_K_PARAM; + } + + FK = (uint16_t)(device->tx->deframer->K * 2 * device->tx->deframer->M / L); + + if (FK < 20 || FK > 256 || FK % 4 != 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DEFRAMER_INV_FK_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_DEFRAMER_INV_FK_PARAM)); + return MYKONOS_ERR_DEFRAMER_INV_FK_PARAM; + } + + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_DEFRAMER_SYNC_REQ_RETIME, (device->tx->deframer->K - 1), 0x1F, 0x00); + + if (!device->tx->deframer->externalSysref) + { + /* Deframer: Generate SYSREF internally */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_TEST, 0x02); + } + + /* enabling the SYSREF for relink if newSysrefOnRelink is set */ + if (device->tx->deframer->newSysrefOnRelink) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_DEFRAMER_SYSREF_FIFO_EN, 0x01, 0x40, 6); + } + + /* enabling auto channel if the enableAutoChanXbar structure member is set */ + if (device->tx->deframer->enableAutoChanXbar) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_STRT_DAC_XBAR_REV, 0x01, 0x04, 2); + } + + /* Fix bad default bit to allow deterministic latency on deframer (Clear bit 4)*/ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_STRT_DAC_XBAR_REV, 0x00, 0x10, 4); + + /* Deframer: Set DAC Crossbar */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_DAC_XBAR_SEL, 0xB1); + + if (device->tx->deframer->enableManualLaneXbar == 1) + { + laneXbar = device->tx->deframer->deserializerLaneCrossbar; + } + else + { + /* Lane crossbar - Allow user to reorder lanes in deframer->deserializerLaneCrossbar, but this code still */ + /* maps used lanes to deframer inputs */ + deframerInput = 0; + for (lane = 0; lane < 4; lane++) + { + if ((device->tx->deframer->deserializerLanesEnabled >> lane) & 1) + { + laneXbar |= (uint8_t)(((device->tx->deframer->deserializerLaneCrossbar >> (lane << 1)) & 3) << (deframerInput << 1)); + deframerInput += 1; + } + } + + if (ML == 42) + { + /* M4L2 uses internal deframer ports 0 and 2 */ + /* swap bits 3:2 and 5:4, keep 1:0 and 7:6 in place */ + laneXbar = (laneXbar & 0xC3U) | ((laneXbar & 0x30) >> 2) | ((laneXbar & 0x0C) << 2); + } + } + + /* Deframer: Set Lane Crossbar */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_LANE_XBAR_SEL, laneXbar); + + //Find value for Framer F depending on M and L + switch (ML) + { + case 21: + reg080 = 0x04; + break; + case 22: + reg080 = 0x22; + break; + case 24: + reg080 = 0x41; + break; + case 41: + reg080 = 0x18; + break; + case 42: + reg080 = 0x34; + break; + case 44: + reg080 = 0x52; + break; + default: + reg080 = 0x04; + break; + } + + /* Deframer: Set F (Octets in Frame) */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_CONFIG_F, reg080); + + /* Deframer: Enable clocks and lane clocks */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_CLK_EN, 0x03); + + /* Set deframer lane FIFO enable for each lane enabled */ + temp = (device->tx->deframer->deserializerLanesEnabled & 0x0F); + + /* Deframer: Enable Lane FIFOs */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_LANE_FIFO_CTL, temp); + + /* Setup submap registers */ + SUBCLASSV = 1; /* JESD subclass 1 */ + JESDV = 1; /* Version: JESD204B */ + DID = device->tx->deframer->deviceId; + BID = device->tx->deframer->bankId; + LID0 = device->tx->deframer->lane0Id; + CS = 2; /* 2 control bits */ + N = 0x0D; /* 14 bits */ + Np = 0x0F; + S = 0; + CF = 0; + K = device->tx->deframer->K - 1; + HD = 0; /* only one case has HD = 1 */ + CTRLREG0 = 1; + DeframerL = L - 1; + DeframerM = device->tx->deframer->M - 1; + DeframerF = (uint8_t)((2*device->tx->deframer->M/L) - 1); + CheckSum = 0; + + if (ML == 21) + { + CTRLREG1 = 4; + CTRLREG2 = 0x14; + DeframerLaneEnable = 1; + } + else if (ML == 22) + { + CTRLREG1 = 2; + CTRLREG2 = 4; + DeframerLaneEnable = 3; + } + else if (ML == 24) + { + HD = 1; + CTRLREG1 = 1; + CTRLREG2 = 0; + DeframerLaneEnable = 0x0F; + } + else if (ML == 41) + { + CTRLREG1 = 8; + CTRLREG2 = 0; + DeframerLaneEnable = 1; + } + else if (ML == 42) + { + CTRLREG1 = 4; + CTRLREG2 = 0; + DeframerLaneEnable = 5; + } + else if (ML == 44) + { + CTRLREG1 = 2; + CTRLREG2 = 0; + DeframerLaneEnable = 0x0F; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DEFRAMER_INV_M_PARM, getMykonosErrorMessage(MYKONOS_ERR_DEFRAMER_INV_M_PARM)); + return MYKONOS_ERR_DEFRAMER_INV_M_PARM; + } + + /* LMFC offset limit check */ + if (device->tx->deframer->lmfcOffset < device->tx->deframer->K) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_LMFC_K_OFFSET, device->tx->deframer->lmfcOffset); + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DEFRAMER_INV_K_OFFSET_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_DEFRAMER_INV_K_OFFSET_PARAM)); + return MYKONOS_ERR_DEFRAMER_INV_K_OFFSET_PARAM; + } + + subaddr[0] = 0x50; + subdata[0] = DID & 0xFFU; /* Device ID */ + subaddr[1] = 0x51; + subdata[1] = BID & 0x0F; /* Bank ID */ + subaddr[2] = 0x52; + subdata[2] = LID0 & 0x1F; /* Lane 0 ID */ + subaddr[3] = 0x53; + subdata[3] = (uint8_t)(device->tx->deframer->scramble << 7) | (DeframerL & 0x1F); /* [7] = Scramble Enable, #Lanes[4:0] */ + subaddr[4] = 0x54; + subdata[4] = DeframerF & 0xFFU; /* F[7:0] */ + subaddr[5] = 0x55; + subdata[5] = K & 0x1F; /* K[4:0] */ + subaddr[6] = 0x56; + subdata[6] = DeframerM & 0xFFU; /* M[7:0] */ + subaddr[7] = 0x57; + subdata[7] = ((CS & 0x3) << 6) | (N & 0x1F); /* [7:6] = CS[1:0], N[4:0] */ + subaddr[8] = 0x58; + subdata[8] = ((SUBCLASSV & 7) << 5) | (Np & 0x1F); /* Np[4:0] */ + subaddr[9] = 0x59; + subdata[9] = ((JESDV & 7) << 5) | (S & 0x1F); /* S[4:0] */ + subaddr[10] = 0x5A; + subdata[10] = ((HD & 1) << 7) | (CF & 0x1F); /* [7]=HD, CF[4:0] */ + subaddr[11] = 0x5B; + subdata[11] = 0x00; /* reserved */ + subaddr[12] = 0x5C; + subdata[12] = 0x00; /* reserved */ + CheckSum = (DID & 0xFF) + (BID & 0xF) + (LID0 & 0x1F) + (device->tx->deframer->scramble) + (DeframerL & 0x1F) + (DeframerF & 0xFF) + (K & 0x1F) + (DeframerM & 0xFF) + + (CS & 0x3) + (N & 0x1F) + (Np & 0x1F) + (S & 0x1F) + (HD & 1) + (CF & 0x1F) + (SUBCLASSV & 7) + (JESDV & 7); + subaddr[13] = 0x5D; + subdata[13] = CheckSum & 0xFFU; /* Checksum Lane 0 */ + subaddr[14] = 0x6D; + subdata[14] = 0xA0U; /* Bad Disparity setup */ + subaddr[15] = 0x6E; + subdata[15] = 0xA0U; /* Not in Table setup */ + subaddr[16] = 0x6F; + subdata[16] = 0xA0U; /* UnExpected K character setup */ + subaddr[17] = 0x75; + subdata[17] = CTRLREG0; /* CTRLREG 0 */ + subaddr[18] = 0x76; + subdata[18] = CTRLREG1; /* CTRLREG 1 (Bytes per frame) */ + subaddr[19] = 0x77; + subdata[19] = CTRLREG2; /* CTRLREG 2 */ + subaddr[20] = 0x78; + subdata[20] = 0x01; /* # 4*K multiframes during ILAS */ + subaddr[21] = 0x7A; + subdata[21] = 0xE0U; /* Setup JESD interrupt sources */ + subaddr[22] = 0x7B; + subdata[22] = 0x08U; /* Sync assertion setup */ + subaddr[23] = 0x7C; + subdata[23] = 0xFFU; /* Error count threshold */ + subaddr[24] = 0x7D; + subdata[24] = DeframerLaneEnable & 0xFFU; /* Lane enable */ + + for (i = 0; i <= 24; i++) + { + /* Set deframer sub-register map address */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_ADDR, subaddr[i]); + + /* Set deframer sub-register map data word */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_DATA, subdata[i]); + + /* Set write enable to latch data into deframer sub register map */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_WR_EN, 0x01); + } + + /* Deframer: Enable lane FIFO sync */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_DEFRAMER_SYSREF_FIFO_EN, 0x01, 0x10, 4); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets up the chip for multichip sync, and cleans up after MCS. + * + * When working with multiple transceivers or even only one transceiver that requires deterministic + * latency between the Tx and observation and or main Rx JESD204B data path, Multichip sync is + * necessary. This function should be run after all transceivers are initialized. + * + * After the SYSREF pulses have been sent, call the MYKONOS_enableMultichipSync() function again with the + * enableMcs parameter set to 0. When enableMcs = 0, the MCS status will be returned in the mcsStatus + * parameter. + * + * Typical sequence: + * 1) Initialize all Mykonos devices in system using MYKONOS_initialize() + * 2) Run MYKONOS_enableMultichipSync with enableMcs = 1 + * 3) Send at least 3 SYSREF pulses + * 4) Run MYKONOS_enableMultichipSync with enableMcs = 0 + * 5) Load ARM, run ARM cals and continue to active Transmit/Receive + * + * mcsStatus | bit Description + * -----------|-------------------------------------------------------- + * [0] | MCS JESD SYSREF Status (1 = sync occurred) + * [1] | MCS Digital Clocks Sync Status (1 = sync occurred) + * [2] | MCS CLKPLL SDM Sync Status (1 = sync occurred) + * [3] | MCS Device Clock divider Sync Status (1 = sync occurred) + * + * Dependencies + * - device->spiSettings + * + * \param device is a pointer to the device settings structure + * \param enableMcs =1 will enable the MCS state machine, =0 will allow reading back MCS status + * \param mcsStatus optional parameter, if pointer is not null the function Which will be populated with the mcsStatus word described in the table above. + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_enableMultichipSync(mykonosDevice_t *device, uint8_t enableMcs, uint8_t *mcsStatus) +{ + uint8_t clkPllSdmBypass = 0; + uint8_t mcsEnable = 0x9B; /* [7] Keeps RF LO divider enabled, Enable MCS[4] and reset Device Clock divider[3], Digital clocks[1], and JESD204 SYSREF[0] */ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableMultichipSync()\n"); +#endif + + if (enableMcs) + { + /* If CLKPLL SDM not bypassed, reset CLKPLL SDM as well. */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE1, &clkPllSdmBypass, 0x40, 6); + + if (clkPllSdmBypass == 0) + { + mcsEnable |= 0x04; /* enable MCS for CLKPLL SDM */ + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_MCS_CONTROL, mcsEnable); + } + + /* if mcsStatus is a valid pointer, return the MCS status */ + if (mcsStatus != NULL) + { + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_MCS_STATUS, mcsStatus); + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Enables or disables SYSREF to the transceiver's RX framer + * + * Dependencies + * - device->spiSettings + * + * \param device is a pointer to the device settings structure + * \param enable = '1' enables SYSREF to RX framer, '0' disables SYSREF to framer + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_enableSysrefToRxFramer(mykonosDevice_t *device, uint8_t enable) +{ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableSysrefToRxFramer()\n"); +#endif + + if (enable) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_FRAMER_SYSREF_FIFO_EN, 0x01, 0x01, 0); + } + else + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_FRAMER_SYSREF_FIFO_EN, 0x00, 0x01, 0); + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Enables or disables SYSREF to the transceiver's Observation RX framer + * + * Dependencies + * - device->spiSettings + * + * \param device is a pointer to the device settings structure + * \param enable = '1' enables SYSREF to OBSRX framer, '0' disables SYSREF to framer + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_enableSysrefToObsRxFramer(mykonosDevice_t *device, uint8_t enable) +{ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableSysrefToObsRxFramer()\n"); +#endif + + if (enable) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_SYSREF_FIFO_EN, 0x01, 0x01, 0); + } + else + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_SYSREF_FIFO_EN, 0x00, 0x01, 0); + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Enables or disables SYSREF to the transceiver's deframer + * + * Dependencies + * - device->spiSettings + * + * \param device is a pointer to the device settings structure + * \param enable = '1' enables SYSREF to deframer, '0' disables SYSREF to deframer + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_enableSysrefToDeframer(mykonosDevice_t *device, uint8_t enable) +{ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableSysrefToDeframer()\n"); +#endif + + if (enable) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_DEFRAMER_SYSREF_FIFO_EN, 0x01, 0x01, 0); + } + else + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_DEFRAMER_SYSREF_FIFO_EN, 0x00, 0x01, 0); + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads the transceiver's RX framer status + * + * Dependencies + * - device->spiSettings + * + * framerStatus | Description + * -------------|----------------------------------------------------------------------------- + * [7] | SYSREF phase error ? a new SYSREF had different timing than the first that set the LMFC timing. + * [6] | Framer lane FIFO read/write pointer delta has changed. Can help debug issues with deterministic latency. + * [5] | Framer has received the SYSREF and has retimed its LMFC + * [4:2] | Framer ILAS state: 0=CGS, 1= 1st Multframe, 2= 2nd Multiframe, 3= 3rd Multiframe, 4= 4th multiframe, 5= Last multiframe, 6=invalid, 7= ILAS complete + * [1:0] | Framer Tx state: 0=CGS, 1= ILAS, 2 = ADC Data + * + * \param device is a pointer to the device settings structure + * \param framerStatus is the RX framer status byte read + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_READ_RXFRAMERSTATUS_NULL_PARAM Function parameter framerStatus has NULL pointer + */ +mykonosErr_t MYKONOS_readRxFramerStatus(mykonosDevice_t *device, uint8_t *framerStatus) +{ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_readRxFramerStatus()\n"); +#endif + + if (framerStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READ_RXFRAMERSTATUS_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_READ_RXFRAMERSTATUS_NULL_PARAM)); + return MYKONOS_ERR_READ_RXFRAMERSTATUS_NULL_PARAM; + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_STATUS_STRB, 0x01); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_STATUS_STRB, 0x00); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_FRAMER_STATUS, framerStatus); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads the transceiver's Observation RX framer status + * + * Dependencies + * * - device->spiSettings + * + * obsFramerStatus | Description + * ----------------|----------------------------------------------------------------------------- + * [7] | SYSREF phase error ? a new SYSREF had different timing than the first that set the LMFC timing. + * [6] | Framer lane FIFO read/write pointer delta has changed. Can help debug issues with deterministic latency. + * [5] | Framer has received the SYSREF and has retimed its LMFC + * [4:2] | Framer ILAS state: 0=CGS, 1= 1st Multframe, 2= 2nd Multiframe, 3= 3rd Multiframe, 4= 4th multiframe, 5= Last multiframe, 6=invalid, 7= ILAS complete + * [1:0] | Framer Tx state: 0=CGS, 1= ILAS, 2 = ADC Data + * + * \param device is a pointer to the device settings structure + * \param obsFramerStatus is the OBSRX framer status byte read + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_READ_ORXFRAMERSTATUS_NULL_PARAM Function parameter obsFramerStatus has NULL pointer + */ +mykonosErr_t MYKONOS_readOrxFramerStatus(mykonosDevice_t *device, uint8_t *obsFramerStatus) +{ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_readOrxFramerStatus()\n"); +#endif + + if (obsFramerStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READ_ORXFRAMERSTATUS_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_READ_ORXFRAMERSTATUS_NULL_PARAM)); + return MYKONOS_ERR_READ_ORXFRAMERSTATUS_NULL_PARAM; + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_STATUS_STRB, 0x01); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_STATUS_STRB, 0x00); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_STATUS, obsFramerStatus); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads the transceiver's deframer status + * + * Dependencies + * - device->spiSettings + * + * deframerStatus | Bit Name | Description + * ----------------|--------------------------|--------------------------------------------- + * [7] | Unused | Unused + * [6] | Deframer IRQ | This bit indicates that the IRQ interrupt was asserted. + * [5] | Deframer SYSREF Received | When this bit is set, it indicates that the SYSREF pulse was received by the deframer IP + * [4] | Deframer Receiver Error | This bit is set when PRBS has received an error. + * [3] | Valid Checksum | This bit is set when the received ILAS checksum is valid. + * [2] | EOF Event | This bit captures the internal status of the framer End of Frame event. Value =1 if framing error during ILAS + * [1] | EOMF Event | This bit captures the internal status of the framer End of Multi-Frame event. Value =1 if framing error during ILAS + * [0] | FS Lost | This bit captures the internal status of the framer Frame Symbol event. Value =1 if framing error during ILAS or user data (invalid replacement characters) + * + * + * \param device is a pointer to the device settings structure + * \param deframerStatus is the deframer status byte read + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_READ_DEFRAMERSTATUS_NULL_PARAM Function parameter deframerStatus has NULL pointer + */ +mykonosErr_t MYKONOS_readDeframerStatus(mykonosDevice_t *device, uint8_t *deframerStatus) +{ + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_readDeframerStatus()\n"); +#endif + + if (deframerStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READ_DEFRAMERSTATUS_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_READ_DEFRAMERSTATUS_NULL_PARAM)); + return MYKONOS_ERR_READ_DEFRAMERSTATUS_NULL_PARAM; + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_STAT_STRB, 0x01); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_STAT_STRB, 0x00); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_STAT, deframerStatus); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads the Mykonos JESD204b Deframer determinstic FIFO depth + * + * To verify that the deterministic latency FIFO is not close to a underflow or + * overflow condition, it is recommended to check the FIFO depth. If the FIFO + * is close to an overflow or underflow condition, it is possible that from + * power up to powerup, deterministic latency may not be met. If a underflow + * or overflow occurred, the data would still be correct, but would possibly + * slip by 1 multiframe (losing deterministic latency). To correct for an + * overflow/underflow, the BBIC would need to add delay from SYSREF until + * the first symbol in a multiframe + * + * Dependencies + * - device->spiSettings + * + * \param device is a pointer to the device settings structure + * \param fifoDepth Return value that describes the depth of the Mykonos + * deterministic latency deframer FIFO. + * \param readEnLmfcCount Returns the LMFC count value when the deterministic FIFO read enable was asserted. + * Counts at the Mykonos internal deframer PCLK frequency. + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_READ_DEFFIFODEPTH_NULL_PARAM Error: function parameter fifoDepth is a NULL pointer + * \retval MYKONOS_ERR_READ_DEFFIFODEPTH_LMFCCOUNT_NULL_PARAM Error: function parameter readEnLmfcCount is a NULL pointer + * + */ +mykonosErr_t MYKONOS_getDeframerFifoDepth(mykonosDevice_t *device, uint8_t *fifoDepth, uint8_t *readEnLmfcCount) +{ + uint8_t fifoReadPtr = 0; + uint8_t fifoWritePtr = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getDeframerFifoDepth()\n"); +#endif + + if (fifoDepth == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READ_DEFFIFODEPTH_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_READ_DEFFIFODEPTH_NULL_PARAM)); + return MYKONOS_ERR_READ_DEFFIFODEPTH_NULL_PARAM; + } + + if (readEnLmfcCount == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READ_DEFFIFODEPTH_LMFCCOUNT_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_READ_DEFFIFODEPTH_LMFCCOUNT_NULL_PARAM)); + return MYKONOS_ERR_READ_DEFFIFODEPTH_LMFCCOUNT_NULL_PARAM; + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_STAT_STRB, 0x01); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_STAT_STRB, 0x00); + + /* read/write pointers are 7 bits, (0 - 127) */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_DEFRAMER_DET_FIFO_RD_ADDR, &fifoReadPtr, 0x7F, 0); + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_ADDR, &fifoWritePtr, 0x7F, 0); + + /* Adding 128 and modulus 128 handle the wrap cases where the read pointer + * is less than write pointer + */ + *fifoDepth = (((fifoWritePtr + 128) - fifoReadPtr) % 128); + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_DET_FIFO_PHASE, readEnLmfcCount); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Selects the PRBS type and enables or disables RX Framer PRBS20 generation + * + * Dependencies + * - device->spiSettings + * + * \param device is a pointer to the device settings structure + * \param polyOrder selects the PRBS type based on a two-bit value range from 0-3 + * \param enable '1' = enables PRBS RX framer PRBS generator, '0' = disables PRBS generator + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_RX_FRAMER_INV_PRBS_POLYORDER_PARAM Invalid polyOrder parameter, use ENUM + * + */ +mykonosErr_t MYKONOS_enableRxFramerPrbs(mykonosDevice_t *device, mykonosPrbsOrder_t polyOrder, uint8_t enable) +{ + uint8_t wrmask = 0; + uint8_t enableBit = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableRxFramerPrbs()\n"); +#endif + + enableBit = (enable > 0) ? 1 : 0; + + if ((polyOrder == MYK_PRBS7) || (polyOrder == MYK_PRBS15) || (polyOrder == MYK_PRBS31)) + { + wrmask = ((uint8_t)polyOrder << 1) | enableBit; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RX_FRAMER_INV_PRBS_POLYORDER_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_RX_FRAMER_INV_PRBS_POLYORDER_PARAM)); + return MYKONOS_ERR_RX_FRAMER_INV_PRBS_POLYORDER_PARAM; + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_PRBS20_CTL, wrmask); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Selects the PRBS type and enables or disables OBSRX Framer PRBS20 generation + * + * Dependencies + * - device->spiSettings + * + * \param device is a pointer to the device settings structure + * \param polyOrder selects the PRBS type based on a two-bit value range from 0-3 + * \param enable '1' = enables PRBS OBSRX framer PRBS generator, '0' = disables PRBS generator + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_OBSRX_FRAMER_INV_PRBS_POLYORDER_PARAM polyOrder parameter is not a valid value - use ENUM + */ +mykonosErr_t MYKONOS_enableObsRxFramerPrbs(mykonosDevice_t *device, mykonosPrbsOrder_t polyOrder, uint8_t enable) +{ + uint8_t wrmask = 0; + uint8_t enableBit = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableObsRxFramerPrbs()\n"); +#endif + + enableBit = (enable > 0) ? 1 : 0; + + if ((polyOrder == MYK_PRBS7) || (polyOrder == MYK_PRBS15) || (polyOrder == MYK_PRBS31)) + { + wrmask = ((uint8_t)polyOrder << 1) | enableBit; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBSRX_FRAMER_INV_PRBS_POLYORDER_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_OBSRX_FRAMER_INV_PRBS_POLYORDER_PARAM)); + return MYKONOS_ERR_OBSRX_FRAMER_INV_PRBS_POLYORDER_PARAM; + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_PRBS20_CTL, wrmask); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Injects a PRBS error into the RX data path + * + * Dependencies + * - device->spiSettings + * + * \param device is a pointer to the device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_rxInjectPrbsError(mykonosDevice_t *device) +{ + uint8_t prbsControl = 0x00; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_rxInjectPrbsError()\n"); +#endif + + /* reading current PRBS20 control register contents */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_FRAMER_PRBS20_CTL, &prbsControl); + + /* setting bit 4 in framer PRBS20 control register and then clearing it for error injection */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_PRBS20_CTL, prbsControl |= 0x10); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FRAMER_PRBS20_CTL, prbsControl &= ~0x10); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Initiates a PRBS error injection into the Observation RX data path + * + * Dependencies + * - device->spiSettings + * + * \param device is a pointer to the device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_obsRxInjectPrbsError(mykonosDevice_t *device) +{ + uint8_t prbsControl = 0x00; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_obsRxInjectPrbsError()\n"); +#endif + + /* reading current PRBS20 control register contents */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_PRBS20_CTL, &prbsControl); + + /* setting bit 4 in framer PRBS20 control register and then clearing it for error injection */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_PRBS20_CTL, prbsControl |= 0x10); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_PRBS20_CTL, prbsControl &= ~0x10); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Configures and enables or disables the transceiver's deframer PRBS checker + * + * Dependencies + * - device->spiSettings + * + * \param device is a pointer to the device settings structure + * \param lanes selects the lane for PRBS checking based on a 4-bit mask, where each weighted bit + * corresponds with a different lane selection as such: '1' = lane 0, '2' = lane 1, '4' = lane 2, '8' = lane 3 + * \param polyOrder selects the PRBS type based on enum values (MYK_PRBS7, MYK_PRBS15, MYK_PRBS31) + * \param enable '1' = enables checking, '0' = disables checking + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_DEFRAMER_INV_PRBS_POLYORDER_PARAM Invalid polyOrder parameter - use ENUM + * \retval MYKONOS_ERR_DEFRAMER_INV_PRBS_ENABLE_PARAM Invalid enable (valid 0-1) or lanes (valid 0-15) parameter + */ +mykonosErr_t MYKONOS_enableDeframerPrbsChecker(mykonosDevice_t *device, uint8_t lanes, mykonosPrbsOrder_t polyOrder, uint8_t enable) +{ + uint8_t wrmask = 0x00; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableDeframerPrbsChecker()\n"); +#endif + + if ((enable <= 0x01) && (lanes <= 0x0F)) + { + if ((polyOrder == MYK_PRBS7) || (polyOrder == MYK_PRBS15) || (polyOrder == MYK_PRBS31)) + { + wrmask = ((lanes << 4) | ((uint8_t)polyOrder << 1) | enable); + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DEFRAMER_INV_PRBS_POLYORDER_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_DEFRAMER_INV_PRBS_POLYORDER_PARAM)); + return MYKONOS_ERR_DEFRAMER_INV_PRBS_POLYORDER_PARAM; + } + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DEFRAMER_INV_PRBS_ENABLE_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_DEFRAMER_INV_PRBS_ENABLE_PARAM)); + return MYKONOS_ERR_DEFRAMER_INV_PRBS_ENABLE_PARAM; + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_PRBS20_CTL, wrmask); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads the deframer PRBS counters + * + * Dependencies + * - device->spiSettings + * + * \param device is a pointer to the device settings structure + * \param counterSelect selects the PRBS error counter to be read based on values between 0-3 + * If counterSelect exceeds this value an error is thrown. + * + * \param prbsErrorCount is return value after reading the PRBS error count + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_READ_DEFRAMERPRBS_NULL_PARAM Function parameter prbsErrorCount has NULL pointer + * \retval MYKONOS_ERR_DEFRAMER_INV_PRBS_CNTR_SEL_PARAM if counterSelect is out of bounds + */ +mykonosErr_t MYKONOS_readDeframerPrbsCounters(mykonosDevice_t *device, uint8_t counterSelect, uint32_t *prbsErrorCount) +{ + uint8_t wrmask = 0x00; + uint8_t errorCnt[3] = {0}; + const uint8_t COUNTER_SATURATE = 0x40; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_readDeframerPrbsCounters()\n"); +#endif + + if (prbsErrorCount == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READ_DEFRAMERPRBS_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_READ_DEFRAMERPRBS_NULL_PARAM)); + return MYKONOS_ERR_READ_DEFRAMERPRBS_NULL_PARAM; + } + + if (counterSelect & ~0x03) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DEFRAMER_INV_PRBS_CNTR_SEL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_DEFRAMER_INV_PRBS_CNTR_SEL_PARAM)); + return MYKONOS_ERR_DEFRAMER_INV_PRBS_CNTR_SEL_PARAM; + } + else + { + wrmask = (uint8_t)(COUNTER_SATURATE | (counterSelect << 4)); + *prbsErrorCount = 0x00000000; + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_PRBS20_STRB_CHKSUM_TYPE, wrmask); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_PRBS20_STRB_CHKSUM_TYPE, wrmask |= 0x01); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_PRBS20_STRB_CHKSUM_TYPE, wrmask &= ~0x01); + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_7_TO_0, &errorCnt[0]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_15_TO_8, &errorCnt[1]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_23_TO_16, &errorCnt[2]); + + *prbsErrorCount = (uint32_t)(errorCnt[2] << 16) | (uint32_t)(errorCnt[1] << 8) | (uint32_t)(errorCnt[0]); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Clears the deframer/deserializer PRBS counters + * + * Dependencies + * - device->spiSettings + * + * \param device is a pointer to the device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_clearDeframerPrbsCounters(mykonosDevice_t *device) +{ + uint8_t spiReg = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_clearDeframerPrbsCounters()\n"); +#endif + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_PRBS20_CTL, &spiReg); + spiReg &= ~0x08; //make sure PRBS clear bit is 0 + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_PRBS20_CTL, (spiReg | 0xF8)); //clear counters for all lanes + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_PRBS20_CTL, spiReg); //set reg back to previous value + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads the lane 0 JESD204B deframer configuration and compares it against the ILAS received values + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param mismatch [15-0] is a bit-encoded word which for mismatch[15] = '0' = no mismatch, '1' = mismatch for one or more parameters + * mismatch bits [14-0] are aligned with the mykonosJesd204bLane0Config_t structure members starting at '0' = DID. The aligned bit is set to + * '1' if the configuration parameter does not agree with its corresponding received ILAS value, otherwise '0' if they agree. + * + * The bit assignments for the 16-bit word are: + * mismatch | bit description + * -----------|-------------------------------------------------------- + * [0] | JESD204B DID: device ID + * [1] | JESD204B BID: bank ID + * [2] | JESD204B LID0: lane ID + * [3] | JESD204B L: lanes per data converter + * [4] | JESD204B SCR: scramble setting + * [5] | JESD204B F: octets per frame + * [6] | JESD204B K: frames per multiframe + * [7] | JESD204B M: number of data converters + * [8] | JESD204B N: data converter sample resolution + * [9] | JESD204B CS: number of control bits transferred per sample per frame + * [10] | JESD204B NP: JESD204B word size based on the highest data converter resolution + * [11] | JESD204B S: number of samples per converter per frame + * [12] | JESD204B CF: '0' = control bits appended to each sample, '1' = control bits appended to end of frame + * [13] | JESD204B HD: high density bit, where '0' = samples are contained with single lane, '1' = samples are divided over more than one lane + * [14] | JESD204B FCHK0: configuration checksum OK bit. where '1' = fail, '0' = pass + * [15] | MISMATCH DETECTED BIT: bits 0-14 are ored together to set this bit + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_JESD204B_ILAS_MISMATCH_NULLPARAM Function parameter mismatch has NULL pointer + */ +mykonosErr_t MYKONOS_jesd204bIlasCheck(mykonosDevice_t *device, uint16_t *mismatch) +{ + uint8_t i = 0; + uint8_t ilasdata[15] = {0}; + uint8_t cfgdata[15] = {0}; + mykonosJesd204bLane0Config_t lane0ILAS; + mykonosJesd204bLane0Config_t lane0Cfg; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_jesd204bIlasCheck()\n"); +#endif + + if (mismatch == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_JESD204B_ILAS_MISMATCH_NULLPARAM, + getMykonosErrorMessage(MYKONOS_ERR_JESD204B_ILAS_MISMATCH_NULLPARAM)); + return MYKONOS_ERR_JESD204B_ILAS_MISMATCH_NULLPARAM; + } + + *mismatch = 0; + + /* setting deframer read received ILAS data */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_WR_EN, 0x00); + + /* reading deframer received ILAS register contents into array */ + for (i = 0; i < 15; i++) + { + /* setting the deframer sub-address for received ilas data */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_ADDR, MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_RECVD + i); + + /* reading the received ILAS data into byte array */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_DATA, &ilasdata[i]); + } + + /* reading deframer config register contents into array */ + for (i = 0; i < 15; i++) + { + /* setting the deframer sub-address for received ilas data */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_ADDR, MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_CFG + i); + + /* reading the received ILAS data into byte array */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_DEFRAMER_DATA, &cfgdata[i]); + } + + /* loading the structures with the read values for easier reading when doing compares */ + lane0ILAS.DID = ilasdata[0]; + lane0ILAS.BID = ilasdata[1] & 0x0F; + lane0ILAS.LID0 = ilasdata[2] & 0x1F; + lane0ILAS.L = ilasdata[3] & 0x1F; + lane0ILAS.SCR = ilasdata[3] >> 7; + lane0ILAS.F = ilasdata[4]; + lane0ILAS.K = ilasdata[5] & 0x1F; + lane0ILAS.M = ilasdata[6]; + lane0ILAS.N = ilasdata[7] & 0x1F; + lane0ILAS.CS = ilasdata[7] >> 6; + lane0ILAS.NP = ilasdata[8] & 0x1F; + lane0ILAS.S = ilasdata[9] & 0x1F; + lane0ILAS.CF = ilasdata[10] & 0x1F; + lane0ILAS.HD = ilasdata[10] >> 7; + lane0ILAS.FCHK0 = ilasdata[13]; + + lane0Cfg.DID = cfgdata[0]; + lane0Cfg.BID = cfgdata[1] & 0x0F; + lane0Cfg.LID0 = cfgdata[2] & 0x0F; + lane0Cfg.L = cfgdata[3] & 0x1F; + lane0Cfg.SCR = cfgdata[3] >> 7; + lane0Cfg.F = cfgdata[4]; + lane0Cfg.K = cfgdata[5] & 0x1F; + lane0Cfg.M = cfgdata[6]; + lane0Cfg.N = cfgdata[7] & 0x1F; + lane0Cfg.CS = cfgdata[7] >> 6; + lane0Cfg.NP = cfgdata[8] & 0x1F; + lane0Cfg.S = cfgdata[9] & 0x1F; + lane0Cfg.CF = cfgdata[10] & 0x1F; + lane0Cfg.HD = cfgdata[10] >> 7; + lane0Cfg.FCHK0 = cfgdata[13]; + + /* performing ILAS mismatch check */ + if (lane0ILAS.DID != lane0Cfg.DID) + { + *mismatch |= 0x0001; + } + + if (lane0ILAS.BID != lane0Cfg.BID) + { + *mismatch |= 0x0002; + } + + if (lane0ILAS.LID0 != lane0Cfg.LID0) + { + *mismatch |= 0x0004; + } + + if (lane0ILAS.L != lane0Cfg.L) + { + *mismatch |= 0x0008; + } + + if (lane0ILAS.SCR != lane0Cfg.SCR) + { + *mismatch |= 0x0010; + } + + if (lane0ILAS.F != lane0Cfg.F) + { + *mismatch |= 0x0020; + } + + if (lane0ILAS.K != lane0Cfg.K) + { + *mismatch |= 0x0040; + } + + if (lane0ILAS.M != lane0Cfg.M) + { + *mismatch |= 0x0080; + } + + if (lane0ILAS.N != lane0Cfg.N) + { + *mismatch |= 0x0100; + } + + if (lane0ILAS.CS != lane0Cfg.CS) + { + *mismatch |= 0x0200; + } + + if (lane0ILAS.NP != lane0Cfg.NP) + { + *mismatch |= 0x0400; + } + + if (lane0ILAS.S != lane0Cfg.S) + { + *mismatch |= 0x0800; + } + + if (lane0ILAS.CF != lane0Cfg.CF) + { + *mismatch |= 0x1000; + } + + if (lane0ILAS.HD != lane0Cfg.HD) + { + *mismatch |= 0x2000; + } + + if (lane0ILAS.FCHK0 != lane0Cfg.FCHK0) + { + *mismatch |= 0x4000; + } + + if (*mismatch) + { + *mismatch |= 0x8000; + CMB_writeToLog(ADIHAL_LOG_WARNING, device->spiSettings->chipSelectIndex, MYKONOS_ERR_JESD204B_ILAS_MISMATCH, + getMykonosErrorMessage(MYKONOS_ERR_JESD204B_ILAS_MISMATCH)); + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Select data to inject into the Rx framer input (ADC data or Loopback data from deframer output) + * + * This function allows inputting deframed data (IQ samples) from the Tx data path into the Rx framer. + * For this to work correctly, the IQ data rate of the Tx data path must match the Rx IQ data rate. + * Framer/Deframer JESD204 config parameters can vary as long as the Rx and Tx IQ rates match. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device A pointer to the device settings structure + * \param dataSource 0 = ADC data at Rx Framer input, 1 = Deframed Tx JESD204 IQ samples input into Rx framer + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setRxFramerDataSource(mykonosDevice_t *device, uint8_t dataSource) +{ + uint8_t enableLoopBack = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setRxFramerDataSource()\n"); +#endif + + enableLoopBack = (dataSource > 0) ? 1 : 0; + + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_FRAMER_CONFIG_LOOPBACK_XBAR_REV, enableLoopBack, 0x10, 4); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Select data to inject into the ObsRx framer input (ADC data or Loopback data from deframer output) + * + * This function allows inputting deframed data (IQ samples) from the Tx data path into the Obs Rx framer. + * For this to work correctly, the IQ data rate of the Tx data path must match the ORx IQ data rate. + * Framer/Deframer JESD204 config parameters can vary as long as the Obs Rx and Tx IQ rates match. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device A pointer to the device settings structure + * \param dataSource 0 = ADC data at ObsRx Framer input, 1 = Deframed Tx JESD204 IQ samples input into Obs Rx framer + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setObsRxFramerDataSource(mykonosDevice_t *device, uint8_t dataSource) +{ + uint8_t enableLoopBack = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setObsRxFramerDataSource()\n"); +#endif + + enableLoopBack = (dataSource > 0) ? 1 : 0; + + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_OBS_FRAMER_CONFIG_LOOPBACK_XBAR_REV, enableLoopBack, 0x10, 4); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Runs the Mykonos initialization calibrations + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * ENUM mykonosInitCalibrations_t can be used to OR together to generate the calMask parameter. + * + * calMask Bit | Calibration + * ------------|---------------------- + * 0 | Tx BB Filter + * 1 | ADC Tuner + * 2 | TIA 3dB Corner + * 3 | DC Offset + * 4 | Tx Attenuation Delay + * 5 | Rx Gain Delay + * 6 | Flash Cal + * 7 | Path Delay + * 8 | Tx LO Leakage Internal + * 9 | Tx LO Leakage External + * 10 | Tx QEC Init + * 11 | LoopBack Rx LO Delay + * 12 | LoopBack Rx Rx QEC Init + * 13 | Rx LO Delay + * 14 | Rx QEC Init + * 15 | DPD Init + * 16 | Tx CLGC (Closed Loop Gain Control) + * 17 | Tx VSWR Init + * [31-18] | Ignored - Future space for new calibrations + * + * \param device A pointer to the device settings structure + * \param calMask A bitmask that informs the Mykonos ARM processor which calibrations to run + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_runInitCals(mykonosDevice_t *device, uint32_t calMask) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + const uint8_t RUNINITCALS_OPCODE = 0x02; + uint8_t payload[4] = {0}; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_runInitCals()\n"); +#endif + + payload[0] = (uint8_t)(calMask & 0xFF); + payload[1] = (uint8_t)((calMask >> 8) & 0xFF); + payload[2] = (uint8_t)((calMask >> 16) & 0xFF); + payload[3] = (uint8_t)((calMask >> 24) & 0xFF); + + retVal = MYKONOS_sendArmCommand(device, RUNINITCALS_OPCODE, &payload[0], sizeof(payload)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Blocking waits for the Mykonos initialization calibrations to complete + * + * The *errorFlag and *errorCode parameters are optional. If the pointers are + * set to null, no values will be returned. If the function returns an error + * that the init calibration failed, use the MYKONOS_getInitCalStatus() function + * to get more detailed information about why the init cal failed. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device A pointer to the device settings structure + * \param timeoutMs A timeout value in Ms to wait for the calibrations to complete + * \param errorFlag A 3bit error flag that helps identify what went wrong in the ARM. 0=No Error + * \param errorCode The value represents the init calibration object ID that caused a failure. + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_WAIT_INITCALS_ARMERROR ARM returned error unrelated to init cals + */ +mykonosErr_t MYKONOS_waitInitCals(mykonosDevice_t *device, uint32_t timeoutMs, uint8_t *errorFlag, uint8_t *errorCode) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + mykonosErr_t retValCalStatus = MYKONOS_ERR_OK; + uint8_t cmdStatusByte = 0; + uint8_t _errorFlag = 0; /* Local version of parameter */ + mykonosInitCalStatus_t initCalStatus = {0}; + + const uint8_t INITCALS_CAL_ERROR = 0x07; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_waitInitCals()\n"); +#endif + + /* Clear before making any calls that can throw errors */ + if (errorFlag != NULL) + { + *errorFlag = 0; + } + + /* Clear before making any calls that can throw errors */ + if (errorCode != NULL) + { + *errorCode = 0; + } + + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_RUNINIT_OPCODE, timeoutMs, &cmdStatusByte); + _errorFlag = cmdStatusByte >> 1; /* remove pending bit in [0], error flag is in bits [3:1] */ + + if (errorFlag != NULL) + { + *errorFlag = _errorFlag; + } + + if (retVal != MYKONOS_ERR_OK) + { + if (_errorFlag == INITCALS_CAL_ERROR) + { + /* return Error code if a calibration had an error */ + retValCalStatus = MYKONOS_getInitCalStatus(device, &initCalStatus); + if (retValCalStatus == MYKONOS_ERR_OK) + { + if (errorCode != NULL) + { + *errorCode = initCalStatus.initErrCal; + } + } + + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WAIT_INITCALS_CALFAILED, + getMykonosErrorMessage(MYKONOS_ERR_WAIT_INITCALS_CALFAILED)); + return MYKONOS_ERR_WAIT_INITCALS_CALFAILED; + } + else if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WAIT_INITCALS_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_WAIT_INITCALS_ARMERROR)); + return MYKONOS_ERR_WAIT_INITCALS_ARMERROR; + } + } + + /* Same logic if MYKONOS_waitArmCmdStatus() did not return an error, but cmdStatusByte shows an ARM error */ + if (_errorFlag == INITCALS_CAL_ERROR) + { + /* return Error code if a calibration had an error */ + retValCalStatus = MYKONOS_getInitCalStatus(device, &initCalStatus); + if (retValCalStatus == MYKONOS_ERR_OK) + { + if (errorCode != NULL) + { + *errorCode = initCalStatus.initErrCal; + } + } + + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WAIT_INITCALS_CALFAILED, + getMykonosErrorMessage(MYKONOS_ERR_WAIT_INITCALS_CALFAILED)); + return MYKONOS_ERR_WAIT_INITCALS_CALFAILED; + } + else if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WAIT_INITCALS_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_WAIT_INITCALS_ARMERROR)); + return MYKONOS_ERR_WAIT_INITCALS_ARMERROR; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Aborts from an on going ARM init calibration operation. + * + * The ARM init calibrations can take several seconds. If for any reason the Baseband processor + * needs to stop the running ARM calibration sequence, call this function. The *calsCompleted + * parameter is an option parameter that will return which cals completed before the abort + * command was received. If *calsCompleted is a null pointer, no value will be returned. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device A pointer to the device settings structure + * \param calsCompleted A bitmask is returned which describes which cals completed during the previous + * MYKONOS_runInitCals() call. + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_ABORT_INITCALS_NULL_PARAM Function parameter calsCompleted has NULL pointer + */ +mykonosErr_t MYKONOS_abortInitCals(mykonosDevice_t *device, uint32_t *calsCompleted) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint32_t timeoutMs = 1000; //1 second timeout + uint8_t cmdStatusByte = 0; + uint8_t payload = 0x43; /* object ID to get INIT_CAL_DONE status */ + uint8_t calCompleteBitField[4] = {0, 0, 0, 0}; + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_ABORT_OPCODE, 0, 0); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; /* Will return if mailbox busy bit is busy for more than 2 seconds */ + } + + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_ABORT_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; /* Will return if timeout occurred */ + } + + /* Read back Calibration Completion status */ + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &payload, sizeof(payload)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; /* Will return if mailbox busy bit is busy for more than 2 seconds */ + } + + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; /* Will return if timeout occurred */ + } + + retVal = MYKONOS_readArmMem(device, (MYKONOS_ADDR_ARM_START_DATA_ADDR + 4), &calCompleteBitField[0], 4, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + if (calsCompleted != NULL) + { + *calsCompleted = ((uint32_t)(calCompleteBitField[3]) << 24) | ((uint32_t)(calCompleteBitField[2]) << 16) | ((uint32_t)(calCompleteBitField[1]) << 8) + | ((uint32_t)(calCompleteBitField[0])); + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ABORT_INITCALS_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_ABORT_INITCALS_NULL_PARAM)); + return MYKONOS_ERR_ABORT_INITCALS_NULL_PARAM; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Gets the device initialization calibration status + * + * This function requests the init cal status information from the Mykonos ARM + * processor. The ARM returns information including a bitmask that describes + * which calibrations have completed during the last cal of runInitCals, as + * well as the init cals that have run successfully since loading the ARM. If + * an ARM error does occur during one of the init calibrations, the initErrCal + * member returns the object ID of the failing calibration. The initErrCode + * returns the specific ARM error code that caused that calibration to fail. + * The calsMinimum structure member describes the minimum set of init calibrations + * required to complete by the ARM before it will allow the device to move to + * the radioOn state. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device A pointer to the device settings structure + * \param initCalStatus Pointer to a structure that returns cal status information such as cals completed since last run, and init error codes + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETINITCALSTATUS_NULL_PARAM if initCalStatus parameter is a NULL pointer + * \retval MYKONOS_ERR_GETINITCALSTATUS_ARMERROR if ARM returned an error while requesting the init cal status information + */ +mykonosErr_t MYKONOS_getInitCalStatus(mykonosDevice_t *device, mykonosInitCalStatus_t *initCalStatus) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t cmdStatusByte = 0; + uint8_t calStatusArray[14] = {0}; + uint8_t payload[1] = {MYKONOS_ARM_OBJECTID_INIT_CAL_DONE}; + + uint32_t timeoutMs = 1000; + + /* Verify function parameter pointer is not NULL */ + if (initCalStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETINITCALSTATUS_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETINITCALSTATUS_NULL_PARAM)); + return MYKONOS_ERR_GETINITCALSTATUS_NULL_PARAM; + } + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &payload[0], sizeof(payload)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; /* Will return if mailbox busy bit is busy for more than 2 seconds */ + } + + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETINITCALSTATUS_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_GETINITCALSTATUS_ARMERROR)); + return MYKONOS_ERR_GETINITCALSTATUS_ARMERROR; + } + + return retVal; /* Will return if timeout occurred */ + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETINITCALSTATUS_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_GETINITCALSTATUS_ARMERROR)); + return MYKONOS_ERR_GETINITCALSTATUS_ARMERROR; + } + + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &calStatusArray[0], sizeof(calStatusArray), 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + initCalStatus->calsDoneLifetime = ((uint32_t)(calStatusArray[3]) << 24) | ((uint32_t)(calStatusArray[2]) << 16) | ((uint32_t)(calStatusArray[1]) << 8) + | ((uint32_t)(calStatusArray[0])); + initCalStatus->calsDoneLastRun = ((uint32_t)(calStatusArray[7]) << 24) | ((uint32_t)(calStatusArray[6]) << 16) | ((uint32_t)(calStatusArray[5]) << 8) + | ((uint32_t)(calStatusArray[4])); + initCalStatus->calsMinimum = ((uint32_t)(calStatusArray[11]) << 24) | ((uint32_t)(calStatusArray[10]) << 16) | ((uint32_t)(calStatusArray[9]) << 8) + | ((uint32_t)(calStatusArray[8])); + initCalStatus->initErrCal = calStatusArray[12]; + initCalStatus->initErrCode = calStatusArray[13]; + + return MYKONOS_ERR_OK; +} + +/** + * \brief Instructs the ARM processor to move the radio state to the Radio ON state + * + * When the ARM to the Radio On state, the enabled Rx and Tx signal chains will power up, + * and the ARM tracking calibrations will begin. To exit this state back to a low power, + * offline state, call the MYKONOS_radioOff() function. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_ARM_RADIOON_FAILED ARM returned error running this command + */ +mykonosErr_t MYKONOS_radioOn(mykonosDevice_t *device) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint32_t timeoutMs = 1000; //1 second timeout + uint8_t cmdStatusByte = 0; + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_RADIOON_OPCODE, 0, 0); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; /* Will return if mailbox busy bit is busy for more than 2 seconds */ + } + + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_RADIOON_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ARM_RADIOON_FAILED, + getMykonosErrorMessage(MYKONOS_ERR_ARM_RADIOON_FAILED)); + return MYKONOS_ERR_ARM_RADIOON_FAILED; + } + + return retVal; /* Will return if timeout occurred */ + } + + /* If ARM command error flag is 2, the command was not accepted, RUN_INIT must complete first */ + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ARM_RADIOON_FAILED, getMykonosErrorMessage(MYKONOS_ERR_ARM_RADIOON_FAILED)); + return MYKONOS_ERR_ARM_RADIOON_FAILED; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Instructs the ARM processor to move the radio state to the off state + * + * When the ARM moves from the Radio On state to Radio Off (Idle) the ARM tracking calibrations + * are stopped and the TxEnable/RxEnable, etc GPIO control pins will be ignored. This will also + * keep the receive and transmit chains powered down until the MYKONOS_radioOn() function + * is called again. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_ARM_RADIOOFF_FAILED ARM returned error running this command + */ +mykonosErr_t MYKONOS_radioOff(mykonosDevice_t *device) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + const uint8_t ABORTCAL_OPCODE = 0x00; + uint32_t timeoutMs = 1000; //1 second timeout + uint8_t cmdStatusByte = 0; + + retVal = MYKONOS_sendArmCommand(device, ABORTCAL_OPCODE, 0, 0); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; /* Will return if mailbox busy bit is busy for more than 2 seconds */ + } + + retVal = MYKONOS_waitArmCmdStatus(device, ABORTCAL_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ARM_RADIOOFF_FAILED, + getMykonosErrorMessage(MYKONOS_ERR_ARM_RADIOOFF_FAILED)); + return MYKONOS_ERR_ARM_RADIOOFF_FAILED; + } + + return retVal; /* Will return if timeout occurred */ + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ARM_RADIOOFF_FAILED, getMykonosErrorMessage(MYKONOS_ERR_ARM_RADIOOFF_FAILED)); + return MYKONOS_ERR_ARM_RADIOOFF_FAILED; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads the current ARM radio state + * + * Currently, *radioStatus only returns data in the lower 8 bits, but + * is defined as a 32bit status to allow for more information to be returned + * in the future. + * + * radioStatus | Bitfield + * -------------|------------------ + * [1:0] | State[1:0], 0=POWERUP, 1=READY, 2=INIT, 3=RADIO ON + * [3:2] | unused + * [4] | TDD_nFDD , 1= TDD, 0=FDD + * [7:5] | unused + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * \param radioStatus The current ARM radio state is returned in this parameter + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETRADIOSTATE_NULL_PARAM Function parameter radioStatus has a NULL pointer + */ +mykonosErr_t MYKONOS_getRadioState(mykonosDevice_t *device, uint32_t *radioStatus) +{ + uint8_t status = 0; + + /* if radioStatus is not null */ + if (radioStatus != NULL) + { + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_ARM_OPCODE_STATE_0, &status); + *radioStatus = (uint32_t)status; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRADIOSTATE_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETRADIOSTATE_NULL_PARAM)); + return MYKONOS_ERR_GETRADIOSTATE_NULL_PARAM; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets which ARM tracking cals are enabled during the radioOn state. + * + * This command must be called during radioOff state. If called during radioOn, + * an error will be returned. The enum mykonosTrackingCalibrations_t can be used to + * OR together to form the enableMask parameter. + * + * enableMask | Bit description + * ------------|------------ + * [0] | TRACK_RX1_QEC + * [1] | TRACK_RX2_QEC + * [2] | TRACK_ORX1_QEC + * [3] | TRACK_ORX2_QEC + * [4] | TRACK_TX1_LOL + * [5] | TRACK_TX2_LOL + * [6] | TRACK_TX1_QEC + * [7] | TRACK_TX2_QEC + * [8] | TRACK_TX1_DPD + * [9] | TRACK_TX2_DPD + * [10] | TRACK_TX1_CLGC + * [11] | TRACK_TX2_CLGC + * [12] | TRACK_TX1_VSWR + * [13] | TRACK_TX2_VSWR + * [16] | TRACK_ORX1_QEC_SNLO + * [17] | TRACK_ORX2_QEC_SNLO + * [18] | TRACK_SRX_QEC + * + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * \param enableMask A bitmask that selects which cals to run during radioOn state. + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_EN_TRACKING_CALS_ARMSTATE_ERROR Error: Tracking cals can only be enabled in the radioOff state. + * \retval MYKONOS_ERR_EN_TRACKING_CALS_ARMERROR ARM returned error when executing this command + */ +mykonosErr_t MYKONOS_enableTrackingCals(mykonosDevice_t *device, uint32_t enableMask) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armData[4] = {0, 0, 0, 0}; + uint8_t extData[4] = {MYKONOS_ARM_OBJECTID_CALSCHEDULER, 0x00, 0x00, 0x04}; //Target ARM Object ID, Offset LSB, Offset MSB, Length + uint32_t timeoutMs = 0; + uint8_t cmdStatusByte = 0; + uint32_t radioStatus = 0; + uint8_t allowTx1AttenUpdates = 0; + uint8_t allowTx2AttenUpdates = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableTrackingCals()\n"); +#endif + + /* read radio state to make sure ARM is in radioOff /IDLE */ + retVal = MYKONOS_getRadioState(device, &radioStatus); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* throw error if not in radioOff/IDLE state */ + if ((radioStatus & 0x03) != MYKONOS_ARM_SYSTEMSTATE_IDLE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_EN_TRACKING_CALS_ARMSTATE_ERROR, + getMykonosErrorMessage(MYKONOS_ERR_EN_TRACKING_CALS_ARMSTATE_ERROR)); + return MYKONOS_ERR_EN_TRACKING_CALS_ARMSTATE_ERROR; + } + + /* In the ARM, DPD tracking and CLGC tracking share the same cal. Must + * set extra enable bits in ARM Memory to tell which cal to run. */ + retVal = enableDpdTracking(device, ((enableMask & (uint32_t)TRACK_TX1_DPD) ? 1 : 0), ((enableMask & (uint32_t)TRACK_TX2_DPD) ? 1 : 0)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + if (((device->profilesValid & TX_PROFILE_VALID) > 0) && (device->tx->clgcConfig != NULL)) + { + allowTx1AttenUpdates = device->tx->clgcConfig->allowTx1AttenUpdates; + allowTx2AttenUpdates = device->tx->clgcConfig->allowTx2AttenUpdates; + } + else + { + allowTx1AttenUpdates = 0; + allowTx2AttenUpdates = 0; + } + + retVal = enableClgcTracking(device, ((allowTx1AttenUpdates > 0) ? 1 : 0), ((allowTx2AttenUpdates > 0) ? 1 : 0)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + armData[0] = (uint8_t)(enableMask & 0xFF); + armData[1] = (uint8_t)((enableMask >> 8) & 0xFF); + armData[2] = (uint8_t)((enableMask >> 16) & 0xFF); + armData[3] = (uint8_t)((enableMask >> 24) & 0xFF); + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &armData[0], sizeof(armData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_WRITECFG_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_WRITECFG_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_EN_TRACKING_CALS_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_EN_TRACKING_CALS_ARMERROR)); + return MYKONOS_ERR_EN_TRACKING_CALS_ARMERROR; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_EN_TRACKING_CALS_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_EN_TRACKING_CALS_ARMERROR)); + return MYKONOS_ERR_EN_TRACKING_CALS_ARMERROR; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reschedules a tracking calibration to run. Can be used to + * override the tracking calibration timer and force a tracking calibration to run. + * Can be used to reschedule a tracking calibration after a tracking calibration + * error has been detected. Only one tracking calibration object can be scheduled + * per channel per function call. + * + * \pre Command can be called in either Radio On or Radio Off state. ARM must be + * initialized. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * \param trackingCal Selects the tracking calibration to schedule. + * + * \retval MYKONOS_ERR_RESCHEDULE_TRACK_CAL_INV Not valid calibration passed + * \retval MYKONOS_ERR_RESCHEDULE_TRACK_ARMERRFLAG ARM error + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_rescheduleTrackingCal(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t extData[3] = {0}; + uint8_t cmdStatusByte = 0; + uint32_t timeoutMs = 1000; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_rescheduleTrackingCal()\n"); +#endif + + switch (trackingCal) + { + case TRACK_RX1_QEC: + extData[1] = MYKONOS_ARM_OBJECTID_RXQEC_TRACKING; + extData[2] = 0; + break; + + case TRACK_RX2_QEC: + extData[1] = MYKONOS_ARM_OBJECTID_RXQEC_TRACKING; + extData[2] = 1; + break; + + case TRACK_ORX1_QEC: + extData[1] = MYKONOS_ARM_OBJECTID_ORXQEC_TRACKING; + extData[2] = 0; + break; + + case TRACK_ORX2_QEC: + extData[1] = MYKONOS_ARM_OBJECTID_ORXQEC_TRACKING; + extData[2] = 1; + break; + + case TRACK_TX1_LOL: + extData[1] = MYKONOS_ARM_OBJECTID_TXLOL_TRACKING; + extData[2] = 0; + break; + + case TRACK_TX2_LOL: + extData[1] = MYKONOS_ARM_OBJECTID_TXLOL_TRACKING; + extData[2] = 1; + break; + + case TRACK_TX1_QEC: + extData[1] = MYKONOS_ARM_OBJECTID_TXQEC_TRACKING; + extData[2] = 0; + break; + + case TRACK_TX2_QEC: + extData[1] = MYKONOS_ARM_OBJECTID_TXQEC_TRACKING; + extData[2] = 1; + break; + + case TRACK_TX1_DPD: + extData[1] = MYKONOS_ARM_OBJECTID_DPDCONFIG; + extData[2] = 0; + break; + + case TRACK_TX2_DPD: + extData[1] = MYKONOS_ARM_OBJECTID_DPDCONFIG; + extData[2] = 1; + break; + + case TRACK_TX1_CLGC: + extData[1] = MYKONOS_ARM_OBJECTID_CLGCCONFIG; + extData[2] = 0; + break; + + case TRACK_TX2_CLGC: + extData[1] = MYKONOS_ARM_OBJECTID_CLGCCONFIG; + extData[2] = 1; + break; + + case TRACK_TX1_VSWR: + extData[1] = MYKONOS_ARM_OBJECTID_VSWRCONFIG; + extData[2] = 0; + break; + + case TRACK_TX2_VSWR: + extData[1] = MYKONOS_ARM_OBJECTID_VSWRCONFIG; + extData[2] = 1; + break; + + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RESCHEDULE_TRACK_CAL_INV, + getMykonosErrorMessage(MYKONOS_ERR_RESCHEDULE_TRACK_CAL_INV)); + return MYKONOS_ERR_RESCHEDULE_TRACK_CAL_INV; + } + + extData[0] = MYKONOS_ARM_OBJECTID_TRACKING_CAL_PENDING; + + /* sending ARM command */ + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_SET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* check for completion */ + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_SET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RESCHEDULE_TRACK_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_RESCHEDULE_TRACK_ARMERRFLAG)); + return MYKONOS_ERR_RESCHEDULE_TRACK_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RESCHEDULE_TRACK_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_RESCHEDULE_TRACK_ARMERRFLAG)); + return MYKONOS_ERR_RESCHEDULE_TRACK_ARMERRFLAG; + } + + return retVal; +} + +/** + * \brief Suspend or resume tracking calibrations in RADIO_ON. + * + * This function is used to suspend or resume active tracking calibrations based on the passed mask trackingCals. + * + * \pre Command can be called in Radio On. + * + * trackCals[bit] | Bit description + * ----------------|------------ + * [0] | TRACK_RX1_QEC + * [1] | TRACK_RX2_QEC + * [2] | TRACK_ORX1_QEC + * [3] | TRACK_ORX2_QEC + * [4] | TRACK_TX1_LOL + * [5] | TRACK_TX2_LOL + * [6] | TRACK_TX1_QEC + * [7] | TRACK_TX2_QEC + * [8] | TRACK_TX1_DPD + * [9] | TRACK_TX2_DPD + * [10] | TRACK_TX1_CLGC + * [11] | TRACK_TX2_CLGC + * [12] | TRACK_TX1_VSWR + * [13] | TRACK_TX2_VSWR + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * \param trackCals Selects the tracking calibrations to suspend or resume during the radio ON state. + * mykonosTrackingCalibrations_t enumerated types are or'd together to form the tracking calibration + * mask word. If the bit is high the calibration will resume, if the bit is low the calibration will be suspended. + * + * \retval MYKONOS_ERR_SETSTATEALL_TRACK_CAL_INV Not valid calibration mask passed for trackCals + * \retval MYKONOS_ERR_SETSTATEALL_TRACK_ARMERRFLAG ARM error + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setAllTrackCalState(mykonosDevice_t *device, uint32_t trackCals) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t cfgData[4] = {0}; + uint8_t extData[3] = {MYKONOS_ARM_OBJECTID_TRACKING_CAL_SUSPEND_RESUME, 0x0F, 0}; + uint8_t cmdStatusByte = 0; + uint32_t enTrackCal = 0x00; + uint32_t timeoutMs = 1000; + + const uint32_t TRACKING_MASK = 0x3FFF; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setAllTrackCalState()\n"); +#endif + + /* reading enabled tracking calibrations */ + retVal = MYKONOS_getEnabledTrackingCals(device, &enTrackCal); + + /* trackingCalMask check */ + if (((trackCals | enTrackCal) > enTrackCal) || (trackCals > TRACKING_MASK)) + { + /* invalid cal mask error return, tracking cal not enable so we can not resume it */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETSTATEALL_TRACK_CAL_INV, + getMykonosErrorMessage(MYKONOS_ERR_SETSTATEALL_TRACK_CAL_INV)); + return MYKONOS_ERR_SETSTATEALL_TRACK_CAL_INV; + } + + /* convert tracking mask to array of uint8_t type */ + cfgData[0] = (uint8_t)(trackCals & 0xFF); + cfgData[1] = (uint8_t)((trackCals >> 8) & 0xFF); + cfgData[2] = (uint8_t)((trackCals >> 16) & 0x0FF); + cfgData[3] = (uint8_t)((trackCals >> 24) & 0xFF); + + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &cfgData[0], sizeof(cfgData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_SET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* check for completion */ + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_SET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETSTATEALL_TRACK_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_SETSTATEALL_TRACK_ARMERRFLAG)); + return MYKONOS_ERR_SETSTATEALL_TRACK_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETSTATEALL_TRACK_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_SETSTATEALL_TRACK_ARMERRFLAG)); + return MYKONOS_ERR_SETSTATEALL_TRACK_ARMERRFLAG; + } + + return retVal; +} + +/** + * \brief Get the Suspended or Resumed state for tracking calibrations + * + * This function is used to get the suspend or resume state of all active tracking calibrations and the state is stored in trackCals. + * + * \pre Command can be called in Radio On. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * \param trackCals pointer to store the tracking calibration state. + * If the bit is set then the tracking calibration is resumed and if not set then the tracking cal is suspended, the bit field follows: + * + * trackCals[bit] | Bit description + * ---------------|------------ + * [0] | TRACK_RX1_QEC + * [1] | TRACK_RX2_QEC + * [2] | TRACK_ORX1_QEC + * [3] | TRACK_ORX2_QEC + * [4] | TRACK_TX1_LOL + * [5] | TRACK_TX2_LOL + * [6] | TRACK_TX1_QEC + * [7] | TRACK_TX2_QEC + * [8] | TRACK_TX1_DPD + * [9] | TRACK_TX2_DPD + * [10] | TRACK_TX1_CLGC + * [11] | TRACK_TX2_CLGC + * [12] | TRACK_TX1_VSWR + * [13] | TRACK_TX2_VSWR + * + * \retval MYKONOS_ERR_GETSTATEALL_TRACK_NULL_PARAM Null parameter passed for trackCals + * \retval MYKONOS_ERR_GETSTATEALL_TRACK_ARMERRFLAG ARM error flag set. + * \retval MYKONOS_ERR_GETSTATEALL_TRACK_ARMERROR ARM command error. + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getAllTrackCalState(mykonosDevice_t *device, uint32_t *trackCals) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t extData = MYKONOS_ARM_OBJECTID_TRACKING_CAL_SUSPEND_RESUME; + uint8_t armData[4] = {0}; + uint8_t cmdStatusByte = 0; + uint32_t timeoutMs = 1000; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getAllTrackCalState()\n"); +#endif + + /* Check for passed parameter */ + if (trackCals == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETSTATEALL_TRACK_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETSTATEALL_TRACK_NULL_PARAM)); + return MYKONOS_ERR_GETSTATEALL_TRACK_NULL_PARAM; + } + + /* sending ARM command */ + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData, sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* check for completion */ + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETSTATEALL_TRACK_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETSTATEALL_TRACK_ARMERRFLAG)); + return MYKONOS_ERR_GETSTATEALL_TRACK_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETSTATEALL_TRACK_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETSTATEALL_TRACK_ARMERRFLAG)); + return MYKONOS_ERR_GETSTATEALL_TRACK_ARMERRFLAG; + } + + /* read 32-bit tracking state from ARM memory */ + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &armData[0], sizeof(armData), 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + *trackCals = (uint32_t)armData[0] | ((uint32_t)armData[1] << 8) | ((uint32_t)armData[2] << 16) | ((uint32_t)armData[3] << 24); + + return retVal; +} + +/** + * \brief Suspend or resume individual tracking calibration + * + * \pre The tracking calibration must have been enabled with MYKONOS_enableTrackingCals(), this command can be called in Radio On. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * \param trackingCal Selects the tracking calibration to resume or suspend. + * \param trackCalState if set then the selected tracking calibration will be resumed and if not set then the tracking cal will be suspended + * + * \retval MYKONOS_ERR_SETSTATE_TRACK_CAL_INV Not valid calibration passed + * \retval MYKONOS_ERR_SETSTATE_TRACK_ARMERRFLAG ARM error + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setTrackingCalState(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal, uint8_t trackCalState) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t extData[2] = {0}; + uint8_t cmdStatusByte = 0; + uint8_t suspendTrack = 0x0F; + uint32_t timeoutMs = 1000; + uint32_t enTrackCal = 0x00; + + const uint8_t CHANNEL_1 = 0x00; + const uint8_t CHANNEL_2 = 0x10; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setTrackingCalState()\n"); +#endif + + if (trackCalState > 0) + { + suspendTrack = 0x2F; + } + + /* reading enabled tracking calibrations */ + retVal = MYKONOS_getEnabledTrackingCals(device, &enTrackCal); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* trackingCalMask check */ + if (((uint8_t)trackingCal & enTrackCal) != (uint8_t)trackingCal) + { + /* invalid cal mask error return, tracking cal not enable so we can not resume or suspend it */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETSTATE_TRACK_CAL_INV, + getMykonosErrorMessage(MYKONOS_ERR_SETSTATE_TRACK_CAL_INV)); + return MYKONOS_ERR_SETSTATE_TRACK_CAL_INV; + } + + switch (trackingCal) + { + case TRACK_RX1_QEC: + extData[1] = MYKONOS_ARM_OBJECTID_RXQEC_TRACKING & suspendTrack; + extData[1] |= CHANNEL_1; + break; + + case TRACK_RX2_QEC: + extData[1] = MYKONOS_ARM_OBJECTID_RXQEC_TRACKING & suspendTrack; + extData[1] |= CHANNEL_2; + break; + + case TRACK_ORX1_QEC: + extData[1] = MYKONOS_ARM_OBJECTID_ORXQEC_TRACKING & suspendTrack; + extData[1] |= CHANNEL_1; + break; + + case TRACK_ORX2_QEC: + extData[1] = MYKONOS_ARM_OBJECTID_ORXQEC_TRACKING & suspendTrack; + extData[1] |= CHANNEL_2; + break; + + case TRACK_TX1_LOL: + extData[1] = MYKONOS_ARM_OBJECTID_TXLOL_TRACKING & suspendTrack; + extData[1] |= CHANNEL_1; + break; + + case TRACK_TX2_LOL: + extData[1] = MYKONOS_ARM_OBJECTID_TXLOL_TRACKING & suspendTrack; + extData[1] |= CHANNEL_2; + break; + + case TRACK_TX1_QEC: + extData[1] = MYKONOS_ARM_OBJECTID_TXQEC_TRACKING & suspendTrack; + extData[1] |= CHANNEL_1; + break; + + case TRACK_TX2_QEC: + extData[1] = MYKONOS_ARM_OBJECTID_TXQEC_TRACKING & suspendTrack; + extData[1] |= CHANNEL_2; + break; + + case TRACK_TX1_DPD: + extData[1] = MYKONOS_ARM_OBJECTID_DPDCONFIG & suspendTrack; + extData[1] |= CHANNEL_1; + break; + + case TRACK_TX2_DPD: + extData[1] = MYKONOS_ARM_OBJECTID_DPDCONFIG & suspendTrack; + extData[1] |= CHANNEL_2; + break; + + case TRACK_TX1_CLGC: + extData[1] = MYKONOS_ARM_OBJECTID_CLGCCONFIG & suspendTrack; + extData[1] |= CHANNEL_1; + break; + + case TRACK_TX2_CLGC: + extData[1] = MYKONOS_ARM_OBJECTID_CLGCCONFIG & suspendTrack; + extData[1] |= CHANNEL_2; + break; + + case TRACK_TX1_VSWR: + extData[1] = MYKONOS_ARM_OBJECTID_VSWRCONFIG & suspendTrack; + extData[1] |= CHANNEL_1; + break; + + case TRACK_TX2_VSWR: + extData[1] = MYKONOS_ARM_OBJECTID_VSWRCONFIG & suspendTrack; + extData[1] |= CHANNEL_2; + break; + + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETSTATE_TRACK_CAL_INV, + getMykonosErrorMessage(MYKONOS_ERR_SETSTATE_TRACK_CAL_INV)); + return MYKONOS_ERR_SETSTATE_TRACK_CAL_INV; + } + + extData[0] = MYKONOS_ARM_OBJECTID_TRACKING_CAL_SUSPEND_RESUME; + + /* sending ARM command */ + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_SET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* check for completion */ + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_SET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETSTATE_TRACK_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_SETSTATE_TRACK_ARMERRFLAG)); + return MYKONOS_ERR_SETSTATE_TRACK_ARMERRFLAG; + } + } + + return retVal; +} + +/** + * \brief Get the Suspended or Resumed state for individual tracking calibration + * + * \pre Command can be called in Radio On. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * \param trackingCal Selects the tracking calibration to get the resumed or suspended state. + * \param trackCalState pointer to store the tracking calibration state, + * if set then the selected tracking calibration is resumed and if not set then the tracking cal is suspended + * + * \retval MYKONOS_ERR_GETSTATE_TRACK_NULL_PARAM Null parameter passed to trackCalState + * \retval MYKONOS_ERR_GETSTATE_TRACK_ARMERRFLAG ARM command error flag set. + * \retval MYKONOS_ERR_GETSTATE_TRACK_ARMERROR ARM command error. + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getTrackingCalState(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal, uint8_t *trackCalState) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t extData = MYKONOS_ARM_OBJECTID_TRACKING_CAL_SUSPEND_RESUME; + uint8_t armData[4] = {0}; + uint8_t cmdStatusByte = 0; + uint32_t timeoutMs = 1000; + uint32_t trackMask = 0x00; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getTrackingCalState()\n"); +#endif + + /* Check for passed parameter */ + if (trackCalState == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETSTATE_TRACK_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETSTATE_TRACK_NULL_PARAM)); + return MYKONOS_ERR_GETSTATE_TRACK_NULL_PARAM; + } + + /* sending ARM command */ + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData, sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* check for completion */ + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETSTATE_TRACK_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETSTATE_TRACK_ARMERRFLAG)); + return MYKONOS_ERR_GETSTATE_TRACK_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETSTATE_TRACK_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETSTATE_TRACK_ARMERRFLAG)); + return MYKONOS_ERR_GETSTATE_TRACK_ARMERRFLAG; + } + + /* read 32-bit tracking state from ARM memory */ + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &armData[0], sizeof(armData), 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + trackMask = (uint32_t)armData[0] | ((uint32_t)armData[1] << 8) | ((uint32_t)armData[2] << 16) | ((uint32_t)armData[3] << 24); + + if (trackMask & (uint32_t)trackingCal) + { + *trackCalState = 1; + } + else + { + *trackCalState = 0; + } + + return retVal; +} + +/** + * \brief Reads back which ARM tracking cals are enabled + * + * enableMask | Bit description + * ------------|---------------------- + * [0] | TRACK_RX1_QEC + * [1] | TRACK_RX2_QEC + * [2] | TRACK_ORX1_QEC + * [3] | TRACK_ORX2_QEC + * [4] | TRACK_TX1_LOL + * [5] | TRACK_TX2_LOL + * [6] | TRACK_TX1_QEC + * [7] | TRACK_TX2_QEC + * [8] | TRACK_TX1_DPD + * [9] | TRACK_TX2_DPD + * [10] | TRACK_TX1_CLGC + * [11] | TRACK_TX2_CLGC + * [12] | TRACK_TX1_VSWR + * [13] | TRACK_TX2_VSWR + * [16] | TRACK_ORX1_QEC_SNLO + * [17] | TRACK_ORX1_QEC_SNLO + * [18] | TRACK_SRX_QEC + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * \param enableMask Returned bitmask that shows which tracking cals are enabled + * to run during radioOn state. See mykonosTrackingCalibrations_t enum of tracking cals. + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getEnabledTrackingCals(mykonosDevice_t *device, uint32_t *enableMask) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armData[4] = {0}; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getEnabledTrackingCals()\n"); +#endif + + /* Ask ARM to read tracking cal enable bits and place in mailbox buffer memory */ + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_CALSCHEDULER, 0, &armData[0], 4); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + *enableMask = ((uint32_t)(armData[0]) | ((uint32_t)(armData[1]) << 8) | ((uint32_t)(armData[2]) << 16) | ((uint32_t)(armData[3]) << 24)); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Returns the tracking calibration pending and error status. + * + * When in radioOn state, the enabled tracking calibrations will set the pending + * flag when the particular calibration is ready to be run, but has not completed + * yet. For Tx tracking cals to complete, the BBIC must set the ObsRx path to + * the INTERNAL CALS mode. If a tracking calibration had an error, the corresponding + * error flag will be asserted. + * + * pendingCalMask | bit Description + * ----------------|-------------------------------------------------------- + * [0] | Rx1 QEC tracking pending + * [1] | Rx1 QEC tracking error + * [2] | Rx2 QEC tracking pending + * [3] | Rx2 QEC tracking error + * [4] | ORx1 QEC tracking pending + * [5] | ORx1 QEC tracking error + * [6] | ORx2 QEC tracking pending + * [7] | ORx2 QEC tracking error + * [8] | Tx1 LOL tracking pending + * [9] | Tx1 LOL tracking error + * [10] | Tx2 LOL tracking pending + * [11] | Tx2 LOL tracking error + * [12] | Tx1 QEC tracking pending + * [13] | Tx1 QEC tracking error + * [14] | Tx2 QEC tracking pending + * [15] | Tx2 QEC tracking error + * [16] | Tx1 DPD tracking pending + * [17] | Tx1 DPD tracking error + * [18] | Tx2 DPD tracking pending + * [19] | Tx2 DPD tracking error + * [20] | Tx1 CLGC tracking pending + * [21] | Tx1 CLGC tracking error + * [22] | Tx2 CLGC tracking pending + * [23] | Tx2 CLGC tracking error + * [24] | Tx1 VSWR tracking pending + * [25] | Tx1 VSWR tracking error + * [26] | Tx2 VSWR tracking pending + * [27] | Tx2 VSWR tracking error + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * \param pendingCalMask Bit mask that describes which tracking cals are pending + * or had errors + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETPENDTRKCALS_NULL_PARAM Function parameter pendingCalMask is a NULL pointer + */ +mykonosErr_t MYKONOS_getPendingTrackingCals(mykonosDevice_t *device, uint32_t *pendingCalMask) +{ + uint8_t readData[4] = {0}; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getPendingTrackingCals()\n"); +#endif + + if (pendingCalMask == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETPENDTRKCALS_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETPENDTRKCALS_NULL_PARAM)); + return MYKONOS_ERR_GETPENDTRKCALS_NULL_PARAM; + } + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_ARM_OPCODE_STATE_3, &readData[0]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_ARM_OPCODE_STATE_4, &readData[1]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_ARM_OPCODE_STATE_5, &readData[2]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_ARM_OPCODE_STATE_6, &readData[3]); + *pendingCalMask = ((uint32_t)readData[3] << 24) | ((uint32_t)readData[2] << 16) | ((uint32_t)readData[1] << 8) | ((uint32_t)readData[0]); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Returns the status of the TxLOL external tracking calibration + * + * The Tx LOL external tracking calibration is run during the radioOn state. + * The function can be called to read back the status of the TxLOL external + * calibration including metrics like error codes, percentage of data + * collected for current cal, the performance of the cal and the number of + * times the cal has run and updated the hardware. + * + * \pre Before the function is called, the device must be initialized, the ARM + * loaded, and init cals run. These functions can be called in radioOff or + * radioOn state. + * + * \param device Pointer to the device settings structure + * \param txChannel The channel (Tx1/Tx2) whose status is to be read back + * \param txLolStatus Status of the TxLOL external calibration, as a structure + * of type mykonosTxLolStatus_t is returned to this pointer address + * + * \retval MYKONOS_ERR_GETTXLOLSTATUS_NULLPARAM Function parameter mykonosTxLolStatus_t is a NULL pointer + * \retval MYKONOS_ERR_GETTXLOLSTATUS_INV_CH Channel selection not valid + * \retval MYKONOS_ERR_GETTXLOLSTATUS_ARMERRFLAG ARM command error + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getTxLolStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosTxLolStatus_t *txLolStatus) +{ + uint8_t extData[3] = {MYKONOS_ARM_OBJECTID_CAL_STATUS, MYKONOS_ARM_OBJECTID_TXLOL_TRACKING, 0}; + uint8_t cmdStatusByte = 0; + uint32_t offset = 0; + uint32_t timeoutMs = 0; + uint8_t armReadBack[20] = {0}; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getTxLolStatus()\n"); +#endif + + if (txLolStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTXLOLSTATUS_NULLPARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETTXLOLSTATUS_NULLPARAM)); + return MYKONOS_ERR_GETTXLOLSTATUS_NULLPARAM; + } + + switch (txChannel) + { + case TX1: + extData[2] = 0; + break; + case TX2: + extData[2] = 1; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTXLOLSTATUS_INV_CH, + getMykonosErrorMessage(MYKONOS_ERR_GETTXLOLSTATUS_INV_CH)); + return MYKONOS_ERR_GETTXLOLSTATUS_INV_CH; + } + } + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTXLOLSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETTXLOLSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETTXLOLSTATUS_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTXLOLSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETTXLOLSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETTXLOLSTATUS_ARMERRFLAG; + } + + /* read status from ARM memory */ + offset = 0; + retVal = MYKONOS_readArmMem(device, (MYKONOS_ADDR_ARM_START_DATA_ADDR + offset), &armReadBack[0], sizeof(armReadBack), 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Assign to data structure */ + txLolStatus->errorCode = (((uint32_t)armReadBack[3]) << 24) | (((uint32_t)armReadBack[2]) << 16) | (((uint32_t)armReadBack[1]) << 8) | ((uint32_t)armReadBack[0]); + txLolStatus->percentComplete = (((uint32_t)armReadBack[7]) << 24) | (((uint32_t)armReadBack[6]) << 16) | (((uint32_t)armReadBack[5]) << 8) + | ((uint32_t)armReadBack[4]); + txLolStatus->performanceMetric = (((uint32_t)armReadBack[11]) << 24) | (((uint32_t)armReadBack[10]) << 16) | (((uint32_t)armReadBack[9]) << 8) + | ((uint32_t)armReadBack[8]); + txLolStatus->iterCount = (((uint32_t)armReadBack[15]) << 24) | (((uint32_t)armReadBack[14]) << 16) | (((uint32_t)armReadBack[13]) << 8) | ((uint32_t)armReadBack[12]); + txLolStatus->updateCount = (((uint32_t)armReadBack[19]) << 24) | (((uint32_t)armReadBack[18]) << 16) | (((uint32_t)armReadBack[17]) << 8) + | ((uint32_t)armReadBack[16]); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Returns the status of the TxQEC tracking calibration + * + * The Tx QEC tracking calibration is run during the radioOn state. + * The function can be called to read back the status of the TxQEC + * calibration including metrics like error codes, percentage of data + * collected for current cal, the performance of the cal and the number of + * times the cal has run and updated the hardware. + * + * \pre Before the function is called, the device must be initialized, the ARM + * loaded, and init cals run. These functions can be called in radioOff or + * radioOn state. + * + * \param device Pointer to the device settings structure + * \param txChannel The channel (Tx1/Tx2) whose status is to be read back + * \param txQecStatus Status of the TxQEC external calibration, as a structure + * of type mykonosTxQecStatus_t is returned to this pointer address + * + * \retval MYKONOS_ERR_GETTXQECSTATUS_NULLPARAM Function parameter txQecStatus is a NULL pointer + * \retval MYKONOS_ERR_GETTXQECSTATUS_INV_CH Channel selection not valid + * \retval MYKONOS_ERR_GETTXQECSTATUS_ARMERRFLAG ARM command error + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getTxQecStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosTxQecStatus_t *txQecStatus) +{ + uint8_t extData[3] = {MYKONOS_ARM_OBJECTID_CAL_STATUS, MYKONOS_ARM_OBJECTID_TXQEC_TRACKING, 0}; + uint8_t cmdStatusByte = 0; + uint32_t offset = 0; + uint32_t timeoutMs = 0; + uint8_t armReadBack[20] = {0}; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getTxQecStatus()\n"); +#endif + + if (txQecStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTXQECSTATUS_NULLPARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETTXQECSTATUS_NULLPARAM)); + return MYKONOS_ERR_GETTXQECSTATUS_NULLPARAM; + } + + switch (txChannel) + { + case TX1: + extData[2] = 0; + break; + case TX2: + extData[2] = 1; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTXQECSTATUS_INV_CH, + getMykonosErrorMessage(MYKONOS_ERR_GETTXQECSTATUS_INV_CH)); + return MYKONOS_ERR_GETTXQECSTATUS_INV_CH; + } + } + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTXQECSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETTXQECSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETTXQECSTATUS_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTXQECSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETTXQECSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETTXQECSTATUS_ARMERRFLAG; + } + + /* read status from ARM memory */ + offset = 0; + retVal = MYKONOS_readArmMem(device, (MYKONOS_ADDR_ARM_START_DATA_ADDR + offset), &armReadBack[0], sizeof(armReadBack), 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Assign to data structure */ + txQecStatus->errorCode = (((uint32_t)armReadBack[3]) << 24) | (((uint32_t)armReadBack[2]) << 16) | (((uint32_t)armReadBack[1]) << 8) | ((uint32_t)armReadBack[0]); + txQecStatus->percentComplete = (((uint32_t)armReadBack[7]) << 24) | (((uint32_t)armReadBack[6]) << 16) | (((uint32_t)armReadBack[5]) << 8) + | ((uint32_t)armReadBack[4]); + txQecStatus->performanceMetric = (((uint32_t)armReadBack[11]) << 24) | (((uint32_t)armReadBack[10]) << 16) | (((uint32_t)armReadBack[9]) << 8) + | ((uint32_t)armReadBack[8]); + txQecStatus->iterCount = (((uint32_t)armReadBack[15]) << 24) | (((uint32_t)armReadBack[14]) << 16) | (((uint32_t)armReadBack[13]) << 8) | ((uint32_t)armReadBack[12]); + txQecStatus->updateCount = (((uint32_t)armReadBack[19]) << 24) | (((uint32_t)armReadBack[18]) << 16) | (((uint32_t)armReadBack[17]) << 8) + | ((uint32_t)armReadBack[16]); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Returns the status of the RxQEC tracking calibration + * + * The Rx QEC tracking calibration is run during the radioOn state. + * The function can be called to read back the status of the RxQEC external + * calibration including metrics like error codes, percentage of data + * collected for current cal, the performance of the cal and the number of + * times the cal has run and updated the hardware. + * + * \pre Before the function is called, the device must be initialized, the ARM + * loaded, and init cals run. These functions can be called in radioOff or + * radioOn state. + * + * \param device Pointer to the device settings structure + * \param rxChannel The channel (Rx1/Rx2) whose status is to be read back + * \param rxQecStatus Status of the RxQEC calibration, as a structure + * of type mykonosRxQecStatus_t is returned to this pointer address + * + * \retval MYKONOS_ERR_GETRXQECSTATUS_NULLPARAM Function parameter rxQecStatus is a NULL pointer + * \retval MYKONOS_ERR_GETRXQECSTATUS_INV_CH Channel selection not valid + * \retval MYKONOS_ERR_GETRXQECSTATUS_ARMERRFLAG ARM command error + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getRxQecStatus(mykonosDevice_t *device, mykonosRxChannels_t rxChannel, mykonosRxQecStatus_t *rxQecStatus) +{ + uint8_t extData[3] = {MYKONOS_ARM_OBJECTID_CAL_STATUS, MYKONOS_ARM_OBJECTID_RXQEC_TRACKING, 0}; + uint8_t cmdStatusByte = 0; + uint32_t offset = 0; + uint32_t timeoutMs = 0; + uint8_t armReadBack[20] = {0}; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getRxQecStatus()\n"); +#endif + + if (rxQecStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRXQECSTATUS_NULLPARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETRXQECSTATUS_NULLPARAM)); + return MYKONOS_ERR_GETRXQECSTATUS_NULLPARAM; + } + + switch (rxChannel) + { + case RX1: + extData[2] = 0; + break; + case RX2: + extData[2] = 1; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRXQECSTATUS_INV_CH, + getMykonosErrorMessage(MYKONOS_ERR_GETRXQECSTATUS_INV_CH)); + return MYKONOS_ERR_GETRXQECSTATUS_INV_CH; + } + } + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRXQECSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETRXQECSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETRXQECSTATUS_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRXQECSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETRXQECSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETRXQECSTATUS_ARMERRFLAG; + } + + /* read status from ARM memory */ + offset = 0; + retVal = MYKONOS_readArmMem(device, (MYKONOS_ADDR_ARM_START_DATA_ADDR + offset), &armReadBack[0], sizeof(armReadBack), 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Assign to data structure */ + rxQecStatus->errorCode = (((uint32_t)armReadBack[3]) << 24) | (((uint32_t)armReadBack[2]) << 16) | (((uint32_t)armReadBack[1]) << 8) | ((uint32_t)armReadBack[0]); + rxQecStatus->percentComplete = (((uint32_t)armReadBack[7]) << 24) | (((uint32_t)armReadBack[6]) << 16) | (((uint32_t)armReadBack[5]) << 8) + | ((uint32_t)armReadBack[4]); + rxQecStatus->selfcheckIrrDb = (((uint32_t)armReadBack[11]) << 24) | (((uint32_t)armReadBack[10]) << 16) | (((uint32_t)armReadBack[9]) << 8) + | ((uint32_t)armReadBack[8]); + rxQecStatus->iterCount = (((uint32_t)armReadBack[15]) << 24) | (((uint32_t)armReadBack[14]) << 16) | (((uint32_t)armReadBack[13]) << 8) | ((uint32_t)armReadBack[12]); + rxQecStatus->updateCount = (((uint32_t)armReadBack[19]) << 24) | (((uint32_t)armReadBack[18]) << 16) | (((uint32_t)armReadBack[17]) << 8) + | ((uint32_t)armReadBack[16]); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Returns the status of the ORxQEC tracking calibration + * + * The ORx QEC tracking calibration is run during the radioOn state. + * The function can be called to read back the status of the ORxQEC external + * calibration including metrics like error codes, percentage of data + * collected for current cal, the performance of the cal and the number of + * times the cal has run and updated the hardware. + * + * \pre Before the function is called, the device must be initialized, the ARM + * loaded, and init cals run. These functions can be called in radioOff or + * radioOn state. + * + * \param device Pointer to the device settings structure + * \param orxChannel The channel whose status is to be read back + * \param orxQecStatus Status of the ORxQEC external calibration, as a structure + * of type mykonosOrxQecStatus_t is returned to this pointer address + * + * \retval MYKONOS_ERR_GETORXQECSTATUS_NULLPARAM Function parameter orxQecStatus is a NULL pointer + * \retval MYKONOS_ERR_GETORXQECSTATUS_INV_CH Channel selection not valid + * \retval MYKONOS_ERR_GETORXQECSTATUS_ARMERRFLAG ARM command error + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getOrxQecStatus(mykonosDevice_t *device, mykonosObsRxChannels_t orxChannel, mykonosOrxQecStatus_t *orxQecStatus) +{ + uint8_t extData[3] = {MYKONOS_ARM_OBJECTID_CAL_STATUS, MYKONOS_ARM_OBJECTID_ORXQEC_TRACKING, 0}; + uint8_t cmdStatusByte = 0; + uint32_t offset = 0; + uint32_t timeoutMs = 0; + uint8_t armReadBack[20] = {0}; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getOrxQecStatus()\n"); +#endif + + if (orxQecStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETORXQECSTATUS_NULLPARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETORXQECSTATUS_NULLPARAM)); + return MYKONOS_ERR_GETORXQECSTATUS_NULLPARAM; + } + + switch (orxChannel) + { + case OBS_RX1_TXLO: + case OBS_RX1_SNIFFERLO: + extData[2] = 0; + break; + case OBS_RX2_TXLO: + case OBS_RX2_SNIFFERLO: + extData[2] = 1; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETORXQECSTATUS_INV_CH, + getMykonosErrorMessage(MYKONOS_ERR_GETORXQECSTATUS_INV_CH)); + return MYKONOS_ERR_GETORXQECSTATUS_INV_CH; + } + } + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETORXQECSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETORXQECSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETORXQECSTATUS_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETORXQECSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETORXQECSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETORXQECSTATUS_ARMERRFLAG; + } + + /* read status from ARM memory */ + offset = 0; + retVal = MYKONOS_readArmMem(device, (MYKONOS_ADDR_ARM_START_DATA_ADDR + offset), &armReadBack[0], sizeof(armReadBack), 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Assign to data structure */ + orxQecStatus->errorCode = (((uint32_t)armReadBack[3]) << 24) | (((uint32_t)armReadBack[2]) << 16) | (((uint32_t)armReadBack[1]) << 8) | ((uint32_t)armReadBack[0]); + orxQecStatus->percentComplete = (((uint32_t)armReadBack[7]) << 24) | (((uint32_t)armReadBack[6]) << 16) | (((uint32_t)armReadBack[5]) << 8) + | ((uint32_t)armReadBack[4]); + orxQecStatus->selfcheckIrrDb = (((uint32_t)armReadBack[11]) << 24) | (((uint32_t)armReadBack[10]) << 16) | (((uint32_t)armReadBack[9]) << 8) + | ((uint32_t)armReadBack[8]); + orxQecStatus->iterCount = (((uint32_t)armReadBack[15]) << 24) | (((uint32_t)armReadBack[14]) << 16) | (((uint32_t)armReadBack[13]) << 8) + | ((uint32_t)armReadBack[12]); + orxQecStatus->updateCount = (((uint32_t)armReadBack[19]) << 24) | (((uint32_t)armReadBack[18]) << 16) | (((uint32_t)armReadBack[17]) << 8) + | ((uint32_t)armReadBack[16]); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Selects the Sniffer RF input to use for the observation receiver when in ObsRx pin mode and ORX_MODE = SNIFFER(4) + * + * This function is only valid when using the ObsRx Pin mode. In pin mode, 3 GPIO pins select an Observation Rx source. + * See mykonosObsRxChannels_t enum values less than 7. When the ORX_MODE GPIO pins are set to 4 for Sniffer, Sniffer inputs + * A, B, and C can be chosen by calling this function. This function can be called any time after the ARM is loaded and running. + * It can be called in radioOn or radioOff state. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * \param snifferChannel Desired channel to set. This channel will be enabled when ORX_MODE = SNIFFER. + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR ARM returned an error + */ +mykonosErr_t MYKONOS_setSnifferChannel(mykonosDevice_t *device, mykonosSnifferChannel_t snifferChannel) +{ + uint8_t armData[2] = {0}; + uint32_t timeoutMs = 0; + uint8_t cmdStatusByte = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + + armData[0] = 0x6A; /* SET SRX_SOURCE ARM object ID */ + armData[1] = (uint8_t)snifferChannel; + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_SET_OPCODE, &armData[0], sizeof(armData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_SET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR, + getGpioMykonosErrorMessage(MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR)); + retVal = (mykonosErr_t)MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR, + getGpioMykonosErrorMessage(MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR)); + return (mykonosErr_t)MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Resets the ARM processor and performs initialization + * + * Sets ARM Run = 0, Disables parity checks, sets ARM and SPI reg clock selects, + * resets ARM, and enables ARM SPI register access + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->rx->rxProfile->iqRate_kHz + * - device->deviceClock_kHz + * - device->rx->rxProfile->rfBandwidth_Hz + * - device->tx->txProfile->rfBandwidth_Hz + * - device->rx->rxProfile->rxFirDecimation + * - device->rx->rxProfile->rhb1Decimation + * - device->spiSettings + * + * \param device Pointer to the device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_INITARM_INV_VCODIV + * \retval MYKONOS_ERR_INITARM_INV_REGCLK Could not calculate a valid ARM Register clock divider + * \retval MYKONOS_ERR_INITARM_INV_ARMCLK_PARAM Could not calculate a valid ARM clock divider + */ +mykonosErr_t MYKONOS_initArm(mykonosDevice_t *device) +{ + uint8_t regClkSel = 0; + uint8_t armClkSel = 0; + uint32_t hsClkRateDiv4or5_Khz = 0; + uint32_t hb1Clk = 0; + uint32_t vcoDivTimes10 = 1; + uint8_t adcDiv = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_initArm()\n"); +#endif + + /* Finish init - this is part of init that must run after Multi Chip Sync */ + retVal = MYKONOS_initSubRegisterTables(device); + if (retVal != MYKONOS_ERR_OK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, retVal, getMykonosErrorMessage(retVal)); + return retVal; + } + + switch (device->clocks->clkPllVcoDiv) + { + case VCODIV_1: + vcoDivTimes10 = 10; + break; + case VCODIV_1p5: + vcoDivTimes10 = 15; + break; + case VCODIV_2: + vcoDivTimes10 = 20; + break; + case VCODIV_3: + vcoDivTimes10 = 30; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INITARM_INV_VCODIV, + getMykonosErrorMessage(MYKONOS_ERR_INITARM_INV_VCODIV)); + return MYKONOS_ERR_INITARM_INV_VCODIV; + } + } + + hsClkRateDiv4or5_Khz = device->clocks->clkPllVcoFreq_kHz * 10 / vcoDivTimes10 / 20; + + /* If ADC divider is set, divide hsClkRateDiv4or5_kHz by 2 (ADC divider) */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_CLOCK_CONTROL_1, &adcDiv, 0x01, 0); + hb1Clk = (adcDiv == 1) ? (hsClkRateDiv4or5_Khz >> 1) : (hsClkRateDiv4or5_Khz); + + /* the ARM clock should not exceed 250 Mhz */ + if (hb1Clk <= 250000) + { + armClkSel = 0x00; + } + else if (hb1Clk > 250000 && hb1Clk <= 500000) + { + armClkSel = 0x02; + } + else if (hb1Clk > 500000 && hb1Clk <= 1000000) + { + armClkSel = 0x04; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INITARM_INV_ARMCLK_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_INITARM_INV_ARMCLK_PARAM)); + return MYKONOS_ERR_INITARM_INV_ARMCLK_PARAM; + } + + /* the SPI read reg clock must be equal or less than 100MHz and the SPI write reg clock must be less equal or less than 200 Mhz*/ + if (hb1Clk <= 100000) + { + regClkSel = 0x00; + } + else if (hb1Clk > 100000 && hb1Clk <= 200000) + { + regClkSel = 0x04; + } + else if (hb1Clk > 200000 && hb1Clk <= 400000) + { + regClkSel = 0x09; + } + else if (hb1Clk > 400000 && hb1Clk <= 800000) + { + regClkSel = 0x0E; + } + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INITARM_INV_REGCLK, getMykonosErrorMessage(MYKONOS_ERR_INITARM_INV_REGCLK)); + return MYKONOS_ERR_INITARM_INV_REGCLK; + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_CTL_1, 0x8C); /* arm_debug_enable[7]=1, mem_hresp_mask[3]=1, auto_incr[2]=1, arm_m3_run[0]=0 */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_CLK_CTL, armClkSel |= 0x41); /* setting the ARM clock rate, resetting the PC, and enabling the ARM clock */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_CLK_CTL, armClkSel &= ~0x40); /* maintaining the ARM clock rate, disabling the PC reset, and maintaining ARM clock enable */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_BRIDGE_CLK_CTL, regClkSel); /* setting the SPI read and write clock rates */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AHB_SPI_BRIDGE, 0x13); /* blockout_window_size[4:1] = 9, ahb_spi_bridge_enable[0] = 1 */ + + retVal = MYKONOS_writeArmProfile(device); + if (retVal != MYKONOS_ERR_OK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, retVal, getMykonosErrorMessage(retVal)); + return retVal; + } + + retVal = MYKONOS_loadAdcProfiles(device); + if (retVal != MYKONOS_ERR_OK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, retVal, getMykonosErrorMessage(retVal)); + return retVal; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Loads binary byte array into ARM program memory + * + * This function assumes the ARM auto increment bit is set in 0x0D00[2]. Valid memory + * addresses are: Program Memory (0x01000000 - 0x01017FFF) + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param binary is a byte array containing ARM program memory data bytes (directly from .bin file) + * \param count is the number of bytes in the byte array + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_LOADBIN_NULL_PARAM Function parameter binary has a NULL pointer + * \retval MYKONOS_ERR_LOADBIN_INVALID_BYTECOUNT Count parameter must be 98304 bytes + */ +mykonosErr_t MYKONOS_loadArmFromBinary(mykonosDevice_t *device, uint8_t *binary, uint32_t count) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t stackPtr[4] = {0}; + uint8_t bootAddr[4] = {0}; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_loadArmFromBinary()\n"); +#endif + + if (binary == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOADBIN_NULL_PARAM, getMykonosErrorMessage(MYKONOS_ERR_LOADBIN_NULL_PARAM)); + return MYKONOS_ERR_LOADBIN_NULL_PARAM; + } + + if (count != 98304) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOADBIN_INVALID_BYTECOUNT, + getMykonosErrorMessage(MYKONOS_ERR_LOADBIN_INVALID_BYTECOUNT)); + return MYKONOS_ERR_LOADBIN_INVALID_BYTECOUNT; + } + else + { + /* extraction of stack pointer and boot address from top of array */ + stackPtr[0] = binary[0]; + stackPtr[1] = binary[1]; + stackPtr[2] = binary[2]; + stackPtr[3] = binary[3]; + + bootAddr[0] = binary[4]; + bootAddr[1] = binary[5]; + bootAddr[2] = binary[6]; + bootAddr[3] = binary[7]; + + /* writing binary data to ARM memory */ + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_PROG_ADDR, &binary[0], count); + } + + if (retVal != MYKONOS_ERR_OK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, retVal, getMykonosErrorMessage(retVal)); + return retVal; + } + else + { + /* writing the stack pointer address */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_STACK_PTR_BYTE_0, stackPtr[0]); /* stack pointer [7:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_STACK_PTR_BYTE_1, stackPtr[1]); /* stack pointer [15:8] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_STACK_PTR_BYTE_2, stackPtr[2]); /* stack pointer [23:16] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_STACK_PTR_BYTE_3, stackPtr[3]); /* stack pointer [31:24] */ + + /* writing the boot address */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_0, bootAddr[0]); /* boot address [7:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_1, bootAddr[1]); /* boot address [15:8] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_2, bootAddr[2]); /* boot address [23:16] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_3, bootAddr[3]); /* boot address [31:24] */ + + /* setting the ARM run bit */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_CTL_1, 0x8D); /* arm_debug_enable[7]=1, mem_hresp_mask[3]=1, auto_incr[2]=1, arm_m3_run[0]=1 */ + } + + /* verifying ARM checksum */ + if ((retVal = MYKONOS_verifyArmChecksum(device)) != MYKONOS_ERR_OK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, retVal, getMykonosErrorMessage(retVal)); + return retVal; + } + + /* verifying ARM state is in MYKONOS_ARM_READY state, otherwise return error */ + if ((retVal = MYKONOS_checkArmState(device, MYK_ARM_READY)) != MYKONOS_ERR_OK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, retVal, getMykonosErrorMessage(retVal)); + return retVal; + } + + /* Setup ARM GPIO pins and program ARMs radio control structure */ + if ((retVal = (mykonosErr_t)MYKONOS_setArmGpioPins(device)) != MYKONOS_ERR_OK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, retVal, getMykonosErrorMessage(retVal)); + return retVal; + } + + if ((retVal = MYKONOS_setRadioControlPinMode(device)) != MYKONOS_ERR_OK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, retVal, getMykonosErrorMessage(retVal)); + return retVal; + } + + /* Set the default ObsRx Path source for when the device moves to RadioOn */ + if ((retVal = MYKONOS_setDefaultObsRxPath(device, device->obsRx->defaultObsRxChannel)) != MYKONOS_ERR_OK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, retVal, getMykonosErrorMessage(retVal)); + return retVal; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Loads binary byte array into ARM program memory. This API function allows user to load the ARM concurrently. + * This is specially to reduce the system initialization time. + * + * \pre MYKONOS_initArm() function must be called before calling this API. + * + * \post after calling this function the user must verify: + * Arm Checksum using MYKONOS_verifyArmChecksum(mykonosDevice_t *device) + * verify ARM state is in MYKONOS_ARM_READY state using MYKONOS_checkArmState(device, MYK_ARM_READY); + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param binary is a byte array containing ARM program memory data bytes (directly from .bin file) + * \param count is the number of bytes in the byte array + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_LOADARMCON_NULL_PARAM Function parameter binary has a NULL pointer + * \retval MYKONOS_ERR_LOADARMCON_INVALID_BYTECOUNT Count parameter must be 98304 bytes + * \retval MYKONOS_ERR_ARM_INV_ADDR_PARM Invalid memory address + */ +mykonosErr_t MYKONOS_loadArmConcurrent(mykonosDevice_t *device, uint8_t *binary, uint32_t count) +{ + uint8_t stackPtr[4] = {0}; + uint8_t bootAddr[4] = {0}; + uint32_t i; + uint32_t address = MYKONOS_ADDR_ARM_START_PROG_ADDR; + +#if MYK_ENABLE_SPIWRITEARRAY == 1 + uint32_t addrIndex = 0; + uint32_t dataIndex = 0; + uint32_t spiBufferSize = MYK_SPIWRITEARRAY_BUFFERSIZE; + uint16_t addrArray[MYK_SPIWRITEARRAY_BUFFERSIZE] = {0}; +#endif + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_loadArmConcurrent()\n"); +#endif + + if (binary == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOADARMCON_NULL_PARAM, getMykonosErrorMessage(MYKONOS_ERR_LOADARMCON_NULL_PARAM)); + return MYKONOS_ERR_LOADARMCON_NULL_PARAM; + } + + if (count != 98304) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOADARMCON_INVALID_BYTECOUNT, + getMykonosErrorMessage(MYKONOS_ERR_LOADARMCON_INVALID_BYTECOUNT)); + return MYKONOS_ERR_LOADARMCON_INVALID_BYTECOUNT; + } + else + { + /* extraction of stack pointer and boot address from top of array */ + stackPtr[0] = binary[0]; + stackPtr[1] = binary[1]; + stackPtr[2] = binary[2]; + stackPtr[3] = binary[3]; + + bootAddr[0] = binary[4]; + bootAddr[1] = binary[5]; + bootAddr[2] = binary[6]; + bootAddr[3] = binary[7]; + + /* set auto increment address bit */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_CTL_1, 0x8C); + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_ADDR_BYTE_0, (uint8_t)((address) >> 2)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_ADDR_BYTE_1, (uint8_t)(address >> 10)); + + /* start write at correct byte offset */ + /* write data is located at SPI address 0xD04=data[7:0], 0xD05=data[15:8], 0xD06=data[23:16], 0xD07=data[31:24] */ + /* with address auto increment set, after x407 is written, the address will automatically increment */ + +#if (MYK_ENABLE_SPIWRITEARRAY == 0) + + for (i = 0; i < byteCount; i++) + { + CMB_SPIWriteByte(device->spiSettings, (MYKONOS_ADDR_ARM_DATA_BYTE_0 | (((address & 0x3) + i) % 4)), data[i]); + } + +#elif (MYK_ENABLE_SPIWRITEARRAY == 1) + + addrIndex = 0; + dataIndex = 0; + for (i = 0; i < count; i++) + { + addrArray[addrIndex++] = (MYKONOS_ADDR_ARM_DATA_BYTE_0 | (((address & 0x3) + i) % 4)); + + if (addrIndex == spiBufferSize) + { + CMB_SPIWriteBytes(device->spiSettings, &addrArray[0], &binary[dataIndex], addrIndex); + dataIndex = dataIndex + addrIndex; + addrIndex = 0; + } + } + + if (addrIndex > 0) + { + CMB_SPIWriteBytes(device->spiSettings, &addrArray[0], &binary[dataIndex], addrIndex); + } + +#endif + + /* writing the stack pointer address */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_STACK_PTR_BYTE_0, stackPtr[0]); /* stack pointer [7:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_STACK_PTR_BYTE_1, stackPtr[1]); /* stack pointer [15:8] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_STACK_PTR_BYTE_2, stackPtr[2]); /* stack pointer [23:16] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_STACK_PTR_BYTE_3, stackPtr[3]); /* stack pointer [31:24] */ + + /* writing the boot address */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_0, bootAddr[0]); /* boot address [7:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_1, bootAddr[1]); /* boot address [15:8] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_2, bootAddr[2]); /* boot address [23:16] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_3, bootAddr[3]); /* boot address [31:24] */ + + /* setting the ARM run bit */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_CTL_1, 0x8D); + + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Verifies the ARM checksum value + * + * The checksum which is written into the .hex file is verified with the calculated checksum + * in the Mykonos ARM after the hex file has been loaded + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_verifyArmChecksum(mykonosDevice_t *device) +{ + uint32_t buildTimeChecksum = 0x00000000; + uint32_t calculatedChecksum = 0x00000000; + uint8_t buildData[4] = {0}; + uint8_t calcData[4] = {0}; + mykonosErr_t retVal = MYKONOS_ERR_OK; + + const uint8_t CHECKSUM_BYTES = 0x4; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_verifyArmChecksum()\n"); +#endif + + /* disabling auto increment and reading four (4) bytes at ARM checksum memory location */ + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_BUILD_CHKSUM_ADDR, buildData, CHECKSUM_BYTES, 0); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + /* determining build time checksum */ + buildTimeChecksum = (((uint32_t)buildData[3] << 24) | ((uint32_t)buildData[2] << 16) | ((uint32_t)buildData[1] << 8) | (uint32_t)buildData[0]); + + /* using 200 msec timeout for exit out of while loop [maximum checksum calculation time = 5 ms] */ + CMB_setTimeout_ms(200); + + /* determining calculated checksum */ + do + { + if ((retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_CALC_CHKSUM_ADDR, calcData, CHECKSUM_BYTES, 0)) != MYKONOS_ERR_OK) + { + return retVal; + } + calculatedChecksum = (((uint32_t)calcData[3] << 24) | ((uint32_t)calcData[2] << 16) | ((uint32_t)calcData[1] << 8) | (uint32_t)calcData[0]); + } while ((!calculatedChecksum) && (!CMB_hasTimeoutExpired())); + + /* performing consistency check */ + if (buildTimeChecksum == calculatedChecksum) + { + return MYKONOS_ERR_OK; + } + else + { + return MYKONOS_ERR_ARM_INVALID_BUILDCHKSUM; + } +} + +/** + * \brief Verifies the ARM status once it is start running + * + * Wait for ARM to go into radio state, if takes longer there is and ARM error + * get error in Application layer calling MYKONOS_getRadioState() + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param armStateCheck if the ARM is not in this state it will return an error, + * + * \retval MYKONOS_ERR_ARMSTATE_EXCEPTION ARM system problem has been detected. + * \retval MYKONOS_ERR_ARMSTATE_CAL_ERROR ARM has detected an error in the tracking calibrations. + * \retval MYKONOS_ERR_ARMSTATE_EXCEPTION ARM has detected an illegal profile. + * \retval MYKONOS_ERR_WAITARMCSTATE_TIMEOUT Timeout occurred in check ARM state. + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_checkArmState(mykonosDevice_t *device, mykonosArmState_t armStateCheck) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint32_t armStatus = 0x00; + uint32_t armStatusMapped = 0x00; + uint32_t timeoutMs = 500; /* 500ms timeOut */ + uint8_t endCheck = 0x00; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_checkArmState()\n"); +#endif + + CMB_setTimeout_ms(timeoutMs); + + do + { + if ((retVal = MYKONOS_getRadioState(device, &armStatus)) != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Mapping of the armStatus bit to the enum value. */ + switch(armStatus) + { + case 0: + armStatusMapped = (uint32_t)MYK_ARM_POWERUP; + break; + case 1: + armStatusMapped = (uint32_t)MYK_ARM_READY; + break; + case 2: + armStatusMapped = (uint32_t)MYK_ARM_IDLE; + break; + case 3: + armStatusMapped = (uint32_t)MYK_ARM_RADIO_ON; + break; + case 4: + armStatusMapped = (uint32_t)MYK_ARM_PROFILE_ERROR; + break; + default: + armStatusMapped = armStatus; + break; + } + + if (armStateCheck && armStatusMapped) + { + retVal = MYKONOS_ERR_OK; + break; + } + + if (CMB_hasTimeoutExpired()) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WAITARMCSTATE_TIMEOUT, + getMykonosErrorMessage(MYKONOS_ERR_WAITARMCSTATE_TIMEOUT)); + retVal = MYKONOS_ERR_WAITARMCSTATE_TIMEOUT; + break; + } + + switch (armStatusMapped) + { + /* this cases are not ARM errors */ + case MYK_ARM_POWERUP: + case MYK_ARM_READY: + case MYK_ARM_IDLE: + case MYK_ARM_RADIO_ON: + break; + + case MYK_ARM_PROFILE_ERROR: + /* return error directly */ + retVal = MYKONOS_ERR_ARMSTATE_PROFILE_ERROR; + endCheck = 1; + break; + + case MYK_ARM_CAL_ERROR: + /* return error directly */ + retVal = MYKONOS_ERR_ARMSTATE_CAL_ERROR; + endCheck = 1; + break; + + case MYK_ARM_EXCEPTION: + /* return error directly */ + retVal = MYKONOS_ERR_ARMSTATE_EXCEPTION; + endCheck = 1; + break; + + case (uint32_t)MYK_ARM_EXCEPTION | (uint32_t)MYK_ARM_PROFILE_ERROR: + /* return error directly */ + retVal = MYKONOS_ERR_ARMSTATE_EXCEPTION; + endCheck = 1; + break; + + default: + endCheck = 0; + break; + } + + } while (!endCheck); + + return retVal; +} + +/** + * \brief Reads back the version of the ARM binary loaded into the Mykonos ARM memory + * + * This function reads the ARM memory to read back the major.minor.releaseCandidate + * version for the ARM binary loaded into ARM memory. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param majorVer The Major version is returned in this parameter + * \param minorVer The Minor version is returned in this parameter + * \param rcVer The release candidate version (build number) is returned in this parameter + * \param buildType The Type of the build [Debug / Test_Object / Release] + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETARMVER_NULL_PARM One of the function parameters has a NULL pointer + */ +mykonosErr_t MYKONOS_getArmVersion(mykonosDevice_t *device, uint8_t *majorVer, uint8_t *minorVer, uint8_t *rcVer, mykonosBuild_t *buildType) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t ver[5] = {0}; + uint32_t fullVersion = 0; + uint8_t validBuilds = 0x05; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getArmVersion()\n"); +#endif + + if ((majorVer == NULL) || (minorVer == NULL) || (rcVer == NULL)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETARMVER_NULL_PARM, getMykonosErrorMessage(MYKONOS_ERR_GETARMVER_NULL_PARM)); + return MYKONOS_ERR_GETARMVER_NULL_PARM; + } + + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_VERSION, &ver[0], sizeof(ver), 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + fullVersion = ((uint32_t)(ver[0]) | (uint32_t)((uint32_t)(ver[1]) << 8) | (uint32_t)((uint32_t)(ver[2]) << 16) | (uint32_t)((uint32_t)(ver[3]) << 24)); + *rcVer = (uint8_t)(fullVersion % 100); + *minorVer = (uint8_t)((fullVersion / 100) % 100); + *majorVer = (uint8_t)(fullVersion / 10000); + + switch (ver[4] & validBuilds) + { + case MYK_BUILD_DEBUG: + *buildType = MYK_BUILD_DEBUG; + break; + case MYK_BUILD_TEST_OBJECT: + *buildType = MYK_BUILD_TEST_OBJECT; + break; + default: + *buildType = MYK_BUILD_RELEASE; + break; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function will configure DPD settings + * + * A DPD-enabled transceiver is required for DPD to be enabled. The DPD has several user + * adjustable settings that can be configured before running the runInitCals + * with the calMask set for the DPD init cal. Call this function with desired + * settings set before running the DPD init cal or enabling DPD tracking. + * + * This function can be called in either Radio On or Off state. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * - device->tx->dpdConfig (All members) + * + * + * \retval MYKONOS_ERR_CFGDPD_TXORX_PROFILE_INV ERROR: to use these features, a valid Tx and ORx profile must exist in the device data structure + * \retval MYKONOS_ERR_CFGDPD_NULL_DPDCFGSTRUCT ERROR: device->tx->dpdConfig is a NULL pointer + * \retval MYKONOS_ERR_CFGDPD_INV_DPDDAMPING ERROR: damping parameter is out of range + * \retval MYKONOS_ERR_CFGDPD_INV_DPDSAMPLES ERROR: samples parameter is out of range + * \retval MYKONOS_ERR_CFGDPD_INV_NUMWEIGHTS ERROR: numWeights parameter is out of range (0-3) + * \retval MYKONOS_ERR_CFGDPD_INV_MODELVERSION ERROR: modelVersion parameter is out of range (0-3) + * \retval MYKONOS_ERR_CFGDPD_INV_DPDOUTLIERTHRESH ERROR: outlierThreshold parameter is out of range + * \retval MYKONOS_ERR_CFGDPD_INV_DPD_ADDDELAY ERROR: additionalDelayOffset parameter is out of range + * \retval MYKONOS_ERR_CFGDPD_INV_PNSEQLEVEL ERROR: pathDelayPnSeqLevel parameter is out of range + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_configDpd(mykonosDevice_t *device) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armFieldValue[6] = {0}; + uint8_t byteOffset = 0; + uint16_t negPnLevel = 0; + uint8_t highPowerModelUpdate = 0; + uint8_t robustModeling = 0; + uint32_t radioStatus = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_configDpd()\n"); +#endif + + /* DPD requires Tx and ORx enabled, throw error if both are not enabled */ + if ((device->profilesValid & (TX_PROFILE_VALID | ORX_PROFILE_VALID)) != (TX_PROFILE_VALID | ORX_PROFILE_VALID)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGDPD_TXORX_PROFILE_INV, + getMykonosErrorMessage(MYKONOS_ERR_CFGDPD_TXORX_PROFILE_INV)); + return MYKONOS_ERR_CFGDPD_TXORX_PROFILE_INV; + } + + if (device->tx->dpdConfig == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGDPD_NULL_DPDCFGSTRUCT, + getMykonosErrorMessage(MYKONOS_ERR_CFGDPD_NULL_DPDCFGSTRUCT)); + return MYKONOS_ERR_CFGDPD_NULL_DPDCFGSTRUCT; + } + + /* check DPD damping and samples parameters */ + if (device->tx->dpdConfig->damping > 15) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGDPD_INV_DPDDAMPING, + getMykonosErrorMessage(MYKONOS_ERR_CFGDPD_INV_DPDDAMPING)); + return MYKONOS_ERR_CFGDPD_INV_DPDDAMPING; + } + + if ((device->tx->dpdConfig->samples < 64) || (device->tx->dpdConfig->samples > 32768)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGDPD_INV_DPDSAMPLES, + getMykonosErrorMessage(MYKONOS_ERR_CFGDPD_INV_DPDSAMPLES)); + return MYKONOS_ERR_CFGDPD_INV_DPDSAMPLES; + } + + if (device->tx->dpdConfig->numWeights > 3) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGDPD_INV_NUMWEIGHTS, + getMykonosErrorMessage(MYKONOS_ERR_CFGDPD_INV_NUMWEIGHTS)); + return MYKONOS_ERR_CFGDPD_INV_NUMWEIGHTS; + } + + if (device->tx->dpdConfig->modelVersion > 3) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGDPD_INV_MODELVERSION, + getMykonosErrorMessage(MYKONOS_ERR_CFGDPD_INV_MODELVERSION)); + return MYKONOS_ERR_CFGDPD_INV_MODELVERSION; + } + + highPowerModelUpdate = (device->tx->dpdConfig->highPowerModelUpdate > 0) ? 1 : 0; + robustModeling = (device->tx->dpdConfig->robustModeling > 0) ? 1 : 0; + + armFieldValue[0] = (uint8_t)(((device->tx->dpdConfig->numWeights & 3) << 4) | (device->tx->dpdConfig->damping & 0xF)); + armFieldValue[1] = (uint8_t)((robustModeling << 3) | (highPowerModelUpdate << 2) | (device->tx->dpdConfig->modelVersion & 3)); + armFieldValue[2] = (device->tx->dpdConfig->samples & 0xFF); + armFieldValue[3] = ((device->tx->dpdConfig->samples >> 8) & 0xFF); + byteOffset = 0; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_DPDCONFIG, byteOffset, &armFieldValue[0], 4); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* set DPD outlier threshold parameter */ + if ((device->tx->dpdConfig->outlierThreshold < 1) || (device->tx->dpdConfig->outlierThreshold > 8192)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGDPD_INV_DPDOUTLIERTHRESH, + getMykonosErrorMessage(MYKONOS_ERR_CFGDPD_INV_DPDOUTLIERTHRESH)); + return MYKONOS_ERR_CFGDPD_INV_DPDOUTLIERTHRESH; + } + + armFieldValue[0] = (device->tx->dpdConfig->outlierThreshold & 0xFF); + armFieldValue[1] = ((device->tx->dpdConfig->outlierThreshold >> 8) & 0xFF); + byteOffset = 10; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_DPDCONFIG, byteOffset, &armFieldValue[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* set DPD Model Prior Weight parameter */ + if (device->tx->dpdConfig->modelPriorWeight > 32) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGDPD_INV_DPDPRIORWEIGHT, + getMykonosErrorMessage(MYKONOS_ERR_CFGDPD_INV_DPDPRIORWEIGHT)); + return MYKONOS_ERR_CFGDPD_INV_DPDPRIORWEIGHT; + } + armFieldValue[0] = (device->tx->dpdConfig->modelPriorWeight & 0xFF); + armFieldValue[1] = 0; + byteOffset = 12; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_DPDCONFIG, byteOffset, &armFieldValue[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* no need to verify weights min/max as all int8 values are valid */ + armFieldValue[0] = (uint8_t)(device->tx->dpdConfig->weights[0].real); + armFieldValue[1] = (uint8_t)(device->tx->dpdConfig->weights[0].imag); + armFieldValue[2] = (uint8_t)(device->tx->dpdConfig->weights[1].real); + armFieldValue[3] = (uint8_t)(device->tx->dpdConfig->weights[1].imag); + armFieldValue[4] = (uint8_t)(device->tx->dpdConfig->weights[2].real); + armFieldValue[5] = (uint8_t)(device->tx->dpdConfig->weights[2].imag); + + byteOffset = 14; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_DPDCONFIG, byteOffset, &armFieldValue[0], 6); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* set DPD additional delay offset parameter */ + if ((device->tx->dpdConfig->additionalDelayOffset < -64) || (device->tx->dpdConfig->additionalDelayOffset > 64)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGDPD_INV_DPD_ADDDELAY, + getMykonosErrorMessage(MYKONOS_ERR_CFGDPD_INV_DPD_ADDDELAY)); + return MYKONOS_ERR_CFGDPD_INV_DPD_ADDDELAY; + } + + /* read radio state to make sure ARM is in radioOff /IDLE */ + retVal = MYKONOS_getRadioState(device, &radioStatus); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Radio state check */ + if (((radioStatus & 0x03) == MYKONOS_ARM_SYSTEMSTATE_IDLE) || ((radioStatus & 0x03) == MYKONOS_ARM_SYSTEMSTATE_READY)) + { + armFieldValue[0] = (uint8_t)(device->tx->dpdConfig->additionalDelayOffset & 0xFF); + armFieldValue[1] = (uint8_t)(((uint16_t)device->tx->dpdConfig->additionalDelayOffset >> 8) & 0xFF); + byteOffset = 2; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_DPDINIT_CONFIG, byteOffset, &armFieldValue[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + if ((device->tx->dpdConfig->pathDelayPnSeqLevel < 1) || (device->tx->dpdConfig->pathDelayPnSeqLevel > 8191)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGDPD_INV_PNSEQLEVEL, + getMykonosErrorMessage(MYKONOS_ERR_CFGDPD_INV_PNSEQLEVEL)); + return MYKONOS_ERR_CFGDPD_INV_PNSEQLEVEL; + } + + /* Set Path Delay PN sequence amplitude - positive and negative */ + armFieldValue[0] = (uint8_t)(device->tx->dpdConfig->pathDelayPnSeqLevel & 0xFF); + armFieldValue[1] = (uint8_t)((device->tx->dpdConfig->pathDelayPnSeqLevel >> 8) & 0xFF); + + negPnLevel = ((~device->tx->dpdConfig->pathDelayPnSeqLevel) + 1); /* times -1 */ + armFieldValue[2] = (uint8_t)(negPnLevel & 0xFF); + armFieldValue[3] = (uint8_t)(((negPnLevel) >> 8) & 0xFF); + byteOffset = 10; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_DPDINIT_CONFIG, byteOffset, &armFieldValue[0], 4); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + } + else + { + /* record warning about not updated members */ + CMB_writeToLog(ADIHAL_LOG_WARNING, device->spiSettings->chipSelectIndex, MYKONOS_WRN_RADIO_ON_NOT_MODIFIABLE, + getMykonosErrorMessage(MYKONOS_WRN_RADIO_ON_NOT_MODIFIABLE)); + } + + return MYKONOS_ERR_OK; +} + +/* \brief Reads the DPD config structure from ARM memory + * + * This function reads the DPD structure + * from ARM memory and returns in the device->tx->dpdConfig structure. + * + * A DPD-enabled transceiver is required for DPD to be enabled. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * - device->tx->dpdConfig (All members) + * + * \param device is structure pointer to the Mykonos data structure containing settings + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETDPDCFG_TXORX_PROFILE_INV Error: Tx and ORx profiles must be valid for DPD functions + * \retval MYKONOS_ERR_GETDPDCFG_NULL_DPDCFGSTRUCT Error: NULL pointer to device->tx->dpdConfig structure + */ +mykonosErr_t MYKONOS_getDpdConfig(mykonosDevice_t *device) +{ + uint16_t byteOffset = 0; + uint8_t armMem[20] = {0}; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getDpdConfig()\n"); +#endif + + /* DPD requires Tx and ORx enabled, throw error if both are not enabled */ + if ((device->profilesValid & (TX_PROFILE_VALID | ORX_PROFILE_VALID)) != (TX_PROFILE_VALID | ORX_PROFILE_VALID)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETDPDCFG_TXORX_PROFILE_INV, + getMykonosErrorMessage(MYKONOS_ERR_GETDPDCFG_TXORX_PROFILE_INV)); + return MYKONOS_ERR_GETDPDCFG_TXORX_PROFILE_INV; + } + + if (device->tx->dpdConfig == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETDPDCFG_NULL_DPDCFGSTRUCT, + getMykonosErrorMessage(MYKONOS_ERR_GETDPDCFG_NULL_DPDCFGSTRUCT)); + return MYKONOS_ERR_GETDPDCFG_NULL_DPDCFGSTRUCT; + } + + byteOffset = 0; + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_DPDCONFIG, byteOffset, &armMem[0], 20); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + device->tx->dpdConfig->damping = (armMem[0] & 0x0F); + device->tx->dpdConfig->numWeights = ((armMem[0] >> 4) & 0x03); + + device->tx->dpdConfig->modelVersion = (armMem[1] & 0x03); + device->tx->dpdConfig->highPowerModelUpdate = ((armMem[1] >> 2) & 0x01); + device->tx->dpdConfig->robustModeling = 0; + device->tx->dpdConfig->samples = ((uint16_t)(armMem[3]) << 8) | (uint16_t)(armMem[2]); + + device->tx->dpdConfig->outlierThreshold = ((uint16_t)(armMem[11]) << 8) | (uint16_t)(armMem[10]); + device->tx->dpdConfig->modelPriorWeight = armMem[12]; + device->tx->dpdConfig->weights[0].real = (int8_t)(armMem[14]); + device->tx->dpdConfig->weights[0].imag = (int8_t)(armMem[15]); + device->tx->dpdConfig->weights[1].real = (int8_t)(armMem[16]); + device->tx->dpdConfig->weights[1].imag = (int8_t)(armMem[17]); + device->tx->dpdConfig->weights[2].real = (int8_t)(armMem[18]); + device->tx->dpdConfig->weights[2].imag = (int8_t)(armMem[19]); + + byteOffset = 2; + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_DPDINIT_CONFIG, byteOffset, &armMem[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + device->tx->dpdConfig->additionalDelayOffset = (int16_t)(((uint16_t)(armMem[1]) << 8) | (uint16_t)(armMem[0])); + + byteOffset = 10; + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_DPDINIT_CONFIG, byteOffset, &armMem[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + device->tx->dpdConfig->pathDelayPnSeqLevel = (((uint16_t)(armMem[1]) << 8) | (uint16_t)(armMem[0])); + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function reads the DPD calibration status from the Mykonos ARM processor. + * + * The dpdStatus is read back from the ARM processor and returned in the function + * parameter dpdStatus. + * + * A DPD-enabled transceiver is required for this feature to be enabled. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param txChannel Desired Transmit channel to read back DPD status for (Valid ENUM values: TX1 or TX2 only) + * \param dpdStatus Pointer to a structure to return the status information to + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETDPDSTATUS_NULLPARAM dpdStatus function parameter is a NULL pointer + * \retval MYKONOS_ERR_GETDPDSTATUS_INV_CH txChannel parameter is a non-supported value. + * \retval MYKONOS_ERR_GETDPDSTATUS_ARMERRFLAG ARM reported an error while processing the GET ARM command + */ +mykonosErr_t MYKONOS_getDpdStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosDpdStatus_t *dpdStatus) +{ + uint8_t extData[3] = {MYKONOS_ARM_OBJECTID_CAL_STATUS, MYKONOS_ARM_OBJECTID_DPDCONFIG, 0}; + uint8_t armData[64] = {0}; + uint32_t timeoutMs = 0; + uint8_t cmdStatusByte = 0; + uint8_t channelSelect = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getDpdStatus()\n"); +#endif + + if (dpdStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETDPDSTATUS_NULLPARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETDPDSTATUS_NULLPARAM)); + return MYKONOS_ERR_GETDPDSTATUS_NULLPARAM; + } + + switch (txChannel) + { + case TX1: + channelSelect = 0; + break; + case TX2: + channelSelect = 1; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETDPDSTATUS_INV_CH, + getMykonosErrorMessage(MYKONOS_ERR_GETDPDSTATUS_INV_CH)); + return MYKONOS_ERR_GETDPDSTATUS_INV_CH; + } + } + + extData[2] = channelSelect; + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETDPDSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETDPDSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETDPDSTATUS_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETDPDSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETDPDSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETDPDSTATUS_ARMERRFLAG; + } + + /* read status from ARM memory */ + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &armData[0], sizeof(armData), 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + dpdStatus->dpdErrorStatus = ((uint32_t)(armData[1]) << 8) | (uint32_t)(armData[0]); /* Only lower 16 bits */ + dpdStatus->dpdTrackCount = ((uint32_t)(armData[11]) << 24) | ((uint32_t)(armData[10]) << 16) | ((uint32_t)(armData[9]) << 8) | (uint32_t)(armData[8]); + dpdStatus->dpdModelErrorPercent = ((uint32_t)(armData[15]) << 24) | ((uint32_t)(armData[14]) << 16) | ((uint32_t)(armData[13]) << 8) | (uint32_t)(armData[12]); + dpdStatus->dpdExtPathDelay = ((uint32_t)(armData[26]) * 16) + (uint32_t)(armData[24]); + dpdStatus->dpdMaxAdaptationCurrent = ((uint16_t)(armData[41]) << 8) + (uint16_t)(armData[40]); + dpdStatus->dpdMaxAdaptation = ((uint16_t)(armData[43]) << 8) + (uint16_t)(armData[42]); + dpdStatus->dpdIterCount = ((uint32_t)(armData[47]) << 24) | ((uint32_t)(armData[46]) << 16) | ((uint32_t)(armData[45]) << 8) | (uint32_t)(armData[44]); + + return MYKONOS_ERR_OK; +} + +/** + * \brief This private helper function called during RadioOff, will allow DPD tracking to be scheduled + * by the ARM when back in the RadioOn state. + * + * This function sets a flag in the ARM memory that if the enableDpd tracking cal mask + * and this setting are both set, then the ARM will schedule DPD tracking to occur + * in the radioOn ARM state. + * + * A DPD-enabled transceiver is required for DPD to be enabled. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->tx->dpdConfig + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param tx1Enable 0=disable DPD Tx1 tracking, 1= enable DPD Tx1 tracking + * \param tx2Enable 0=disable DPD Tx2 tracking, 1= enable DPD Tx2 tracking + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_EN_DPDTRACKING_ARMSTATE_ERROR ARM is not in the RadioOff state, call MYKONOS_radioOff() + */ +static mykonosErr_t enableDpdTracking(mykonosDevice_t *device, uint8_t tx1Enable, uint8_t tx2Enable) +{ + uint32_t radioStatus = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t enableBit[4] = {0}; + uint8_t byteOffset = 20; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableDpdTracking()\n"); +#endif + + /* read radio state to make sure ARM is in radioOff /IDLE */ + retVal = MYKONOS_getRadioState(device, &radioStatus); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* throw error if not in radioOff/IDLE state */ + if (((radioStatus & 0x03) != MYKONOS_ARM_SYSTEMSTATE_IDLE) && ((radioStatus & 0x03) != MYKONOS_ARM_SYSTEMSTATE_READY)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_EN_DPDTRACKING_ARMSTATE_ERROR, + getMykonosErrorMessage(MYKONOS_ERR_EN_DPDTRACKING_ARMSTATE_ERROR)); + return MYKONOS_ERR_EN_DPDTRACKING_ARMSTATE_ERROR; + } + + enableBit[0] = (tx1Enable > 0) ? 1 : 0; + enableBit[1] = 0; + enableBit[2] = (tx2Enable > 0) ? 1 : 0; + enableBit[3] = 0; + + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_DPDCONFIG, byteOffset, &enableBit[0], 4); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function will allow loading of the DPD model file. + * + * This function writes a copy of the user's DPD model to ARM memory and instructs the ARM to install that DPD model + * into hardware. Note that initializing the device will over write DPD model data. Note that the DPD model being + * restored must match the PA for which it is configured. Restoring a DPD model to a different PA than for which it + * is configured will not yield the desired performance. The user is responsible to insure the DPD model matches the + * PA configuration. + * + * \param device Structure pointer to the Mykonos data structure containing settings + * \param txChannel Desired transmit channel to which to write the DPD model file (Valid ENUM type mykonosTxChannels_t: TX1 or TX2 or TX1_TX2) + * \param modelDataBuffer Pointer to the user buffer containing the history/model data to be loaded to a txChannel + * Valid sizes: 182 bytes for a single model load to either TX1 or TX2. + * 364 bytes for a dual model load to both TX1_TX2, where the TX1 model data will occupy the first 182 bytes + * and TX2 model data will occupy the second 182 bytes. + * \param modelNumberBytes Total buffer size of the user history/model data buffer. Allowed sizes are 182 bytes for TX1 or TX2 and + * 364 bytes for TX1_TX2. + * + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE User suppled modelNumberBytes size is incorrect. TX1 or TX2 = 182, TX1_TX2 = 364 + * \retval MYKONOS_ERR_RESTDPDMOD_INVALID_TXCHANNEL User supplied txChannel does not match TX1 or TX2 or TX1_TX2 + * \retval MYKONOS_ERR_RESTDPDMOD_ARMERRFLAG ARM returned error for Set ARM Command + */ +mykonosErr_t MYKONOS_restoreDpdModel(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t *modelDataBuffer, uint32_t modelNumberBytes) +{ + uint32_t radioStatus = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armData[4] = {0}; + uint32_t armBufferAddr = 0; + uint8_t *bufferPtr = 0; + uint8_t extendedData[4] = {0}; + uint8_t cmdStatusByte = 0; + + const uint8_t RESTORE = 0x08; + const uint32_t timeoutMs = 1000; + const uint32_t MODEL_SIZE = 182; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_restoreDpdModel()\n"); +#endif + + /* read radio state to make sure ARM is in radioOff /IDLE */ + retVal = MYKONOS_getRadioState(device, &radioStatus); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + if (txChannel == TX1) + { + /* check for single valid provided buffer size */ + if (modelNumberBytes != MODEL_SIZE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE, + getMykonosErrorMessage(MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE)); + return MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE; + } + + /* retrieve the arm TX1 model buffer address */ + retVal = MYKONOS_readArmMem(device, (MYKONOS_ADDR_ARM_START_PROG_ADDR + MYKONOS_ADDR_TX1_DPD_MODEL_INDIRECT_PTR), &armData[0], 4, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + armBufferAddr = (((uint32_t)armData[0]) | (((uint32_t)armData[1]) << 8) | (((uint32_t)armData[2]) << 16) | (((uint32_t)armData[3]) << 24)); + + /* write the TX1 model */ + bufferPtr = modelDataBuffer; + retVal = MYKONOS_writeArmMem(device, armBufferAddr, bufferPtr, MODEL_SIZE); /* write TX1 model */ + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + }/*end TX1 */ + + else if (txChannel == TX2) + { + /* check for single valid provided buffer size */ + if (modelNumberBytes != MODEL_SIZE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE, + getMykonosErrorMessage(MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE)); + return MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE; + } + + /* retrieve the arm TX2 model buffer address */ + retVal = MYKONOS_readArmMem(device, (MYKONOS_ADDR_ARM_START_PROG_ADDR + MYKONOS_ADDR_TX2_DPD_MODEL_INDIRECT_PTR), &armData[0], 4, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + armBufferAddr = (((uint32_t)armData[0]) | (((uint32_t)armData[1]) << 8) | (((uint32_t)armData[2]) << 16) | (((uint32_t)armData[3]) << 24)); + + /* write the TX2 model */ + bufferPtr = modelDataBuffer; + retVal = MYKONOS_writeArmMem(device, armBufferAddr, bufferPtr, MODEL_SIZE); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + }/* end TX2 */ + + /* check for dual txChannel type */ + else if (txChannel == TX1_TX2) + { + /* check for single valid provided buffer size */ + if (modelNumberBytes != (2 * MODEL_SIZE)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE, + getMykonosErrorMessage(MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE)); + return MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE; + } + + /* retrieve the arm TX1 model buffer address */ + retVal = MYKONOS_readArmMem(device, (MYKONOS_ADDR_ARM_START_PROG_ADDR + MYKONOS_ADDR_TX1_DPD_MODEL_INDIRECT_PTR), &armData[0], 4, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + armBufferAddr = (((uint32_t)armData[0]) | (((uint32_t)armData[1]) << 8) | (((uint32_t)armData[2]) << 16) | (((uint32_t)armData[3]) << 24)); + + /* write the TX1 model */ + bufferPtr = modelDataBuffer; + retVal = MYKONOS_writeArmMem(device, armBufferAddr, bufferPtr, MODEL_SIZE); /* write TX1 model */ + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + bufferPtr += MODEL_SIZE; + + /* retrieve the arm TX2 model buffer address */ + retVal = MYKONOS_readArmMem(device, (MYKONOS_ADDR_ARM_START_PROG_ADDR + MYKONOS_ADDR_TX2_DPD_MODEL_INDIRECT_PTR), &armData[0], 4, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + armBufferAddr = (((uint32_t)armData[0]) | (((uint32_t)armData[1]) << 8) | (((uint32_t)armData[2]) << 16) | (((uint32_t)armData[3]) << 24)); + + /* write the TX2 model */ + retVal = MYKONOS_writeArmMem(device, armBufferAddr, bufferPtr, MODEL_SIZE); /* write TX2 model */ + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + }/*end two txChannel model data load */ + + /* invalid txChannel for this API command */ + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RESTDPDMOD_INVALID_TXCHANNEL, + getMykonosErrorMessage(MYKONOS_ERR_RESTDPDMOD_INVALID_TXCHANNEL)); + return MYKONOS_ERR_RESTDPDMOD_INVALID_TXCHANNEL; + }/* end invalid txChannel check */ + + /* instruct ARM to load DPD Model */ + extendedData[0] = MYKONOS_ARM_OBJECTID_GS_TRACKCALS; + extendedData[1] = MYKONOS_ARM_DPD_RESET; + extendedData[2] = (uint8_t)txChannel + RESTORE; + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_SET_OPCODE, &extendedData[0], sizeof(extendedData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* wait max of 1sec for command to complete */ + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_SET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RESTDPDMOD_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_RESTDPDMOD_ARMERRFLAG)); + return MYKONOS_ERR_RESTDPDMOD_ARMERRFLAG; + } + return retVal; + } + + return MYKONOS_ERR_OK; +} + + +/** + * \brief This function called during RadioOff, will allow retrieval of the DPD model file. + * + * This function reads a copy of the DPD model from ARM memory to user memory specified by the modelDataBuffer pointer. + * The user must provide the correct buffer size with the modelNumberBytes argument. + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param txChannel Desired Transmit channel to read back DPD status for (Valid ENUM type mykonosTxChannels_t: TX1 or TX2 or TX1_TX2) + * \param modelDataBuffer a pointer to the user buffer where the model data is to be written. + * Valid sizes: 182 bytes for a single model load to either TX1 or TX2. + * 364 bytes for a dual model load to both TX1_TX2, where the TX1 model data will occupy the first 182 bytes + * and TX2 model data will occupy the second 182 bytes. + * \param modelNumberBytes is the total buffer size of the user model data buffer. Allowed sizes are 182 bytes for TX1 or TX2 and + * 364 bytes for TX1_TX2. + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_SAVEDPDMODEL_ARMSTATE_ERROR ARM is not in the RadioOff state, call MYKONOS_radioOff() + * \retval MYKONOS_ERR_SAVEDPDMODEL_BUFFERSIZE_ERROR suppled modelNumberBytes size is incorrect. TX1 or TX2 = 182, TX1_TX2 = 364 + * \retval MYKONOS_ERR_SAVEDPDMODEL_INVALID_TXCHANNEL_ERROR supplied txChannel does not match TX1 or TX2 or TX1_TX2 + */ +mykonosErr_t MYKONOS_saveDpdModel(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t *modelDataBuffer, uint32_t modelNumberBytes) +{ + uint32_t radioStatus = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint16_t modelSize = 0; + uint8_t armData[4] = {0}; + uint32_t armBufferAddr = 0; + + const uint32_t MODEL_SIZE = 182; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_saveDpdModel()\n"); +#endif + + /* read radio state to make sure ARM is in radioOff /IDLE */ + retVal = MYKONOS_getRadioState(device, &radioStatus); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* throw error if not in radioOff/IDLE state */ + if (((radioStatus & 0x03) != MYKONOS_ARM_SYSTEMSTATE_IDLE) && ((radioStatus & 0x03) != MYKONOS_ARM_SYSTEMSTATE_READY)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SAVDPDMOD_ARMSTATE, getMykonosErrorMessage(MYKONOS_ERR_SAVDPDMOD_ARMSTATE)); /* radio not off or initialized */ + return MYKONOS_ERR_SAVDPDMOD_ARMSTATE; + } + + if (txChannel == TX1) + { + /* check for single valid provided buffer size */ + if (modelNumberBytes != MODEL_SIZE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SAVDPDMOD_WRONGBUFFERSIZE, + getMykonosErrorMessage(MYKONOS_ERR_SAVDPDMOD_WRONGBUFFERSIZE)); + return MYKONOS_ERR_SAVDPDMOD_WRONGBUFFERSIZE; /* wrong buffer size */ + } + + /* retrieve the arm TX1 model buffer address */ + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_PROG_ADDR + MYKONOS_ADDR_TX1_DPD_MODEL_WORKING_PTR, &armData[0], 4, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + armBufferAddr = (((uint32_t)armData[0]) | (((uint32_t)armData[1]) << 8) | (((uint32_t)armData[2]) << 16) | (((uint32_t)armData[3]) << 24)); + + /* read the TX1 model */ + retVal = MYKONOS_readArmMem(device, armBufferAddr, modelDataBuffer, MODEL_SIZE, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + modelDataBuffer += modelSize; + }/*end TX1 */ + + else if (txChannel == TX2) + { + /* check for single valid provided buffer size */ + if (modelNumberBytes != MODEL_SIZE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SAVDPDMOD_WRONGBUFFERSIZE, + getMykonosErrorMessage(MYKONOS_ERR_SAVDPDMOD_WRONGBUFFERSIZE)); + return MYKONOS_ERR_SAVDPDMOD_WRONGBUFFERSIZE; /* wrong buffer size */ + } + + /* retrieve the arm TX2 model buffer address */ + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_PROG_ADDR + MYKONOS_ADDR_TX2_DPD_MODEL_WORKING_PTR, &armData[0], 4, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + armBufferAddr = (((uint32_t)armData[0]) | (((uint32_t)armData[1]) << 8) | (((uint32_t)armData[2]) << 16) | (((uint32_t)armData[3]) << 24)); + + /* read the TX2 model */ + retVal = MYKONOS_readArmMem(device, armBufferAddr, modelDataBuffer, MODEL_SIZE, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + }/*end TX2 */ + + /* check for dual txChannel type */ + else if (txChannel == TX1_TX2) + { + /* check for single valid provided buffer size */ + if (modelNumberBytes != (2 * MODEL_SIZE)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SAVDPDMOD_WRONGBUFFERSIZE, + getMykonosErrorMessage(MYKONOS_ERR_SAVDPDMOD_WRONGBUFFERSIZE)); + return MYKONOS_ERR_SAVDPDMOD_WRONGBUFFERSIZE; /* wrong buffer size */ + } + + /* retrieve the arm TX1 model buffer address */ + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_PROG_ADDR + MYKONOS_ADDR_TX1_DPD_MODEL_WORKING_PTR, &armData[0], 4, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + armBufferAddr = (((uint32_t)armData[0]) | (((uint32_t)armData[1]) << 8) | (((uint32_t)armData[2]) << 16) | (((uint32_t)armData[3]) << 24)); + + /* read the TX1 model */ + retVal = MYKONOS_readArmMem(device, armBufferAddr, modelDataBuffer, MODEL_SIZE, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + modelDataBuffer += MODEL_SIZE; + + /* retrieve the arm TX2 model buffer address */ + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_PROG_ADDR + MYKONOS_ADDR_TX2_DPD_MODEL_WORKING_PTR, &armData[0], 4, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + armBufferAddr = (((uint32_t)armData[0]) | (((uint32_t)armData[1]) << 8) | (((uint32_t)armData[2]) << 16) | (((uint32_t)armData[3]) << 24)); + + /* read the TX2 model */ + retVal = MYKONOS_readArmMem(device, armBufferAddr, modelDataBuffer, MODEL_SIZE, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + }/* end TX1_TX2 txChannel */ + + /* invalid txChannel for this API command */ + else + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SAVDPDMOD_INVALID_TXCHANNEL, + getMykonosErrorMessage(MYKONOS_ERR_SAVDPDMOD_INVALID_TXCHANNEL)); + return MYKONOS_ERR_SAVDPDMOD_INVALID_TXCHANNEL; /* invalid txChannel */ + }/* end invalid txChannel check */ + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function sets the state of the DPD actuator. + * + * This function can be called in either Radio On or Off state. + * + * \pre A DPD-enabled transceiver is required for DPD to be enabled. DPD init cal has been run and DPD tracking enable. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param txChannel Desired Transmit channel to set the Actuator State (Valid ENUM values: TX1, TX2 or TX1_TX2) + * \param actState Desired actuator state for the DPD, valid states are 0-disable and 1-enable + * + * \retval MYKONOS_ERR_SETDPDACT_INV_TXCHANNEL ERROR: Tx channel is not valid (Valid ENUM values: TX1, TX2 or TX1_TX2) + * \retval MYKONOS_ERR_SETDPDACT_INV_STATE ERROR: Invalid Actuator state, valid states are 0-disable and 1-enable. + * \retval MYKONOS_ERR_SETDPDACT_ARMERRFLAG ERROR: ARM command flag error set + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setDpdActState(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t actState) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint32_t timeoutMs = 1000; + uint8_t extData[3] = {0}; + uint8_t actuatorSet = 0x00; + uint8_t cmdStatusByte = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setDpdActState()\n"); +#endif + + switch (txChannel) + { + case TX1: + break; + case TX2: + break; + case TX1_TX2: + break; + + default: + /* this function allow single channel gain only */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETDPDACT_INV_TXCHANNEL, + getMykonosErrorMessage(MYKONOS_ERR_SETDPDACT_INV_TXCHANNEL)); + return MYKONOS_ERR_SETDPDACT_INV_TXCHANNEL; + } + switch (actState) + { + case 0: + actuatorSet = DISABLE_DPD_ACTUATOR; + break; + case 1: + actuatorSet = ENABLE_DPD_ACTUATOR; + break; + + default: + /* this function allow single channel gain only */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETDPDACT_INV_STATE, + getMykonosErrorMessage(MYKONOS_ERR_SETDPDACT_INV_STATE)); + return MYKONOS_ERR_SETDPDACT_INV_STATE; + } + + extData[0] = MYKONOS_ARM_OBJECTID_TRACKING_CAL_CONTROL; + extData[1] = actuatorSet; + extData[2] = (uint8_t)txChannel; + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_SET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* check for completion */ + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_SET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETDPDACT_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_SETDPDACT_ARMERRFLAG)); + return MYKONOS_ERR_SETDPDACT_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETDPDACT_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_SETDPDACT_ARMERRFLAG)); + return MYKONOS_ERR_SETDPDACT_ARMERRFLAG; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function resets the DPD model. + * + * This function allows the user to reset the DPD actuator and prior model in radioOn or radioOff mode. + * The reset can restore prior model if the parameter passed is set to 2: this resets DPD first and then restores the previously loaded + * model into ARM memory for use with subsequent iterations of DPD. + * + * If reset is 1 then the reset function just reset the DPD actuator and not use any model. + * + * \pre A DPD-enabled transceiver is required for DPD to be enabled. DPD init cal has been run and DPD tracking enable. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param txChannel Desired Transmit channel to be reseted (Valid ENUM values: TX1, TX2 or TX1_TX2) + * \param reset is the required reset condition that is needed, the available options are given by the enum + * ::mykonosDpdResetMode_t + * + * \retval MYKONOS_ERR_RESETDPD_INV_TXCHANNEL: Tx channel is not valid (Valid ENUM values: TX1, TX2 or TX1_TX2) + * \retval MYKONOS_ERR_RESETDPD_WRONG_PARAM ERROR: reset parameter is not valid (Valid values: MYK_DPD_RESET_FULL, MYK_DPD_RESET_PRIOR or MYK_DPD_RESET_CORRELATOR) + * \retval MYKONOS_ERR_RESETDPD_ARMERRFLAG ERROR: ARM command flag error set + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_resetDpd(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosDpdResetMode_t reset) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint32_t timeoutMs = 1000; + uint8_t extData[3] = {0}; + uint8_t cmdStatusByte = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_resetDpd()\n"); +#endif + + switch (txChannel) + { + case TX1: + break; + case TX2: + break; + case TX1_TX2: + break; + + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RESETDPD_INV_TXCHANNEL, + getMykonosErrorMessage(MYKONOS_ERR_RESETDPD_INV_TXCHANNEL)); + return MYKONOS_ERR_RESETDPD_INV_TXCHANNEL; + } + + if ((reset >= MYK_DPD_RESET_END) || (reset == MYK_DPD_NO_ACTION)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RESETDPD_WRONG_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_RESETDPD_WRONG_PARAM)); + return MYKONOS_ERR_RESETDPD_WRONG_PARAM; + } + + /* instruct ARM to reset DPD Model */ + extData[0] = MYKONOS_ARM_OBJECTID_GS_TRACKCALS; + extData[1] = MYKONOS_ARM_DPD_RESET; + extData[2] = (uint8_t)(reset << 2) + (uint8_t)txChannel; + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_SET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* wait max of 1sec for command to complete */ + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_SET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RESETDPD_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_RESETDPD_ARMERRFLAG)); + return MYKONOS_ERR_RESETDPD_ARMERRFLAG; + } + return retVal; + } + + return MYKONOS_ERR_OK; +} +/** + * \brief This function will configure CLGC settings + * + * A DPD-enabled transceiver is required for CLGC to be enabled. The CLGC has several user + * adjustable settings that can be configured before running the runInitCals + * with the calMask set for the CLGC init cal. Call this function with desired + * settings set before running the CLGC init cal or enabling CLGC tracking. + * + * This function can be called in either Radio On or Off state. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * - device->tx->clgcConfig (All members) + * + * \retval MYKONOS_ERR_CFGCLGC_TXORX_PROFILE_INV ERROR: Tx and ObsRx profiles must be valid to use the CLGC feature + * \retval MYKONOS_ERR_CFGCLGC_NULL_CLGCCFGSTRUCT ERROR: CLGC config structure pointer is null in device->tx->clgcConfig + * \retval MYKONOS_ERR_CFGCLGC_INV_DESIREDGAIN ERROR: CLGC tx1DesiredGain or tx2DesiredGain parameter is out of range + * \retval MYKONOS_ERR_CFGCLGC_INV_TXATTENLIMIT ERROR: CLGC tx1AttenLimit or tx2AttenLimit parameter is out of range + * \retval MYKONOS_ERR_CFGCLGC_INV_CLGC_CTRLRATIO ERROR: clgcControlRatio parameter is out of range + * \retval MYKONOS_ERR_CFGCLGC_INV_THRESHOLD Error: tx1RelThreshold or tx2RelThreshold parameter is out of range + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_configClgc(mykonosDevice_t *device) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armFieldValue[4] = {0}; + uint8_t byteOffset = 0; + uint16_t negPnLevel = 0; + uint32_t radioStatus = 0x00; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_configClgc()\n"); +#endif + + /* CLGC requires Tx and ORx enabled, throw error if both are not enabled */ + if ((device->profilesValid & (TX_PROFILE_VALID | ORX_PROFILE_VALID)) != (TX_PROFILE_VALID | ORX_PROFILE_VALID)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGCLGC_TXORX_PROFILE_INV, + getMykonosErrorMessage(MYKONOS_ERR_CFGCLGC_TXORX_PROFILE_INV)); + return MYKONOS_ERR_CFGCLGC_TXORX_PROFILE_INV; + } + + if (device->tx->clgcConfig == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGCLGC_NULL_CLGCCFGSTRUCT, + getMykonosErrorMessage(MYKONOS_ERR_CFGCLGC_NULL_CLGCCFGSTRUCT)); + return MYKONOS_ERR_CFGCLGC_NULL_CLGCCFGSTRUCT; + } + + /* set CLGC desired gain parameter */ + if ((device->tx->clgcConfig->tx1DesiredGain < -10000) || (device->tx->clgcConfig->tx1DesiredGain > 10000) || (device->tx->clgcConfig->tx2DesiredGain < -10000) + || (device->tx->clgcConfig->tx2DesiredGain > 10000)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGCLGC_INV_DESIREDGAIN, + getMykonosErrorMessage(MYKONOS_ERR_CFGCLGC_INV_DESIREDGAIN)); + return MYKONOS_ERR_CFGCLGC_INV_DESIREDGAIN; + } + + armFieldValue[0] = (device->tx->clgcConfig->tx1DesiredGain & 0xFF); + armFieldValue[1] = (((uint16_t)device->tx->clgcConfig->tx1DesiredGain >> 8) & 0xFF); + armFieldValue[2] = (device->tx->clgcConfig->tx2DesiredGain & 0xFF); + armFieldValue[3] = (((uint16_t)device->tx->clgcConfig->tx2DesiredGain >> 8) & 0xFF); + + byteOffset = 0; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armFieldValue[0], sizeof(armFieldValue)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* set CLGC Tx Atten limit parameter */ + if ((device->tx->clgcConfig->tx1AttenLimit > 40) || (device->tx->clgcConfig->tx2AttenLimit > 40)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGCLGC_INV_TXATTENLIMIT, + getMykonosErrorMessage(MYKONOS_ERR_CFGCLGC_INV_TXATTENLIMIT)); + return MYKONOS_ERR_CFGCLGC_INV_TXATTENLIMIT; + } + + armFieldValue[0] = (device->tx->clgcConfig->tx1AttenLimit & 0xFF); + armFieldValue[1] = ((device->tx->clgcConfig->tx1AttenLimit >> 8) & 0xFF); + armFieldValue[2] = (device->tx->clgcConfig->tx2AttenLimit & 0xFF); + armFieldValue[3] = ((device->tx->clgcConfig->tx2AttenLimit >> 8) & 0xFF); + + byteOffset = 8; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armFieldValue[0], sizeof(armFieldValue)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* set CLGC Control Ratio parameter */ + if ((device->tx->clgcConfig->tx1ControlRatio < 1) || (device->tx->clgcConfig->tx1ControlRatio > 100) || (device->tx->clgcConfig->tx2ControlRatio < 1) + || (device->tx->clgcConfig->tx2ControlRatio > 100)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGCLGC_INV_CLGC_CTRLRATIO, + getMykonosErrorMessage(MYKONOS_ERR_CFGCLGC_INV_CLGC_CTRLRATIO)); + return MYKONOS_ERR_CFGCLGC_INV_CLGC_CTRLRATIO; + } + + armFieldValue[0] = (device->tx->clgcConfig->tx1ControlRatio & 0xFF); + armFieldValue[1] = ((device->tx->clgcConfig->tx1ControlRatio >> 8) & 0xFF); + armFieldValue[2] = (device->tx->clgcConfig->tx2ControlRatio & 0xFF); + armFieldValue[3] = ((device->tx->clgcConfig->tx2ControlRatio >> 8) & 0xFF); + + byteOffset = 12; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armFieldValue[0], sizeof(armFieldValue)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* set enable threshold for channel 1 */ + armFieldValue[0] = (device->tx->clgcConfig->tx1RelThresholdEn > 0) ? 1 : 0; + byteOffset = 0x24; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armFieldValue[0], 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* set enable threshold for channel 2 */ + armFieldValue[0] = (device->tx->clgcConfig->tx2RelThresholdEn > 0) ? 1 : 0; + byteOffset = 0x26; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armFieldValue[0], 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* set thresholds */ + if ((device->tx->clgcConfig->tx1RelThreshold > 10000) || (device->tx->clgcConfig->tx2RelThreshold > 10000)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGCLGC_INV_THRESHOLD, + getMykonosErrorMessage(MYKONOS_ERR_CFGCLGC_INV_THRESHOLD)); + return MYKONOS_ERR_CFGCLGC_INV_THRESHOLD; + } + + /* set threshold for channel 1 */ + armFieldValue[0] = (device->tx->clgcConfig->tx1RelThreshold & 0xFF); + armFieldValue[1] = ((device->tx->clgcConfig->tx1RelThreshold >> 8) & 0xFF); + byteOffset = 0x28; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armFieldValue[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* set threshold for channel 2 */ + armFieldValue[0] = (device->tx->clgcConfig->tx2RelThreshold & 0xFF); + armFieldValue[1] = ((device->tx->clgcConfig->tx2RelThreshold >> 8) & 0xFF); + byteOffset = 0x2A; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armFieldValue[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + if ((device->tx->clgcConfig->pathDelayPnSeqLevel < 1) || (device->tx->clgcConfig->pathDelayPnSeqLevel > 8191)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGCLGC_INV_PNSEQLEVEL, + getMykonosErrorMessage(MYKONOS_ERR_CFGCLGC_INV_PNSEQLEVEL)); + return MYKONOS_ERR_CFGCLGC_INV_PNSEQLEVEL; + } + + /* read radio state to make sure ARM is in radioOff /IDLE */ + retVal = MYKONOS_getRadioState(device, &radioStatus); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Radio state check */ + if (((radioStatus & 0x03) == MYKONOS_ARM_SYSTEMSTATE_IDLE) || ((radioStatus & 0x03) == MYKONOS_ARM_SYSTEMSTATE_READY)) + { + /* set CLGC additional delay offset parameter (init cal)*/ + if ((device->tx->clgcConfig->additionalDelayOffset < -64) || (device->tx->clgcConfig->additionalDelayOffset > 64)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGCLGC_INV_CLGC_ADDDELAY, + getMykonosErrorMessage(MYKONOS_ERR_CFGCLGC_INV_CLGC_ADDDELAY)); + return MYKONOS_ERR_CFGCLGC_INV_CLGC_ADDDELAY; + } + + armFieldValue[0] = (device->tx->clgcConfig->additionalDelayOffset & 0xFF); + armFieldValue[1] = (((uint16_t)device->tx->clgcConfig->additionalDelayOffset >> 8) & 0xFF); + byteOffset = 2; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCINIT_CONFIG, byteOffset, &armFieldValue[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + if ((device->tx->clgcConfig->pathDelayPnSeqLevel < 1) || (device->tx->clgcConfig->pathDelayPnSeqLevel > 8191)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGCLGC_INV_PNSEQLEVEL, + getMykonosErrorMessage(MYKONOS_ERR_CFGCLGC_INV_PNSEQLEVEL)); + return MYKONOS_ERR_CFGCLGC_INV_PNSEQLEVEL; + } + + /* Can not be changed in radio on */ + /* Set Path Delay PN sequence amplitude - positive and negative (init cal)*/ + armFieldValue[0] = (device->tx->clgcConfig->pathDelayPnSeqLevel & 0xFF); + armFieldValue[1] = ((device->tx->clgcConfig->pathDelayPnSeqLevel >> 8) & 0xFF); + + negPnLevel = ((~device->tx->clgcConfig->pathDelayPnSeqLevel) + 1); /* times -1 */ + armFieldValue[2] = (negPnLevel & 0xFF); + armFieldValue[3] = (((negPnLevel) >> 8) & 0xFF); + byteOffset = 10; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCINIT_CONFIG, byteOffset, &armFieldValue[0], sizeof(armFieldValue)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = enableClgcTracking(device, ((device->tx->clgcConfig->allowTx1AttenUpdates > 0) ? 1 : 0), ((device->tx->clgcConfig->allowTx2AttenUpdates > 0) ? 1 : 0)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + } + else + { + /* record warning about not updated members */ + CMB_writeToLog(ADIHAL_LOG_WARNING, device->spiSettings->chipSelectIndex, MYKONOS_WRN_RADIO_ON_NOT_MODIFIABLE, + getMykonosErrorMessage(MYKONOS_WRN_RADIO_ON_NOT_MODIFIABLE)); + } + + return MYKONOS_ERR_OK; +} + +/* \brief Reads the CLGC config structure from ARM memory + * + * This function reads the Closed Loop Gain Control structure + * from ARM memory and returns in the device->tx->clgcConfig structure. + * + * A DPD-enabled transceiver is required for CLGC to be enabled. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * - device->tx->clgcConfig (All members) + * + * \param device is structure pointer to the Mykonos data structure containing settings + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETCLGCCFG_TXORX_PROFILE_INV Error: Tx and ORx profiles must be valid for CLGC functions + * \retval MYKONOS_ERR_GETCLGCCFG_NULL_CFGSTRUCT Error: NULL pointer to device->tx->clgcConfig structure + */ +mykonosErr_t MYKONOS_getClgcConfig(mykonosDevice_t *device) +{ + uint16_t byteOffset = 0; + uint8_t armMem[16] = {0}; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getClgcConfig()\n"); +#endif + + /* CLGC requires Tx and ORx enabled, throw error if both are not enabled */ + if ((device->profilesValid & (TX_PROFILE_VALID | ORX_PROFILE_VALID)) != (TX_PROFILE_VALID | ORX_PROFILE_VALID)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETCLGCCFG_TXORX_PROFILE_INV, + getMykonosErrorMessage(MYKONOS_ERR_GETCLGCCFG_TXORX_PROFILE_INV)); + return MYKONOS_ERR_GETCLGCCFG_TXORX_PROFILE_INV; + } + + if (device->tx->clgcConfig == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETCLGCCFG_NULL_CFGSTRUCT, + getMykonosErrorMessage(MYKONOS_ERR_GETCLGCCFG_NULL_CFGSTRUCT)); + return MYKONOS_ERR_GETCLGCCFG_NULL_CFGSTRUCT; + } + + byteOffset = 0; + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armMem[0], sizeof(armMem)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + device->tx->clgcConfig->tx1DesiredGain = (int16_t)(((uint16_t)(armMem[1]) << 8) | (uint16_t)(armMem[0])); + device->tx->clgcConfig->tx2DesiredGain = (int16_t)(((uint16_t)(armMem[3]) << 8) | (uint16_t)(armMem[2])); + device->tx->clgcConfig->tx1AttenLimit = (((uint16_t)(armMem[9]) << 8) | (uint16_t)(armMem[8])); + device->tx->clgcConfig->tx2AttenLimit = (((uint16_t)(armMem[11]) << 8) | (uint16_t)(armMem[10])); + device->tx->clgcConfig->tx1ControlRatio = (((uint16_t)(armMem[13]) << 8) | (uint16_t)(armMem[12])); + device->tx->clgcConfig->tx2ControlRatio = (((uint16_t)(armMem[15]) << 8) | (uint16_t)(armMem[14])); + + byteOffset = 2; + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCINIT_CONFIG, byteOffset, &armMem[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + device->tx->clgcConfig->additionalDelayOffset = (int16_t)(((uint16_t)(armMem[1]) << 8) | (uint16_t)(armMem[0])); + + byteOffset = 10; + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCINIT_CONFIG, byteOffset, &armMem[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + device->tx->clgcConfig->pathDelayPnSeqLevel = (((uint16_t)(armMem[1]) << 8) | (uint16_t)(armMem[0])); + + /* need to figure out if this are the right addresses */ + byteOffset = 0x24; + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armMem[0], 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + device->tx->clgcConfig->tx1RelThresholdEn = (uint8_t)armMem[0]; + + byteOffset = 0x26; + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armMem[0], 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + device->tx->clgcConfig->tx2RelThresholdEn = (uint8_t)armMem[0]; + + byteOffset = 0x28; + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armMem[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + device->tx->clgcConfig->tx1RelThreshold = (((uint16_t)(armMem[1]) << 8) | (uint16_t)(armMem[0])); + + byteOffset = 0x2A; + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armMem[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + device->tx->clgcConfig->tx2RelThreshold = (((uint16_t)(armMem[1]) << 8) | (uint16_t)(armMem[0])); + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function reads the CLGC calibration status from the Mykonos ARM processor. + * + * The Closed Loop Gain Control Status is read back from the ARM processor and + * returned in the function parameter clgcStatus. + * + * A DPD-enabled transceiver is required for this feature to be enabled. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param txChannel Desired Transmit channel to read back CLGC status for (Valid ENUM values: TX1 or TX2 only) + * \param clgcStatus Pointer to a structure to return the status information to + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETCLGCSTATUS_NULLPARAM clgcStatus function parameter is a NULL pointer + * \retval MYKONOS_ERR_GETCLGCSTATUS_INV_CH txChannel parameter is a non supported value. + * \retval MYKONOS_ERR_GETCLGCSTATUS_ARMERRFLAG ARM reported an error while processing the GET ARM command + */ +mykonosErr_t MYKONOS_getClgcStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosClgcStatus_t *clgcStatus) +{ + uint8_t extData[3] = {MYKONOS_ARM_OBJECTID_CAL_STATUS, MYKONOS_ARM_OBJECTID_CLGCCONFIG, 0}; + uint8_t armData[52] = {0}; + uint32_t timeoutMs = 0; + uint8_t cmdStatusByte = 0; + uint32_t offset = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t channelSelect = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getClgcStatus()\n"); +#endif + + if (clgcStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETCLGCSTATUS_NULLPARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETCLGCSTATUS_NULLPARAM)); + return MYKONOS_ERR_GETCLGCSTATUS_NULLPARAM; + } + + switch (txChannel) + { + case TX1: + channelSelect = 0; + break; + case TX2: + channelSelect = 1; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETCLGCSTATUS_INV_CH, + getMykonosErrorMessage(MYKONOS_ERR_GETCLGCSTATUS_INV_CH)); + return MYKONOS_ERR_GETCLGCSTATUS_INV_CH; + } + } + + extData[2] = channelSelect; + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETCLGCSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETCLGCSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETCLGCSTATUS_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETCLGCSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETCLGCSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETCLGCSTATUS_ARMERRFLAG; + } + + /* read status from ARM memory */ + offset = 0; + retVal = MYKONOS_readArmMem(device, (MYKONOS_ADDR_ARM_START_DATA_ADDR + offset), &armData[0], sizeof(armData), 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + clgcStatus->errorStatus = ((uint32_t)(armData[3]) << 24) | ((uint32_t)(armData[2]) << 16) | ((uint32_t)(armData[1]) << 8) | (uint32_t)(armData[0]); + clgcStatus->desiredGain = (int32_t)(((uint32_t)(armData[23]) << 24) | ((uint32_t)(armData[22]) << 16) | ((uint32_t)(armData[21]) << 8) | (uint32_t)(armData[20])); + clgcStatus->currentGain = (int32_t)(((uint32_t)(armData[27]) << 24) | ((uint32_t)(armData[26]) << 16) | ((uint32_t)(armData[25]) << 8) | (uint32_t)(armData[24])); + clgcStatus->txGain = ((uint32_t)(armData[39]) << 24) | ((uint32_t)(armData[38]) << 16) | ((uint32_t)(armData[37]) << 8) | (uint32_t)(armData[36]); + clgcStatus->txRms = (int32_t)(((uint32_t)(armData[43]) << 24) | ((uint32_t)(armData[42]) << 16) | ((uint32_t)(armData[41]) << 8) | (uint32_t)(armData[40])); + clgcStatus->orxRms = (int32_t)(((uint32_t)(armData[47]) << 24) | ((uint32_t)(armData[46]) << 16) | ((uint32_t)(armData[45]) << 8) | (uint32_t)(armData[44])); + clgcStatus->trackCount = ((uint32_t)(armData[51]) << 24) | ((uint32_t)(armData[50]) << 16) | ((uint32_t)(armData[49]) << 8) | (uint32_t)(armData[48]); + + return retVal; +} + +/** + * \brief This private helper function called during RadioOff, will allow CLGC tracking to be scheduled + * by the ARM when back in the RadioOn state. + * + * This function sets a flag in the ARM memory that if the enableDpd tracking cal mask + * and this setting are both set, then the ARM will schedule closed loop gain control + * tracking to occur in the radioOn ARM state. + * + * A DPD-enabled transceiver is required for this feature to be enabled. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->tx->dpdConfig + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param tx1Enable 0=disable CLGC Tx1 tracking, 1= enable CLGC Tx1 tracking + * \param tx2Enable 0=disable CLGC Tx2 tracking, 1= enable CLGC Tx2 tracking + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_EN_CLGCTRACKING_ARMSTATE_ERROR ARM is not in the RadioOff state, call MYKONOS_radioOff() + */ +static mykonosErr_t enableClgcTracking(mykonosDevice_t *device, uint8_t tx1Enable, uint8_t tx2Enable) +{ + uint32_t radioStatus = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t enableBit[4] = {0}; + uint8_t byteOffset = 4; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_enableClgcTracking()\n"); +#endif + + /* read radio state to make sure ARM is in radioOff /IDLE */ + retVal = MYKONOS_getRadioState(device, &radioStatus); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* throw error if not in radioOff/IDLE state */ + if (((radioStatus & 0x03) != MYKONOS_ARM_SYSTEMSTATE_IDLE) && ((radioStatus & 0x03) != MYKONOS_ARM_SYSTEMSTATE_READY)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_EN_CLGCTRACKING_ARMSTATE_ERROR, + getMykonosErrorMessage(MYKONOS_ERR_EN_CLGCTRACKING_ARMSTATE_ERROR)); + return MYKONOS_ERR_EN_CLGCTRACKING_ARMSTATE_ERROR; + } + + enableBit[0] = (tx1Enable > 0) ? 1 : 0; + enableBit[1] = 0; + enableBit[2] = (tx2Enable > 0) ? 1 : 0; + enableBit[3] = 0; + + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &enableBit[0], 4); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function updates the CLGC desired gain parameter. + * + * This function can be called in either Radio On or Off state. + * + * \pre A DPD-enabled transceiver is required for CLGC to be enabled. CLGC init cal has been run and CLGC tracking enable. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param txChannel Desired Transmit channel to set the (Valid ENUM values: TX1 or TX2 only) + * \param gain Total gain and attenuation (dB * 100) for the selected channel txChannel + * + * \retval MYKONOS_ERR_SETCLGCGAIN_INV_TXCHANNEL ERROR: Tx channel is not valid (Valid ENUM values: TX1 or TX2 only) + * \retval MYKONOS_ERR_SETCLGCGAIN_TRACK_ARMERRFLAG ERROR: ARM command flag error set + * \retval MYKONOS_ERR_SETCLGCGAIN_INV_DESIREDGAIN ERROR: CLGC gain parameter is out of range, valid range is from -10000 to 10000. + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setClgcGain(mykonosDevice_t *device, mykonosTxChannels_t txChannel, int16_t gain) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint32_t timeoutMs = 1000; + uint8_t extData[4] = {0}; + uint8_t clcgChannel = 0x00; + uint8_t cmdStatusByte = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setClgcGain()\n"); +#endif + + /* Range check for desired gain parameter */ + if ((gain < -10000) || (gain > 10000)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETCLGCGAIN_INV_DESIREDGAIN, + getMykonosErrorMessage(MYKONOS_ERR_SETCLGCGAIN_INV_DESIREDGAIN)); + return MYKONOS_ERR_SETCLGCGAIN_INV_DESIREDGAIN; + } + + switch (txChannel) + { + case TX1: + clcgChannel = SET_CLGC_DESIRED_GAIN_1; + break; + case TX2: + clcgChannel = SET_CLGC_DESIRED_GAIN_2; + break; + + default: + /* this function allow single channel gain only */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETCLGCGAIN_INV_TXCHANNEL, + getMykonosErrorMessage(MYKONOS_ERR_SETCLGCGAIN_INV_TXCHANNEL)); + return MYKONOS_ERR_SETCLGCGAIN_INV_TXCHANNEL; + } + + extData[0] = MYKONOS_ARM_OBJECTID_TRACKING_CAL_CONTROL; + extData[1] = clcgChannel; + extData[2] = (gain & 0xFF); + extData[3] = (((uint16_t)gain >> 8) & 0xFF); + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_SET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* check for completion */ + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_SET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETCLGCGAIN_TRACK_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_SETCLGCGAIN_TRACK_ARMERRFLAG)); + return MYKONOS_ERR_SETCLGCGAIN_TRACK_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETCLGCGAIN_TRACK_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_SETCLGCGAIN_TRACK_ARMERRFLAG)); + return MYKONOS_ERR_SETCLGCGAIN_TRACK_ARMERRFLAG; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function, when called during RadioOff, will configure VSWR settings + * + * A DPD-enabled transceiver is required for VSWR to be enabled. The VSWR has several user + * adjustable settings that can be configured before running the runInitCals + * with the calMask set for the VSWR init cal. Call this function with desired + * settings set before running the VSWR init cal or enabling VSWR tracking. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * - device->tx->vswrConfig (All members) + * + * \retval MYKONOS_ERR_CFGVSWR_TXORX_PROFILE_INV ERROR: Tx and ObsRx profiles must be valid to use the VSWR feature + * \retval MYKONOS_ERR_CFGVSWR_NULL_VSWRCFGSTRUCT ERROR: CLGC config structure pointer is null in device->tx->clgcConfig + * \retval MYKONOS_ERR_CFGVSWR_ARMSTATE_ERROR ERROR: ARM is not in the IDLE(radioOff) or Ready state. + */ +mykonosErr_t MYKONOS_configVswr(mykonosDevice_t *device) +{ + uint32_t radioStatus = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armFieldValue[16] = {0}; + uint8_t byteOffset = 0; + uint16_t negPnLevel = 0; + + const uint8_t ENABLE_VSWR = 1; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_configVswr()\n"); +#endif + + /* VSWR requires Tx and ORx enabled, throw error if both are not enabled */ + if ((device->profilesValid & (TX_PROFILE_VALID | ORX_PROFILE_VALID)) != (TX_PROFILE_VALID | ORX_PROFILE_VALID)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGVSWR_TXORX_PROFILE_INV, + getMykonosErrorMessage(MYKONOS_ERR_CFGVSWR_TXORX_PROFILE_INV)); + return MYKONOS_ERR_CFGVSWR_TXORX_PROFILE_INV; + } + + if (device->tx->vswrConfig == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGVSWR_NULL_VSWRCFGSTRUCT, + getMykonosErrorMessage(MYKONOS_ERR_CFGVSWR_NULL_VSWRCFGSTRUCT)); + return MYKONOS_ERR_CFGVSWR_NULL_VSWRCFGSTRUCT; + } + + /* read radio state to make sure ARM is in radioOff /IDLE */ + retVal = MYKONOS_getRadioState(device, &radioStatus); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* throw error if not in radioOff/IDLE state */ + if (((radioStatus & 0x03) != MYKONOS_ARM_SYSTEMSTATE_IDLE) && ((radioStatus & 0x03) != MYKONOS_ARM_SYSTEMSTATE_READY)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGVSWR_ARMSTATE_ERROR, + getMykonosErrorMessage(MYKONOS_ERR_CFGVSWR_ARMSTATE_ERROR)); + return MYKONOS_ERR_CFGVSWR_ARMSTATE_ERROR; + } + + /* range check valid 3p3 GPIO pin */ + if ((device->tx->vswrConfig->tx1VswrSwitchGpio3p3Pin > 11) || (device->tx->vswrConfig->tx2VswrSwitchGpio3p3Pin > 11)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGVSWR_INV_3P3GPIOPIN, + getMykonosErrorMessage(MYKONOS_ERR_CFGVSWR_INV_3P3GPIOPIN)); + return MYKONOS_ERR_CFGVSWR_INV_3P3GPIOPIN; + } + + armFieldValue[0] = ENABLE_VSWR; + armFieldValue[1] = 0; + armFieldValue[2] = ENABLE_VSWR; + armFieldValue[3] = 0; + armFieldValue[4] = (device->tx->vswrConfig->tx1VswrSwitchGpio3p3Pin & 0xFF); + armFieldValue[5] = 0; + armFieldValue[6] = (device->tx->vswrConfig->tx2VswrSwitchGpio3p3Pin & 0xFF); + armFieldValue[7] = 0; + armFieldValue[8] = (device->tx->vswrConfig->tx1VswrSwitchPolarity > 0) ? 1 : 0; + armFieldValue[9] = 0; + armFieldValue[10] = (device->tx->vswrConfig->tx2VswrSwitchPolarity > 0) ? 1 : 0; + armFieldValue[11] = 0; + armFieldValue[12] = device->tx->vswrConfig->tx1VswrSwitchDelay_us; /* support full 0 to 255 us range */ + armFieldValue[13] = 0; + armFieldValue[14] = device->tx->vswrConfig->tx2VswrSwitchDelay_us; /* support full 0 to 255 us range */ + armFieldValue[15] = 0; + byteOffset = 0; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_VSWRCONFIG, byteOffset, &armFieldValue[0], 16); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* set VSWR additional delay offset parameter (init cal)*/ + if ((device->tx->vswrConfig->additionalDelayOffset < -64) || (device->tx->vswrConfig->additionalDelayOffset > 64)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGVSWR_INV_VSWR_ADDDELAY, + getMykonosErrorMessage(MYKONOS_ERR_CFGVSWR_INV_VSWR_ADDDELAY)); + return MYKONOS_ERR_CFGVSWR_INV_VSWR_ADDDELAY; + } + + armFieldValue[0] = (device->tx->vswrConfig->additionalDelayOffset & 0xFF); + armFieldValue[1] = (((uint16_t)device->tx->vswrConfig->additionalDelayOffset >> 8) & 0xFF); + byteOffset = 2; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_VSWRINIT_CONFIG, byteOffset, &armFieldValue[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + if ((device->tx->vswrConfig->pathDelayPnSeqLevel < 1) || (device->tx->vswrConfig->pathDelayPnSeqLevel > 8191)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGVSWR_INV_PNSEQLEVEL, + getMykonosErrorMessage(MYKONOS_ERR_CFGVSWR_INV_PNSEQLEVEL)); + return MYKONOS_ERR_CFGVSWR_INV_PNSEQLEVEL; + } + + /* Set Path Delay PN sequence amplitude - positive and negative (init cal)*/ + armFieldValue[0] = (device->tx->vswrConfig->pathDelayPnSeqLevel & 0xFF); + armFieldValue[1] = ((device->tx->vswrConfig->pathDelayPnSeqLevel >> 8) & 0xFF); + + negPnLevel = ((~device->tx->vswrConfig->pathDelayPnSeqLevel) + 1); /* times -1 */ + armFieldValue[2] = (negPnLevel & 0xFF); + armFieldValue[3] = (((negPnLevel) >> 8) & 0xFF); + byteOffset = 10; + + /* Set for Tx1 channel */ + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_VSWRINIT_CONFIG, byteOffset, &armFieldValue[0], 4); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Set for Tx2 channel */ + byteOffset = 30; + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_VSWRINIT_CONFIG, byteOffset, &armFieldValue[0], 4); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + return MYKONOS_ERR_OK; +} + +/* \brief Reads the VSWR config structure from ARM memory + * + * This function reads the VSWR structure + * from ARM memory and returns in the device->tx->vswrConfig structure. + * + * A DPD-enabled transceiver is required for VSWR to be enabled. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * - device->tx->vswrConfig (All members) + * + * \param device is structure pointer to the Mykonos data structure containing settings + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETVSWRCFG_TXORX_PROFILE_INV Error: Tx and ORx profiles must be valid for VSWR functions + * \retval MYKONOS_ERR_GETVSWRCFG_NULL_CFGSTRUCT Error: NULL pointer to device->tx->vswrConfig structure + */ +mykonosErr_t MYKONOS_getVswrConfig(mykonosDevice_t *device) +{ + uint16_t byteOffset = 0; + uint8_t armMem[12] = {0}; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getVswrConfig()\n"); +#endif + + /* VSWR requires Tx and ORx enabled, throw error if both are not enabled */ + if ((device->profilesValid & (TX_PROFILE_VALID | ORX_PROFILE_VALID)) != (TX_PROFILE_VALID | ORX_PROFILE_VALID)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETVSWRCFG_TXORX_PROFILE_INV, + getMykonosErrorMessage(MYKONOS_ERR_GETVSWRCFG_TXORX_PROFILE_INV)); + return MYKONOS_ERR_GETVSWRCFG_TXORX_PROFILE_INV; + } + + if (device->tx->vswrConfig == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETVSWRCFG_NULL_CFGSTRUCT, + getMykonosErrorMessage(MYKONOS_ERR_GETVSWRCFG_NULL_CFGSTRUCT)); + return MYKONOS_ERR_GETVSWRCFG_NULL_CFGSTRUCT; + } + + byteOffset = 4; + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_VSWRCONFIG, byteOffset, &armMem[0], sizeof(armMem)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + device->tx->vswrConfig->tx1VswrSwitchGpio3p3Pin = armMem[0]; + device->tx->vswrConfig->tx2VswrSwitchGpio3p3Pin = armMem[2]; + device->tx->vswrConfig->tx1VswrSwitchPolarity = armMem[4]; + device->tx->vswrConfig->tx2VswrSwitchPolarity = armMem[6]; + device->tx->vswrConfig->tx1VswrSwitchDelay_us = armMem[8]; + device->tx->vswrConfig->tx2VswrSwitchDelay_us = armMem[10]; + + byteOffset = 2; + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_VSWRINIT_CONFIG, byteOffset, &armMem[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + device->tx->vswrConfig->additionalDelayOffset = (int16_t)(((uint16_t)(armMem[1]) << 8) | (uint16_t)(armMem[0])); + + byteOffset = 10; + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_VSWRINIT_CONFIG, byteOffset, &armMem[0], 2); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + device->tx->vswrConfig->pathDelayPnSeqLevel = (((uint16_t)(armMem[1]) << 8) | (uint16_t)(armMem[0])); + + return MYKONOS_ERR_OK; +} + +/** + * \brief This function reads the VSWR calibration status from the Mykonos ARM processor. + * + * The VSWR Status is read back from the ARM processor and + * returned in the function parameter vswrStatus. + * + * A DPD-enabled transceiver is required for this feature to be enabled. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param txChannel Desired Transmit channel to read back VSWR status for (Valid ENUM values: TX1 or TX2 only) + * \param vswrStatus Pointer to a structure to return the status information to + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETVSWRSTATUS_NULLPARAM vswrStatus function parameter is a NULL pointer + * \retval MYKONOS_ERR_GETVSWRSTATUS_INV_CH txChannel parameter is a non supported value. + * \retval MYKONOS_ERR_GETVSWRSTATUS_ARMERRFLAG ARM reported an error while processing the GET ARM command + */ +mykonosErr_t MYKONOS_getVswrStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosVswrStatus_t *vswrStatus) +{ + uint8_t extData[3] = {MYKONOS_ARM_OBJECTID_CAL_STATUS, MYKONOS_ARM_OBJECTID_VSWRCONFIG, 0}; + uint8_t armData[64] = {0}; + uint32_t timeoutMs = 0; + uint8_t cmdStatusByte = 0; + uint32_t offset = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t channelSelect = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getVswrStatus()\n"); +#endif + + if (vswrStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETVSWRSTATUS_NULLPARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETVSWRSTATUS_NULLPARAM)); + return MYKONOS_ERR_GETVSWRSTATUS_NULLPARAM; + } + + switch (txChannel) + { + case TX1: + channelSelect = 0; + break; + case TX2: + channelSelect = 1; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETVSWRSTATUS_INV_CH, + getMykonosErrorMessage(MYKONOS_ERR_GETVSWRSTATUS_INV_CH)); + return MYKONOS_ERR_GETVSWRSTATUS_INV_CH; + } + } + + extData[2] = channelSelect; + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + /* throw more specific error message instead of returning error code from waitArmCmdStatus */ + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETVSWRSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETVSWRSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETVSWRSTATUS_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETVSWRSTATUS_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETVSWRSTATUS_ARMERRFLAG)); + return MYKONOS_ERR_GETVSWRSTATUS_ARMERRFLAG; + } + + /* read status from ARM memory */ + offset = 0; + retVal = MYKONOS_readArmMem(device, (MYKONOS_ADDR_ARM_START_DATA_ADDR + offset), &armData[0], sizeof(armData), 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + vswrStatus->errorStatus = ((uint32_t)(armData[3]) << 24) | ((uint32_t)(armData[2]) << 16) | ((uint32_t)(armData[1]) << 8) | (uint32_t)(armData[0]); + vswrStatus->forwardGainRms_dB = (int32_t)(((uint32_t)(armData[23]) << 24) | ((uint32_t)(armData[22]) << 16) | ((uint32_t)(armData[21]) << 8) | (uint32_t)(armData[20])); + vswrStatus->forwardGainReal = (int32_t)(((uint32_t)(armData[27]) << 24) | ((uint32_t)(armData[26]) << 16) | ((uint32_t)(armData[25]) << 8) | (uint32_t)(armData[24])); + vswrStatus->forwardGainImag = (int32_t)(((uint32_t)(armData[31]) << 24) | ((uint32_t)(armData[30]) << 16) | ((uint32_t)(armData[29]) << 8) | (uint32_t)(armData[28])); + vswrStatus->reflectedGainRms_dB = (int32_t)(((uint32_t)(armData[35]) << 24) | ((uint32_t)(armData[34]) << 16) | ((uint32_t)(armData[33]) << 8) | (uint32_t)(armData[32])); + vswrStatus->reflectedGainReal = (int32_t)(((uint32_t)(armData[39]) << 24) | ((uint32_t)(armData[38]) << 16) | ((uint32_t)(armData[37]) << 8) | (uint32_t)(armData[36])); + vswrStatus->reflectedGainImag = (int32_t)(((uint32_t)(armData[43]) << 24) | ((uint32_t)(armData[42]) << 16) | ((uint32_t)(armData[41]) << 8) | (uint32_t)(armData[40])); + vswrStatus->trackCount = ((uint32_t)(armData[63]) << 24) | ((uint32_t)(armData[62]) << 16) | ((uint32_t)(armData[61]) << 8) | (uint32_t)(armData[60]); + vswrStatus->vswr_forward_tx_rms = (int32_t)(((uint32_t)(armData[47]) << 24) | ((uint32_t)(armData[46]) << 16) | ((uint32_t)(armData[45]) << 8) | (uint32_t)(armData[44])); + vswrStatus->vswr_forward_orx_rms = (int32_t)(((uint32_t)(armData[51]) << 24) | ((uint32_t)(armData[50]) << 16) | ((uint32_t)(armData[49]) << 8) | (uint32_t)(armData[48])); + vswrStatus->vswr_reflection_tx_rms = (int32_t)(((uint32_t)(armData[55]) << 24) | ((uint32_t)(armData[54]) << 16) | ((uint32_t)(armData[53]) << 8) | (uint32_t)(armData[52])); + vswrStatus->vswr_reflection_orx_rms = (int32_t)(((uint32_t)(armData[59]) << 24) | ((uint32_t)(armData[58]) << 16) | ((uint32_t)(armData[57]) << 8) | (uint32_t)(armData[56])); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Read from the Mykonos ARM program or data memory + * + * Valid memory addresses are: Program Memory (0x01000000 - 0x01017FFF), + * Data Memory (0x20000000 - 0x2000FFFF) + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param address The 32bit ARM address to read from. + * \param returnData Byte(uint8_t) array containing the data read from the ARM memory. + * \param bytesToRead Number of bytes in the returnData array. + * \param autoIncrement is boolean flag to enable or disable autoincrement of ARM register address + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_READARMMEM_INV_ADDR_PARM ARM memory address is out of range + * + */ +mykonosErr_t MYKONOS_readArmMem(mykonosDevice_t *device, uint32_t address, uint8_t *returnData, uint32_t bytesToRead, uint8_t autoIncrement) +{ + uint8_t dataMem; + uint32_t i; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_readArmMem()\n"); +#endif + + /* check that start and stop address are in valid range */ + if ((!(address >= MYKONOS_ADDR_ARM_START_PROG_ADDR && address <= MYKONOS_ADDR_ARM_END_PROG_ADDR)) + && !(address >= MYKONOS_ADDR_ARM_START_DATA_ADDR && address <= MYKONOS_ADDR_ARM_END_DATA_ADDR)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READARMMEM_INV_ADDR_PARM, + getMykonosErrorMessage(MYKONOS_ERR_READARMMEM_INV_ADDR_PARM)); + return MYKONOS_ERR_READARMMEM_INV_ADDR_PARM; + } + + if ((!(((address + bytesToRead - 1) >= MYKONOS_ADDR_ARM_START_PROG_ADDR) && (address + bytesToRead - 1) <= MYKONOS_ADDR_ARM_END_PROG_ADDR)) + && (!(((address + bytesToRead - 1) >= MYKONOS_ADDR_ARM_START_DATA_ADDR) && (address + bytesToRead - 1) <= MYKONOS_ADDR_ARM_END_DATA_ADDR))) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READARMMEM_INV_ADDR_PARM, + getMykonosErrorMessage(MYKONOS_ERR_READARMMEM_INV_ADDR_PARM)); + return MYKONOS_ERR_READARMMEM_INV_ADDR_PARM; + } + + if (address >= MYKONOS_ADDR_ARM_START_DATA_ADDR && address <= MYKONOS_ADDR_ARM_END_DATA_ADDR) + { + dataMem = 1; + } + else + { + dataMem = 0; + } + + /* NOT assuming auto increment bit is already set from MYKONOS_initARM function call */ + /* setting auto increment address bit if autoIncrement evaluates true */ + if (autoIncrement) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_ARM_CTL_1, 0x01, 0x04, 2); + } + else + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_ARM_CTL_1, 0x00, 0x04, 2); + } + + /* setting up for ARM read */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_ARM_CTL_1, 0x01, 0x20, 5); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_ADDR_BYTE_0, (uint8_t)((address) >> 2)); /* write address[9:2] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_ADDR_BYTE_1, (uint8_t)(address >> 10) | (uint8_t)(dataMem << 7)); /* write address[15:10] */ + + /* start read-back at correct byte offset */ + /* read data is located at SPI address 0xD04=data[7:0], 0xD05=data[15:8], 0xD06=data[23:16], 0xD07=data[31:24]. */ + /* with address auto increment set, after xD07 is read, the address will automatically increment */ + /* without address auto increment set, 0x4 must be added to the address for correct indexing */ + if (autoIncrement) + { + for (i = 0; i < bytesToRead; i++) + { + CMB_SPIReadByte(device->spiSettings, (MYKONOS_ADDR_ARM_DATA_BYTE_0 | (((address & 0x3) + i) % 4)), &returnData[i]); + } + } + else + { + for (i = 0; i < bytesToRead; i++) + { + CMB_SPIReadByte(device->spiSettings, (MYKONOS_ADDR_ARM_DATA_BYTE_0 | (((address & 0x3) + i) % 4)), &returnData[i]); + + if ((MYKONOS_ADDR_ARM_DATA_BYTE_0 | (((address & 0x3) + i) % 4)) == MYKONOS_ADDR_ARM_DATA_BYTE_3) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_ADDR_BYTE_0, (uint8_t)(((address + 0x4) & 0x3FF) >> 2)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_ADDR_BYTE_1, ((address + 0x4) & 0x1FC00U) >> 10 | (uint8_t)(dataMem << 7)); + } + } + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Write to the Mykonos ARM program or data memory + * + * Valid memory addresses are: Program Memory (0x01000000 - 0x01017FFF), + * Data Memory (0x20000000 - 0x2000FFFF) + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param address The 32bit ARM address to write to. + * \param data Byte(uint8_t) array containing the data to write to the ARM memory. + * \param byteCount Number of bytes in the data array. + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_WRITEARMMEM_NULL_PARM Function parameter data has NULL pointer when byteCount is >0 + * \retval MYKONOS_ERR_WRITEARMMEM_INV_ADDR_PARM ARM memory address is out of range of valid ARM memory + */ +mykonosErr_t MYKONOS_writeArmMem(mykonosDevice_t *device, uint32_t address, uint8_t *data, uint32_t byteCount) +{ + /* write address, then data with auto increment enabled. */ + uint8_t dataMem; + uint32_t i; + +#if MYK_ENABLE_SPIWRITEARRAY == 1 + uint32_t addrIndex = 0; + uint32_t dataIndex = 0; + uint32_t spiBufferSize = MYK_SPIWRITEARRAY_BUFFERSIZE; + uint16_t addrArray[MYK_SPIWRITEARRAY_BUFFERSIZE] = {0}; +#endif + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_writeArmMem()\n"); +#endif + + if ((data == NULL) && (byteCount > 0)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WRITEARMMEM_NULL_PARM, + getMykonosErrorMessage(MYKONOS_ERR_WRITEARMMEM_NULL_PARM)); + return MYKONOS_ERR_WRITEARMMEM_NULL_PARM; + } + + if ((!(address >= MYKONOS_ADDR_ARM_START_PROG_ADDR && address <= MYKONOS_ADDR_ARM_END_PROG_ADDR)) + && !(address >= MYKONOS_ADDR_ARM_START_DATA_ADDR && address <= MYKONOS_ADDR_ARM_END_DATA_ADDR)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WRITEARMMEM_INV_ADDR_PARM, + getMykonosErrorMessage(MYKONOS_ERR_WRITEARMMEM_INV_ADDR_PARM)); + return MYKONOS_ERR_WRITEARMMEM_INV_ADDR_PARM; + } + + if ((!(((address + byteCount - 1) >= MYKONOS_ADDR_ARM_START_PROG_ADDR) && ((address + byteCount - 1) <= MYKONOS_ADDR_ARM_END_PROG_ADDR))) + && (!(((address + byteCount - 1) >= MYKONOS_ADDR_ARM_START_DATA_ADDR) && ((address + byteCount - 1) <= MYKONOS_ADDR_ARM_END_DATA_ADDR)))) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WRITEARMMEM_INV_ADDR_PARM, + getMykonosErrorMessage(MYKONOS_ERR_WRITEARMMEM_INV_ADDR_PARM)); + return MYKONOS_ERR_WRITEARMMEM_INV_ADDR_PARM; + } + + if (address >= MYKONOS_ADDR_ARM_START_DATA_ADDR && address <= MYKONOS_ADDR_ARM_END_DATA_ADDR) + { + dataMem = 1; + } + else + { + dataMem = 0; + } + + /* set auto increment address bit */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_ARM_CTL_1, 0x01, 0x04, 2); + + /* writing the address */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_ARM_CTL_1, 0x00, 0x20, 5); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_ADDR_BYTE_0, (uint8_t)((address) >> 2)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_ADDR_BYTE_1, (uint8_t)(address >> 10) | (uint8_t)(dataMem << 7)); + + /* start write at correct byte offset */ + /* write data is located at SPI address 0xD04=data[7:0], 0xD05=data[15:8], 0xD06=data[23:16], 0xD07=data[31:24] */ + /* with address auto increment set, after x407 is written, the address will automatically increment */ + +#if (MYK_ENABLE_SPIWRITEARRAY == 0) + + for (i = 0; i < byteCount; i++) + { + CMB_SPIWriteByte(device->spiSettings, (MYKONOS_ADDR_ARM_DATA_BYTE_0 | (((address & 0x3) + i) % 4)), data[i]); + } + +#elif (MYK_ENABLE_SPIWRITEARRAY == 1) + + addrIndex = 0; + dataIndex = 0; + for (i = 0; i < byteCount; i++) + { + addrArray[addrIndex++] = (MYKONOS_ADDR_ARM_DATA_BYTE_0 | (((address & 0x3) + i) % 4)); + + if (addrIndex == spiBufferSize) + { + CMB_SPIWriteBytes(device->spiSettings, &addrArray[0], &data[dataIndex], addrIndex); + dataIndex = dataIndex + addrIndex; + addrIndex = 0; + } + } + + if (addrIndex > 0) + { + CMB_SPIWriteBytes(device->spiSettings, &addrArray[0], &data[dataIndex], addrIndex); + } + +#endif + + return MYKONOS_ERR_OK; +} + +/** + * \brief Low level helper function used by Mykonos API to write the ARM memory config structures + * + * Normally this function should not be required to be used directly by the BBIC. This is a helper + * function used by other Mykonos API commands to write settings into the ARM memory. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param objectId ARM id of a particular structure or setting in ARM memory + * \param offset Byte offset from the start of the objectId's memory location in ARM memory + * \param data A byte array containing data to write to the ARM memory buffer. + * \param byteCount Number of bytes in the data array (Valid size = 1-255 bytes) + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_WRITEARMCFG_ARMERRFLAG ARM write config command failed with a nonzero error code + */ +mykonosErr_t MYKONOS_writeArmConfig(mykonosDevice_t *device, uint8_t objectId, uint16_t offset, uint8_t *data, uint8_t byteCount) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t extendedData[4] = {0}; /* ARM Object id, byte offset LSB, offset MSB = 0, copy 2 bytes */ + uint32_t timeoutMs = 1000; + uint8_t cmdStatusByte = 0; + + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &data[0], byteCount); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + extendedData[0] = objectId; + extendedData[1] = (offset & 0xFF); + extendedData[2] = ((offset >> 8) & 0xFF); + extendedData[3] = byteCount; + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_WRITECFG_OPCODE, &extendedData[0], sizeof(extendedData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_WRITECFG_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WRITEARMCFG_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_WRITEARMCFG_ARMERRFLAG)); + return MYKONOS_ERR_WRITEARMCFG_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WRITEARMCFG_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_WRITEARMCFG_ARMERRFLAG)); + return MYKONOS_ERR_WRITEARMCFG_ARMERRFLAG; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Low level helper function used by Mykonos API to read the ARM memory config structures + * + * Normally this function should not be required to be used directly by the BBIC. This is a helper + * function used by other Mykonos API commands to read settings from the ARM memory. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param objectId ARM id of a particular structure or setting in ARM memory + * \param offset Byte offset from the start of the objectId's memory location in ARM memory + * \param data A byte array containing data to write to the ARM memory buffer. + * \param byteCount Number of bytes in the data array (Valid size = 1-255 bytes) + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_READARMCFG_ARMERRFLAG ARM read config command failed with a nonzero error code + */ +mykonosErr_t MYKONOS_readArmConfig(mykonosDevice_t *device, uint8_t objectId, uint16_t offset, uint8_t *data, uint8_t byteCount) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t extendedData[4] = {0}; /* ARM Object id, byte offset LSB, offset MSB = 0, copy 2 bytes */ + uint32_t timeoutMs = 1000; + uint8_t cmdStatusByte = 0; + const uint8_t AUTO_INCREMENT = 1; + extendedData[0] = objectId; + extendedData[1] = (offset & 0xFF); + extendedData[2] = ((offset >> 8) & 0xFF); + extendedData[3] = byteCount; + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_READCFG_OPCODE, &extendedData[0], sizeof(extendedData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_READCFG_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READARMCFG_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_READARMCFG_ARMERRFLAG)); + return MYKONOS_ERR_READARMCFG_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READARMCFG_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_READARMCFG_ARMERRFLAG)); + return MYKONOS_ERR_READARMCFG_ARMERRFLAG; + } + + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &data[0], byteCount, AUTO_INCREMENT); + + return retVal; +} + +/** + * \brief Sends a command to the Mykonos ARM processor + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->spiSettings + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param opCode Value (0-30, even only) indicating the desired function to run in the ARM. + * \param extendedData A byte array containing extended data to write to the ARM command interface. + * \param extendedDataNumBytes Number of bytes in the extendedData array (Valid size = 0-4 bytes) + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_ARMCMD_NULL_PARM Function parameter extendedData is NULL and extendedDataNumBytes is positive + * \retval MYKONOS_ERR_ARMCMD_INV_OPCODE_PARM ARM opcode is out of range (valid 0-30, even only) + * \retval MYKONOS_ERR_ARMCMD_INV_NUMBYTES_PARM Number of extended bytes parameter is out of range (valid 0-4) + * \retval MYKONOS_ERR_TIMEDOUT_ARMMAILBOXBUSY ARM control interface is busy, command could not be executed by ARM + */ +mykonosErr_t MYKONOS_sendArmCommand(mykonosDevice_t *device, uint8_t opCode, uint8_t *extendedData, uint8_t extendedDataNumBytes) +{ + uint8_t armCommandBusy = 0; + uint8_t i = 0; + uint16_t extCmdByteStartAddr = MYKONOS_ADDR_ARM_EXT_CMD_BYTE_1; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_sendArmCommand()\n"); +#endif + + if ((extendedData == NULL) && (extendedDataNumBytes > 0)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ARMCMD_NULL_PARM, getMykonosErrorMessage(MYKONOS_ERR_ARMCMD_NULL_PARM)); + return MYKONOS_ERR_ARMCMD_NULL_PARM; + } + + /* check for even-numbered opCodes only including opcode 0, but not must be greater than opCode 30 */ + if ((opCode != 0) && ((opCode % 2) || (opCode > 30))) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ARMCMD_INV_OPCODE_PARM, + getMykonosErrorMessage(MYKONOS_ERR_ARMCMD_INV_OPCODE_PARM)); + return MYKONOS_ERR_ARMCMD_INV_OPCODE_PARM; + } + + /* the number of valid extended data bytes is from 0-4 */ + if (extendedDataNumBytes > 4) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ARMCMD_INV_NUMBYTES_PARM, + getMykonosErrorMessage(MYKONOS_ERR_ARMCMD_INV_NUMBYTES_PARM)); + return MYKONOS_ERR_ARMCMD_INV_NUMBYTES_PARM; + } + + /* setting a 2 sec timeout for mailbox busy bit to be clear (can't send an arm mailbox command until mailbox is ready) */ + CMB_setTimeout_ms(2000); + + do + { + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_ARM_CMD, &armCommandBusy, 0x80, 7); + + if (CMB_hasTimeoutExpired()) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_TIMEDOUT_ARMMAILBOXBUSY, + getMykonosErrorMessage(MYKONOS_ERR_TIMEDOUT_ARMMAILBOXBUSY)); + return MYKONOS_ERR_TIMEDOUT_ARMMAILBOXBUSY; + } + } while (armCommandBusy); + + if (extendedDataNumBytes) + { + for (i = 0; i < extendedDataNumBytes; i++) + { + CMB_SPIWriteByte(device->spiSettings, extCmdByteStartAddr + i, extendedData[i]); + } + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_ARM_CMD, opCode); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Reads the Mykonos ARM 64-bit command status register + * + * A 64-bit status register consisting of a pending bit and three-bit error type is read one byte at + * a time for opcodes 0-30. The function parses the pending bits and error bits into + * two (2) separate 16-bit words containing pending bits, and error bits if the error type > 0 + * The words are weighted according to each even-numbered opcode from 0-30, + * where, 0x0001 = opcode '0', 0x0002 = opcode '2', 0x0004 = opcode '4', 0x0008 = opcode '6' and so on. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param errorWord 16-bit error word comprised of weighted bits according to each opcode number + * The weighted bit = '1' if error type > 0, '0' if OK + * \param statusWord 16-bit pending bits word comprised of weighted bits according to each opcode number + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_READARMCMDSTATUS_NULL_PARM Function parameters errorWord or statusWord have a NULL pointer + */ +mykonosErr_t MYKONOS_readArmCmdStatus(mykonosDevice_t *device, uint16_t *errorWord, uint16_t *statusWord) +{ + uint8_t i = 0; + uint8_t bytes[8] = {0}; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_readArmCmdStatus()\n"); +#endif + + if (errorWord == NULL || statusWord == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READARMCMDSTATUS_NULL_PARM, + getMykonosErrorMessage(MYKONOS_ERR_READARMCMDSTATUS_NULL_PARM)); + return MYKONOS_ERR_READARMCMDSTATUS_NULL_PARM; + } + + /* making sure the errorWord and statusWord are clear */ + *errorWord = 0; + *statusWord = 0; + + /* read in the entire 64-bit status register into a byte array for parsing */ + for (i = 0; i < 8; i++) + { + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_ARM_CMD_STATUS_0 + i, &bytes[i]); + } + + /* parse the byte array for pending bits and error types and generate statusWord and errorWord bits */ + for (i = 0; i < 8; i++) + { + *statusWord |= (uint16_t)((uint16_t)(((bytes[i] & 0x10) >> 3) | (bytes[i] & 0x01)) << (i * 2)); + + if (bytes[i] & 0x0E) + { + *errorWord |= (uint16_t)(0x0001 << (i * 2)); + } + else if (bytes[i] & 0xE0) + { + *errorWord |= (uint16_t)(0x0002 << (i * 2)); + } + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Isolated byte read of the Mykonos ARM 64-bit command status register based on the opcode + * + * A single byte read is performed on the 64-bit command status register according to + * the opcode of interest. The pending bit and the error type are extracted from the status + * register and returned as a single byte in the lower nibble. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param opCode Valid values are even increments from 0-30. The ARM opCode is used to determine which status register byte to read + * \param cmdStatByte returns cmdStatByte[3:1] = error type, cmdStatByte[0] = pending flag for selected opCode + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_READARMCMDSTATUSBYTE_NULL_PARM Function parameter cmdStatByte has NULL pointer + * \retval MYKONOS_ERR_READARMCMDSTATUS_INV_OPCODE_PARM ARM opcode is out of range (valid 0-30, even only) + */ +mykonosErr_t MYKONOS_readArmCmdStatusByte(mykonosDevice_t *device, uint8_t opCode, uint8_t *cmdStatByte) +{ + uint8_t cmdByteIndex = 0; + uint8_t cmdByte = 0; + +#if 0 +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_readArmCmdStatByte()\n"); +#endif +#endif + + if (cmdStatByte == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READARMCMDSTATUSBYTE_NULL_PARM, + getMykonosErrorMessage(MYKONOS_ERR_READARMCMDSTATUSBYTE_NULL_PARM)); + return MYKONOS_ERR_READARMCMDSTATUSBYTE_NULL_PARM; + } + + /* check for even-numbered opCodes only including opcode 0, but not must be greater than opCode 30 */ + if ((opCode != 0) && ((opCode % 2) || (opCode > 30))) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READARMCMDSTATUS_INV_OPCODE_PARM, + getMykonosErrorMessage(MYKONOS_ERR_READARMCMDSTATUS_INV_OPCODE_PARM)); + return MYKONOS_ERR_READARMCMDSTATUS_INV_OPCODE_PARM; + } + else + { + cmdByteIndex = (opCode / 4); + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_ARM_CMD_STATUS_0 + cmdByteIndex, &cmdByte); + + if ((opCode / 2) % 2) + { + *cmdStatByte = ((cmdByte >> 4) & 0x0F); + } + else + { + *cmdStatByte = (cmdByte & 0x0F); + } + + return MYKONOS_ERR_OK; + } +} + +/** + * \brief Mykonos ARM command status wait function polls command status until opcode completes + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param opCode Valid values are even increments from 0-30. The ARM opCode is used to determine which pending bit to wait for + * \param timeoutMs conveys the time-out period in milliseconds + * \param cmdStatByte returns cmdStatByte[3:1] = error type, cmdStatByte[0] = pending flag for selected opCode + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_ARMCMDSTATUS_NULL_PARM Function parameter cmdStatByte has NULL pointer + * \retval MYKONOS_ERR_ARMCMDSTATUS_INV_OPCODE_PARM Invalid ARM opcode (valid 0-30, even numbers only) + * \retval MYKONOS_ERR_ARMCMDSTATUS_ARMERROR ARM Mailbox error flag for requested opcode returned a nonzero error flag + * \retval MYKONOS_ERR_WAITARMCMDSTATUS_TIMEOUT Timeout occurred before ARM command completed + */ +mykonosErr_t MYKONOS_waitArmCmdStatus(mykonosDevice_t *device, uint8_t opCode, uint32_t timeoutMs, uint8_t *cmdStatByte) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_waitArmCmdStatus()\n"); +#endif + + if (cmdStatByte == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ARMCMDSTATUS_NULL_PARM, + getMykonosErrorMessage(MYKONOS_ERR_ARMCMDSTATUS_NULL_PARM)); + return MYKONOS_ERR_ARMCMDSTATUS_NULL_PARM; + } + + /* check for even-numbered opCodes only including opcode 0, but not must be greater than opCode 30 */ + if ((opCode != 0) && ((opCode % 2) || (opCode > 30))) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ARMCMDSTATUS_INV_OPCODE_PARM, + getMykonosErrorMessage(MYKONOS_ERR_ARMCMDSTATUS_INV_OPCODE_PARM)); + return MYKONOS_ERR_ARMCMDSTATUS_INV_OPCODE_PARM; + } + + /* start wait */ + CMB_setTimeout_ms(timeoutMs); + + do + { + retVal = MYKONOS_readArmCmdStatusByte(device, opCode, cmdStatByte); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* If error flag is non zero in [3:1], - return error */ + if ((*cmdStatByte & 0x0E) > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_ARMCMDSTATUS_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_ARMCMDSTATUS_ARMERROR)); + return MYKONOS_ERR_ARMCMDSTATUS_ARMERROR; + } + + if (CMB_hasTimeoutExpired()) + { + return MYKONOS_ERR_WAITARMCMDSTATUS_TIMEOUT; + } + } while (*cmdStatByte & 0x01); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Mykonos ARM configuration write + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_writeArmProfile(mykonosDevice_t *device) +{ + const uint8_t length = 100; + + int32_t i = 0; + uint8_t vcoDiv = 0; + uint8_t hsDiv = 0; + uint16_t channelsEnabled = 0; + uint8_t cfgData[100] = {0}; + + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_writeArmConfig()\n"); +#endif + + /* reading in required mykonosDevice_t structure data into array - not pretty but it works */ + for (i = 0; i < 4; i++) + { + cfgData[i] = (uint8_t)(((device->clocks->deviceClock_kHz * 1000) >> (i * 8)) & 0x000000FF); + } + + for (i = 4; i < 8; i++) + { + cfgData[i] = (uint8_t)(((device->clocks->clkPllVcoFreq_kHz) >> ((i - 4) * 8)) & 0x000000FF); + } + + vcoDiv = (uint8_t)(device->clocks->clkPllVcoDiv); + hsDiv = device->clocks->clkPllHsDiv; + + cfgData[8] = vcoDiv; /* uint8_t vco_div */ + cfgData[9] = hsDiv; /* uint8_t hs_div */ + + channelsEnabled |= ((uint16_t)device->tx->txChannels & 0x03); + channelsEnabled |= ((uint16_t)device->rx->rxChannels & 0x03) << 2; + if (device->profilesValid & ORX_PROFILE_VALID) + { + channelsEnabled |= (((uint16_t)device->obsRx->obsRxChannelsEnable & 3) << 4); + } + + if (device->profilesValid & SNIFF_PROFILE_VALID) + { + channelsEnabled |= ((((uint16_t)device->obsRx->obsRxChannelsEnable >> 2) & 7) << 6); + } + + for (i = 10; i < 12; i++) + { + cfgData[i] = (uint8_t)((channelsEnabled >> ((i - 10) * 8)) & 0xFF); + } + + cfgData[12] = ((device->rx->rxPllUseExternalLo & 0x01) << 1) | (device->tx->txPllUseExternalLo & 0x01); + cfgData[13] = 0x00; /* Not used...padding */ + cfgData[14] = 0x00; /* Not used...padding */ + cfgData[15] = 0x00; /* Not used...padding */ + + if (device->profilesValid & TX_PROFILE_VALID) + { + /* start of Tx profile data */ + cfgData[16] = (uint8_t)device->tx->txProfile->dacDiv; + cfgData[17] = device->tx->txProfile->txFirInterpolation; + cfgData[18] = device->tx->txProfile->thb1Interpolation; + cfgData[19] = device->tx->txProfile->thb2Interpolation; + + for (i = 20; i < 24; i++) + { + cfgData[i] = (uint8_t)(((device->tx->txProfile->iqRate_kHz * 1000) >> ((i - 20) * 8)) & 0x000000FF); + } + + for (i = 24; i < 28; i++) + { + cfgData[i] = (uint8_t)(((device->tx->txProfile->primarySigBandwidth_Hz) >> ((i - 24) * 8)) & 0x000000FF); + } + + for (i = 28; i < 32; i++) + { + cfgData[i] = (uint8_t)(((device->tx->txProfile->rfBandwidth_Hz) >> ((i - 28) * 8)) & 0x000000FF); + } + + for (i = 32; i < 36; i++) + { + cfgData[i] = (uint8_t)(((device->tx->txProfile->txDac3dBCorner_kHz) >> ((i - 32) * 8)) & 0x000000FF); + } + + for (i = 36; i < 40; i++) + { + cfgData[i] = (uint8_t)(((device->tx->txProfile->txBbf3dBCorner_kHz * 1000) >> ((i - 36) * 8)) & 0x000000FF); + } + } + else + { + cfgData[16] = 0; + cfgData[17] = 0; + cfgData[18] = 0; + cfgData[19] = 0; + cfgData[20] = 0; + cfgData[21] = 0; + cfgData[22] = 0; + cfgData[23] = 0; + cfgData[24] = 0; + cfgData[25] = 0; + cfgData[26] = 0; + cfgData[27] = 0; + cfgData[28] = 0; + cfgData[29] = 0; + cfgData[30] = 0; + cfgData[31] = 0; + cfgData[32] = 0; + cfgData[33] = 0; + cfgData[34] = 0; + cfgData[35] = 0; + cfgData[36] = 0; + cfgData[37] = 0; + cfgData[38] = 0; + cfgData[39] = 0; + } + + if (device->profilesValid & RX_PROFILE_VALID) + { + /* start of Rx profile data */ + cfgData[40] = device->rx->rxProfile->adcDiv; + cfgData[41] = device->rx->rxProfile->rxFirDecimation; + cfgData[42] = device->rx->rxProfile->rxDec5Decimation; + cfgData[43] = device->rx->rxProfile->rhb1Decimation; + + for (i = 44; i < 48; i++) + { + cfgData[i] = (uint8_t)(((device->rx->rxProfile->iqRate_kHz * 1000) >> ((i - 44) * 8)) & 0x000000FF); + } + + for (i = 48; i < 52; i++) + { + /* sig bw placeholder */ + cfgData[i] = (uint8_t)(((device->rx->rxProfile->rfBandwidth_Hz) >> ((i - 48) * 8)) & 0x000000FF); + } + + for (i = 52; i < 56; i++) + { + cfgData[i] = (uint8_t)(((device->rx->rxProfile->rfBandwidth_Hz) >> ((i - 52) * 8)) & 0x000000FF); + } + + for (i = 56; i < 60; i++) + { + cfgData[i] = (uint8_t)(((device->rx->rxProfile->rxBbf3dBCorner_kHz * 1000) >> ((i - 56) * 8)) & 0x000000FF); + } + } + else + { + cfgData[40] = 0; + cfgData[41] = 0; + cfgData[42] = 0; + cfgData[43] = 0; + cfgData[44] = 0; + cfgData[45] = 0; + cfgData[46] = 0; + cfgData[47] = 0; + cfgData[48] = 0; + cfgData[49] = 0; + cfgData[50] = 0; + cfgData[51] = 0; + cfgData[52] = 0; + cfgData[53] = 0; + cfgData[54] = 0; + cfgData[55] = 0; + cfgData[56] = 0; + cfgData[57] = 0; + cfgData[58] = 0; + cfgData[59] = 0; + } + + if (device->profilesValid & ORX_PROFILE_VALID) + { + /* start of ObsRx profile data */ + cfgData[60] = device->obsRx->orxProfile->adcDiv; + cfgData[61] = device->obsRx->orxProfile->rxFirDecimation; + cfgData[62] = device->obsRx->orxProfile->rxDec5Decimation; + cfgData[63] = device->obsRx->orxProfile->rhb1Decimation; + + for (i = 64; i < 68; i++) + { + cfgData[i] = (uint8_t)(((device->obsRx->orxProfile->iqRate_kHz * 1000) >> ((i - 64) * 8)) & 0x000000FF); + } + + for (i = 68; i < 72; i++) + { + /* sig bw placeholder */ + cfgData[i] = (uint8_t)(((device->obsRx->orxProfile->rfBandwidth_Hz) >> ((i - 68) * 8)) & 0x000000FF); + } + + for (i = 72; i < 76; i++) + { + cfgData[i] = (uint8_t)(((device->obsRx->orxProfile->rfBandwidth_Hz) >> ((i - 72) * 8)) & 0x000000FF); + } + + for (i = 76; i < 80; i++) + { + cfgData[i] = (uint8_t)(((device->obsRx->orxProfile->rxBbf3dBCorner_kHz * 1000) >> ((i - 76) * 8)) & 0x000000FF); + } + } + else + { + cfgData[60] = 0; + cfgData[61] = 0; + cfgData[62] = 0; + cfgData[63] = 0; + cfgData[64] = 0; + cfgData[65] = 0; + cfgData[66] = 0; + cfgData[67] = 0; + cfgData[68] = 0; + cfgData[69] = 0; + cfgData[70] = 0; + cfgData[71] = 0; + cfgData[72] = 0; + cfgData[73] = 0; + cfgData[74] = 0; + cfgData[75] = 0; + cfgData[76] = 0; + cfgData[77] = 0; + cfgData[78] = 0; + cfgData[79] = 0; + } + + if (device->profilesValid & SNIFF_PROFILE_VALID) + { + /* start of SnRx profile data */ + cfgData[80] = device->obsRx->snifferProfile->adcDiv; + cfgData[81] = device->obsRx->snifferProfile->rxFirDecimation; + cfgData[82] = device->obsRx->snifferProfile->rxDec5Decimation; + cfgData[83] = device->obsRx->snifferProfile->rhb1Decimation; + + for (i = 84; i < 88; i++) + { + cfgData[i] = (uint8_t)(((device->obsRx->snifferProfile->iqRate_kHz * 1000) >> ((i - 84) * 8)) & 0x000000FF); + } + + for (i = 88; i < 92; i++) + { + /* sig bw placeholder */ + cfgData[i] = (uint8_t)(((device->obsRx->snifferProfile->rfBandwidth_Hz) >> ((i - 88) * 8)) & 0x000000FF); + } + + for (i = 92; i < 96; i++) + { + cfgData[i] = (uint8_t)(((device->obsRx->snifferProfile->rfBandwidth_Hz) >> ((i - 92) * 8)) & 0x000000FF); + } + + for (i = 96; i < 100; i++) + { + cfgData[i] = (uint8_t)(((device->obsRx->snifferProfile->rxBbf3dBCorner_kHz * 1000) >> ((i - 96) * 8)) & 0x000000FF); + } + } + else + { + cfgData[80] = 0; + cfgData[81] = 0; + cfgData[82] = 0; + cfgData[83] = 0; + cfgData[84] = 0; + cfgData[85] = 0; + cfgData[86] = 0; + cfgData[87] = 0; + cfgData[88] = 0; + cfgData[89] = 0; + cfgData[90] = 0; + cfgData[91] = 0; + cfgData[92] = 0; + cfgData[93] = 0; + cfgData[94] = 0; + cfgData[95] = 0; + cfgData[96] = 0; + cfgData[97] = 0; + cfgData[98] = 0; + cfgData[99] = 0; + } + + /* writing to the ARM memory with the array data */ + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &cfgData[0], length); + + return retVal; +} + +/** + * \brief Function called automatically that loads the ADC profiles into the ARM + * + * User should not need to call this function normally. It is called automatically + * during MYKONOS_initArm() to load the ADC profiles (tunes the ADC performance). + * + * Rx ADC profile is only loaded if the Rx Profile is valid, ORx ADC profile is + * only loaded if the ORx Profile is valid. Sniffer ADC profile is only loaded + * if the Sniffer profile is valid. The Loopback ADC profile is always + * loaded. If Tx profile is valid, the loopback ADC profile is chosen based + * on the Tx Primary Signal bandwidth. If no valid Tx Profile, the Rx profile + * is used to set the Loopback ADC profile. Else, ORx, then sniffer profiles + * are used to set the loopback ADC profile. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_LOAD_ADCPROFILE_INV_VCODIV Mykonos CLKPLL has invalid VCO divider in the clocks structure + * \retval MYKONOS_ERR_LOAD_ADCPROFILE_MISSING_ORX_PROFILE When Tx Profile used, a matching ORx Profile must be provided with a valid ADC divider. + * The ORx digital filters and clock dividers are used with the Loopback Rx path for Tx calibrations. + * \retval MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_RXREQUIRED ADC Profile Lookup table does not have a match + * for current Rx Profile settings. Custom ADC profile required + * \retval MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_ORXREQUIRED ADC Profile Lookup table does not have a match + * for current ORx Profile settings. Custom ADC profile required + * \retval MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_SNRXREQUIRED ADC Profile Lookup table does not have a match + * for current Sniffer Rx Profile settings. Custom ADC profile required + * \retval MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_LBREQUIRED ADC Profile Lookup table does not have a match + * for Loopback passband BW and ADC Clock frequency settings. Custom ADC profile required + * \retval MYKONOS_ERR_LOAD_ADCPROFILE_RXADCDIV_ZERO Rx Profile has invalid ADC divider = 0, causing a divide by zero error + * \retval MYKONOS_ERR_LOAD_ADCPROFILE_ORXADCDIV_ZERO ORx profile has invalid ADC divider = 0, causing a divide by zero error + * \retval MYKONOS_ERR_LOAD_ADCPROFILE_SNRX_ADCDIV_ZERO Sniffer profile has invalid ADC divider = 0, causing a divide by zero error + * \retval MYKONOS_ERR_LOAD_RXADCPROFILE_ARMMEM_FAILED Error returned while trying to write Rx ADC profile to ARM memory + * \retval MYKONOS_ERR_LOAD_ORXADCPROFILE_ARMMEM_FAILED Error returned while trying to write ORx ADC profile to ARM memory + * \retval MYKONOS_ERR_LOAD_SNRXADCPROFILE_ARMMEM_FAILED Error returned while trying to write Sniffer ADC profile into ARM memory + * \retval MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED Error returned while trying to write Loopback ADC profile into ARM memory + */ +mykonosErr_t MYKONOS_loadAdcProfiles(mykonosDevice_t *device) +{ + uint8_t adcProfile[32] = {0}; + uint8_t i = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint32_t hsDigClk_MHz = 0; + uint32_t adcClk_MHz = 0; + uint32_t vcoDiv = 0; + uint32_t vcoDivTimes10 = 10; + uint8_t profileIndex = 0; + const uint8_t ARM_CONFIG_OFFSET = 100; /* number of bytes written in MYKONOS_writeArmProfile() to ARM memory */ + + const uint8_t NUM_ADCPROFILE_COEFS = 16; + const uint8_t NUM_ADC_PROFILES = 20; + static const uint16_t adcProfileLut[20][18] = { + /* Max RFBW, ADCCLK_MHz, adcProfile[16] */ + { 20, 491, 1494, 564, 201, 98, 1280, 134, 945, 40, 529, 10, 326, 39, 30, 16, 9, 201}, + { 60, 983, 712, 462, 201, 98, 1280, 291, 1541, 149, 1054, 46, 645, 34, 48, 32, 18, 193}, + { 75, 983, 680, 477, 201, 98, 1280, 438, 1577, 242, 1046, 73, 636, 30, 48, 31, 18, 192}, + {100, 983, 655, 446, 201, 98, 1280, 336, 1631, 334, 1152, 207, 733, 33, 48, 32, 21, 212}, + { 75, 1228, 569, 369, 201, 98, 1280, 291, 1541, 149, 1320, 58, 807, 34, 48, 40, 23, 189}, + {100, 1228, 534, 386, 201, 98, 1280, 491, 1591, 279, 1306, 104, 792, 28, 48, 39, 23, 187}, + {160, 1228, 491, 375, 201, 98, 1280, 514, 1728, 570, 1455, 443, 882, 27, 48, 39, 25, 205}, + {200, 1228, 450, 349, 201, 98, 1280, 730, 1626, 818, 1476, 732, 834, 20, 41, 36, 24, 200}, + { 80, 1250, 555, 365, 201, 98, 1280, 317, 1547, 165, 1341, 65, 819, 33, 48, 40, 24, 188}, + {102, 1250, 524, 379, 201, 98, 1280, 494, 1592, 281, 1328, 107, 805, 28, 48, 40, 23, 187}, + { 80, 1333, 526, 339, 201, 98, 1280, 281, 1539, 143, 1433, 60, 877, 35, 48, 43, 25, 188}, + {217, 1333, 414, 321, 201, 98, 1280, 730, 1626, 818, 1603, 794, 905, 20, 41, 40, 26, 199}, + { 75, 1474, 486, 302, 199, 98, 1280, 206, 1523, 101, 1578, 47, 977, 37, 48, 48, 28, 186}, + {100, 1474, 465, 311, 201, 98, 1280, 353, 1556, 187, 1581, 86, 964, 32, 48, 47, 28, 185}, + {150, 1474, 436, 296, 190, 98, 1280, 336, 1631, 334, 1638, 293, 1102, 33, 48, 46, 31, 205}, + { 40, 1536, 479, 285, 190, 98, 1280, 112, 1505, 53, 1574, 25, 1026, 40, 48, 48, 29, 186}, + {100, 1536, 450, 297, 193, 98, 1280, 328, 1550, 171, 1586, 79, 1006, 33, 48, 48, 29, 184}, + {150, 1536, 421, 283, 182, 98, 1280, 313, 1620, 306, 1638, 269, 1153, 34, 48, 46, 33, 204}, + {200, 1536, 392, 299, 180, 98, 1280, 514, 1728, 570, 1638, 498, 1104, 27, 48, 44, 32, 200}, + {240, 1536, 366, 301, 178, 98, 1280, 686, 1755, 818, 1638, 742, 1056, 22, 45, 41, 31, 196}}; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_loadAdcProfiles\n"); +#endif + + vcoDiv = (uint32_t)device->clocks->clkPllVcoDiv; + switch (vcoDiv) + { + case VCODIV_1: + vcoDivTimes10 = 10; + break; + case VCODIV_1p5: + vcoDivTimes10 = 15; + break; + case VCODIV_2: + vcoDivTimes10 = 20; + break; + case VCODIV_3: + vcoDivTimes10 = 30; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_ADCPROFILE_INV_VCODIV, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_ADCPROFILE_INV_VCODIV)); + return MYKONOS_ERR_LOAD_ADCPROFILE_INV_VCODIV; + } + } + + hsDigClk_MHz = device->clocks->clkPllVcoFreq_kHz / vcoDivTimes10 / 100 / device->clocks->clkPllHsDiv; + + /* If Tx Profile is valid, set loopback ADC profile based on Tx primary signal BW */ + if ((device->profilesValid & TX_PROFILE_VALID) > 0) + { + /* If custom profile, load it */ + if (device->obsRx->customLoopbackAdcProfile != NULL) + { + for (i = 0; i < NUM_ADCPROFILE_COEFS; i++) + { + adcProfile[i * 2] = device->obsRx->customLoopbackAdcProfile[i] & 0xFF; + adcProfile[i * 2 + 1] = (device->obsRx->customLoopbackAdcProfile[i] >> 8) & 0xFF; + } + } + else + { + /* Tx requires ORx profile is configured */ + if (((device->profilesValid & TX_PROFILE_VALID) > 0) && ((device->profilesValid & ORX_PROFILE_VALID) == 0)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_ADCPROFILE_MISSING_ORX_PROFILE, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_ADCPROFILE_MISSING_ORX_PROFILE)); + return MYKONOS_ERR_LOAD_ADCPROFILE_MISSING_ORX_PROFILE; + } + + if (device->obsRx->orxProfile->adcDiv == 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_ADCPROFILE_ORXADCDIV_ZERO, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_ADCPROFILE_ORXADCDIV_ZERO)); + return MYKONOS_ERR_LOAD_ADCPROFILE_ORXADCDIV_ZERO; + } + + adcClk_MHz = hsDigClk_MHz / device->obsRx->orxProfile->adcDiv; + + /* find correct ADC profile in the LUT */ + profileIndex = NUM_ADC_PROFILES; + for (i = 0; i < NUM_ADC_PROFILES; i++) + { + /* Find a row in the LUT that matches the ADC clock frequency */ + if ((adcProfileLut[i][1] == adcClk_MHz) && (adcProfileLut[i][0] >= (device->tx->txProfile->primarySigBandwidth_Hz / 1000000))) + { + profileIndex = i; + break; + } + } + + /* Verify that a profile was found in the LUT, if not return error */ + /* In this case a custom profile would need to be passed in */ + if (profileIndex >= NUM_ADC_PROFILES) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_LBREQUIRED, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_LBREQUIRED)); + return MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_LBREQUIRED; + } + + for (i = 0; i < NUM_ADCPROFILE_COEFS; i++) + { + adcProfile[i * 2] = adcProfileLut[profileIndex][i + 2] & 0xFF; + adcProfile[i * 2 + 1] = (adcProfileLut[profileIndex][i + 2] >> 8) & 0xFF; + } + } + + /* writing to the ARM memory: Set Loopback ADC Profile based on Tx Primary signal Bandwidth */ + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR + ARM_CONFIG_OFFSET + 96, &adcProfile[0], sizeof(adcProfile)); + if (retVal) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED)); + return MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED; + } + } + + if ((device->profilesValid & RX_PROFILE_VALID) > 0) + { + /* If custom profile, load it */ + if (device->rx->rxProfile->customAdcProfile != NULL) + { + for (i = 0; i < NUM_ADCPROFILE_COEFS; i++) + { + adcProfile[i * 2] = device->rx->rxProfile->customAdcProfile[i] & 0xFF; + adcProfile[i * 2 + 1] = (device->rx->rxProfile->customAdcProfile[i] >> 8) & 0xFF; + } + } + else + { + if (device->rx->rxProfile->adcDiv == 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_ADCPROFILE_RXADCDIV_ZERO, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_ADCPROFILE_RXADCDIV_ZERO)); + return MYKONOS_ERR_LOAD_ADCPROFILE_RXADCDIV_ZERO; + } + + adcClk_MHz = hsDigClk_MHz / device->rx->rxProfile->adcDiv; + + /* find correct ADC profile in the LUT */ + profileIndex = NUM_ADC_PROFILES; + for (i = 0; i < NUM_ADC_PROFILES; i++) + { + /* Find a row in the LUT that matches the ADC clock frequency */ + if ((adcProfileLut[i][1] == adcClk_MHz) && (adcProfileLut[i][0] >= (device->rx->rxProfile->rfBandwidth_Hz / 1000000))) + { + profileIndex = i; + break; + } + } + + /* Verify that a profile was found in the LUT, if not return error */ + /* In this case a custom profile would need to be passed in */ + if (profileIndex >= NUM_ADC_PROFILES) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_RXREQUIRED, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_RXREQUIRED)); + return MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_RXREQUIRED; + } + + for (i = 0; i < NUM_ADCPROFILE_COEFS; i++) + { + adcProfile[i * 2] = adcProfileLut[profileIndex][i + 2] & 0xFF; + adcProfile[i * 2 + 1] = (adcProfileLut[profileIndex][i + 2] >> 8) & 0xFF; + } + } + + /* writing to the ARM memory with ADC Profile for Rx path */ + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR + ARM_CONFIG_OFFSET, &adcProfile[0], sizeof(adcProfile)); + if (retVal) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_RXADCPROFILE_ARMMEM_FAILED, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_RXADCPROFILE_ARMMEM_FAILED)); + return MYKONOS_ERR_LOAD_RXADCPROFILE_ARMMEM_FAILED; + } + + /* writing to the ARM memory: Set Loopback ADC Profile = Rx ADC Profile ONLY if Tx profile is not valid */ + if ((device->profilesValid & TX_PROFILE_VALID) == 0) + { + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR + ARM_CONFIG_OFFSET + 96, &adcProfile[0], sizeof(adcProfile)); + if (retVal) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED)); + return MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED; + } + } + } + + if ((device->profilesValid & ORX_PROFILE_VALID) > 0) + { + /* If custom profile, load it */ + if (device->obsRx->orxProfile->customAdcProfile != NULL) + { + for (i = 0; i < NUM_ADCPROFILE_COEFS; i++) + { + adcProfile[i * 2] = device->obsRx->orxProfile->customAdcProfile[i] & 0xFF; + adcProfile[i * 2 + 1] = (device->obsRx->orxProfile->customAdcProfile[i] >> 8) & 0xFF; + } + } + else + { + if (device->obsRx->orxProfile->adcDiv == 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_ADCPROFILE_ORXADCDIV_ZERO, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_ADCPROFILE_ORXADCDIV_ZERO)); + return MYKONOS_ERR_LOAD_ADCPROFILE_ORXADCDIV_ZERO; + } + + adcClk_MHz = hsDigClk_MHz / device->obsRx->orxProfile->adcDiv; + + /* find correct ADC profile in the LUT */ + profileIndex = NUM_ADC_PROFILES; + for (i = 0; i < NUM_ADC_PROFILES; i++) + { + /* Find a row in the LUT that matches the ADC clock frequency */ + if ((adcProfileLut[i][1] == adcClk_MHz) && (adcProfileLut[i][0] >= (device->obsRx->orxProfile->rfBandwidth_Hz / 1000000))) + { + profileIndex = i; + break; + } + } + + /* Verify that a profile was found in the LUT, if not return error */ + /* In this case a custom profile would need to be passed in */ + if (profileIndex >= NUM_ADC_PROFILES) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_ORXREQUIRED, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_ORXREQUIRED)); + return MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_ORXREQUIRED; + } + + for (i = 0; i < NUM_ADCPROFILE_COEFS; i++) + { + adcProfile[i * 2] = adcProfileLut[profileIndex][i + 2] & 0xFF; + adcProfile[i * 2 + 1] = (adcProfileLut[profileIndex][i + 2] >> 8) & 0xFF; + } + } + + /* writing to the ARM memory with ADC Profile for ORx path */ + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR + ARM_CONFIG_OFFSET + 32, &adcProfile[0], sizeof(adcProfile)); + if (retVal) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_ORXADCPROFILE_ARMMEM_FAILED, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_ORXADCPROFILE_ARMMEM_FAILED)); + return MYKONOS_ERR_LOAD_ORXADCPROFILE_ARMMEM_FAILED; + } + + /* If Rx and Tx Profiles are not valid, set Loopback ADC profile to ORx ADC Profile */ + if (((device->profilesValid & TX_PROFILE_VALID) == 0) && ((device->profilesValid & RX_PROFILE_VALID) == 0)) + { + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR + ARM_CONFIG_OFFSET + 96, &adcProfile[0], sizeof(adcProfile)); + if (retVal) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED)); + return MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED; + } + } + } + + if ((device->profilesValid & SNIFF_PROFILE_VALID) > 0) + { + /* If custom profile, load it */ + if (device->obsRx->snifferProfile->customAdcProfile != NULL) + { + for (i = 0; i < NUM_ADCPROFILE_COEFS; i++) + { + adcProfile[i * 2] = device->obsRx->snifferProfile->customAdcProfile[i] & 0xFF; + adcProfile[i * 2 + 1] = (device->obsRx->snifferProfile->customAdcProfile[i] >> 8) & 0xFF; + } + } + else + { + + if (device->obsRx->snifferProfile->adcDiv == 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_ADCPROFILE_SNRX_ADCDIV_ZERO, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_ADCPROFILE_SNRX_ADCDIV_ZERO)); + return MYKONOS_ERR_LOAD_ADCPROFILE_SNRX_ADCDIV_ZERO; + } + + adcClk_MHz = hsDigClk_MHz / device->obsRx->snifferProfile->adcDiv; + + /* find correct ADC profile in the LUT */ + profileIndex = NUM_ADC_PROFILES; + for (i = 0; i < NUM_ADC_PROFILES; i++) + { + /* Find a row in the LUT that matches the ADC clock frequency */ + if ((adcProfileLut[i][1] == adcClk_MHz) && (adcProfileLut[i][0] >= (device->obsRx->snifferProfile->rfBandwidth_Hz / 1000000))) + { + profileIndex = i; + break; + } + } + + /* Verify that a profile was found in the LUT, if not return error */ + /* In this case a custom profile would need to be passed in */ + if (profileIndex >= NUM_ADC_PROFILES) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_SNRXREQUIRED, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_SNRXREQUIRED)); + return MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_SNRXREQUIRED; + } + + for (i = 0; i < NUM_ADCPROFILE_COEFS; i++) + { + adcProfile[i * 2] = adcProfileLut[profileIndex][i + 2] & 0xFF; + adcProfile[i * 2 + 1] = (adcProfileLut[profileIndex][i + 2] >> 8) & 0xFF; + } + } + + /* writing to the ARM memory with ADC Profile for sniffer Rx path */ + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR + ARM_CONFIG_OFFSET + 64, &adcProfile[0], sizeof(adcProfile)); + if (retVal) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_SNRXADCPROFILE_ARMMEM_FAILED, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_SNRXADCPROFILE_ARMMEM_FAILED)); + return MYKONOS_ERR_LOAD_SNRXADCPROFILE_ARMMEM_FAILED; + } + + /* If Tx, Rx, and ORx Profiles are not valid, set Loopback ADC profile to Sniffer Rx ADC Profile */ + if (((device->profilesValid & TX_PROFILE_VALID) == 0) && ((device->profilesValid & RX_PROFILE_VALID) == 0) && ((device->profilesValid & ORX_PROFILE_VALID) == 0)) + { + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR + ARM_CONFIG_OFFSET + 96, &adcProfile[0], sizeof(adcProfile)); + if (retVal) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED, + getMykonosErrorMessage(MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED)); + return MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED; + } + } + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Helper function to calculate commonly used digital clock frequencies in the device + * + * User should not need to call this function normally. It is called automatically + * within other API functions to calculate the main digital clock. If the pointers + * to the return parameters are NULL, that calculation will be skipped and not + * returned. + * + * + * Dependencies + * -device->clocks->clkPllVcoFreq_kHz; + * -device->clocks->clkPllVcoDiv; + * -device->clocks->clkPllHsDiv; + * + * \param device Pointer to the device settings structure + * \param hsDigClk_kHz Return value for the calculated Mykonos high speed Digital clock at the output of the CLKPLL in kHz + * \param hsDigClkDiv4or5_kHz Return value for the Mykonos high speed digital clock divided by 4 or 5 in kHz + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_CALCDIGCLK_NULLDEV_PARAM device parameter is a NULL pointer + * \retval MYKONOS_ERR_CALCDIGCLK_NULL_CLKSTRUCT device->clocks structure is a NULL pointer + * \retval MYKONOS_ERR_CLKPLL_INV_VCODIV Invalid CLKPLL VCO divider in device->clocks->clkPllVcoDiv + * \retval MYKONOS_ERR_CLKPLL_INV_HSDIV Invalid CLKPLL High speed divider in device->clocks->clkPllHsDiv + */ +static mykonosErr_t MYKONOS_calculateDigitalClocks(mykonosDevice_t *device, uint32_t *hsDigClk_kHz, uint32_t *hsDigClkDiv4or5_kHz) +{ + uint32_t hsclkRate_kHz = 0; + uint32_t clkPllVcoFrequency_kHz = 0; + mykonosVcoDiv_t vcoDiv = VCODIV_1; + uint8_t hsDiv = 4; + + if (device == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, 0, MYKONOS_ERR_CALCDIGCLK_NULLDEV_PARAM, getMykonosErrorMessage(MYKONOS_ERR_CALCDIGCLK_NULLDEV_PARAM)); + return MYKONOS_ERR_CALCDIGCLK_NULLDEV_PARAM; + } + + if ((device->clocks == NULL)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CALCDIGCLK_NULL_CLKSTRUCT, + getMykonosErrorMessage(MYKONOS_ERR_CALCDIGCLK_NULL_CLKSTRUCT)); + return MYKONOS_ERR_CALCDIGCLK_NULL_CLKSTRUCT; + } + + clkPllVcoFrequency_kHz = device->clocks->clkPllVcoFreq_kHz; + vcoDiv = device->clocks->clkPllVcoDiv; + hsDiv = device->clocks->clkPllHsDiv; + + switch (vcoDiv) + { + case VCODIV_1: + hsclkRate_kHz = clkPllVcoFrequency_kHz; + break; + case VCODIV_1p5: + hsclkRate_kHz = (clkPllVcoFrequency_kHz / 15) * 10; + break; + case VCODIV_2: + hsclkRate_kHz = clkPllVcoFrequency_kHz >> 1; + break; + case VCODIV_3: + hsclkRate_kHz = (clkPllVcoFrequency_kHz / 30) * 10; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CLKPLL_INV_VCODIV, getMykonosErrorMessage(MYKONOS_ERR_CLKPLL_INV_VCODIV)); + return MYKONOS_ERR_CLKPLL_INV_VCODIV; + } + } + + switch (hsDiv) + { + case 4: + hsDiv = 4; + break; + case 5: + hsDiv = 5; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CLKPLL_INV_HSDIV, getMykonosErrorMessage(MYKONOS_ERR_CLKPLL_INV_HSDIV)); + return MYKONOS_ERR_CLKPLL_INV_HSDIV; + } + } + + if (hsDigClk_kHz != NULL) + { + *hsDigClk_kHz = hsclkRate_kHz / hsDiv; + } + + if (hsDigClkDiv4or5_kHz != NULL) + { + /* This digital div 4 or 5 is always mutually exclusive with the HS Divider (4 or 5) to always + * create a /20 from the hsclk. + */ + *hsDigClkDiv4or5_kHz = hsclkRate_kHz / 20; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Performs reset to the External Tx LO Leakage tracking calibration channel estimate + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param channelSel Enum selects the channel to reset + * + * \retval MYKONOS_ERR_RESET_TXLOL_INV_PARAM Selected channel is not valid + * \retval MYKONOS_ERR_RESET_TXLOL_ARMERROR ARM error + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_resetExtTxLolChannel(mykonosDevice_t *device, mykonosTxChannels_t channelSel) +{ + const uint8_t TXLOL_RESET_CHANNEL_ESTIMATE = 0x01; + const uint32_t GETTXLOLSTATUS_TIMEOUT_MS = 1000; + + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t extData[3] = {MYKONOS_ARM_OBJECTID_GS_TRACKCALS, TXLOL_RESET_CHANNEL_ESTIMATE, 0}; + uint8_t cmdStatusByte = 0; + uint8_t armErrorFlag = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_resetExtTxLolChannel()\n"); +#endif + + /* Check Channel */ + switch (channelSel) + { + case TX1: + extData[2] = 0x01; + break; + case TX2: + extData[2] = 0x02; + break; + case TX1_TX2: + extData[2] = 0x03; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_RESET_TXLOL_INV_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_RESET_TXLOL_INV_PARAM)); + return MYKONOS_ERR_RESET_TXLOL_INV_PARAM; + } + + /* throw error if not in the right state */ + retVal = MYKONOS_checkArmState(device, (MYK_ARM_IDLE | MYK_ARM_RADIO_ON)); + if (retVal) + { + return retVal; + } + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_SET_OPCODE, &extData[0], sizeof(extData)); + if (retVal) + { + return retVal; + } + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_SET_OPCODE, GETTXLOLSTATUS_TIMEOUT_MS, &cmdStatusByte); + + /* Error check WaitArmCmdStatus return */ + armErrorFlag = (cmdStatusByte >> 1); + if (armErrorFlag > 0) + { + return MYKONOS_ERR_RESET_TXLOL_ARMERROR; + } + + return retVal; +} + +/** + * \brief Configures the Radio power up/down control for Rx and Tx paths to be controlled by pins + * (TX1/2_ENABLE, RX1/2_ENABLE, and GPIO pins) or an API function call. + * + * The BBP should not have to call this as it will automatically be setup at the end of the + * MYKONOS_loadArmFromBinary() function call. If the BBP wishes to change the radio power up/down + * control method this function can be called again to change the configuration while + * the ARM is in the radioOff state. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->auxIo->armGpio->useRx2EnablePin + * - device->auxIo->armGpio->useTx2EnablePin + * - device->auxIo->armGpio->txRxPinMode + * - device->auxIo->armGpio->orxPinMode + * + * \param device is a pointer to the device settings structure + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_SET_RADIOCTRL_PINS_ARMERROR ARM returned an error and did not accept the command. + */ +mykonosErr_t MYKONOS_setRadioControlPinMode(mykonosDevice_t *device) +{ + uint8_t extData[4] = {0x81, 0, 0, 4}; /*Object ID 0x81 (radio control structure), offset lsb, offset msb, length*/ + uint8_t armRadioControlStruct[4] = {0}; + uint32_t timeoutMs = 0; + uint8_t cmdStatusByte = 0; + mykonosErr_t retval = MYKONOS_ERR_OK; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setRadioControlPinMode()\n"); +#endif + + /* write ARM radio control structure to enable pin mode/command mode */ + if (device->auxIo->armGpio->useRx2EnablePin > 0) + { + armRadioControlStruct[0] = 0x01; + } + + if (device->auxIo->armGpio->useTx2EnablePin > 0) + { + armRadioControlStruct[1] = 0x01; + } + + if (device->auxIo->armGpio->txRxPinMode > 0) + { + armRadioControlStruct[2] = 0x01; + } + + if (device->auxIo->armGpio->orxPinMode > 0) + { + armRadioControlStruct[3] = 0x01; + } + + retval = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &armRadioControlStruct[0], sizeof(armRadioControlStruct)); + if (retval != MYKONOS_ERR_OK) + { + return retval; + } + + retval = MYKONOS_sendArmCommand(device, MYKONOS_ARM_WRITECFG_OPCODE, &extData[0], sizeof(extData)); + if (retval != MYKONOS_ERR_OK) + { + return retval; + } + + timeoutMs = 1000; + retval = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_WRITECFG_OPCODE, timeoutMs, &cmdStatusByte); + if (retval != MYKONOS_ERR_OK) + { + return retval; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_RADIOCTRL_PINS_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_SET_RADIOCTRL_PINS_ARMERROR)); + return MYKONOS_ERR_SET_RADIOCTRL_PINS_ARMERROR; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Sets the measure count which is the number of samples taken before DC offset correction is applied for the given RF channel. + * This value should be changed after ARM initialization. + * channel can be one of the following ( ::mykonosDcOffsetChannels_t ). + * + * Channel | Channel description + * ------------------------|-------------------------------- + * MYK_DC_OFFSET_RX_CHN | Selects Rx channel + * MYK_DC_OFFSET_ORX_CHN | Selects ORx channel + * MYK_DC_OFFSET_SNF_CHN | Selects Sniffer channel + * + * The total duration 'tCount' is calculated as, + * [tCount = (measureCount * 1024) / IQ data rate of the channel]. + * There is a minimum limit for the value of measureCount, the value passed should satisfy the condition 'tCount > 800us'. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param channel Receive channel to be selected. + * \param measureCount Value to be configured for the selected channel which is the number of samples taken before DC offset correction is applied. + * + * \retval MYKONOS_ERR_DC_OFFSET_INV_CHAN channel passed to the function is invalid, refer mykonosDcOffsetChannels_t enum for valid channels. + * \retval MYKONOS_ERR_SET_RF_DC_OFFSET_INV_MEASURECNT measurement count value passed is invalid + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_SET_RF_DC_OFFSET_MEASURECNT_MIN_LIMIT The measureCount value passed is less than the minimum limit allowed. + */ +mykonosErr_t MYKONOS_setRfDcOffsetCnt(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint16_t measureCount) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint16_t REG_ADDRESS_H = 0; /* Address for Higher byte */ + uint16_t REG_ADDRESS_L = 0; /* Address for Lower byte */ + uint16_t MEASURE_CNT_RANGE = 0xFFFF; /* Mask for measure count range checking */ + + const uint8_t MEASURE_CNT_H = (measureCount & 0xFF00) >> 8; /* Higher byte of the measure count */ + const uint8_t MEASURE_CNT_L = measureCount & 0x00FF; /* Lower byte of the measure count */ + + /* Calculation of Total Duration [ tCount = (measureCount * 0x400) / IQ data rate cycles ] */ + const uint8_t FACTOR = 10; + uint32_t tCount = (measureCount << FACTOR); /* precalculations for Total duration in us */ + uint32_t IQ_RATE = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setRfDcOffsetCnt()\n"); +#endif + + /* check for channel and update the appropriate register address */ + switch (channel) + { + case MYK_DC_OFFSET_RX_CHN: + REG_ADDRESS_H = MYKONOS_ADDR_RFDC_MEASURE_COUNT_2; + REG_ADDRESS_L = MYKONOS_ADDR_RFDC_MEASURE_COUNT_1; + IQ_RATE = device->rx->rxProfile->iqRate_kHz / 1000; /* IQ Rate to calculate total duration */ + break; + case MYK_DC_OFFSET_ORX_CHN: + REG_ADDRESS_H = MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_2; + REG_ADDRESS_L = MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_1; + IQ_RATE = device->obsRx->orxProfile->iqRate_kHz / 1000; /* IQ Rate to calculate total duration */ + break; + case MYK_DC_OFFSET_SNF_CHN: + REG_ADDRESS_H = MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_2; + REG_ADDRESS_L = MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_1; + /* measureCount for Sniffer should be 10 bit */ + MEASURE_CNT_RANGE= 0x03FF; + IQ_RATE = device->obsRx->snifferProfile->iqRate_kHz / 1000; /* IQ Rate to calculate total duration */ + break; + + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DC_OFFSET_INV_CHAN, + getMykonosErrorMessage(MYKONOS_ERR_DC_OFFSET_INV_CHAN)); + return MYKONOS_ERR_DC_OFFSET_INV_CHAN; + } + + tCount = (tCount / IQ_RATE); /* Calculating total duration in us */ + if (tCount < 800) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_RF_DC_OFFSET_MEASURECNT_MIN_LIMIT, + getMykonosErrorMessage(MYKONOS_ERR_SET_RF_DC_OFFSET_MEASURECNT_MIN_LIMIT)); + return MYKONOS_ERR_SET_RF_DC_OFFSET_MEASURECNT_MIN_LIMIT ; + } + + if ((measureCount < 0x11) || (measureCount & ~MEASURE_CNT_RANGE)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_RF_DC_OFFSET_INV_MEASURECNT, + getMykonosErrorMessage(MYKONOS_ERR_SET_RF_DC_OFFSET_INV_MEASURECNT)); + return MYKONOS_ERR_SET_RF_DC_OFFSET_INV_MEASURECNT ; + } + + CMB_SPIWriteField(device->spiSettings, REG_ADDRESS_H, MEASURE_CNT_H, ((MEASURE_CNT_RANGE >>8) & 0xFF),0); + CMB_SPIWriteByte(device->spiSettings, REG_ADDRESS_L, MEASURE_CNT_L); + + return retVal; +} + +/** + * \brief retrieves the measure count which is the number of samples taken before DC offset correction is applied for the given Rf channel. + * channel can be one of the following ( ::mykonosDcOffsetChannels_t ). + * + * Channel | Channel description + * ------------------------|-------------------------------- + * MYK_DC_OFFSET_RX_CHN | Selects Rx channel + * MYK_DC_OFFSET_ORX_CHN | Selects ORx channel + * MYK_DC_OFFSET_SNF_CHN | Selects Sniffer channel + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param channel receive channel to be selected. + * \param measureCount pointer to the variable to store the read value. + * + * \retval MYKONOS_ERR_DC_OFFSET_INV_CHAN channel passed to the function is invalid, refer mykonosDcOffsetChannels_t enum for valid channels. + * \retval MYKONOS_ERR_SET_RF_DC_OFFSET_NULL_MEASURECNT passed pointer of measureCount is NULL + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getRfDcOffsetCnt(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint16_t *measureCount) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint16_t REG_ADDRESS_H = 0; /* Address for Higher byte */ + uint16_t REG_ADDRESS_L = 0; /* Address for Lower byte */ + uint16_t MEASURE_CNT_RANGE = 0xFFFF; /* Mask for measure count range checking */ + uint16_t mCount = 0; /* Temporary variable to store readback from register. */ + uint8_t readbackData = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getRfDcOffsetCnt()\n"); +#endif + + switch (channel) + { + case MYK_DC_OFFSET_RX_CHN: + REG_ADDRESS_H = MYKONOS_ADDR_RFDC_MEASURE_COUNT_2; + REG_ADDRESS_L = MYKONOS_ADDR_RFDC_MEASURE_COUNT_1; + break; + case MYK_DC_OFFSET_ORX_CHN: + REG_ADDRESS_H = MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_2; + REG_ADDRESS_L = MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_1; + break; + case MYK_DC_OFFSET_SNF_CHN: + REG_ADDRESS_H = MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_2; + REG_ADDRESS_L = MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_1; + /* measureCount for Sniffer should be 10 bit */ + MEASURE_CNT_RANGE= 0x03FF; + break; + + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DC_OFFSET_INV_CHAN, + getMykonosErrorMessage(MYKONOS_ERR_DC_OFFSET_INV_CHAN)); + return MYKONOS_ERR_DC_OFFSET_INV_CHAN; + } + + if (measureCount == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_RF_DC_OFFSET_NULL_MEASURECNT, + getMykonosErrorMessage(MYKONOS_ERR_GET_RF_DC_OFFSET_NULL_MEASURECNT)); + return MYKONOS_ERR_GET_RF_DC_OFFSET_NULL_MEASURECNT; + } + + /* Store Higher byte of measureCount */ + CMB_SPIReadField(device->spiSettings, REG_ADDRESS_H, &readbackData, ((MEASURE_CNT_RANGE >>8) & 0xFF),0); + mCount = readbackData; + mCount = mCount << 8; + + /* Store Lower byte of measureCount */ + readbackData = 0; + CMB_SPIReadByte(device->spiSettings, REG_ADDRESS_L, &readbackData); + mCount = mCount | readbackData; + + *measureCount = mCount; + + return retVal; +} + +/** + * \brief Sets M-Shift value which is the Corner frequency of Rx notch filter for the given channel. + * channel can be one of the following ( ::mykonosDcOffsetChannels_t ). + * + * Channel | Channel description + * ------------------------|-------------------------------- + * MYK_DC_OFFSET_RX_CHN | Selects Rx channel + * MYK_DC_OFFSET_ORX_CHN | Selects ORx channel + * MYK_DC_OFFSET_SNF_CHN | Selects Sniffer channel + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param channel receive channel to be selected. + * \param mShift value to be configured for the given channel + * + * \retval MYKONOS_ERR_DC_OFFSET_INV_CHAN channel passed to the function is invalid, refer mykonosDcOffsetChannels_t enum for valid channels. + * \retval MYKONOS_ERR_SET_DIG_DC_OFFSET_INV_MSHIFT mShift value passed is invalid. + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setDigDcOffsetMShift(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint8_t mShift) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint16_t REG_ADDRESS = 0; + + const uint8_t MSHIFT_MIN_RANGE= 0x08; + const uint8_t MSHIFT_MAX_RANGE= 0x14; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setDigDcOffsetMShift()\n"); +#endif + + if ((mShift < MSHIFT_MIN_RANGE) || (mShift > MSHIFT_MAX_RANGE)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_DIG_DC_OFFSET_INV_MSHIFT, + getMykonosErrorMessage(MYKONOS_ERR_SET_DIG_DC_OFFSET_INV_MSHIFT)); + return MYKONOS_ERR_SET_DIG_DC_OFFSET_INV_MSHIFT; + } + + /* check channel and set the address */ + switch (channel) + { + case MYK_DC_OFFSET_RX_CHN: + REG_ADDRESS = MYKONOS_ADDR_DIGITAL_DC_OFFSET_SHIFT; + break; + case MYK_DC_OFFSET_ORX_CHN: + REG_ADDRESS = MYKONOS_ADDR_DIGITAL_DC_OFFSET_CH3_DPD_M_SHIFT; + break; + case MYK_DC_OFFSET_SNF_CHN: + REG_ADDRESS = MYKONOS_ADDR_DIGITAL_DC_OFFSET_SNF; + break; + + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DC_OFFSET_INV_CHAN, + getMykonosErrorMessage(MYKONOS_ERR_DC_OFFSET_INV_CHAN)); + return MYKONOS_ERR_DC_OFFSET_INV_CHAN; + } + + CMB_SPIWriteField(device->spiSettings, REG_ADDRESS, mShift, 0x1F, 0); + + return retVal; +} + +/** + * \brief retrieves the M-Shift value which is the Corner frequency of Rx notch filter for the given channel. + * channel can be one of the following ( ::mykonosDcOffsetChannels_t ). + * + * Channel | Channel description + * ------------------------|-------------------------------- + * MYK_DC_OFFSET_RX_CHN | Selects Rx channel + * MYK_DC_OFFSET_ORX_CHN | Selects ORx channel + * MYK_DC_OFFSET_SNF_CHN | Selects Sniffer channel + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param channel receive channel to be selected. + * \param mShift Pointer to the variable to store mshift value of the given channel + * + * \retval MYKONOS_ERR_DC_OFFSET_INV_CHAN channel passed to the function is invalid, refer mykonosDcOffsetChannels_t enum for valid channels. + * \retval MYKONOS_ERR_GET_DIG_DC_OFFSET_NULL_MSHIFT mShift pointer is NULL + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getDigDcOffsetMShift(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint8_t *mShift) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint16_t REG_ADDRESS = 0x0; + uint8_t readbackData = 0x0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getDigDcOffsetMShift()\n"); +#endif + + if (mShift == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_DIG_DC_OFFSET_NULL_MSHIFT, + getMykonosErrorMessage(MYKONOS_ERR_GET_DIG_DC_OFFSET_NULL_MSHIFT)); + return MYKONOS_ERR_GET_DIG_DC_OFFSET_NULL_MSHIFT; + } + + /* check for the channel and set the address */ + switch (channel) + { + case MYK_DC_OFFSET_RX_CHN: + REG_ADDRESS = MYKONOS_ADDR_DIGITAL_DC_OFFSET_SHIFT; + break; + case MYK_DC_OFFSET_ORX_CHN: + REG_ADDRESS = MYKONOS_ADDR_DIGITAL_DC_OFFSET_CH3_DPD_M_SHIFT; + break; + case MYK_DC_OFFSET_SNF_CHN: + REG_ADDRESS = MYKONOS_ADDR_DIGITAL_DC_OFFSET_SNF; + break; + + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DC_OFFSET_INV_CHAN, + getMykonosErrorMessage(MYKONOS_ERR_DC_OFFSET_INV_CHAN)); + return MYKONOS_ERR_DC_OFFSET_INV_CHAN; + } + + CMB_SPIReadField(device->spiSettings, REG_ADDRESS, &readbackData, 0x1F,0); + + *mShift = readbackData; + + return retVal; +} + +/** + * \brief Sets the RF PLL loop filter bandwith. + * + * \pre Command should be called in Radio Off state. ARM must be initialized. + * + * \post Loop filter should lock successfully + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->spiSettings + * + * \param device is structure pointer to the MYKONOS data structure containing settings + * \param pllName Name of the PLL to configure.RX_PLL and TX_PLL can be configured.SNIFFER_PLL can not be configured. + * \param loopBandwidth_kHz Desired RF pll bandwith to be set. The valid values range of loopBandwidth_kHz for Rx and Tx is 50 to 750.For SRX valid values lies from 500 to 750. + * \param stability PLL Loop stability to be set.The valid values range of stability is from 3 to 15. + * + * \return MYKONOS_ERR_OK Function completed successfully + * \return MYKONOS_ERR_SETRFPLL_LF_ARMERROR ARM Command to set RF PLL loop filter bandwidth failed + * \return MYKONOS_ERR_SETRFPLL_LF_INV_TXRX_LOOPBANDWIDTH Invalid Tx/Rx value bandwith + * \return MYKONOS_ERR_SETRFPLL_LF_PLLNAME Invalid pllName requested + * \return MYKONOS_ERR_SETRFPLL_LF_INV_STABILITY Invalid stability range, valid range is 3-15 + */ +mykonosErr_t MYKONOS_setRfPllLoopFilter(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint16_t loopBandwidth_kHz, uint8_t stability) +{ + const uint8_t SETCMD_OPCODE = 0x0A; + const uint8_t SET_PLL_BANDWIDTH = 0x6D; + const uint16_t LOOP_BW_HIGH = 750; + + uint16_t LOOP_BW_LOW = 50; + uint8_t extData[4] = {0}; + uint8_t cmdStatusByte = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + mykonosErr_t errLoopBw = MYKONOS_ERR_OK; + uint32_t timeoutMs = 1000; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setRfPllLoopFilter()\n"); +#endif + + switch (pllName) + { + case RX_PLL: + extData[1] = 0x00; + LOOP_BW_LOW = 50; + errLoopBw = MYKONOS_ERR_SETRFPLL_LF_INV_TXRX_LOOPBANDWIDTH; + break; + case TX_PLL: + extData[1] = 0x10; + LOOP_BW_LOW = 50; + errLoopBw = MYKONOS_ERR_SETRFPLL_LF_INV_TXRX_LOOPBANDWIDTH; + break; + case SNIFFER_PLL: +#if 0 /* Set for Sniffer PLL loop bandwidth is not supported */ + extData[1] = 0x20; + LOOP_BW_LOW = 500; + errLoopBw = MYKONOS_ERR_SETRFPLL_LF_INV_SNF_LOOPBANDWIDTH; + break; +#endif + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETRFPLL_LF_PLLNAME, + getMykonosErrorMessage(MYKONOS_ERR_SETRFPLL_LF_PLLNAME)); + return MYKONOS_ERR_SETRFPLL_LF_PLLNAME; + } + } + + /* Range check for loopBandwidth - Should be between 50kHz and 750kHz for TX/RX and between 500kHz and 750 for SRX*/ + if ((loopBandwidth_kHz< LOOP_BW_LOW) || (loopBandwidth_kHz >LOOP_BW_HIGH)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, errLoopBw, + getMykonosErrorMessage(errLoopBw)); + return errLoopBw; + } + + /* Range check for stability - Should be between 3 and 15 */ + if ((stability < 3) || (stability > 15)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETRFPLL_LF_INV_STABILITY, + getMykonosErrorMessage(MYKONOS_ERR_SETRFPLL_LF_INV_STABILITY)); + return MYKONOS_ERR_SETRFPLL_LF_INV_STABILITY; + } + + /* Generate payload for SET command */ + extData[0] = SET_PLL_BANDWIDTH; + /*left shift and truncate left side*/ + extData[1] |= stability; + extData[2] = (uint8_t)(loopBandwidth_kHz & 0xFF); //full first byte + extData[3] = (uint8_t)(loopBandwidth_kHz >> 8); //two extra bits + + /* executing the SET command */ + retVal = MYKONOS_sendArmCommand(device, SETCMD_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* waiting for command to complete */ + retVal = MYKONOS_waitArmCmdStatus(device, SETCMD_OPCODE, timeoutMs, &cmdStatusByte); + + /* performing command status check */ + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETRFPLL_LF_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_SETRFPLL_LF_ARMERROR)); + return MYKONOS_ERR_SETRFPLL_LF_ARMERROR; + } + + return retVal; + } + + return retVal; +} + +/** + * \brief Gets the RF PLL loop filter bandwidth and stability. + * + * This function is used to get the RF PLL loop bandwidth. It can get the RX PLL, TX PLL + * Sniffer PLL. + * + * \pre Command can be called in Radio Off state or On state. ARM must be initialized. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->spiSettings + * - device->clocks->deviceClock_kHz + * + * \param device is structure pointer to the MYKONOS data structure containing settings + * \param pllName Name of the PLL for which to read the frequency + * \param loopBandwidth_kHz RF PLL loop bandwidth for the PLL specified + * \param stability RF PLL loop stability + * + * \retval MYKONOS_ERR_OK Function completed successfully + * \retval MYKONOS_ERR_GETRFPLL_LF_INV_PLLNAME Invalid PLL name, can not get PLL frequency. Use PLL name ENUM. + * \retval MYKONOS_ERR_GETRFPLL_LF_ARMERROR ARM Command to get RF PLL frequency failed + * \retval MYKONOS_ERR_GETRFPLL_LF_NULLPARAM input parameter is NULL + */ +mykonosErr_t MYKONOS_getRfPllLoopFilter(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint16_t *loopBandwidth_kHz, uint8_t *stability) +{ + const uint8_t GET_PLL_BANDWIDTH = 0x6D; + + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armData[8] = {0, 0, 0, 0, 0, 0, 0, 0}; + uint8_t extData[2] = {GET_PLL_BANDWIDTH, 0}; + uint32_t timeoutMs = 0; + uint8_t cmdStatusByte = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getRfPllLoopFilter()\n"); +#endif + + /* Check for NULL */ + if ((loopBandwidth_kHz == NULL)|| (stability == NULL)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRFPLL_LF_NULLPARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETRFPLL_LF_NULLPARAM)); + return MYKONOS_ERR_GETRFPLL_LF_NULLPARAM; + } + + switch(pllName) + { + case RX_PLL: extData[1] = 0x00; break; + case TX_PLL: extData[1] = 0x10; break; + case SNIFFER_PLL: extData[1] = 0x20; break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRFPLL_LF_INV_PLLNAME, + getMykonosErrorMessage(MYKONOS_ERR_GETRFPLL_LF_INV_PLLNAME)); + return MYKONOS_ERR_GETRFPLL_LF_INV_PLLNAME; + } + } + /* executing the GET command */ + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + + /* waiting for command to complete */ + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + + /* performing command status check */ + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRFPLL_LF_ARMERROR, + getMykonosErrorMessage(MYKONOS_ERR_GETRFPLL_LF_ARMERROR)); + return MYKONOS_ERR_GETRFPLL_LF_ARMERROR; + } + + return retVal; + } + + /* Read from ARM memory */ + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &armData[0], 8, 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + /* Assign to variables */ + *stability = armData[3]; + *loopBandwidth_kHz = (((uint16_t)armData[1]) << 8) | ((uint16_t)armData[0]); + + return MYKONOS_ERR_OK; +} + +/** + * \brief Enable/ Disable Digital DC Offset channels using the channel mask. + * The mask can be a combination of the following channel values ( ::mykonosRxDcOffsettEn_t ). + * + * Channel | Value | Channel description + * -------------------------|---------|-------------------------- + * MYK_DC_OFFSET_ALL_OFF | 0x00 | Disable all the channels + * MYK_DC_OFFSET_RX1 | 0x01 | Enables Rx1 + * MYK_DC_OFFSET_RX2 | 0x02 | Enables Rx1 + * MYK_DC_OFFSET_SNF | 0x04 | Enables Sniffer + * MYK_DC_OFFSET_ORX | 0x08 | Enables ORx + * MYK_DC_OFFSET_AVAILABLE | 0x0F | Enables all the channels + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param enableMask with bits of channels to be enabled. + * + * \retval MYKONOS_ERR_DIG_DC_OFFSET_INV_ENABLE_MASK enable mask passed to the function is invalid, refer mykonosRxDcOffsettEn_t enum. + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setDigDcOffsetEn(mykonosDevice_t *device, uint8_t enableMask) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint16_t REG_ADDRESS = 0x00; + uint8_t dataToWrite = 0x00; + + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setDigDcOffsetEn()\n"); +#endif + + if (enableMask & ~((uint8_t)MYK_DC_OFFSET_AVAILABLE)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DIG_DC_OFFSET_INV_ENABLE_MASK, + getMykonosErrorMessage(MYKONOS_ERR_DIG_DC_OFFSET_INV_ENABLE_MASK)); + return MYKONOS_ERR_DIG_DC_OFFSET_INV_ENABLE_MASK; + } + + REG_ADDRESS = MYKONOS_ADDR_DIGITAL_DC_OFFSET_CONFIG; /* Address for Rx Digital tracking Enable bits register */ + if (enableMask & ((uint8_t)MYK_DC_OFFSET_RX1 | (uint8_t)MYK_DC_OFFSET_RX2)) /* Enable / Disable Rx1 and/or Rx2 */ + { + dataToWrite |= ((enableMask & ((uint8_t)MYK_DC_OFFSET_RX1 |(uint8_t) MYK_DC_OFFSET_RX2)) << 1 ); + } + CMB_SPIWriteField(device->spiSettings, REG_ADDRESS, dataToWrite, 0x06,0); /* Write RX enable bits to the register */ + + dataToWrite = 0x0; /* Reset dataToWrite */ + REG_ADDRESS = MYKONOS_DIGITAL_DC_OFFSET_CH3_TRACKING; /* Address for ORx and Sniffer Digital trackingEnable bits register */ + if (enableMask & ((uint8_t)MYK_DC_OFFSET_SNF | (uint8_t)MYK_DC_OFFSET_ORX)) /* Check for channel ORx and/or Sniffer */ + { + dataToWrite |= ((enableMask & ((uint8_t)MYK_DC_OFFSET_SNF | (uint8_t)MYK_DC_OFFSET_ORX))>>2); + } + CMB_SPIWriteField(device->spiSettings, REG_ADDRESS, dataToWrite, 0x03,0); /* Write Loopback, ORx and Sniffer enable bits to the register */ + + return retVal; +} + +/** + * \brief reads Enable/ Disable channels Digital DC Offset and returns a mask of it. + * The mask returned will be a combination of the following channel values ( ::mykonosRxDcOffsettEn_t ). + * + * Channel | Value | Channel description + * -------------------------|---------|-------------------------- + * MYK_DC_OFFSET_ALL_OFF | 0x00 | All channels are disabled + * MYK_DC_OFFSET_RX1 | 0x01 | Rx1 is enabled + * MYK_DC_OFFSET_RX2 | 0x02 | Rx2 is enabled + * MYK_DC_OFFSET_SNF | 0x04 | Sniffer is enabled + * MYK_DC_OFFSET_ORX | 0x08 | ORx is enabled + * MYK_DC_OFFSET_AVAILABLE | 0x0F | All channels are enabled + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param enableMask pointer to the variable to store Enable mask of channels + * + * \retval MYKONOS_ERR_DIG_DC_OFFSET_NULL_ENABLE_MASK enableMask is NULL + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getDigDcOffsetEn(mykonosDevice_t *device,uint8_t *enableMask) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint16_t REG_ADDRESS = 0; + uint8_t readbackData = 0; + uint8_t enableMaskData = 0; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getDigDcOffsetEn()\n"); +#endif + + if (enableMask == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_DIG_DC_OFFSET_NULL_ENABLE_MASK, + getMykonosErrorMessage(MYKONOS_ERR_DIG_DC_OFFSET_NULL_ENABLE_MASK)); + return MYKONOS_ERR_DIG_DC_OFFSET_NULL_ENABLE_MASK; + } + + REG_ADDRESS = MYKONOS_ADDR_DIGITAL_DC_OFFSET_CONFIG; /* register address of Rx1 and Rx2 enable bits*/ + CMB_SPIReadField(device->spiSettings, REG_ADDRESS, &readbackData, 0x06,0); + enableMaskData |= (readbackData>>1); /* adjust bits to match channel :refer enum mykonosRfDcOffsettEn_t. */ + + readbackData = 0x00; + REG_ADDRESS = MYKONOS_DIGITAL_DC_OFFSET_CH3_TRACKING; /* register address of Orx and sniffer enable bits*/ + CMB_SPIReadField(device->spiSettings, REG_ADDRESS, &readbackData, 0x03,0); + enableMaskData |= (uint8_t)(readbackData<<2); /* adjust bits to match channel :refer enum mykonosRfDcOffsettEn_t. */ + + *enableMask = enableMaskData; + + return retVal; +} + +/** + * \brief This function will configure the path delay settings for all the features: + * DPD, VSWR and CLGC. + * + * A DPD device is required. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param pathDelay pointer to structure of type ::mykonosPathdelay_t to be programmed + * + * \retval MYKONOS_ERR_SET_PATH_DELAY_NULL_PARAM pathDelay is null + * \retval MYKONOS_ERR_SET_PATH_DELAY_PARAM_OUT_OF_RANGE path delay valid range is from 0 to 4095 at 1/16 sample resolution of ORx sample rate + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setPathDelay(mykonosDevice_t *device, mykonosPathdelay_t *pathDelay) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armFieldValue[16] = {0}; + uint8_t extData[3] = {(uint8_t)MYKONOS_ARM_OBJECTID_TRACKING_CAL_CONTROL, (uint8_t)SET_PATH_DELAY, 0}; + uint8_t writeSize = 0; + uint8_t fifoDel[4] = {0}; + uint8_t interpIndex[4] = {0}; + uint32_t *delPointer = &pathDelay->forwardPathDelayCh1; + uint8_t i = 0; + + const uint32_t RANGE_PATH_DELAY = 4095; + const uint8_t PATH_DELAY_SIZE = 4; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setPathDelay()\n"); +#endif + + if (pathDelay == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_PATH_DELAY_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_SET_PATH_DELAY_NULL_PARAM)); + return MYKONOS_ERR_SET_PATH_DELAY_NULL_PARAM; + } + + /* Loop to set the ARM memory data */ + for (i = 0; i < PATH_DELAY_SIZE ; i++) + { + /* Verify all the data in the structure is in range */ + if (*delPointer > RANGE_PATH_DELAY) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_PATH_DELAY_PARAM_OUT_OF_RANGE, + getMykonosErrorMessage(MYKONOS_ERR_SET_PATH_DELAY_PARAM_OUT_OF_RANGE)); + return MYKONOS_ERR_SET_PATH_DELAY_PARAM_OUT_OF_RANGE; + } + + fifoDel[i] = (uint8_t)(*delPointer >> 4); + interpIndex[i] = (uint8_t)(*delPointer - (fifoDel[i] * 16)); + + delPointer++; + } + + if ((device->tx->vswrConfig == NULL) || ((pathDelay->reversePathDelayCh1 == 0) && (pathDelay->reversePathDelayCh2 == 0))) + { + armFieldValue[0] = interpIndex[0]; + armFieldValue[1] = 0; + armFieldValue[2] = fifoDel[0]; + armFieldValue[3] = 0; + armFieldValue[4] = interpIndex[2]; + armFieldValue[5] = 0; + armFieldValue[6] = fifoDel[2]; + armFieldValue[7] = 0; + extData[2] = 0; + writeSize = 8; + } + else + { + armFieldValue[0] = interpIndex[0]; + armFieldValue[1] = 0; + armFieldValue[2] = fifoDel[0]; + armFieldValue[3] = 0; + armFieldValue[4] = interpIndex[2]; + armFieldValue[5] = 0; + armFieldValue[6] = fifoDel[2]; + armFieldValue[7] = 0; + armFieldValue[8] = interpIndex[1]; + armFieldValue[9] = 0; + armFieldValue[10] = fifoDel[1]; + armFieldValue[11] = 0; + armFieldValue[12] = interpIndex[3]; + armFieldValue[13] = 0; + armFieldValue[14] = fifoDel[3]; + armFieldValue[15] = 0; + extData[2] = 1; + writeSize = 16; + } + + retVal = MYKONOS_writeArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &armFieldValue[0], writeSize); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_SET_OPCODE, &extData[0], sizeof(extData)); + + return retVal; +} + +/** + * \brief This function will read the current path delay settings for the selected calibration. + * + * A DPD-enabled transceiver is required + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param select path delay status selection from ::mykonosPathDelaySel_t + * \param pathDelay pointer to structure of type ::mykonosPathdelay_t to store the read back path delay + * + * \retval MYKONOS_ERR_GET_PATH_DELAY_NULL_PARAM pathDelay is null + * \retval MYKONOS_ERR_GET_PATH_DELAY_INVALID_SELECTION invalid selection for getting the path delay, valid selections are given by mykonosPathDelaySel_t + * \retval MYKONOS_ERR_GET_PATH_DELAY_ARMERRFLAG Arm error while reading path delay for the selected calibration status + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getPathDelay(mykonosDevice_t *device, mykonosPathDelaySel_t select, mykonosPathdelay_t *pathDelay) +{ + uint8_t extData[3] = {(uint8_t)MYKONOS_ARM_OBJECTID_CAL_STATUS, (uint8_t)MYKONOS_ARM_OBJECTID_VSWRCONFIG, 0}; + uint8_t armData[80] = {0}; + uint32_t timeoutMs = 0; + uint8_t cmdStatusByte = 0; + uint32_t *delPointer = &pathDelay->forwardPathDelayCh1; + uint8_t channel = 0; + uint8_t addr[4] = {0}; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getPathDelay()\n"); +#endif + + if (pathDelay == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_PATH_DELAY_NULL_PARAM, + getMykonosErrorMessage(MYKONOS_ERR_GET_PATH_DELAY_NULL_PARAM)); + return MYKONOS_ERR_GET_PATH_DELAY_NULL_PARAM; + } + + switch (select) + { + case MYK_DPD_PATH_DELAY: + extData[1] = MYKONOS_ARM_OBJECTID_DPDCONFIG; + addr[0] = 24; + addr[1] = 26; + addr[2] = 0; + addr[3] = 0; + break; + case MYK_CLGC_PATH_DELAY: + extData[1] = MYKONOS_ARM_OBJECTID_CLGCCONFIG; + addr[0] = 60; + addr[1] = 62; + addr[2] = 0; + addr[3] = 0; + break; + case MYK_VSWR_PATH_DELAY: + extData[1] = MYKONOS_ARM_OBJECTID_VSWRCONFIG; + addr[0] = 72; + addr[1] = 74; + addr[2] = 76; + addr[3] = 78; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_PATH_DELAY_INVALID_SELECTION, + getMykonosErrorMessage(MYKONOS_ERR_GET_PATH_DELAY_INVALID_SELECTION)); + return MYKONOS_ERR_GET_PATH_DELAY_INVALID_SELECTION; + } + + /* reading 2 channels, channel being the channel selector */ + for (channel = 0; channel < 2; channel++) + { + if (channel) + { + delPointer++; + } + + extData[2] = channel; + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + /* throw more specific error message instead of returning error code from waitArmCmdStatus */ + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_PATH_DELAY_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GET_PATH_DELAY_ARMERRFLAG)); + return MYKONOS_ERR_GET_PATH_DELAY_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_PATH_DELAY_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GET_PATH_DELAY_ARMERRFLAG)); + return MYKONOS_ERR_GET_PATH_DELAY_ARMERRFLAG; + } + + /* read status from ARM memory */ + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &armData[0], sizeof(armData), 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + *delPointer = ((uint32_t)(armData[addr[1]]) * 16) + (uint32_t)(armData[addr[0]]); + delPointer++; + if ((addr[2] != 0) && (addr[3] != 0)) + { + /* reverse path delay only applies to VSWR */ + *delPointer = ((uint32_t)(armData[addr[3]]) * 16) + (uint32_t)(armData[addr[2]]); + } + else + { + /* the rest of path delays will not have a reverse delay value */ + *delPointer = 0; + } + } + + return retVal; +} + +/** + * \brief This function reads the current error counters for all the DPD error codes from ::mykonosDpdErrors_t. + * + * A DPD-enabled transceiver is required + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param txChannel Tx channel selection from ::mykonosTxChannels_t + * \param dpdErrCnt pointer to structure of type ::mykonosDpdErrorCounters_t to store the read back error counters + * + * \retval MYKONOS_ERR_GETDPD_ERROR_CNT_NULLPARAM dpdErrCnt is null + * \retval MYKONOS_ERR_GETDPD_ERROR_CNT_INV_CH invalid selection for getting the error counters tx channel, only valid values are Tx1 and Tx2 + * \retval MYKONOS_ERR_GETDPD_ERROR_CNT_ARMERRFLAG Arm error while reading the error counters for the DPD status + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getDpdErrorCounters(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosDpdErrorCounters_t *dpdErrCnt) +{ + uint8_t extData[3] = {MYKONOS_ARM_OBJECTID_CAL_STATUS, MYKONOS_ARM_OBJECTID_DPDCONFIG, 0}; + uint8_t armData[200] = {0}; + uint32_t timeoutMs = 0; + uint8_t cmdStatusByte = 0; + uint8_t loop = 0; + uint8_t index = 0; + uint8_t channelSelect = 0; + mykonosErr_t retVal = MYKONOS_ERR_OK; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getDpdErrorCounters()\n"); +#endif + + if (dpdErrCnt == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETDPD_ERROR_CNT_NULLPARAM, + getMykonosErrorMessage(MYKONOS_ERR_GETDPD_ERROR_CNT_NULLPARAM)); + return MYKONOS_ERR_GETDPD_ERROR_CNT_NULLPARAM; + } + + switch (txChannel) + { + case TX1: + channelSelect = 0; + break; + case TX2: + channelSelect = 1; + break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETDPD_ERROR_CNT_INV_CH, + getMykonosErrorMessage(MYKONOS_ERR_GETDPD_ERROR_CNT_INV_CH)); + return MYKONOS_ERR_GETDPD_ERROR_CNT_INV_CH; + } + } + + extData[2] = channelSelect; + + retVal = MYKONOS_sendArmCommand(device, MYKONOS_ARM_GET_OPCODE, &extData[0], sizeof(extData)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + timeoutMs = 1000; + retVal = MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_GET_OPCODE, timeoutMs, &cmdStatusByte); + if (retVal != MYKONOS_ERR_OK) + { + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETDPD_ERROR_CNT_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETDPD_ERROR_CNT_ARMERRFLAG)); + return MYKONOS_ERR_GETDPD_ERROR_CNT_ARMERRFLAG; + } + + return retVal; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETDPD_ERROR_CNT_ARMERRFLAG, + getMykonosErrorMessage(MYKONOS_ERR_GETDPD_ERROR_CNT_ARMERRFLAG)); + return MYKONOS_ERR_GETDPD_ERROR_CNT_ARMERRFLAG; + } + + /* read status from ARM memory */ + retVal = MYKONOS_readArmMem(device, MYKONOS_ADDR_ARM_START_DATA_ADDR, &armData[0], sizeof(armData), 1); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + dpdErrCnt->dpdErrorCount = ((uint32_t)(armData[67]) << 24) | ((uint32_t)(armData[66]) << 16) | ((uint32_t)(armData[65]) << 8) | (uint32_t)(armData[64]); + index = 68; + for (loop = 1; loop < (uint8_t)MYK_DPD_ERROR_END; loop++) + { + dpdErrCnt->errorCounter[loop] = ((uint32_t)(armData[index + 3]) << 24) | ((uint32_t)(armData[index + 2]) << 16) | ((uint32_t)(armData[index + 1]) << 8) | (uint32_t)(armData[index]); + index +=4; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief DPD feature to set the bypassing actuator when Tx signal power is below a programmable threshold given in + * ::mykonosDpdBypassConfig_t lowPowerActuatorBypassLevel. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param actConfig Pointer to actuator structure of type ::mykonosDpdBypassConfig_t which contains the settings to be programmed + * + * \retval MYKONOS_ERR_SETDPDACT_NULL_ACTSTRUCT passed structure is null + * \retval MYKONOS_ERR_SETDPDACT_INV_ACTMODE invalid mode in actConfig->lowPowerActuatorBypassMode for valid modes ::mykonosDpdResetMode_t + * \retval MYKONOS_ERR_SETDPDACT_INV_LEVEL actConfig->lowPowerActuatorBypassLevel outside the range, valid range is 0 to 6000 (0 to 60dB) + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setDpdBypassConfig(mykonosDevice_t *device, mykonosDpdBypassConfig_t *actConfig) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armFieldValue[4] = {0}; + uint8_t byteOffset = 62; + + const uint16_t LEVEL_RANGE_CHECK = 6000; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setDpdBypassConfig()\n"); +#endif + + if (actConfig == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETDPDACT_NULL_ACTSTRUCT, + getMykonosErrorMessage(MYKONOS_ERR_SETDPDACT_NULL_ACTSTRUCT)); + return MYKONOS_ERR_SETDPDACT_NULL_ACTSTRUCT; + } + + if (actConfig->bypassActuatorMode >= MYK_DPD_RESET_END) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETDPDACT_INV_ACTMODE, + getMykonosErrorMessage(MYKONOS_ERR_SETDPDACT_INV_ACTMODE)); + return MYKONOS_ERR_SETDPDACT_INV_ACTMODE; + } + + if (actConfig->bypassActuatorLevel > LEVEL_RANGE_CHECK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETDPDACT_INV_LEVEL, + getMykonosErrorMessage(MYKONOS_ERR_SETDPDACT_INV_LEVEL)); + return MYKONOS_ERR_SETDPDACT_INV_LEVEL; + } + + armFieldValue[0] = (actConfig->bypassActuatorEn > 0) ? 1 : 0; + armFieldValue[1] = (uint8_t)(actConfig->bypassActuatorMode); + armFieldValue[2] = (uint8_t)(actConfig->bypassActuatorLevel & 0xFF); + armFieldValue[3] = (uint8_t)((actConfig->bypassActuatorLevel >> 8) & 0xFF); + + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_DPDCONFIG, byteOffset, &armFieldValue[0], sizeof(armFieldValue)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + return MYKONOS_ERR_OK; +} + +/** + * \brief Get configuration for bypassing DPD actuator + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param actConfig actuator structure of type ::mykonosDpdBypassConfig_t + * + * \retval MYKONOS_ERR_GETDPDACT_NULL_ACTSTRUCT passed structure is null + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getDpdBypassConfig(mykonosDevice_t *device, mykonosDpdBypassConfig_t *actConfig) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armFieldValue[4] = {0}; + uint8_t byteOffset = 62; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getDpdBypassConfig()\n"); +#endif + + if (actConfig == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETDPDACT_NULL_ACTSTRUCT, + getMykonosErrorMessage(MYKONOS_ERR_GETDPDACT_NULL_ACTSTRUCT)); + return MYKONOS_ERR_GETDPDACT_NULL_ACTSTRUCT; + } + + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_DPDCONFIG, byteOffset, &armFieldValue[0], sizeof(armFieldValue)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + actConfig->bypassActuatorEn = armFieldValue[0]; + actConfig->bypassActuatorMode = (mykonosDpdResetMode_t)armFieldValue[1]; + actConfig->bypassActuatorLevel = (uint16_t)(((uint16_t)(armFieldValue[3]) << 8) | (uint16_t)(armFieldValue[2])); + + return MYKONOS_ERR_OK; +} + +/** + * \brief DPD feature to set the actuator gain difference check. + * If the gain before and after the actuator exceeds the value actCheck->actuatorGainCheckLevel an error will be issued + * and the actuator will reset depending on the actCheck->actuatorGainCheckMode. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param actCheck Pointer to structure of type mykonosDpdActuatorCheck_t which contains the settings to be programmed + * + * \retval MYKONOS_ERR_SETDPDACTCHECK_NULL_ACTSTRUCT passed structure is null + * \retval MYKONOS_ERR_SETDPDACTCHECK_INV_ACTMODE invalid mode in actCheck->actuatorGainCheckMode for valid modes ::mykonosDpdResetMode_t + * \retval MYKONOS_ERR_SETDPDACTCHECK_INV_LEVEL actCheck->actuatorGainCheckLevel outside the range, valid range is from 0 to 3000 (0 to 30dB) + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setDpdActuatorCheck(mykonosDevice_t *device, mykonosDpdActuatorCheck_t *actCheck) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armFieldValue[4] = {0}; + uint8_t byteOffset = 58; + + const uint16_t LEVEL_RANGE_CHECK = 3000; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setDpdActuatorCheck()\n"); +#endif + + if (actCheck == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETDPDACTCHECK_NULL_ACTSTRUCT, + getMykonosErrorMessage(MYKONOS_ERR_SETDPDACTCHECK_NULL_ACTSTRUCT)); + return MYKONOS_ERR_SETDPDACTCHECK_NULL_ACTSTRUCT; + } + + if (actCheck->actuatorGainCheckMode >= MYK_DPD_RESET_END) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETDPDACTCHECK_INV_ACTMODE, + getMykonosErrorMessage(MYKONOS_ERR_SETDPDACTCHECK_INV_ACTMODE)); + return MYKONOS_ERR_SETDPDACTCHECK_INV_ACTMODE; + } + + if (actCheck->actuatorGainCheckLevel > LEVEL_RANGE_CHECK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETDPDACTCHECK_INV_LEVEL, + getMykonosErrorMessage(MYKONOS_ERR_SETDPDACTCHECK_INV_LEVEL)); + return MYKONOS_ERR_SETDPDACTCHECK_INV_LEVEL; + } + + armFieldValue[0] = (actCheck->actuatorGainCheckEn > 0) ? 1 : 0; + armFieldValue[1] = (uint8_t)(actCheck->actuatorGainCheckMode); + armFieldValue[2] = (uint8_t)(actCheck->actuatorGainCheckLevel & 0xFF); + armFieldValue[3] = (uint8_t)((actCheck->actuatorGainCheckLevel >> 8) & 0xFF); + + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_DPDCONFIG, byteOffset, &armFieldValue[0], sizeof(armFieldValue)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + return MYKONOS_ERR_OK; +} + + +/** + * \brief Get configuration for DPD actuator check + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param actCheck Pointer to structure of type mykonosDpdActuatorCheck_t which will contain the programmed settings + * + * \retval MYKONOS_ERR_GETDPDACTCHECK_NULL_ACTSTRUCT passed structure is null + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getDpdActuatorCheck(mykonosDevice_t *device, mykonosDpdActuatorCheck_t *actCheck) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armFieldValue[4] = {0}; + uint8_t byteOffset = 58; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getDpdActuatorCheck()\n"); +#endif + + if (actCheck == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETDPDACTCHECK_NULL_ACTSTRUCT, + getMykonosErrorMessage(MYKONOS_ERR_GETDPDACTCHECK_NULL_ACTSTRUCT)); + return MYKONOS_ERR_GETDPDACTCHECK_NULL_ACTSTRUCT; + } + + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_DPDCONFIG, byteOffset, &armFieldValue[0], sizeof(armFieldValue)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + actCheck->actuatorGainCheckEn = armFieldValue[0]; + actCheck->actuatorGainCheckMode = (mykonosDpdResetMode_t)armFieldValue[1]; + actCheck->actuatorGainCheckLevel = (uint16_t)(((uint16_t)(armFieldValue[3]) << 8) | (uint16_t)(armFieldValue[2])); + + return MYKONOS_ERR_OK; +} + + +/** + * \brief CLGC feature to set the TX attenuation tuning range to a relative range around a nominal value + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param attRangeCfg Pointer to structure of type mykonosClgcAttenTuningConfig_t which contains the settings to be programmed + * + * \retval MYKONOS_ERR_CFGCLGC_TXORX_PROFILE_INV Tx and ObsRx profiles must be valid to use the CLGC feature + * \retval MYKONOS_ERR_CLGCATTENTUNCFG_NULL_ATTRANGECFGSTRUCT Passed structure is null + * \retval MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_MODE Invalid mode in attRangeCfg member, for valid modes ::mykonosClgcAttenTuningMode_t + * \retval MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_PRESET Invalid AttenTuningPreset in attRangeCfg member, valid range is from 0 to 839 (0 to 41.95dB) + * \retval MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_RANGE Invalid AttenTuningRange in attRangeCfg member, valid range is from 0 to 420 (0 to 21dB) + * \retval MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX1_SETTINGS Invalid Tx1 AttenTuningRange and AttenTuningPreset combination + * \retval MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX2_SETTINGS Invalid Tx2 AttenTuningRange and AttenTuningPreset combination + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_setClgcAttenTuningConfig(mykonosDevice_t *device, mykonosClgcAttenTuningConfig_t *attRangeCfg) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armFieldValue[10] = {0}; + uint8_t byteOffset = 0x2C; + + const uint16_t PRESET_CHECK = 840; + const uint16_t RANGE_CHECK = 420; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_setClgcAttenTuningConfig()\n"); +#endif + + /* CLGC requires Tx and ORx enabled, throw error if both are not enabled */ + if ((device->profilesValid & (TX_PROFILE_VALID | ORX_PROFILE_VALID)) != (TX_PROFILE_VALID | ORX_PROFILE_VALID)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CFGCLGC_TXORX_PROFILE_INV, + getMykonosErrorMessage(MYKONOS_ERR_CFGCLGC_TXORX_PROFILE_INV)); + return MYKONOS_ERR_CFGCLGC_TXORX_PROFILE_INV; + } + + if (attRangeCfg == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CLGCATTENTUNCFG_NULL_ATTRANGECFGSTRUCT, + getMykonosErrorMessage(MYKONOS_ERR_CLGCATTENTUNCFG_NULL_ATTRANGECFGSTRUCT)); + return MYKONOS_ERR_CLGCATTENTUNCFG_NULL_ATTRANGECFGSTRUCT; + } + + /* Range checks */ + if ((attRangeCfg->tx1AttenTuningLimitMode >= MYK_CLGC_ATTEN_END) || (attRangeCfg->tx2AttenTuningLimitMode >= MYK_CLGC_ATTEN_END)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_MODE, + getMykonosErrorMessage(MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_MODE)); + return MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_MODE; + } + + if ((attRangeCfg->tx1AttenTuningPreset >= PRESET_CHECK) || (attRangeCfg->tx2AttenTuningPreset >= PRESET_CHECK)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_PRESET, + getMykonosErrorMessage(MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_PRESET)); + return MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_PRESET; + } + + if ((attRangeCfg->tx1AttenTuningRange > RANGE_CHECK) || (attRangeCfg->tx2AttenTuningRange > RANGE_CHECK)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_RANGE, + getMykonosErrorMessage(MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_RANGE)); + return MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_RANGE; + } + + if (((attRangeCfg->tx1AttenTuningPreset - attRangeCfg->tx1AttenTuningRange) < 0) || + ((attRangeCfg->tx1AttenTuningPreset + attRangeCfg->tx1AttenTuningRange) > PRESET_CHECK)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX1_SETTINGS, + getMykonosErrorMessage(MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX1_SETTINGS)); + return MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX1_SETTINGS; + } + + if (((attRangeCfg->tx2AttenTuningPreset - attRangeCfg->tx2AttenTuningRange) < 0) || + ((attRangeCfg->tx2AttenTuningPreset + attRangeCfg->tx2AttenTuningRange) > PRESET_CHECK)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX2_SETTINGS, + getMykonosErrorMessage(MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX2_SETTINGS)); + return MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX2_SETTINGS; + } + + armFieldValue[0] = (uint8_t)(attRangeCfg->tx1AttenTuningLimitMode & 0xFF); + armFieldValue[1] = (uint8_t)(attRangeCfg->tx2AttenTuningLimitMode & 0xFF); + armFieldValue[2] = (uint8_t)(attRangeCfg->tx1AttenTuningPreset & 0xFF); + armFieldValue[3] = (uint8_t)((attRangeCfg->tx1AttenTuningPreset >> 8) & 0xFF); + armFieldValue[4] = (uint8_t)(attRangeCfg->tx2AttenTuningPreset & 0xFF); + armFieldValue[5] = (uint8_t)((attRangeCfg->tx2AttenTuningPreset >> 8) & 0xFF); + armFieldValue[6] = (uint8_t)(attRangeCfg->tx1AttenTuningRange & 0xFF); + armFieldValue[7] = (uint8_t)((attRangeCfg->tx1AttenTuningRange >> 8) & 0xFF); + armFieldValue[8] = (uint8_t)(attRangeCfg->tx2AttenTuningRange & 0xFF); + armFieldValue[9] = (uint8_t)((attRangeCfg->tx2AttenTuningRange >> 8) & 0xFF); + + retVal = MYKONOS_writeArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armFieldValue[0], sizeof(armFieldValue)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + return MYKONOS_ERR_OK; +} + + +/** + * \brief Get configuration for CLGC Tx attenuation tuning range. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->profilesValid + * + * \param device Pointer to the Mykonos device data structure containing settings + * \param attRangeCfg Pointer to structure of type mykonosClgcAttenTuningConfig_t which will contain the programmed settings + * + * \retval MYKONOS_ERR_CLGCATTENTUNCFGGET_NULL_ATTRANGECFGSTRUCT passed structure is null + * \retval MYKONOS_ERR_OK Function completed successfully + */ +mykonosErr_t MYKONOS_getClgcAttenTuningConfig(mykonosDevice_t *device, mykonosClgcAttenTuningConfig_t *attRangeCfg) +{ + mykonosErr_t retVal = MYKONOS_ERR_OK; + uint8_t armFieldValue[10] = {0}; + uint8_t byteOffset = 0x2C; + +#if (MYKONOS_VERBOSE == 1) + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OK, "MYKONOS_getClgcAttenTuningConfig()\n"); +#endif + + if (attRangeCfg == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CLGCATTENTUNCFGGET_NULL_ATTRANGECFGSTRUCT, + getMykonosErrorMessage(MYKONOS_ERR_CLGCATTENTUNCFGGET_NULL_ATTRANGECFGSTRUCT)); + return MYKONOS_ERR_CLGCATTENTUNCFGGET_NULL_ATTRANGECFGSTRUCT; + } + + retVal = MYKONOS_readArmConfig(device, MYKONOS_ARM_OBJECTID_CLGCCONFIG, byteOffset, &armFieldValue[0], sizeof(armFieldValue)); + if (retVal != MYKONOS_ERR_OK) + { + return retVal; + } + + attRangeCfg->tx1AttenTuningLimitMode = (mykonosClgcAttenTuningMode_t)armFieldValue[0]; + attRangeCfg->tx2AttenTuningLimitMode = (mykonosClgcAttenTuningMode_t)armFieldValue[1]; + attRangeCfg->tx1AttenTuningPreset = (uint16_t)(((uint16_t)(armFieldValue[3]) << 8) | (uint16_t)(armFieldValue[2])); + attRangeCfg->tx2AttenTuningPreset = (uint16_t)(((uint16_t)(armFieldValue[5]) << 8) | (uint16_t)(armFieldValue[4])); + attRangeCfg->tx1AttenTuningRange = (uint16_t)(((uint16_t)(armFieldValue[7]) << 8) | (uint16_t)(armFieldValue[6])); + attRangeCfg->tx2AttenTuningRange = (uint16_t)(((uint16_t)(armFieldValue[9]) << 8) | (uint16_t)(armFieldValue[8])); + + return MYKONOS_ERR_OK; +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos.h new file mode 100644 index 00000000..b852b58a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos.h @@ -0,0 +1,277 @@ +/*! + * \file mykonos.h + * \brief Contains macro definitions and function prototypes for mykonos.c + * + * Mykonos API version: 1.5.2.3566 + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#ifndef _MYKONOS_LIB_H_ +#define _MYKONOS_LIB_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "t_mykonos.h" +#include "mykonos_version.h" + +#define TX_PROFILE_VALID 0x01 +#define RX_PROFILE_VALID 0x02 +#define ORX_PROFILE_VALID 0x04 +#define SNIFF_PROFILE_VALID 0x08 + +/* + **************************************************************************** + * General Initialization functions + **************************************************************************** + */ +mykonosErr_t MYKONOS_resetDevice(mykonosDevice_t *device); +mykonosErr_t MYKONOS_getDeviceRev(mykonosDevice_t *device, uint8_t *revision); +mykonosErr_t MYKONOS_getProductId(mykonosDevice_t *device, uint8_t *productId); +mykonosErr_t MYKONOS_setSpiSettings(mykonosDevice_t *device); +mykonosErr_t MYKONOS_verifyDeviceDataStructure(mykonosDevice_t *device); +mykonosErr_t MYKONOS_verifyProfiles(mykonosDevice_t *device); +mykonosErr_t MYKONOS_initialize(mykonosDevice_t *device); +mykonosErr_t MYKONOS_waitForEvent(mykonosDevice_t *device, waitEvent_t waitEvent, uint32_t timeout_us); +mykonosErr_t MYKONOS_readEventStatus(mykonosDevice_t *device, waitEvent_t waitEvent, uint8_t *eventDone); +mykonosErr_t MYKONOS_getApiVersion (mykonosDevice_t *device, uint32_t *siVer, uint32_t *majorVer, uint32_t *minorVer, uint32_t *buildVer); + +/* + ***************************************************************************** + * PLL / Synthesizer functions + ***************************************************************************** + */ +mykonosErr_t MYKONOS_initDigitalClocks(mykonosDevice_t *device); +mykonosErr_t MYKONOS_setRfPllFrequency(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint64_t rfPllLoFrequency_Hz); +mykonosErr_t MYKONOS_getRfPllFrequency(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint64_t *rfPllLoFrequency_Hz); +mykonosErr_t MYKONOS_checkPllsLockStatus(mykonosDevice_t *device, uint8_t *pllLockStatus); +mykonosErr_t MYKONOS_setRfPllLoopFilter(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint16_t loopBandwidth_kHz, uint8_t stability); +mykonosErr_t MYKONOS_getRfPllLoopFilter(mykonosDevice_t *device, mykonosRfPllName_t pllName, uint16_t *loopBandwidth_kHz, uint8_t *stability); +/* + ***************************************************************************** + * ARM Processor Control Functions + ***************************************************************************** + */ +mykonosErr_t MYKONOS_initArm(mykonosDevice_t *device); +mykonosErr_t MYKONOS_loadArmFromBinary(mykonosDevice_t *device, uint8_t *binary, uint32_t count); +mykonosErr_t MYKONOS_loadArmConcurrent(mykonosDevice_t *device, uint8_t *binary, uint32_t count); +mykonosErr_t MYKONOS_verifyArmChecksum(mykonosDevice_t *device); +mykonosErr_t MYKONOS_checkArmState(mykonosDevice_t *device, mykonosArmState_t armStateCheck); +mykonosErr_t MYKONOS_getArmVersion(mykonosDevice_t *device, uint8_t *majorVer, uint8_t *minorVer, uint8_t *rcVer, mykonosBuild_t *buildType); + +mykonosErr_t MYKONOS_configDpd(mykonosDevice_t *device); +mykonosErr_t MYKONOS_getDpdConfig(mykonosDevice_t *device); +mykonosErr_t MYKONOS_getDpdStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosDpdStatus_t *dpdStatus); +mykonosErr_t MYKONOS_restoreDpdModel(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t *modelDataBuffer, uint32_t modelNumberBytes); +mykonosErr_t MYKONOS_saveDpdModel(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t *modelDataBuffer, uint32_t modelNumberBytes); +mykonosErr_t MYKONOS_setDpdActState(mykonosDevice_t *device, mykonosTxChannels_t txChannel, uint8_t actState); +mykonosErr_t MYKONOS_resetDpd(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosDpdResetMode_t reset); +mykonosErr_t MYKONOS_setDpdBypassConfig(mykonosDevice_t *device, mykonosDpdBypassConfig_t *actConfig); +mykonosErr_t MYKONOS_getDpdBypassConfig(mykonosDevice_t *device, mykonosDpdBypassConfig_t *actConfig); +mykonosErr_t MYKONOS_setDpdActuatorCheck(mykonosDevice_t *device, mykonosDpdActuatorCheck_t *actCheck); +mykonosErr_t MYKONOS_getDpdActuatorCheck(mykonosDevice_t *device, mykonosDpdActuatorCheck_t *actCheck); + +mykonosErr_t MYKONOS_setClgcAttenTuningConfig(mykonosDevice_t *device, mykonosClgcAttenTuningConfig_t *attRangeCfg); +mykonosErr_t MYKONOS_getClgcAttenTuningConfig(mykonosDevice_t *device, mykonosClgcAttenTuningConfig_t *attRangeCfg); + +mykonosErr_t MYKONOS_configClgc(mykonosDevice_t *device); +mykonosErr_t MYKONOS_getClgcConfig(mykonosDevice_t *device); +mykonosErr_t MYKONOS_getClgcStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosClgcStatus_t *clgcStatus); +mykonosErr_t MYKONOS_setClgcGain(mykonosDevice_t *device, mykonosTxChannels_t txChannel, int16_t gain); + +mykonosErr_t MYKONOS_configVswr(mykonosDevice_t *device); +mykonosErr_t MYKONOS_getVswrConfig(mykonosDevice_t *device); +mykonosErr_t MYKONOS_getVswrStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosVswrStatus_t *vswrStatus); + +mykonosErr_t MYKONOS_runInitCals(mykonosDevice_t *device, uint32_t calMask); +mykonosErr_t MYKONOS_waitInitCals(mykonosDevice_t *device, uint32_t timeoutMs, uint8_t *errorFlag, uint8_t *errorCode); +mykonosErr_t MYKONOS_abortInitCals(mykonosDevice_t *device, uint32_t *calsCompleted); +mykonosErr_t MYKONOS_getInitCalStatus(mykonosDevice_t *device, mykonosInitCalStatus_t *initCalStatus); + +mykonosErr_t MYKONOS_resetExtTxLolChannel(mykonosDevice_t *device, mykonosTxChannels_t channelSel); + +mykonosErr_t MYKONOS_radioOn(mykonosDevice_t *device); +mykonosErr_t MYKONOS_radioOff(mykonosDevice_t *device); +mykonosErr_t MYKONOS_getRadioState(mykonosDevice_t *device, uint32_t *radioStatus); +mykonosErr_t MYKONOS_enableTrackingCals(mykonosDevice_t *device, uint32_t enableMask); +mykonosErr_t MYKONOS_rescheduleTrackingCal(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal); +mykonosErr_t MYKONOS_setAllTrackCalState(mykonosDevice_t *device, uint32_t trackingCalMask); +mykonosErr_t MYKONOS_getAllTrackCalState(mykonosDevice_t *device, uint32_t *trackCals); +mykonosErr_t MYKONOS_setTrackingCalState(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal, uint8_t trackCalState); +mykonosErr_t MYKONOS_getTrackingCalState(mykonosDevice_t *device, mykonosTrackingCalibrations_t trackingCal, uint8_t *trackCalState); +mykonosErr_t MYKONOS_getEnabledTrackingCals(mykonosDevice_t *device, uint32_t *enableMask); +mykonosErr_t MYKONOS_getPendingTrackingCals(mykonosDevice_t *device, uint32_t *pendingCalMask); +mykonosErr_t MYKONOS_getTxLolStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosTxLolStatus_t *txLolStatus); +mykonosErr_t MYKONOS_getTxQecStatus(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosTxQecStatus_t *txQecStatus); + +mykonosErr_t MYKONOS_getRxQecStatus(mykonosDevice_t *device, mykonosRxChannels_t rxChannel, mykonosRxQecStatus_t *rxQecStatus); +mykonosErr_t MYKONOS_getOrxQecStatus(mykonosDevice_t *device, mykonosObsRxChannels_t orxChannel, mykonosOrxQecStatus_t *orxQecStatus); + +mykonosErr_t MYKONOS_setSnifferChannel(mykonosDevice_t *device, mykonosSnifferChannel_t snifferChannel); +mykonosErr_t MYKONOS_setRadioControlPinMode(mykonosDevice_t *device); + +mykonosErr_t MYKONOS_setPathDelay(mykonosDevice_t *device, mykonosPathdelay_t *pathDelay); +mykonosErr_t MYKONOS_getPathDelay(mykonosDevice_t *device, mykonosPathDelaySel_t select, mykonosPathdelay_t *pathDelay); + +mykonosErr_t MYKONOS_getDpdErrorCounters(mykonosDevice_t *device, mykonosTxChannels_t txChannel, mykonosDpdErrorCounters_t *dpdErrCnt); + +/* Low level ARM functions */ +mykonosErr_t MYKONOS_readArmMem(mykonosDevice_t *device, uint32_t address, uint8_t *returnData, uint32_t bytesToRead, uint8_t autoIncrement); +mykonosErr_t MYKONOS_writeArmMem(mykonosDevice_t *device, uint32_t address, uint8_t *data, uint32_t byteCount); +mykonosErr_t MYKONOS_writeArmConfig(mykonosDevice_t *device, uint8_t objectId, uint16_t offset, uint8_t *data, uint8_t byteCount); +mykonosErr_t MYKONOS_readArmConfig(mykonosDevice_t *device, uint8_t objectId, uint16_t offset, uint8_t *data, uint8_t byteCount); +mykonosErr_t MYKONOS_sendArmCommand(mykonosDevice_t *device, uint8_t opCode, uint8_t *extendedData, uint8_t extendedDataNumBytes); +mykonosErr_t MYKONOS_readArmCmdStatus(mykonosDevice_t *device, uint16_t *errorWord, uint16_t *statusWord); +mykonosErr_t MYKONOS_readArmCmdStatusByte(mykonosDevice_t *device, uint8_t opCode, uint8_t *cmdStatByte); +mykonosErr_t MYKONOS_waitArmCmdStatus(mykonosDevice_t *device, uint8_t opCode, uint32_t timeoutMs, uint8_t *cmdStatByte); +mykonosErr_t MYKONOS_writeArmProfile(mykonosDevice_t *device); +mykonosErr_t MYKONOS_loadAdcProfiles(mykonosDevice_t *device); + + +/* + ***************************************************************************** + * JESD204B Datapath Functions + ***************************************************************************** + */ +/* Functions to setup the JESD204B IP */ +mykonosErr_t MYKONOS_resetDeframer(mykonosDevice_t *device); +mykonosErr_t MYKONOS_setupSerializers(mykonosDevice_t *device); +mykonosErr_t MYKONOS_setupDeserializers(mykonosDevice_t *device); +mykonosErr_t MYKONOS_setupJesd204bFramer(mykonosDevice_t *device); +mykonosErr_t MYKONOS_setupJesd204bObsRxFramer(mykonosDevice_t *device); +mykonosErr_t MYKONOS_setupJesd204bDeframer(mykonosDevice_t *device); +mykonosErr_t MYKONOS_enableRxFramerLink(mykonosDevice_t *device, uint8_t enable); +mykonosErr_t MYKONOS_enableObsRxFramerLink(mykonosDevice_t *device, uint8_t enable); + +/* Functions to initialize the JESD204B link */ +mykonosErr_t MYKONOS_enableMultichipSync(mykonosDevice_t *device, uint8_t enableMcs, uint8_t *mcsStatus); +mykonosErr_t MYKONOS_enableSysrefToRxFramer(mykonosDevice_t *device, uint8_t enable); +mykonosErr_t MYKONOS_enableSysrefToObsRxFramer(mykonosDevice_t *device, uint8_t enable); +mykonosErr_t MYKONOS_enableSysrefToDeframer(mykonosDevice_t *device, uint8_t enable); + +/* Functions to help debug the JESD204B link */ +mykonosErr_t MYKONOS_readRxFramerStatus(mykonosDevice_t *device, uint8_t *framerStatus); +mykonosErr_t MYKONOS_readOrxFramerStatus(mykonosDevice_t *device, uint8_t *obsFramerStatus); +mykonosErr_t MYKONOS_readDeframerStatus(mykonosDevice_t *device, uint8_t *deframerStatus); +mykonosErr_t MYKONOS_getDeframerFifoDepth(mykonosDevice_t *device, uint8_t *fifoDepth, uint8_t *readEnLmfcCount); + +/* PRBS debug functions */ +mykonosErr_t MYKONOS_enableRxFramerPrbs(mykonosDevice_t *device, mykonosPrbsOrder_t polyOrder, uint8_t enable); +mykonosErr_t MYKONOS_enableObsRxFramerPrbs(mykonosDevice_t *device, mykonosPrbsOrder_t polyOrder, uint8_t enable); +mykonosErr_t MYKONOS_rxInjectPrbsError(mykonosDevice_t *device); +mykonosErr_t MYKONOS_obsRxInjectPrbsError(mykonosDevice_t *device); +mykonosErr_t MYKONOS_enableDeframerPrbsChecker(mykonosDevice_t *device, uint8_t lanes, mykonosPrbsOrder_t polyOrder, uint8_t enable); +mykonosErr_t MYKONOS_clearDeframerPrbsCounters(mykonosDevice_t *device); +mykonosErr_t MYKONOS_readDeframerPrbsCounters(mykonosDevice_t *device, uint8_t counterSelect, uint32_t *prbsErrorCount); + +/* Miscellaneous debug functions */ +mykonosErr_t MYKONOS_jesd204bIlasCheck(mykonosDevice_t *device, uint16_t *mismatch); +mykonosErr_t MYKONOS_setRxFramerDataSource(mykonosDevice_t *device, uint8_t dataSource); +mykonosErr_t MYKONOS_setObsRxFramerDataSource(mykonosDevice_t *device, uint8_t dataSource); + +/* + ***************************************************************************** + * Shared Data path functions + ***************************************************************************** + */ +mykonosErr_t MYKONOS_programFir(mykonosDevice_t *device, mykonosfirName_t filterToProgram, mykonosFir_t *firFilter); +mykonosErr_t MYKONOS_readFir(mykonosDevice_t *device, mykonosfirName_t filterToRead, mykonosFir_t *firFilter); + +/* + ***************************************************************************** + * Rx Data path functions + ***************************************************************************** + */ +mykonosErr_t MYKONOS_programRxGainTable(mykonosDevice_t *device, uint8_t *gainTablePtr, uint8_t numGainIndexesInTable, mykonosGainTable_t rxChannel); +mykonosErr_t MYKONOS_setRx1ManualGain(mykonosDevice_t *device, uint8_t gainIndex); +mykonosErr_t MYKONOS_setRx2ManualGain(mykonosDevice_t *device, uint8_t gainIndex); +mykonosErr_t MYKONOS_getRx1Gain(mykonosDevice_t *device, uint8_t *rx1GainIndex); +mykonosErr_t MYKONOS_getRx2Gain(mykonosDevice_t *device, uint8_t *rx2GainIndex); +mykonosErr_t MYKONOS_setupRxAgc(mykonosDevice_t *device); +mykonosErr_t MYKONOS_resetRxAgc(mykonosDevice_t *device); +mykonosErr_t MYKONOS_setRxAgcMinMaxGainIndex(mykonosDevice_t *device, mykonosRxChannels_t rxChannelSelect, uint8_t maxGainIndex, uint8_t minGainIndex); +mykonosErr_t MYKONOS_setObsRxAgcMinMaxGainIndex(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxChannelSelect, uint8_t maxGainIndex, uint8_t minGainIndex); +mykonosErr_t MYKONOS_setRx1TempGainComp(mykonosDevice_t *device, int16_t rx1TempCompGain_mdB); +mykonosErr_t MYKONOS_getRx1TempGainComp(mykonosDevice_t *device, int16_t *rx1TempCompGain_mdB); +mykonosErr_t MYKONOS_setRx2TempGainComp(mykonosDevice_t *device, int16_t rx2TempCompGain_mdB); +mykonosErr_t MYKONOS_getRx2TempGainComp(mykonosDevice_t *device, int16_t *rx2TempCompGain_mdB); +mykonosErr_t MYKONOS_setObsRxTempGainComp(mykonosDevice_t *device, int16_t obsRxTempCompGain_mdB); +mykonosErr_t MYKONOS_getObsRxTempGainComp(mykonosDevice_t *device, int16_t *obsRxTempCompGain_mdB); +mykonosErr_t MYKONOS_enableRxGainCtrSyncPulse(mykonosDevice_t *device, uint8_t enable); +mykonosErr_t MYKONOS_setRxGainControlMode(mykonosDevice_t *device, mykonosGainMode_t mode); +mykonosErr_t MYKONOS_getRx1DecPower(mykonosDevice_t *device, uint16_t *rx1DecPower_mdBFS); +mykonosErr_t MYKONOS_getRx2DecPower(mykonosDevice_t *device, uint16_t *rx2DecPower_mdBFS); + +/* + ***************************************************************************** + * Observation Rx Data path functions + ***************************************************************************** + */ +mykonosErr_t MYKONOS_setDefaultObsRxPath(mykonosDevice_t *device, mykonosObsRxChannels_t defaultObsRxCh); +mykonosErr_t MYKONOS_setObsRxPathSource(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxCh); +mykonosErr_t MYKONOS_getObsRxPathSource(mykonosDevice_t *device, mykonosObsRxChannels_t *obsRxCh); +mykonosErr_t MYKONOS_setObsRxManualGain(mykonosDevice_t *device, mykonosObsRxChannels_t obsRxCh, uint8_t gainIndex); +mykonosErr_t MYKONOS_getObsRxGain(mykonosDevice_t *device, uint8_t *gainIndex); +mykonosErr_t MYKONOS_setupObsRxAgc(mykonosDevice_t *device); +mykonosErr_t MYKONOS_enableObsRxGainCtrSyncPulse(mykonosDevice_t *device, uint8_t enable); +mykonosErr_t MYKONOS_setObsRxGainControlMode(mykonosDevice_t *device, mykonosGainMode_t mode); +mykonosErr_t MYKONOS_getObsRxDecPower(mykonosDevice_t *device, uint16_t *obsRxDecPower_mdBFS); + +/* + ***************************************************************************** + * Tx Data path functions + ***************************************************************************** + */ +mykonosErr_t MYKONOS_setTx1Attenuation(mykonosDevice_t *device, uint16_t tx1Attenuation_mdB); +mykonosErr_t MYKONOS_setTx2Attenuation(mykonosDevice_t *device, uint16_t tx2Attenuation_mdB); +mykonosErr_t MYKONOS_getTx1Attenuation(mykonosDevice_t *device, uint16_t *tx1Attenuation_mdB); +mykonosErr_t MYKONOS_getTx2Attenuation(mykonosDevice_t *device, uint16_t *tx2Attenuation_mdB); +mykonosErr_t MYKONOS_getTxFilterOverRangeStatus(mykonosDevice_t *device, uint8_t *txFilterStatus); +mykonosErr_t MYKONOS_enableTxNco(mykonosDevice_t *device, uint8_t enable, int32_t tx1ToneFreq_kHz, int32_t tx2ToneFreq_kHz); + +/* + ***************************************************************************** + * PA Protection Functions + ***************************************************************************** + */ +mykonosErr_t MYKONOS_setupPaProtection(mykonosDevice_t *device, uint16_t powerThreshold, uint8_t attenStepSize, uint8_t avgDuration, uint8_t stickyFlagEnable, uint8_t txAttenControlEnable); +mykonosErr_t MYKONOS_enablePaProtection(mykonosDevice_t *device, uint8_t enable); +mykonosErr_t MYKONOS_getDacPower(mykonosDevice_t *device, mykonosTxChannels_t channel, uint16_t *channelPower); +mykonosErr_t MYKONOS_getPaProtectErrorFlagStatus(mykonosDevice_t *device, uint8_t *errorFlagStatus); +mykonosErr_t MYKONOS_clearPaErrorFlag(mykonosDevice_t *device); + +/* + ***************************************************************************** + * Low level functions and helper functions. BBP should not need to call + ***************************************************************************** + */ +const char* getMykonosErrorMessage(mykonosErr_t errorCode); + +mykonosErr_t MYKONOS_initSubRegisterTables(mykonosDevice_t *device); +mykonosErr_t MYKONOS_setTxPfirSyncClk(mykonosDevice_t *device); /* Helper function */ +mykonosErr_t MYKONOS_setRxPfirSyncClk(mykonosDevice_t *device); /* Helper function */ + +/* + ***************************************************************************** + * Functions to configure DC offsets + ***************************************************************************** + */ +mykonosErr_t MYKONOS_setRfDcOffsetCnt(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint16_t measureCount); +mykonosErr_t MYKONOS_getRfDcOffsetCnt(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint16_t *measureCount); +mykonosErr_t MYKONOS_setDigDcOffsetMShift(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint8_t mShift); +mykonosErr_t MYKONOS_getDigDcOffsetMShift(mykonosDevice_t *device, mykonosDcOffsetChannels_t channel, uint8_t *mShift); +mykonosErr_t MYKONOS_setDigDcOffsetEn(mykonosDevice_t *device, uint8_t enableMask); +mykonosErr_t MYKONOS_getDigDcOffsetEn(mykonosDevice_t *device, uint8_t *enableMask); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonosMmap.c b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonosMmap.c new file mode 100644 index 00000000..076be0c6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonosMmap.c @@ -0,0 +1,136 @@ +/** + * \file mykonosMmap.c + * \brief Contains the Mykonos memory mapping + * + * Mykonos API version: 1.5.2.3566 + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#include +uint8_t mykonosMmap [] = {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x13,0x03,0x03,0x13,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01, + 0x00,0xE4,0xE4,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xA5,0xA5,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x01,0x00,0xE4,0xE4,0x00,0x00,0x00,0x1F,0x00,0x14,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}; +/*!< Mykonos memory map */ diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_gpio.c b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_gpio.c new file mode 100644 index 00000000..caf1e04c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_gpio.c @@ -0,0 +1,5357 @@ +/** + *\file mykonos_gpio.c + * + *\brief Contains Mykonos APIs for transceiver GPIO configuration and control. + * + * Mykonos API version: 1.5.2.3566 + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#include +#include +#include "../common.h" +#include "mykonos.h" +#include "mykonos_gpio.h" +#include "mykonos_macros.h" +#include "mykonos_user.h" + + +/** + * \brief Helper function for return of character string based on 32-bit mykonosGpioErr_t enum value + * + * To save codespace, these error strings are ifdef'd out unless the user + * adds a define MYKONOS_VERBOSE to their workspace. This function can be + * useful for debug. Each function also returns unique error codes to + * make it easier to determine where the code broke. + * + * \param errorCode is enumerated error code value + * + * \return Returns character string based on enumerated value + */ +const char* getGpioMykonosErrorMessage(mykonosGpioErr_t errorCode) +{ +#if MYKONOS_VERBOSE == 0 + return ""; + + #else + + switch (errorCode) + { + case MYKONOS_ERR_GPIO_OK: + return ""; + + case MYKONOS_ERR_EN_MONITOR_OUT_NOT_ENABLED: + return "MYKONOS_setGpioMonitorOut() Mykonos monitor output not enable, please run GPIO setup with the correct setup for enabling the monitor output functionality\n"; + + case MYKONOS_ERR_MONITOR_OUT_INDEX_RANGE: + return "MYKONOS_setGpioMonitorOut()The index specified is incorrect, index available are from 0x01 to 0x42\n"; + + case MYKONOS_ERR_GETGPIOMON_INDEX_NULL_PARM: + return "MYKONOS_getGpioMonitorOut() if the monitorIndex is null.\n"; + + case MYKONOS_ERR_GETGPIOMON_MONITORMASK_NULL_PARM: + return "MYKONOS_getGpioMonitorOut() if the monitorMask is null.\n"; + + case MYKONOS_ERR_MGCRX1_STEP_INV_PARAM: + return "MYKONOS_setRx1GainCtrlPin() An invalid step size has been passed, valid step sizes for increment/decrement is 0-7\n"; + + case MYKONOS_ERR_MGCRX1_GPIO_DECPIN_INV_PARAM: + return "MYKONOS_setRx1GainCtrlPin() An invalid decrement pin has been passed \n"; + + case MYKONOS_ERR_MGCRX1_GPIO_INCPIN_INV_PARAM: + return "MYKONOS_setRx1GainCtrlPin() An invalid increment pin has been passed, \n"; + + case MYKONOS_ERR_MGCRX2_STEP_INV_PARAM: + return "MYKONOS_setRx2GainCtrlPin() An invalid step size has been passed, valid step sizes for increment/decrement is 0-7\n"; + + case MYKONOS_ERR_MGCRX2_GPIO_DECPIN_INV_PARAM: + return "MYKONOS_setRx2GainCtrlPin() An invalid decrement pin has been passed\n"; + + case MYKONOS_ERR_MGCRX2_GPIO_INCPIN_INV_PARAM: + return "MYKONOS_setRx2GainCtrlPin() An invalid increment pin has been passed\n"; + + case MYKONOS_ERR_GETRX1PIN_INCSTEP_NULL_PARM: + return "MYKONOS_getRx1GainCtrlPin() if a null value has been passed to incStep.\n"; + + case MYKONOS_ERR_GETRX1PIN_DECSTEP_NULL_PARM: + return "MYKONOS_getRx1GainCtrlPin() if a null value has been passed to decStep.\n"; + + case MYKONOS_ERR_GETRX1PIN_INCPIN_NULL_PARM: + return "MYKONOS_getRx1GainCtrlPin() if a null value has been passed to rx1GainIncPin.\n"; + + case MYKONOS_ERR_GETRX1PIN_DECPIN_NULL_PARM: + return "MYKONOS_getRx1GainCtrlPin() if a null value has been passed to rx1GainDecPin.\n"; + + case MYKONOS_ERR_GETRX1PIN_EN_NULL_PARM: + return "MYKONOS_getRx1GainCtrlPin() if a null value has been passed to enable.\n"; + + case MYKONOS_ERR_GETRX2PIN_INCSTEP_NULL_PARM: + return "MYKONOS_getRx2GainCtrlPin() if a null value has been passed to incStep.\n"; + + case MYKONOS_ERR_GETRX2PIN_DECSTEP_NULL_PARM: + return "MYKONOS_getRx2GainCtrlPin() if a null value has been passed to decStep.\n"; + + case MYKONOS_ERR_GETRX2PIN_INCPIN_NULL_PARM: + return "MYKONOS_getRx2GainCtrlPin() if a null value has been passed to rx1GainIncPin.\n"; + + case MYKONOS_ERR_GETRX2PIN_DECPIN_NULL_PARM: + return "MYKONOS_getRx2GainCtrlPin() if a null value has been passed to rx1GainDecPin.\n"; + + case MYKONOS_ERR_GETRX2PIN_EN_NULL_PARM: + return "MYKONOS_getRx2GainCtrlPin() if a null value has been passed to enable.\n"; + + case MYKONOS_ERR_TPCTX1_GPIO_STEP_INV_PARAM: + return "MYKONOS_setTx1AttenCtrlPin() An invalid step size has been passed, valid step sizes for att are 0x00-0x1F\n"; + + case MYKONOS_ERR_TPCTX1_GPIO_INCPIN_INV_PARAM: + return "MYKONOS_setTx1AttenCtrlPin() An invalid decrement pin has been passed\n"; + + case MYKONOS_ERR_TPCTX1_GPIO_DECPIN_INV_PARAM: + return "MYKONOS_setTx1AttenCtrlPin() An invalid decrement pin has been passed\n"; + + case MYKONOS_ERR_TPCTX2_GPIO_STEP_INV_PARAM: + return "MYKONOS_setTx2AttenCtrlPin() An invalid step size has been passed, valid step sizes for att are 0x00-0x1F\n"; + + case MYKONOS_ERR_TPCTX2_GPIO_INCPIN_INV_PARAM: + return "MYKONOS_setTx2AttenCtrlPin() An invalid decrement pin has been passed\n"; + + case MYKONOS_ERR_TPCTX2_GPIO_DECPIN_INV_PARAM: + return "MYKONOS_setTx2AttenCtrlPin() An invalid decrement pin has been passed\n"; + + case MYKONOS_ERR_GETTX2PIN_STEP_NULL_PARM: + return "MYKONOS_getTx2AttenCtrlPin() if a null value has been passed to stepSize.\n"; + + case MYKONOS_ERR_GETTX2PIN_INC_NULL_PARM: + return "MYKONOS_getTx2AttenCtrlPin() if a null value has been passed to tx2AttenIncPin.\n"; + + case MYKONOS_ERR_GETTX2PIN_DEC_NULL_PARM: + return "MYKONOS_getTx2AttenCtrlPin() if a null value has been passed to tx2AttenDecPin.\n"; + + case MYKONOS_ERR_GETTX2PIN_EN_NULL_PARM: + return "MYKONOS_getTx2AttenCtrlPin() if a null value has been passed to enable.\n"; + + case MYKONOS_ERR_GETTX2PIN_TX1TX2_NULL_PARM: + return "MYKONOS_getTx2AttenCtrlPin() if a null value has been passed to useTx1ForTx2.\n"; + + case MYKONOS_ERR_GETTX1PIN_STEP_NULL_PARM: + return "MYKONOS_getTx1AttenCtrlPin() if a null value has been passed to stepSize.\n"; + + case MYKONOS_ERR_GETTX1PIN_INC_NULL_PARM: + return "MYKONOS_getTx1AttenCtrlPin() if a null value has been passed to tx1AttenIncPin.\n"; + + case MYKONOS_ERR_GETTX1PIN_DEC_NULL_PARM: + return "MYKONOS_getTx1AttenCtrlPin() if a null value has been passed to tx1AttenDecPin.\n"; + + case MYKONOS_ERR_GETTX1PIN_EN_NULL_PARM: + return "MYKONOS_getTx1AttenCtrlPin() if a null value has been passed to enable.\n"; + + case MYKONOS_ERR_GETTX1PIN_TX1TX2_NULL_PARM: + return "MYKONOS_getTx1AttenCtrlPin() if a null value has been passed to useTx1ForTx2.\n"; + + case MYKONOS_ERR_GPIO_SRC_PARAM_INV: + return "MYKONOS_setGpioSourceCtrl() An invalid source control parameter has been passed\n"; + + case MYKONOS_ERR_GETGPIOSETLEVEL_NULL_PARM: + return "MYKONOS_getGpioSetLevel() gpioPinSetLevel pointer is NULL in function parameter\n"; + + case MYKONOS_ERR_READGPIOSPI_NULL_PARM: + return "MYKONOS_readGpioPinLevel() has a null *gpioPinLevel parameter\n"; + + case MYKONOS_ERR_GETGPIO3V3SPI_NULL_PARM: + return "MYKONOS_getGpio3v3PinLevel() has a null *gpio3v3PinLevel parameter\n"; + + case MYKONOS_ERR_SETUPAUXDAC_NULL_PARAM: + return "MYKONOS_setupAuxDac() has a null device->auxIo pointer\n"; + + case MYKONOS_ERR_GPIO3V3OUTEN_NULL_PARM: + return "MYKONOS_getGpio3v3Oe() has NULL pointer for function parameter gpio3v3OutEn\n;"; + + case MYKONOS_ERR_INV_GP_INT_MASK_PARM: + return "General Purpose Interrupt source mask parameter is invalid\n"; + + case MYKONOS_ERR_GP_INT_STATUS_NULL_PARAM: + return "MYKONOS_readGpInterruptStatus() has NULL status parameter\n"; + + case MYKONOS_ERR_SET_GPIO_3V3_INV_MODE: + return "Invalid GPIO3v3 source control mode\n"; + + case MYKONOS_ERR_SET_GPIO_3V3_INV_SRC_CTRL: + return "gpio3v3 members have invalid value for the GPIO3v3 source control mode.\n"; + + case MYKONOS_ERR_SET_GPIO_1V8_INV_MODE: + return "The GPIO mode enum is not a valid value in MYKONOS_setupGpio\n"; + + case MYKONOS_ERR_GETGPIO3V3OUT_NULL_PARM: + return "MYKONOS_getGpio3v3SetLevel() has NULL pointer for function parameter gpio3v3SetLevel\n"; + + case MYKONOS_ERR_GPIO_OE_INV_PARAM: + return "MYKONOS_setGpioOe() had invalid parameter gpioOutEn (valid range 0 - 0x07FFFF)\n"; + + case MYKONOS_ERR_GETGPIO_OE_NULL_PARM: + return "MYKONOS_getGpioOe() has NULL function parameter\n"; + + case MYKONOS_ERR_WRITEAUXDAC_NULL_AUXIO: + return "device->auxIo structure has NULL pointer in MYKONOS_writeAuxDac()\n"; + + case MYKONOS_ERR_READAUXADC_NULL_PARAM: + return "MYKONOS_readAuxAdc() has NULL function parameter\n"; + + case MYKONOS_ERR_SET_GPIO_3V3_INV_POINTER: + return "Invalid pointer detected in MYKONOS_setupGpio3v3()\n"; + + case MYKONOS_ERR_SET_GPIO_1V8_INV_POINTER: + return "Invalid pointer detected in MYKONOS_setupGpio()\n"; + + case MYKONOS_ERR_SET_ARMGPIO_INV_POINTER: + return "Invalid pointer detected at device->auxIo->armGpio in MYKONOS_setArmGpioPins() \n"; + + case MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR: + return "ARM Command Error in MYKONOS_setArmGpioPins()\n"; + + case MYKONOS_ERR_SET_ARMGPIO_PINS_INV_SIGNALID: + return "Invalid Signal ID detected in device->auxIo->armGpio \n"; + + case MYKONOS_ERR_SET_ARMGPIO_PINS_INV_GPIOPIN: + return "Out of range GPIO pin detected \n"; + + case MYKONOS_ERR_SETUPAUXDAC_INV_AUXDACCODE: + return "device->auxIo->auxDacValue, AUXDAC value out of range in MYKONOS_setupAuxDacs()\n"; + + case MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACCODE: + return "auxDacCode value out of range in MYKONOS_writeAuxDac()\n"; + + case MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACINDEX: + return "auxDacIndex value out of range in MYKONOS_writeAuxDac()\n"; + + case MYKONOS_ERR_INV_AUX_ADC_CHAN_PARM: + return "auxAdcChannel value out of range in MYKONOS_setAuxAdcChannel()\n"; + + case MYKONOS_ERR_SETUPAUXADC_INV_VCODIV: + return "device->clocks->clkPllVcoDiv value not supported in MYKONOS_setupAuxAdcs()\n"; + + case MYKONOS_ERR_INV_AUX_ADC_DEC_PARM: + return "adcDecimation value out of range in MYKONOS_setupAuxAdcs()\n"; + + case MYKONOS_ERR_SLICER_INV_RX1_SEL: + return "invalid RX1 GPIO pin selection for Slicer control in MYKONOS_setRxSlicerCtrl()\n"; + + case MYKONOS_ERR_SLICER_INV_RX2_SEL: + return "invalid RX2 GPIO pin selection for Slicer control in MYKONOS_setRxSlicerCtrl()\n"; + + case MYKONOS_ERR_SLICER_STEP_OUT_OF_RANGE: + return "slicer step is out of range for the SLicer control in MYKONOS_setRxSlicerCtrl()\n"; + + case MYKONOS_ERR_SLICER_EN_INV: + return "invalid enable in MYKONOS_setRxSlicerCtrl()\n"; + + case MYKONOS_ERR_SLICER_RX1PIN_NULL_PARM: + return "rx1Pins is null pointer for the passed parameter in MYKONOS_getRxSlicerCtrl()\n"; + + case MYKONOS_ERR_SLICER_RX2PIN_NULL_PARM: + return "rx1Pins is null pointer for the passed parameter in MYKONOS_getRxSlicerCtrl()\n"; + + case MYKONOS_ERR_SLICER_STEP_NULL_PARM: + return "slicerStep is null pointer for the passed parameter in MYKONOS_getRxSlicerCtrl()\n"; + + case MYKONOS_ERR_SLICER_EN_NULL_PARM: + return "enable is null pointer for the passed parameter in MYKONOS_getRxSlicerCtrl()\n"; + + case MYKONOS_ERR_GAINCOMP_NULL_STRUCT: + return "gain compensation structure gainComp is not initialised in MYKONOS_getRxGainCompensation()\n"; + + case MYKONOS_ERR_GAINCOMP_EN_NULL_PARM: + return "enable is null pointer for the passed parameter in MYKONOS_getRxGainCompensation()\n"; + + case MYKONOS_ERR_GAINCOMP_SET_NULL_STRUCT: + return "gain compensation structure gainComp is not initialised in MYKONOS_setRxGainCompensation()\n"; + + case MYKONOS_ERR_GAINCOMP_INV_RX1_OFFSET: + return "gain compensation structure gainComp->rx1Offset is invalid in MYKONOS_setRxGainCompensation()\n"; + + case MYKONOS_ERR_GAINCOMP_INV_RX2_OFFSET: + return "gain compensation structure gainComp->rx2Offset is invalid in MYKONOS_setRxGainCompensation()\n"; + + case MYKONOS_ERR_GAINCOMP_INV_STEP: + return "gain compensation structure gainComp->compStep is invalid in MYKONOS_setRxGainCompensation()\n"; + + case MYKONOS_ERR_GAINCOMP_INV_EN: + return "enable is not valid in MYKONOS_setRxGainCompensation()\n"; + + case MYKONOS_ERR_FLOATFRMT_NULL_STRUCT: + return "floating point formatter structure floatFrmt not initialised in MYKONOS_getFloatPointFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_SET_NULL_STRUCT: + return "floating point formatter structure floatFrmt not initialised in MYKONOS_setFloatPointFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_INV_ROUND_MODE: + return "floating point formatter structure floatFrmt.roundMode not valid parameter in MYKONOS_setFloatPointFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_INV_DATA_FORMAT: + return "floating point formatter structure floatFrmt.dataFormat not valid parameter in MYKONOS_setFloatPointFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_INV_ENC_NAN: + return "floating point formatter structure floatFrmt.encNan not valid parameter in MYKONOS_setFloatPointFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_INV_EXP_BITS: + return "floating point formatter structure floatFrmt.expBits not valid parameter in MYKONOS_setFloatPointFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_INV_LEADING: + return "floating point formatter structure floatFrmt.leading not valid parameter in MYKONOS_setFloatPointFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_INV_RX1ATT: + return "not valid rx1 attenuation parameter passed in MYKONOS_setFloatPointFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_INV_RX2ATT: + return "not valid rx2 attenuation parameter passed in MYKONOS_setFloatPointFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_SET_INV_RX2ATT: + return "not valid rx2 attenuation parameter passed in MYKONOS_setRxEnFloatPntFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_SET_INV_RX1ATT: + return "not valid rx1 attenuation parameter passed in MYKONOS_setRxEnFloatPntFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_SET_INV_EN: + return "not valid enable parameter passed in MYKONOS_setRxEnFloatPntFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_NULL_RX1ATT: + return "null pointer passed for rx1 attenuation in MYKONOS_setRxEnFloatPntFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_NULL_RX2ATT: + return "null pointer passed for rx2 attenuation in MYKONOS_setRxEnFloatPntFrmt()\n"; + + case MYKONOS_ERR_FLOATFRMT_NULL_ENABLE: + return "null pointer passed for enable in MYKONOS_setRxEnFloatPntFrmt()\n"; + + case MYKONOS_ERR_SETUPTEMPSENSOR_NULL_PARAM: + return "MYKONOS_setupTempSensor() has NULL function parameter\n"; + + case MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPDECIMATION: + return "tempDecimation value out of range in MYKONOS_setupTempSensor()\n"; + + case MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPWINDOW: + return "tempWindow value out of range in MYKONOS_setupTempSensor()\n"; + + case MYKONOS_ERR_SETUPTEMPSENSOR_INV_OFFSET: + return "offset value out of range in MYKONOS_setupTempSensor()\n"; + + case MYKONOS_ERR_GETTEMPSENSORCFG_NULL_PARAM: + return "MYKONOS_getTempSensorConfig() has NULL function parameter\n"; + + case MYKONOS_ERR_READTEMPSENSOR_NULL_PARAM: + return "MYKONOS_readTempSensor() has NULL function parameter\n"; + + case MYKONOS_ERR_READTEMPSENSOR_NOT_LOCKED: + return "MYKONOS_readTempSensor() temperature sensor reading is not locked\n"; + + case MYKONOS_ERR_GPIO_HYBRID_RX1_PIN: + return "MYKONOS_setRxHybridGainChangePin() not valid pin has been passed for RX1 hybrid gain control.\n"; + + case MYKONOS_ERR_GPIO_HYBRID_RX2_PIN: + return "MYKONOS_setRxHybridGainChangePin() not valid pin has been passed for RX2 hybrid gain control.\n"; + + case MYKONOS_ERR_GPIO_HYBRID_ORX_PIN: + return "MYKONOS_setObsRxHybridGainChangePin() if invalid pin has been passed for ORX hybrid gain control.\n"; + + case MYKONOS_ERR_AGC_OBS_NOT_IN_HYBRID: + return "MYKONOS_setObsRxHybridGainChangePin() if the observation gain mode is not set to Hybrid.\n"; + + case MYKONOS_ERR_GPIO_HYBRID_RX1_PIN_NULL_PARM: + return "MYKONOS_getRxHybridGainChangePin() null value has been passed to rx1GainChangePin.\n"; + + case MYKONOS_ERR_GPIO_HYBRID_RX2_PIN_NULL_PARM: + return "MYKONOS_getRxHybridGainChangePin() null value has been passed to rx1GainChangePin.\n"; + + case MYKONOS_ERR_GAIN_CONTROL_NOT_HYBRID: + return "MYKONOS_setRxHybridGainChangePin() if gain control is not hybrid.\n"; + + case MYKONOS_ERR_GAIN_CONTROL_NOT_AGC : + return "MYKONOS_setRxAgcEnSyncPin() or MYKONOS_getObsRxAgcEnSyncPin() if the observation gain control mode is not set to AGC.\n"; + + case MYKONOS_ERR_OBS_GAIN_CONTROL_NOT_AGC: + return "MYKONOS_getObsRxAgcEnSyncPin() if the observation gain control mode is not set to AGC.\n"; + + case MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN: + return "MYKONOS_setRxAgcEnSyncPin() if invalid pin has been passed for RX1 AGC sync gain control.\n"; + + case MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN: + return "MYKONOS_setRxAgcEnSyncPin() if invalid pin has been passed for RX2 AGC sync gain control.\n"; + + case MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN_NULL_PARM: + return "MYKONOS_getRxAgcEnSyncPin() if a null value has been passed to rx1AgcSyncPin.\n"; + + case MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN_NULL_PARM: + return "MYKONOS_getRxAgcEnSyncPin() if a null value has been passed to rx2AgcSyncPin.\n"; + + case MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN: + return "MYKONOS_setObsRxAgcEnSyncPin() if invalid pin has been passed for ORX AGC sync gain control.\n"; + + case MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN_NULL_PARM: + return "MYKONOS_getObsRxAgcEnSyncPin() if a null value has been passed to obsRxAgcSyncPin.\n"; + + case MYKONOS_ERR_SLICER_INV_OBS_RX_SEL: + return "Invalid observation channel GPIO pin selection for Slicer control passed to MYKONOS_setObsRxSlicerCtrl().\n"; + + case MYKONOS_ERR_SLICER_OBS_RX_STEP_OUT_OF_RANGE: + return "Slicer step is out of range passed to MYKONOS_setObsRxSlicerCtrl().\n"; + + case MYKONOS_ERR_SLICER_OBS_RX_EN_INV: + return "Invalid enable passed to MYKONOS_setObsRxSlicerCtrl().\n"; + + case MYKONOS_ERR_SLICER_OBS_RXPIN_NULL_PARM: + return "ObsRxPins is null pointer for the passed parameter passed to MYKONOS_getObsRxSlicerCtrl().\n"; + + case MYKONOS_ERR_SLICER_OBS_RX_STEP_NULL_PARM: + return "SlicerStep is null pointer for the passed parameter passed to MYKONOS_getObsRxSlicerCtrl().\n"; + + case MYKONOS_ERR_SLICER_OBS_RX_EN_NULL_PARM: + return "Enable is null pointer for the passed parameter passed to MYKONOS_getObsRxSlicerCtrl().\n"; + + case MYKONOS_ERR_OBS_RX_GAINCOMP_SET_NULL_STRUCT: + return "Gain compensation structure gainComp is not initialised in MYKONOS_setObsRxGainCompensation().\n"; + + case MYKONOS_ERR_OBS_RX_GAINCOMP_INV_OFFSET: + return "Gain compensation structure gainComp->obsRxOffset is invalid in MYKONOS_setObsRxGainCompensation().\n"; + + case MYKONOS_ERR_OBS_RX_GAINCOMP_INV_STEP: + return "Gain compensation structure gainComp->compStep is invalid in MYKONOS_setObsRxGainCompensation().\n"; + + case MYKONOS_ERR_OBS_RX_GAINCOMP_INV_EN: + return "Enable is not valid in MYKONOS_setObsRxGainCompensation().\n"; + + case MYKONOS_ERR_OBS_RX_GAINCOMP_NULL_STRUCT: + return "Observation channel gain compensation structure gainComp is not initialised in MYKONOS_getObsRxGainCompensation().\n"; + + case MYKONOS_ERR_OBS_RX_GAINCOMP_EN_NULL_PARAM: + return "enabled is null pointer for the parameter passed to MYKONOS_getObsRxGainCompensation().\n"; + + case MYKONOS_ERR_GETGPIODRV_NULL_PARAM: + return "Null parameter passed to the function MYKONOS_getGpioDrv().\n"; + + case MYKONOS_ERR_GPIO_DRV_INV_PARAM: + return "GPIO out of range passed to function MYKONOS_setGpioDrv(), valid GPIOs are in the range 0x00000 to 0x7FFFF.\n"; + + case MYKONOS_ERR_GPIO_SLEW_RATE_INV_PARAM: + return "GPIO out of range -valid GPIOs are in the range 0x00000 to 0x7FFFF.\n"; + + case MYKONOS_ERR_GPIO_GETSLEW_NULL_PARAM: + return "Null parameter passed to the function MYKONOS_getGpioSlewRate().\n"; + + case MYKONOS_ERR_CMOS_DRV_NULL_PARAM: + return "Null parameter passed to the function.\n"; + + case MYKONOS_ERR_CMOS_DRV_INV_PARAM: + return "Incorrect drive strength, valid settings are given by mykonosCmosPadDrvStr_t.\n"; + + case MYKONOS_ERR_SPI2_INV_GPIO: + return "if an invalid GPIO pin configuration is passed to MYKONOS_spi2GpioSetup().\n"; + + case MYKONOS_ERR_GET_GPIO_SOURCE_CONTROL_NULL_PARM: + return "Null parameter passed to the function MYKONOS_getGpioSourceCtrl().\n"; + + default: + return "Unknown error was encountered.\n"; + } + + #endif +} + +/** + * \brief This API function configures the monitor output function for the GPIOs + * + * The monitor outputs are grouped in set of nibbles, the user can set + * individual nibbles for having the monitor output function across the available GPIO. + * In order to enable the GPIO monitor function the function setupGpio has to be run and the + * structure should have the proper setup: + * - device->auxIo->gpio->gpioOe = 0xXXXFF the first D7:D0 GPIOs will have the output enable + * - device->auxIo->gpio->gpioSrcCtrl3_0 = GPIO_MONITOR_MODE + * - device->auxIo->gpio->gpioSrcCtrl4_7 = GPIO_MONITOR_MODE + + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * - device->auxIo->gpio->gpioOe + * - device->auxIo->gpio->gpioSrcCtrl3_0 + * - device->auxIo->gpio->gpioSrcCtrl4_7 + * + * \param device is structure pointer to the Mykonos data structure containing settings + * + * \param monitorIndex which will be the index at which the outputs are going to be set. see table in documentation + * + * \param monitorMask which GPIO outputs are going to active, the available GPIO + * bit 0 will represent MYKGPIO0 and bit 7 will represent MYKGPIO7. + * + * \retval MYKONOS_ERR_MONITOR_OUT_INDEX_RANGE if GPIO Monitor output index is not in table + * \retval MYKONOS_ERR_EN_MONITOR_OUT_NOT_ENABLED if GPIO source control not set for Monitor output + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setGpioMonitorOut(mykonosDevice_t *device, uint8_t monitorIndex, uint8_t monitorMask) +{ + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + + const uint8_t INDEX_MASK = 0x42; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setGpioMonitorOut()\n"); +#endif + + /* Error checking for correct index. */ + if (monitorIndex > INDEX_MASK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_MONITOR_OUT_INDEX_RANGE, + getGpioMykonosErrorMessage(MYKONOS_ERR_MONITOR_OUT_INDEX_RANGE)); + return MYKONOS_ERR_MONITOR_OUT_INDEX_RANGE; + } + + /* Set the GPIO monitor index and the required pin configuration. */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GPIO_MONITOR_INDEX, monitorIndex); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GPIO_MONITOR_ENABLE, monitorMask); + + return error; +} + +/** + * \brief This API function reads the GPIO monitor index from Mykonos + * + * The monitor outputs are grouped in two set of nibbles, the user can set + * individual nibbles for having the monitor output function, this nibbles + * will output the monitor output as per the index set. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * - GPIO output enable + * - GPIO source control + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param monitorIndex which will be the index at which the outputs are set to. + * \param monitorMask which will be enable the monitor function. + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_GETGPIOMON_INDEX_NULL_PARM if the monitorIndex is null. + * \retval MYKONOS_ERR_GETGPIOMON_MONITORMASK_NULL_PARM if the monitorMask is null. + */ +mykonosGpioErr_t MYKONOS_getGpioMonitorOut(mykonosDevice_t *device, uint8_t *monitorIndex, uint8_t *monitorMask) +{ + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + + uint8_t indexRd = 0; + uint8_t monMaskRd = 0; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getGpioMonitorOut()\n"); +#endif + + /* Checking for null passed parameters */ + if (monitorIndex == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETGPIOMON_INDEX_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETGPIOMON_INDEX_NULL_PARM)); + return MYKONOS_ERR_GETGPIOMON_INDEX_NULL_PARM; + } + + if (monitorMask == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETGPIOMON_MONITORMASK_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETGPIOMON_MONITORMASK_NULL_PARM)); + return MYKONOS_ERR_GETGPIOMON_MONITORMASK_NULL_PARM; + } + + /* Get GPIO monitor out enable. */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_MONITOR_ENABLE, &monMaskRd); + + /* Get the GPIO monitor index and the required pin configuration. */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_MONITOR_INDEX, &indexRd); + + /* assigning return values to the pointers passed */ + *monitorMask = monMaskRd; + *monitorIndex = indexRd; + + return error; +} + + + + +/** + * \brief This API function configures the GPIO inputs for controlling RX gain + * + * This API function configures the GPIO input pin and step size to allow the BBP to control gain changes in Rx1 signal chain. + * A high pulse on the 'rx1GainIncPin' in pin control mode will increment the gain by the value set in incStep'. + * A high pulse on the 'rx1GainDecPin' in pin control mode will decrement the gain by the value set in 'decStep'. + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + + * + * \param device is structure pointer to the Mykonos data structure containing settings + * + * \param incStep This sets the change (increase) in gain index that is applied when the + * increment gain pin (in MGC pin control mode) is pulsed. + * + * \param decStep This configures the decrement in gain index that should be applied + * when the decrement gain pin (in MGC pin control mode) is pulsed. + * + * \param rx1GainIncPin mykonosGpioSelect_t These bits select the GPIO used as the enable for + * the Rx1 Manual Increment gain input according to the following: + * MYKGPIO0 or MYKGPIO10 + * + * \param rx1GainDecPin mykonosGpioSelect_t These bits select the GPIO used as the enable for + * the Rx1 Manual Decrement gain input according to the following: + * MYKGPIO1 or MYKGPIO11 + * + * \param enable 0 = Disable the gain pin control for Rx1 + * 1 = enable the gain pin control for Rx1 + * + * \retval MYKONOS_ERR_MGCRX1_STEP_INV_PARAM if an invalid step size has been passed + * \retval MYKONOS_ERR_MGCRX1_GPIO_INCPIN_INV_PARAM if invalid increment pin has been passed + * \retval MYKONOS_ERR_MGCRX1_GPIO_DECPIN_INV_PARAM if invalid decrement pin has been passed + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setRx1GainCtrlPin(mykonosDevice_t *device, uint8_t incStep, uint8_t decStep, mykonosGpioSelect_t rx1GainIncPin, mykonosGpioSelect_t rx1GainDecPin, uint8_t enable) +{ + uint8_t wrtPin = 0x00; + uint8_t wrtStep = 0x00; + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + + const uint8_t SHIFT_CH1 = 0x00; + const uint8_t SHIFT_INC = 0x05; + const uint8_t SHIFT_DEC = 0x02; + const uint8_t MAX_STEP = 0x07; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setRx1GainCtrlPin()\n"); +#endif + + /* If enable then check for the next otherwise go directly to disable */ + if (enable > 0) + { + /* Error checking for correct step. */ + if ((uint8_t)(incStep > MAX_STEP) || (uint8_t)(decStep > MAX_STEP)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_MGCRX1_STEP_INV_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_MGCRX1_STEP_INV_PARAM)); + return MYKONOS_ERR_MGCRX1_STEP_INV_PARAM; + } + + /* Pin configuration assignment*/ + switch (rx1GainIncPin) + { + case MYKGPIO0: + wrtPin |= 0x00; + break; + case MYKGPIO10: + wrtPin |= 0x04; + break; + + default: + return MYKONOS_ERR_MGCRX1_GPIO_INCPIN_INV_PARAM; + } + + switch (rx1GainDecPin) + { + case MYKGPIO1: + wrtPin |= 0x00; + break; + case MYKGPIO11: + wrtPin |= 0x01; + break; + + default: + return MYKONOS_ERR_MGCRX1_GPIO_DECPIN_INV_PARAM; + } + } + + /* Setting increment step. */ + wrtStep = (uint8_t)(incStep<spiSettings, MYKONOS_ADDR_AGC_MANUAL_GAIN_CFG, wrtStep, 0xFD, 0); + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_MANUAL_GAIN_GPIO_SEL, wrtPin, 0x0F, 0); + + return error; +} + +/** + * \brief This API function returns the configuration RX1 gain Pin control + * + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param incStep will contain the step that is used for increment. + * \param decStep will contain the step that is used for decrement. + * \param rx1GainIncPin this will have the pin used for increment. + * \param rx1GainDecPin this will have the pin used for decrement. + * \param enable will contain the enable status for this channel if it is set to 1 then this + * function is enable for this channel, if it is 0 it is not enable + * + * \retval MYKONOS_ERR_GETRX1PIN_INCSTEP_NULL_PARM if a null value has been passed to incStep + * \retval MYKONOS_ERR_GETRX1PIN_DECSTEP_NULL_PARM if a null value has been passed to decStep + * \retval MYKONOS_ERR_GETRX1PIN_INCPIN_NULL_PARM if a null value has been passed to rx1GainIncPin + * \retval MYKONOS_ERR_GETRX1PIN_DECPIN_NULL_PARM if a null value has been passed to rx1GainDecPin + * \retval MYKONOS_ERR_GETRX1PIN_EN_NULL_PARM if a null value has been passed to enable + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getRx1GainCtrlPin(mykonosDevice_t *device, uint8_t *incStep, uint8_t *decStep, mykonosGpioSelect_t *rx1GainIncPin, mykonosGpioSelect_t *rx1GainDecPin, uint8_t *enable) +{ + uint8_t readVal = 0x00; + + const uint8_t MASK_GPIO_CH1 = 0x0F; + const uint8_t MASK_EN_CH1 = 0x01; + const uint8_t MASK_STEP_INC = 0xE0; + const uint8_t MASK_STEP_DEC = 0x1C; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getRx1GainCtrlPin()\n"); +#endif + + /* Checking for null passed parameters */ + if (incStep == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRX1PIN_INCSTEP_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETRX1PIN_INCSTEP_NULL_PARM)); + return MYKONOS_ERR_GETRX1PIN_INCSTEP_NULL_PARM; + } + + if (decStep == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRX1PIN_DECSTEP_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETRX1PIN_DECSTEP_NULL_PARM)); + return MYKONOS_ERR_GETRX1PIN_DECSTEP_NULL_PARM; + } + + if (rx1GainIncPin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRX1PIN_INCPIN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETRX1PIN_INCPIN_NULL_PARM)); + return MYKONOS_ERR_GETRX1PIN_INCPIN_NULL_PARM; + } + + if (rx1GainDecPin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRX1PIN_DECPIN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETRX1PIN_DECPIN_NULL_PARM)); + return MYKONOS_ERR_GETRX1PIN_DECPIN_NULL_PARM; + } + + if (enable == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRX1PIN_EN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETRX1PIN_EN_NULL_PARM)); + return MYKONOS_ERR_GETRX1PIN_EN_NULL_PARM; + } + + /* Getting Pin configuration assignment*/ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_AGC_MANUAL_GAIN_GPIO_SEL, &readVal); + readVal = readVal & MASK_GPIO_CH1; + + if (readVal & 0x04) + { + *rx1GainIncPin = MYKGPIO10; + } + else + { + *rx1GainIncPin = MYKGPIO0; + } + + if (readVal & 0x01) + { + *rx1GainDecPin = MYKGPIO11; + } + else + { + *rx1GainDecPin = MYKGPIO1; + } + + /* Getting Pin configuration assignment*/ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_AGC_MANUAL_GAIN_CFG, &readVal); + + *enable = readVal & MASK_EN_CH1; + + *incStep = (readVal & MASK_STEP_INC) >> 5; + + *decStep = (readVal & MASK_STEP_DEC) >> 2; + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief This API function configures the GPIO inputs for controlling RX gain + * + * This API function configures the GPIO input pin and step size to allow the BBP to control gain changes in Rx2 signal chain. + * A high pulse on the 'rx2GainIncPin' in pin control mode will increment the gain by the value set in incStep'. + * A high pulse on the 'rx2GainDecPin' in pin control mode will decrement the gain by the value set in 'decStep'. + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + + * + * \param device is structure pointer to the Mykonos data structure containing settings + * + * \param incStep This sets the change (increase) in gain index that is applied when the + * increment gain pin (in MGC pin control mode) is pulsed. + * + * \param decStep This configures the decrement in gain index that should be applied + * when the decrement gain pin (in MGC pin control mode) is pulsed. + * + * \param rx2GainIncPin mykonosGpioSelect_t These bits select the GPIO used as the enable for + * the Rx2 Manual Increment gain input according to the following: + * MYKGPIO3 or MYKGPIO13 + * + * \param rx2GainDecPin mykonosGpioSelect_t These bits select the GPIO used as the enable for + * the Rx2 Manual Decrement gain input according to the following: + * MYKGPIO4 or MYKGPIO14 + * + * \param enable 0 = Disable the gain pin control for Rx2 + * 1 = enable the gain pin control for Rx2 + * + * + * \retval MYKONOS_ERR_MGCRX2_STEP_INV_PARAM if an invalid step size is passed + * \retval MYKONOS_ERR_MGCRX2_GPIO_INCPIN_INV_PARAM if invalid increment pin has been passed + * \retval MYKONOS_ERR_MGCRX2_GPIO_DECPIN_INV_PARAM if invalid decrement pin has been passed + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setRx2GainCtrlPin(mykonosDevice_t *device, uint8_t incStep, uint8_t decStep, mykonosGpioSelect_t rx2GainIncPin, mykonosGpioSelect_t rx2GainDecPin, uint8_t enable) +{ + uint8_t wrtPin = 0x00; + uint8_t wrtStep = 0x00; + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + + const uint8_t SHIFT_CH2 = 0x01; + const uint8_t SHIFT_INC = 0x5; + const uint8_t SHIFT_DEC = 0x2; + const uint8_t MAX_STEP = 0x07; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setRx2GainCtrlPin()\n"); +#endif + + /* If enable then check for the next otherwise go directly to disable */ + if (enable > 0) + { + /* Error checking for correct step. */ + if ((uint8_t)(incStep > MAX_STEP) || (uint8_t)(decStep > MAX_STEP)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_MGCRX2_STEP_INV_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_MGCRX2_STEP_INV_PARAM)); + return MYKONOS_ERR_MGCRX2_STEP_INV_PARAM; + } + + /* Pin configuration assignment*/ + switch (rx2GainIncPin) + { + case MYKGPIO3: + wrtPin |= 0x00; + break; + case MYKGPIO13: + wrtPin |= 0x40; + break; + + default: + return MYKONOS_ERR_MGCRX2_GPIO_INCPIN_INV_PARAM; + } + + switch (rx2GainDecPin) + { + case MYKGPIO4: + wrtPin |= 0x00; + break; + case MYKGPIO14: + wrtPin |= 0x10; + break; + + default: + return MYKONOS_ERR_MGCRX2_GPIO_DECPIN_INV_PARAM; + } + } + + /* Setting increment step. */ + wrtStep = (uint8_t)(incStep<spiSettings, MYKONOS_ADDR_AGC_MANUAL_GAIN_CFG, wrtStep, 0xFE, 0); + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_MANUAL_GAIN_GPIO_SEL, wrtPin, 0xF0, 0); + + return error; +} + +/** + * \brief This API function returns the configuration RX2 gain Pin control + * + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param incStep will contain the step that is used for increment. + * \param decStep will contain the step that is used for decrement. + * \param rx2GainIncPin this will have the pin used for increment. + * \param rx2GainDecPin this will have the pin used for decrement. + * \param enable will contain the enable status for this channel if it is set to 1 then this + * function is enable for this channel, if it is 0 it is not enable + * + * \retval MYKONOS_ERR_GETRX2PIN_INCSTEP_NULL_PARM if a null value has been passed to incStep + * \retval MYKONOS_ERR_GETRX2PIN_DECSTEP_NULL_PARM if a null value has been passed to decStep + * \retval MYKONOS_ERR_GETRX2PIN_INCPIN_NULL_PARM if a null value has been passed to rx1GainIncPin + * \retval MYKONOS_ERR_GETRX2PIN_DECPIN_NULL_PARM if a null value has been passed to rx1GainDecPin + * \retval MYKONOS_ERR_GETRX2PIN_EN_NULL_PARM if a null value has been passed to enable + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getRx2GainCtrlPin(mykonosDevice_t *device, uint8_t *incStep, uint8_t *decStep, mykonosGpioSelect_t *rx2GainIncPin, mykonosGpioSelect_t *rx2GainDecPin, uint8_t *enable) +{ + uint8_t readVal = 0x00; + + const uint8_t MASK_GPIO_CH2 = 0xF0; + const uint8_t MASK_EN_CH2 = 0x02; + const uint8_t MASK_STEP_INC = 0xE0; + const uint8_t MASK_STEP_DEC = 0x1C; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getRx2GainCtrlPin()\n"); +#endif + + /* Checking for null passed parameters */ + if (incStep == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRX2PIN_INCSTEP_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETRX2PIN_INCSTEP_NULL_PARM)); + return MYKONOS_ERR_GETRX2PIN_INCSTEP_NULL_PARM; + } + + if (decStep == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRX2PIN_DECSTEP_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETRX2PIN_DECSTEP_NULL_PARM)); + return MYKONOS_ERR_GETRX2PIN_DECSTEP_NULL_PARM; + } + + if (rx2GainIncPin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRX2PIN_INCPIN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETRX2PIN_INCPIN_NULL_PARM)); + return MYKONOS_ERR_GETRX2PIN_INCPIN_NULL_PARM; + } + + if (rx2GainDecPin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRX2PIN_DECPIN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETRX2PIN_DECPIN_NULL_PARM)); + return MYKONOS_ERR_GETRX2PIN_DECPIN_NULL_PARM; + } + + if (enable == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETRX2PIN_EN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETRX2PIN_EN_NULL_PARM)); + return MYKONOS_ERR_GETRX2PIN_EN_NULL_PARM; + } + + /* Getting Pin configuration assignment*/ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_AGC_MANUAL_GAIN_GPIO_SEL, &readVal); + readVal = readVal & MASK_GPIO_CH2; + + if (readVal & 0x40) + { + *rx2GainIncPin = MYKGPIO13; + } + else + { + *rx2GainIncPin = MYKGPIO3; + } + + if (readVal & 0x10) + { + *rx2GainDecPin = MYKGPIO14; + } + else + { + *rx2GainDecPin = MYKGPIO4; + } + + /* Getting Pin configuration assignment*/ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_AGC_MANUAL_GAIN_CFG, &readVal); + + *enable = (readVal & MASK_EN_CH2) >> 1; + + *incStep = (readVal & MASK_STEP_INC) >> 5; + + *decStep = (readVal & MASK_STEP_DEC) >> 2; + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief This API function set the pins for hybrid gain control + * + * In order to call this function the gain mode should be set to Hybrid. + * The AGC gain change will be controlled with the selected GPIO pin: + * A pulse on the 'rx1GainChangePin' in hybrid pin control will enable the AGC gain change for RX1 + * A pulse on the 'rx2GainChangePin' in hybrid pin control will enable the AGC gain change for RX2 + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param rx1GainChangePin GPIO pin that will be used for hybrid gain change control, the available pins for RX1 channel + * hybrid control are: + * MYKGPIO1 + * MYKGPIO10 + * MYKGPIO11 + * MYKGPIONAN for no GPIO selected + * + * \param rx2GainChangePin GPIO pin that will be used for hybrid gain change control, the available pins for RX2 channel + * hybrid control are: + * MYKGPIO4 + * MYKGPIO10 + * MYKGPIO13 + * MYKGPIONAN for no GPIO selected + * + * \retval MYKONOS_ERR_GAIN_CONTROL_NOT_HYBRID if gain control is not hybrid + * \retval MYKONOS_ERR_GPIO_HYBRID_RX1_PIN if invalid pin has been passed for RX1 hybrid gain control. + * \retval MYKONOS_ERR_GPIO_HYBRID_RX2_PIN if invalid pin has been passed for RX2 hybrid gain control. + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t rx1GainChangePin, mykonosGpioSelect_t rx2GainChangePin) +{ + uint8_t hybridPinWrite = 0x00; + uint8_t pinRx1 = 0x00; + uint8_t pinRx2 = 0x00; + + const uint8_t HYBRID_RX_PIN_MASK = 0x0F; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setRxHybridGainChangePin()\n"); +#endif + + /* Check if in Hybrid Mode */ + if (device->rx->rxGainCtrl->gainMode != HYBRID) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GAIN_CONTROL_NOT_HYBRID, + getGpioMykonosErrorMessage(MYKONOS_ERR_GAIN_CONTROL_NOT_HYBRID)); + return MYKONOS_ERR_GAIN_CONTROL_NOT_HYBRID; + } + + /* Pin configuration assignment for RX1 and RX2 */ + switch (rx1GainChangePin) + { + case MYKGPIO1: + pinRx1 |= 0x00; + break; + case MYKGPIO10: + pinRx1 |= 0x01; + break; + case MYKGPIO11: + pinRx1 |= 0x02; + break; + case MYKGPIONAN: + pinRx1 |= 0x03; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_HYBRID_RX1_PIN, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_HYBRID_RX1_PIN)); + return MYKONOS_ERR_GPIO_HYBRID_RX1_PIN; + } + + switch (rx2GainChangePin) + { + case MYKGPIO4: + pinRx2 |= 0x00; + break; + case MYKGPIO10: + pinRx2 |= 0x04; + break; + case MYKGPIO13: + pinRx2 |= 0x08; + break; + case MYKGPIONAN: + pinRx2 |= 0x0C; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_HYBRID_RX2_PIN, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_HYBRID_RX2_PIN)); + return MYKONOS_ERR_GPIO_HYBRID_RX2_PIN; + } + + /* Setting GPIO control for RX1 and RX2 */ + hybridPinWrite = (pinRx1 | pinRx2); + + /* Writing GPIO pin configuration for hybrid mode. */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_GAIN_CHANGE_GPIO_SEL, hybridPinWrite, HYBRID_RX_PIN_MASK, 0); + + return MYKONOS_ERR_GPIO_OK; +} + + + +/** + * \brief This API function gets the pin configuration for hybrid gain control of RX1 and RX2 + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param rx1GainChangePin Will return the GPIO pin used for Rx1 in hybrid gain control. + * \param rx2GainChangePin Will return the GPIO pin used for Rx2 in hybrid gain control. + * + * \retval MYKONOS_ERR_GPIO_HYBRID_RX1_PIN_NULL_PARM if a null value has been passed to rx1GainChangePin + * \retval MYKONOS_ERR_GPIO_HYBRID_RX2_PIN_NULL_PARM if a null value has been passed to rx2GainChangePin + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t *rx1GainChangePin, mykonosGpioSelect_t *rx2GainChangePin) +{ + uint8_t hybridPinRead = 0x00; + uint8_t pinRx1 = 0x00; + uint8_t pinRx2 = 0x00; + mykonosGpioSelect_t rx1Pin = MYKGPIONAN; + mykonosGpioSelect_t rx2Pin = MYKGPIONAN; + + const uint8_t MASK_RX1_PIN = 0x03; + const uint8_t MASK_RX2_PIN = 0x0C; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getRxHybridGainChangePin()\n"); +#endif + + /* Checking for null passed parameters */ + if (rx1GainChangePin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_HYBRID_RX1_PIN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_HYBRID_RX1_PIN_NULL_PARM)); + return MYKONOS_ERR_GPIO_HYBRID_RX1_PIN_NULL_PARM; + } + + if (rx2GainChangePin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_HYBRID_RX2_PIN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_HYBRID_RX2_PIN_NULL_PARM)); + return MYKONOS_ERR_GPIO_HYBRID_RX2_PIN_NULL_PARM; + } + + /* Getting Pin configuration assignment */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_AGC_GAIN_CHANGE_GPIO_SEL, &hybridPinRead); + pinRx1 = hybridPinRead & MASK_RX1_PIN; + pinRx2 = hybridPinRead & MASK_RX2_PIN; + + /* Pin configuration mapping assignment for RX1 and RX2 */ + switch (pinRx1) + { + case 0x00: + rx1Pin = MYKGPIO1; + break; + case 0x01: + rx1Pin = MYKGPIO10; + break; + case 0x02: + rx1Pin = MYKGPIO11; + break; + default: + rx1Pin = MYKGPIONAN; + break; + } + + switch (pinRx2) + { + case 0x00: + rx2Pin = MYKGPIO4; + break; + case 0x04: + rx2Pin = MYKGPIO10; + break; + case 0x08: + rx2Pin = MYKGPIO13; + break; + default: + rx2Pin = MYKGPIONAN; + break; + } + + /* Setting pins to passed pointers */ + *rx1GainChangePin = rx1Pin; + *rx2GainChangePin = rx2Pin; + + return MYKONOS_ERR_GPIO_OK; +} + + +/** + * \brief This API function set the pins for hybrid gain control + * + * In order to call this function the gain mode should be set to Hybrid. + * The AGC gain change will be controlled with the selected GPIO pin: + * A pulse on the 'obsRxGainChangePin' in hybrid pin control will enable the AGC gain change for observation channel + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param obsRxGainChangePin GPIO pin that will be used for hybrid gain change control, the available pins for observation channel + * hybrid control are: + * MYKGPIO6 + * MYKGPIO10 + * MYKGPIO17 + * MYKGPIONAN for none selected + * + * \retval MYKONOS_ERR_AGC_OBS_NOT_IN_HYBRID if the observation gain mode is not set to Hybrid + * \retval MYKONOS_ERR_GPIO_HYBRID_ORX_PIN if invalid pin has been passed for ORX hybrid gain control. + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setObsRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t obsRxGainChangePin) +{ + uint8_t hybridPinWrite = 0x00; + uint8_t pinOrx = 0x00; + + const uint8_t HYBRID_ORX_PIN_MASK = 0x30; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setObsRxHybridGainChangePin()\n"); +#endif + + /* Check if in Hybrid Mode */ + if (device->obsRx->orxGainCtrl->gainMode != HYBRID) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_AGC_OBS_NOT_IN_HYBRID, + getGpioMykonosErrorMessage(MYKONOS_ERR_AGC_OBS_NOT_IN_HYBRID)); + return MYKONOS_ERR_AGC_OBS_NOT_IN_HYBRID; + } + + /* Pin configuration assignment for RX1 and RX2 */ + switch (obsRxGainChangePin) + { + case MYKGPIO6: + pinOrx |= 0x00; + break; + case MYKGPIO10: + pinOrx |= 0x10; + break; + case MYKGPIO17: + pinOrx |= 0x20; + break; + case MYKGPIONAN: + pinOrx |= 0x30; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_HYBRID_ORX_PIN, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_HYBRID_ORX_PIN)); + return MYKONOS_ERR_GPIO_HYBRID_ORX_PIN; + } + + /* Setting GPIO control for observation channel */ + hybridPinWrite = pinOrx; + + /* Writing GPIO pin configuration for hybrid mode. */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_GPIO_SEL, hybridPinWrite, HYBRID_ORX_PIN_MASK, 0); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief This API function gets the pin configuration for hybrid gain control of observation channel + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param obsRxGainChangePin Will return the GPIO pin used for observation channel in hybrid gain control. + * + * \retval MYKONOS_ERR_GPIO_HYBRID_ORX_PIN_NULL_PARM if a null value has been passed to obsRxGainChangePin + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getObsRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t *obsRxGainChangePin) +{ + uint8_t hybridPinRead = 0x00; + uint8_t pinOrx = 0x00; + mykonosGpioSelect_t orxPin = MYKGPIONAN; + + const uint8_t MASK_ORX_PIN = 0x30; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getObsRxHybridGainChangePin()\n"); +#endif + + /* Checking for null passed parameters */ + if (obsRxGainChangePin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_HYBRID_ORX_PIN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_HYBRID_ORX_PIN_NULL_PARM)); + return MYKONOS_ERR_GPIO_HYBRID_ORX_PIN_NULL_PARM; + } + + /* Getting Pin configuration assignment */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_GPIO_SEL, &hybridPinRead); + pinOrx = hybridPinRead & MASK_ORX_PIN; + + /* Pin configuration mapping assignment for RX1 and RX2 */ + switch (pinOrx) + { + case 0x00: + orxPin = MYKGPIO6; + break; + case 0x10: + orxPin = MYKGPIO10; + break; + case 0x20: + orxPin = MYKGPIO17; + break; + default: + orxPin = MYKGPIONAN; + break; + } + + /* Setting pins to passed pointer */ + *obsRxGainChangePin = orxPin; + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief This API function set the pins for sync AGC gain control + * + * In order to call this function the RX gain control should be set to AGC mode. + * The AGC gain sync will be controlled with the selected GPIO pin: + * A pulse on the 'rx1AgcSyncPin' in hybrid pin control will enable the AGC gain sync for RX1 + * A pulse on the 'rx2AgcSyncPin' in hybrid pin control will enable the AGC gain sync for RX2 + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param rx1AgcSyncPin GPIO pin that will be used for AGC sync gain control, the available pins for RX1 channel are: + * MYKGPIO1 + * MYKGPIO10 + * MYKGPIO11 + * MYKGPIONAN for no GPIO selected + * + * \param rx2AgcSyncPin GPIO pin that will be used for AGC sync gain control, the available pins for RX2 channel are: + * MYKGPIO4 + * MYKGPIO10 + * MYKGPIO13 + * MYKGPIONAN for no GPIO selected + * + * \retval MYKONOS_ERR_GAIN_CONTROL_NOT_AGC if the RX gain control mode is not set to AGC. + * \retval MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN if invalid pin has been passed for RX1 AGC sync gain control. + * \retval MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN if invalid pin has been passed for RX2 AGC sync gain control. + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t rx1AgcSyncPin, mykonosGpioSelect_t rx2AgcSyncPin) +{ + uint8_t agcSyncPinWrite = 0x00; + uint8_t pinRx1 = 0x00; + uint8_t pinRx2 = 0x00; + + const uint8_t SYNC_RX_PIN_MASK = 0x0F; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setRxAgcEnSyncPin()\n"); +#endif + + /* Check if in Hybrid Mode */ + if (device->rx->rxGainCtrl->gainMode != AGC) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GAIN_CONTROL_NOT_AGC, + getGpioMykonosErrorMessage(MYKONOS_ERR_GAIN_CONTROL_NOT_AGC)); + return MYKONOS_ERR_GAIN_CONTROL_NOT_AGC; + } + + /* Pin configuration assignment for RX1 and RX2 */ + switch (rx1AgcSyncPin) + { + case MYKGPIO1: + pinRx1 |= 0x00; + break; + case MYKGPIO10: + pinRx1 |= 0x01; + break; + case MYKGPIO11: + pinRx1 |= 0x02; + break; + case MYKGPIONAN: + pinRx1 |= 0x03; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN)); + return MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN; + } + + switch (rx2AgcSyncPin) + { + case MYKGPIO4: + pinRx2 |= 0x00; + break; + case MYKGPIO10: + pinRx2 |= 0x04; + break; + case MYKGPIO13: + pinRx2 |= 0x08; + break; + case MYKGPIONAN: + pinRx2 |= 0x0C; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN)); + return MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN; + } + + /* Setting GPIO control for RX1 and RX2 */ + agcSyncPinWrite = (pinRx1 | pinRx2); + + /* Writing GPIO pin configuration for Sync AGC. */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_GAIN_CHANGE_GPIO_SEL, agcSyncPinWrite, SYNC_RX_PIN_MASK, 0); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief This API function gets the GPIO pin configuration for AGC gain sync control of RX1 and RX2 + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param rx1AgcSyncPin Will return the GPIO pin used for RX1 channel AGC gain sync control, + * + * \param rx2AgcSyncPin Will return the GPIO pin used for RX2 channel AGC gain sync control, + * + * \retval MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN_NULL_PARM if a null value has been passed to rx1AgcSyncPin + * \retval MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN_NULL_PARM if a null value has been passed to rx2AgcSyncPin + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t *rx1AgcSyncPin, mykonosGpioSelect_t *rx2AgcSyncPin) +{ + uint8_t agcSyncPinRead = 0x00; + uint8_t pinRx1 = 0x00; + uint8_t pinRx2 = 0x00; + mykonosGpioSelect_t rx1Pin = MYKGPIONAN; + mykonosGpioSelect_t rx2Pin = MYKGPIONAN; + + const uint8_t MASK_RX1_PIN = 0x03; + const uint8_t MASK_RX2_PIN = 0x0C; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getRxHybridGainChangePin()\n"); +#endif + + /* Checking for null passed parameters */ + if (rx1AgcSyncPin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN_NULL_PARM)); + return MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN_NULL_PARM; + } + + if (rx2AgcSyncPin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN_NULL_PARM)); + return MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN_NULL_PARM; + } + + /* Getting Pin configuration assignment */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_AGC_GAIN_CHANGE_GPIO_SEL, &agcSyncPinRead); + pinRx1 = agcSyncPinRead & MASK_RX1_PIN; + pinRx2 = agcSyncPinRead & MASK_RX2_PIN; + + /* Pin configuration mapping assignment for RX1 and RX2 */ + switch (pinRx1) + { + case 0x00: + rx1Pin = MYKGPIO1; + break; + case 0x01: + rx1Pin = MYKGPIO10; + break; + case 0x02: + rx1Pin = MYKGPIO11; + break; + default: + rx1Pin = MYKGPIONAN; + break; + } + + switch (pinRx2) + { + case 0x00: + rx2Pin = MYKGPIO4; + break; + case 0x04: + rx2Pin = MYKGPIO10; + break; + case 0x08: + rx2Pin = MYKGPIO13; + break; + default: + rx2Pin = MYKGPIONAN; + break; + } + + /* Setting pins to passed pointers */ + *rx1AgcSyncPin = rx1Pin; + *rx2AgcSyncPin = rx2Pin; + + return MYKONOS_ERR_GPIO_OK; +} + + +/** + * \brief This API function set the pins for AGC gain Sync control + * + * In order to call this function the gain mode should be set to AGC mode. + * The AGC gain sync will be controlled with the selected GPIO pin: + * A pulse on the 'obsRxGainChangePin' in hybrid pin control will enable the AGC gain change for observation channel + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param obsRxAgcSyncPin GPIO pin that will be used for AGC sync gain control, the available pins for observation channel are: + * MYKGPIO6 + * MYKGPIO10 + * MYKGPIO17 + * MYKGPIONAN for none selected + * + * \retval MYKONOS_ERR_OBS_GAIN_CONTROL_NOT_AGC if the observation gain control mode is not set to AGC + * \retval MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN if invalid pin has been passed for ORX AGC sync gain control. + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setObsRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t obsRxAgcSyncPin) +{ + uint8_t agcSyncPinWrite = 0x00; + uint8_t pinOrx = 0x00; + + const uint8_t SYNC_ORX_PIN_MASK = 0x30; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setObsRxAgcEnSyncPin()\n"); +#endif + + /* Check if in Hybrid Mode */ + if (device->obsRx->orxGainCtrl->gainMode != AGC) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBS_GAIN_CONTROL_NOT_AGC, + getGpioMykonosErrorMessage(MYKONOS_ERR_OBS_GAIN_CONTROL_NOT_AGC)); + return MYKONOS_ERR_OBS_GAIN_CONTROL_NOT_AGC; + } + + /* Pin configuration assignment for observation channel */ + switch (obsRxAgcSyncPin) + { + case MYKGPIO6: + pinOrx |= 0x00; + break; + case MYKGPIO10: + pinOrx |= 0x10; + break; + case MYKGPIO17: + pinOrx |= 0x20; + break; + case MYKGPIONAN: + pinOrx |= 0x30; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN)); + return MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN; + } + + /* Setting GPIO control for observation channel */ + agcSyncPinWrite = pinOrx; + + /* Writing GPIO pin configuration for Sync AGC mode. */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_GPIO_SEL, agcSyncPinWrite, SYNC_ORX_PIN_MASK, 0); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief This API function gets the pin configuration for AGC Sync gain control of observation channel + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param obsRxAgcSyncPin Will return the GPIO pin used for observation channel AGC gain sync control, + * + * \retval MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN_NULL_PARM if a null value has been passed to obsRxAgcSyncPin + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getObsRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t *obsRxAgcSyncPin) +{ + uint8_t agcSyncPinRead = 0x00; + uint8_t pinOrx = 0x00; + mykonosGpioSelect_t orxPin = MYKGPIONAN; + + const uint8_t MASK_ORX_PIN = 0x30; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getObsRxAgcEnSyncPin()\n"); +#endif + + /* Checking for null passed parameters */ + if (obsRxAgcSyncPin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN_NULL_PARM)); + return MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN_NULL_PARM; + } + + /* Getting Pin configuration assignment */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_AGC_ORX_SNRX_GPIO_SEL, &agcSyncPinRead); + pinOrx = agcSyncPinRead & MASK_ORX_PIN; + + /* Pin configuration mapping assignment for observation channel */ + switch (pinOrx) + { + case 0x00: + orxPin = MYKGPIO6; + break; + case 0x10: + orxPin = MYKGPIO10; + break; + case 0x20: + orxPin = MYKGPIO17; + break; + default: + orxPin = MYKGPIONAN; + break; + } + + /* Setting pins to passed pointer */ + *obsRxAgcSyncPin = orxPin; + + return MYKONOS_ERR_GPIO_OK; +} + + +/** + * \brief This API function configures the GPIO inputs for controlling Tx attenuation settings + * + * This allows to control the TX attenuation using GPIO inputs. When a low to high transition is + * applied to the configure GPIO input the attenuation will change by the desire step. + * The stepSize parameter will set the attenuation change applied. + * + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * + * \param stepSize the step that will increase or decrease the Tx1 channel attenuation. + * This parameter sets the change in Tx attenuation for each increment or decrement signal received in incr/decr mode. + * Step of 1 changes attenuation by 0.05dB. + * + * \param tx1AttenIncPin This parameter is the GPIO pin configuration that will be controlling the increment + * of Tx attenuation. Available pins are: + * Tx1 increment: MYKGPIO4 or MYKGPIO12 + * + * \param tx1AttenDecPin This parameter is the GPIO pin configuration that will be controlling the decrement + * of Tx attenuation. Available pins are: + * Tx1 decrement: MYKGPIO5 or MYKGPIO13 + * + * \param enable 0 = Disable the attenuation pin control for Tx1 + * 1 = enable the attenuation pin control for Tx1 + * + * \param useTx1ForTx2 is used to return if TX1 settings are used for TX2 channel. + * + * \retval MYKONOS_ERR_TPCTX1_GPIO_STEP_INV_PARAM if an invalid step size is passed + * \retval MYKONOS_ERR_TPCTX1_GPIO_INCPIN_INV_PARAM if an invalid channel for TX is passed + * \retval MYKONOS_ERR_TPCTX1_GPIO_DECPIN_INV_PARAM if an invalid channel for TX is passed + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setTx1AttenCtrlPin(mykonosDevice_t *device, uint8_t stepSize, mykonosGpioSelect_t tx1AttenIncPin, mykonosGpioSelect_t tx1AttenDecPin, uint8_t enable, uint8_t useTx1ForTx2) +{ + uint8_t wrtPin = 0; + uint8_t tpcMode = 0x0; + uint8_t tpcMaskTx2 = 0x00; + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + + const uint8_t TX_INCDEC_MASK = 0x1F; + const uint8_t TX_PIN_MASK = 0x0F; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setTx1AttenCtrlPin()\n"); +#endif + + /* If enable then check for the next otherwise go directly to disable */ + if (enable > 0) + { + /* Error checking for correct step. */ + if (stepSize > TX_INCDEC_MASK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_TPCTX1_GPIO_STEP_INV_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_TPCTX1_GPIO_STEP_INV_PARAM)); + return MYKONOS_ERR_TPCTX1_GPIO_STEP_INV_PARAM; + } + + /* Pin configuration assignment for Tx1 increments */ + switch (tx1AttenIncPin) + { + case MYKGPIO4: + wrtPin |= 0x00; + break; + case MYKGPIO12: + wrtPin |= 0x01; + break; + + default: + return MYKONOS_ERR_TPCTX1_GPIO_INCPIN_INV_PARAM; + } + + /* Pin configuration assignment for Tx1 decrements */ + switch (tx1AttenDecPin) + { + case MYKGPIO5: + wrtPin |= 0x00; + break; + case MYKGPIO13: + wrtPin |= 0x04; + break; + + default: + return MYKONOS_ERR_TPCTX1_GPIO_DECPIN_INV_PARAM; + } + + /* Setting TPC mode corresponding to the enable */ + tpcMode = 0x03; + + /* Setting TPC control for Tx2 using Tx1 */ + if (useTx1ForTx2 > 0) + { + tpcMode |= 0x1C; + tpcMaskTx2 = 0x1F; + } + else + { + tpcMaskTx2 = 0x13; + } + } + else + { + /* Setting TPC mode corresponding for no Pin control */ + tpcMode = 0x05; + tpcMaskTx2 = 0x1F; + } + + /* Setting increment step. */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_INCR_DECR_WORD, stepSize, TX_INCDEC_MASK, 0); + + /* Set the TPC mode for GPIO control. */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_TPC_CONFIG, tpcMode, tpcMaskTx2, 0); + + /* Set the GPIO input pin configuration and the step size. */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_TPC_GPIO_CFG, wrtPin, TX_PIN_MASK, 0); + + return error; +} + +/** + * \brief This API function returns the configuration TX1 attenuation Pin control + * + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param stepSize will contain the step that is used for increment and decrement. + * \param tx1AttenIncPin this will have the pin used for increment. + * \param tx1AttenDecPin this will have the pin used for decrement. + * \param enable will contain the enable status for this channel if it is set to 1 then this + * function is enable for this channel, if it is 0 it is not enable + * \param useTx1ForTx2 is used to return if TX1 settings are used for TX2 channel. + * + * \retval MYKONOS_ERR_GETTX1PIN_STEP_NULL_PARM if a null value has been passed to stepSize + * \retval MYKONOS_ERR_GETTX1PIN_INC_NULL_PARM if a null value has been passed to tx1AttenIncPin + * \retval MYKONOS_ERR_GETTX1PIN_DEC_NULL_PARM if a null value has been passed to tx1AttenDecPin + * \retval MYKONOS_ERR_GETTX1PIN_EN_NULL_PARM if a null value has been passed to enable + * \retval MYKONOS_ERR_GETTX1PIN_TX1TX2_NULL_PARM if a null value has been passed to useTx1ForTx2 + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getTx1AttenCtrlPin(mykonosDevice_t *device, uint8_t *stepSize, mykonosGpioSelect_t *tx1AttenIncPin, mykonosGpioSelect_t *tx1AttenDecPin, uint8_t *enable, uint8_t *useTx1ForTx2) +{ + uint8_t readVal = 0x00; + uint8_t en = 0x00; + + const uint8_t MASK_TPC_CH1 = 0x03; + const uint8_t MASK_TPC_CH1FCH2 = 0x10; + const uint8_t MASK_TPC_STEP = 0x1F; + const uint8_t MASK_TPC_GPIO_CH1 = 0x0F; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getTx1AttenCtrlPin()\n"); +#endif + + /* Checking for null passed parameters */ + if (stepSize == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTX1PIN_STEP_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETTX1PIN_STEP_NULL_PARM)); + return MYKONOS_ERR_GETTX1PIN_STEP_NULL_PARM; + } + + if (tx1AttenIncPin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTX1PIN_INC_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETTX1PIN_INC_NULL_PARM)); + return MYKONOS_ERR_GETTX1PIN_INC_NULL_PARM; + } + + if (tx1AttenDecPin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTX1PIN_DEC_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETTX1PIN_DEC_NULL_PARM)); + return MYKONOS_ERR_GETTX1PIN_DEC_NULL_PARM; + } + + if (enable == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTX1PIN_EN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETTX1PIN_EN_NULL_PARM)); + return MYKONOS_ERR_GETTX1PIN_EN_NULL_PARM; + } + + if (useTx1ForTx2 == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTX1PIN_TX1TX2_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETTX1PIN_TX1TX2_NULL_PARM)); + return MYKONOS_ERR_GETTX1PIN_TX1TX2_NULL_PARM; + } + + /* Getting Pin configuration assignment*/ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_TX_TPC_GPIO_CFG, &readVal); + readVal = readVal & MASK_TPC_GPIO_CH1; + + if (readVal & 0x01) + { + *tx1AttenIncPin = MYKGPIO12; + } + else + { + *tx1AttenIncPin = MYKGPIO4; + } + + if (readVal & 0x04) + { + *tx1AttenDecPin = MYKGPIO13; + } + else + { + *tx1AttenDecPin = MYKGPIO5; + } + + /* Getting Pin configuration assignment*/ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_TX_TPC_CONFIG, &readVal); + + en = readVal & MASK_TPC_CH1; + + *enable = (en == MASK_TPC_CH1) ? 1 : 0; + + *useTx1ForTx2 = readVal & MASK_TPC_CH1FCH2; + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_TX_INCR_DECR_WORD, &readVal); + + *stepSize = readVal & MASK_TPC_STEP; + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief This API function configures the GPIO inputs for controlling Tx attenuation settings + * + * This allows to control the TX attenuation using GPIO inputs. when a low to high transition is + * applied to the configure GPIO input the attenuation will change by the desire step. + * The stepSize parameter will set the attenuation change applied. + * + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + * + * \param device is structure pointer to the Mykonos data structure containing settings + * + * \param stepSize the step that will increase or decrease the Tx2 channel attenuation. + * This parameter sets the change in Tx attenuation for each increment or decrement signal received in incr/decr mode. + * Step of 1 changes attenuation by 0.05dB. + * + * \param tx2AttenIncPin This parameter is the GPIO pin configuration that will be controlling the increment + * of Tx attenuation. Available pins are: + * Tx2 increment: MYKGPIO6 or MYKGPIO14 + * + * \param tx2AttenDecPin This parameter is the GPIO pin configuration that will be controlling the decrement + * of Tx attenuation. Available pins are: + * Tx2 decrement: MYKGPIO7 or MYKGPIO15 + * + * \param enable 0 = Disable the attenuation pin control for Tx2 + * 1 = enable the attenuation pin control for Tx2 + * + * \retval MYKONOS_ERR_TPCTX2_GPIO_STEP_INV_PARAM if an invalid step size is passed + * \retval MYKONOS_ERR_TPCTX2_GPIO_INCPIN_INV_PARAM if an invalid channel for TX is passed + * \retval MYKONOS_ERR_TPCTX2_GPIO_INCPIN_INV_PARAM if an invalid channel for TX is passed + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setTx2AttenCtrlPin(mykonosDevice_t *device, uint8_t stepSize, mykonosGpioSelect_t tx2AttenIncPin, mykonosGpioSelect_t tx2AttenDecPin, uint8_t enable) +{ + uint8_t wrtPin = 0; + uint8_t tpcMode = 0x0; + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + + + const uint8_t TX_INCDEC_MASK = 0x1F; + const uint8_t TX2_TPC_MASK = 0x1C; + const uint8_t TX2_WRTPIN = 0xf0; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setTx2AttenCtrlPin()\n"); +#endif + + /* If enable then check for the next otherwise go directly to disable */ + if (enable > 0) + { + /* Error checking for correct step. */ + if (stepSize > TX_INCDEC_MASK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_TPCTX2_GPIO_STEP_INV_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_TPCTX2_GPIO_STEP_INV_PARAM)); + return MYKONOS_ERR_TPCTX2_GPIO_STEP_INV_PARAM; + } + + /* Pin configuration assignment for Tx2 increments */ + switch (tx2AttenIncPin) + { + case MYKGPIO6: + wrtPin |= 0x00; + break; + case MYKGPIO14: + wrtPin |= 0x10; + break; + + default: + return MYKONOS_ERR_TPCTX2_GPIO_INCPIN_INV_PARAM; + } + + /* Pin configuration assignment for Tx2 decrements */ + switch (tx2AttenDecPin) + { + case MYKGPIO7: + wrtPin |= 0x00; + break; + case MYKGPIO15: + wrtPin |= 0x40; + break; + + default: + return MYKONOS_ERR_TPCTX2_GPIO_DECPIN_INV_PARAM; + } + + /* Setting TPC mode corresponding to the enable */ + tpcMode = 0x0C; + } + else + { + /* Setting TPC mode corresponding for no Pin control */ + tpcMode = 0x05; + } + + /* Setting increment step. */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_INCR_DECR_WORD, stepSize, TX_INCDEC_MASK, 0); + + /* Set the TPC mode for GPIO control. */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_TPC_CONFIG, tpcMode, TX2_TPC_MASK, 0); + + /* Set the GPIO input pin configuration and the step size. */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_TX_TPC_GPIO_CFG, wrtPin, TX2_WRTPIN, 0); + + return error; +} + +/** + * \brief This API function returns the configuration TX2 attenuation Pin control + * + * + * Dependencies + * - device->spiSettings + * - device->spiSettings->chipSelectIndex + + * + * \param device is structure pointer to the Mykonos data structure containing settings + * \param stepSize will contain the step that is used for increment and decrement. + * \param tx2AttenIncPin this will have the pin used for increment. + * \param tx2AttenDecPin this will have the pin used for decrement. + * \param enable will contain the enable status for this channel if it is set to 1 then this + * function is enable for this channel, if it is 0 it is not enable + * \param useTx1ForTx2 is used to return if TX1 settings are used for TX2 channel. + * + * \retval MYKONOS_ERR_GETTX2PIN_STEP_NULL_PARM if a null value has been passed to stepSize + * \retval MYKONOS_ERR_GETTX2PIN_STEP_NULL_PARM if a null value has been passed to tx1AttenIncPin + * \retval MYKONOS_ERR_GETTX2PIN_DEC_NULL_PARM if a null value has been passed to tx1AttenDecPin + * \retval MYKONOS_ERR_GETTX2PIN_EN_NULL_PARM if a null value has been passed to enable + * \retval MYKONOS_ERR_GETTX2PIN_TX1TX2_NULL_PARM if a null value has been passed to useTx1ForTx2 + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getTx2AttenCtrlPin(mykonosDevice_t *device, uint8_t *stepSize, mykonosGpioSelect_t *tx2AttenIncPin, mykonosGpioSelect_t *tx2AttenDecPin, uint8_t *enable, uint8_t *useTx1ForTx2) +{ + uint8_t readVal = 0x00; + uint8_t en = 0x00; + + const uint8_t MASK_TPC_CH2 = 0x0C; + const uint8_t MASK_TPC_CH1FCH2 = 0x10; + const uint8_t MASK_TPC_STEP = 0x1F; + const uint8_t MASK_TPC_GPIO_CH2 = 0xF0; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getTx2AttenCtrlPin()\n"); +#endif + + /* Checking for null passed parameters */ + if (stepSize == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTX2PIN_STEP_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETTX2PIN_STEP_NULL_PARM)); + return MYKONOS_ERR_GETTX2PIN_STEP_NULL_PARM; + } + + if (tx2AttenIncPin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTX2PIN_INC_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETTX2PIN_INC_NULL_PARM)); + return MYKONOS_ERR_GETTX2PIN_INC_NULL_PARM; + } + + if (tx2AttenDecPin == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTX2PIN_DEC_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETTX2PIN_DEC_NULL_PARM)); + return MYKONOS_ERR_GETTX2PIN_DEC_NULL_PARM; + } + + if (enable == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTX2PIN_EN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETTX2PIN_EN_NULL_PARM)); + return MYKONOS_ERR_GETTX2PIN_EN_NULL_PARM; + } + + if (useTx1ForTx2 == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTX2PIN_TX1TX2_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETTX2PIN_TX1TX2_NULL_PARM)); + return MYKONOS_ERR_GETTX2PIN_TX1TX2_NULL_PARM; + } + + /* Getting Pin configuration assignment*/ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_TX_TPC_GPIO_CFG, &readVal); + readVal = readVal & MASK_TPC_GPIO_CH2; + + if (readVal & 0x10) + { + *tx2AttenIncPin = MYKGPIO14; + } + else + { + *tx2AttenIncPin = MYKGPIO6; + } + + if (readVal & 0x40) + { + *tx2AttenDecPin = MYKGPIO15; + } + else + { + *tx2AttenDecPin = MYKGPIO7; + } + + /* Getting Pin configuration assignment*/ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_TX_TPC_CONFIG, &readVal); + + en = readVal & MASK_TPC_CH2; + + *enable = (en == MASK_TPC_CH2) ? 1 : 0; + + *useTx1ForTx2 = readVal & MASK_TPC_CH1FCH2; + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_TX_INCR_DECR_WORD, &readVal); + + *stepSize = readVal & MASK_TPC_STEP; + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Sets the Mykonos low voltage GPIO output pins level + * + * This function will only affect the GPIO pins that have their OE direction set to output and + * that have the correct source control for the nibbles in GPIO_BITBANG_MODE + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gpioPinLevel bit per GPIO pin, level to output for each GPIO pin. 0 = low output, 1= high output + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setGpioPinLevel(mykonosDevice_t *device, uint32_t gpioPinLevel) +{ + + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setGpioPinLevel()\n"); +#endif + + /* writing GPIO configuration registers */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GPIO_SPI_SRC_7_0, (gpioPinLevel & 0xFF)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GPIO_SPI_SRC_15_8, ((gpioPinLevel >> 8) & 0xFF)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GPIO_SPI_SRC_18_16, ((gpioPinLevel >> 16) & 0x07)); + + /* Return */ + return error; +} + +/** + * \brief Reads the Mykonos low voltage GPIO pin levels and returns their contents in a single 32-bit word + * + * The GPIO pins that are set to be inputs in BITBANG mode will read back and be returned + * in the gpioPinLevel parameter. The return value is a bit per pin. GPIO 0 returns on bit 0 of + * the gpioPinLevel parameter. A logic low level returns a 0, a logic high level returns a 1. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gpioPinLevel Input Gpio pin levels read back on the pins assigned as inputs (bit per pin) + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_READGPIOSPI_NULL_PARM The pointer passed for gpioPinLevel parameter is NULL + */ +mykonosGpioErr_t MYKONOS_getGpioPinLevel(mykonosDevice_t *device, uint32_t *gpioPinLevel) +{ + uint8_t readBytes[3] = {0, 0, 0}; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getGpioPinLevel()\n"); +#endif + + if (gpioPinLevel == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READGPIOSPI_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_READGPIOSPI_NULL_PARM)); + return MYKONOS_ERR_READGPIOSPI_NULL_PARM; + } + + /* reading the registers into three-byte array */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_SPI_READ_7_0, &readBytes[0]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_SPI_READ_15_8, &readBytes[1]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_SPI_READ_18_16, &readBytes[2]); + + /* performing concatenation and assigning value to gpio1v8SpiRead */ + *gpioPinLevel = ((uint32_t)(readBytes[2] & 0x07) << 16) | ((uint32_t)(readBytes[1]) << 8) | (uint32_t)(readBytes[0]); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Reads the Mykonos GPIO pin output levels for BITBANG mode + * + * This function allows reading the value that the GPIO output pins are + * set to drive out the pins. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gpioPinSetLevel is a unit32_t pointer which contains the level of each GPIO pin (bit per pin) + * + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_GETGPIOSETLEVEL_NULL_PARM gpioPinSetLevel pointer is NULL in function parameter + * + */ +mykonosGpioErr_t MYKONOS_getGpioSetLevel(mykonosDevice_t *device, uint32_t *gpioPinSetLevel) +{ + uint8_t readBytes[3] = {0, 0, 0}; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getGpioSetLevel()\n"); +#endif + + if (gpioPinSetLevel == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETGPIOSETLEVEL_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETGPIOSETLEVEL_NULL_PARM)); + return MYKONOS_ERR_GETGPIOSETLEVEL_NULL_PARM; + } + + /* reading the registers into two-byte array */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_SPI_SRC_7_0, &readBytes[0]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_SPI_SRC_15_8, &readBytes[1]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_SPI_SRC_18_16, &readBytes[2]); + + /* performing concatenation and assigning value to gpioPinSetLevel */ + *gpioPinSetLevel = ((uint32_t)(readBytes[2] & 0x07) << 16) | ((uint32_t)(readBytes[1]) << 8) | (uint32_t)(readBytes[0]); + + return MYKONOS_ERR_GPIO_OK; +} + + + +/** + * \brief Sets the General Purpose (GP) interrupt register bit mask to enable interrupt sources to assert the GP Interrupt pin + * + * Mykonos has a single output pin called General Purpose Interrupt that asserts to a logic high level + * when certain events occur. The events that cause the GP Interrupt pin to assert are user + * selectable by setting the gpMask parameter in this function. Device default is mask = x1FF = ignore + * all events. The ARM Error interrupt can not be ignored and can always assert the GP interrupt pin. + * + * gpMask | Bit description + * ------------|------------ + * [0] | TXPLL LOCK - 0 = allow PLL unlocking to assert GP Interrupt pin, 1 = ignore TXPLL LOCK + * [1] | RXPLL LOCK - 0 = allow PLL unlocking to assert GP Interrupt pin, 1 = ignore RXPLL LOCK + * [2] | SNIFFER PLL LOCK - 0 = allow PLL unlocking to assert GP Interrupt pin, 1 = ignore SNIFFER PLL LOCK + * [3] | CALIBRATION PLL LOCK - 0 = allow PLL unlocking to assert GP Interrupt pin, 1 = ignore CALIBRATION PLL LOCK + * [4] | CLKPLL LOCK - 0 = allow PLL unlocking to assert GP Interrupt pin, 1 = ignore CLKPLL LOCK + * [5] | 0 = Allow JESD204 deframer interrupt to assert GP Interrupt pin, 1 = ignore JESD204 deframer interrupt + * [6] | Tx1 PA protection - 0 = allow Tx1 PA protection event to assert GP Interrupt pin, 1 = ignore Tx1 PA protection + * [7] | Tx2 PA protection - 0 = allow Tx2 PA protection event to assert GP Interrupt pin, 1 = ignore Tx2 PA protection + * [8] | Mykonos ARM Watchdog - 0 = allow Mykonos ARM Watchdog timeout to assert GP Interrupt pin, 1 = ignore Watchdog timeout event + * [15-9] | Reserved for future use + * + * Dependencies + * - device->spiSettings + * + * \param device Pointer to the device settings structure + * \param gpMask Value is passed to enable one or more general purpose interrupt sources + * (1=ignore source, 0 = enable source interrupt to GP Interrupt pin) + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_INV_GP_INT_MASK_PARM if invalid interrupt mask is passed + */ +mykonosGpioErr_t MYKONOS_configGpInterrupt(mykonosDevice_t *device, uint16_t gpMask) +{ + const uint16_t GP_INT_VALID_MASK = 0x1FF; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_configGpInterrupt()\n"); +#endif + + /* checking for valid mask setting */ + if (gpMask & ~GP_INT_VALID_MASK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_GP_INT_MASK_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_INV_GP_INT_MASK_PARM)); + return MYKONOS_ERR_INV_GP_INT_MASK_PARM; + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GP_INTERRUPT_MASK_1, (gpMask & 0xFF)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GP_INTERRUPT_MASK_0, ((gpMask >> 8) & 0x01)); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Reads the General Purpose (GP) interrupt status to determine what caused the GP Interrupt pin to assert + * + * When the BBIC detects a rising edge on the General Purpose Interrupt pin, this function + * allows the BBIC to determine the source of the interrupt. The value returned in the status parameter + * will show one or more sources for the interrupt based on the following table. + * + * The PLL unlock bits are not sticky. They will follow the current status of the PLLs. If the PLL relocks, the + * status bit will clear as well. The GP Interrupt pin is the logical OR of all the sources. When all the status + * bits are low, the GP Interrupt pin will be low. The status word readback will show the current value + * for all interrupt sources, even if they are disabled by the masked. However, the GP Interrupt pin will only assert + * for the enabled sources. + * + * status | Bit description + * ------------|------------ + * [0] | 1 = TXPLL UNLOCK + * [1] | 1 = RXPLL UNLOCK + * [2] | 1 = SNIFFER PLL UNLOCK + * [3] | 1 = CALIBRATION PLL UNLOCK + * [4] | 1 = CLK PLL UNLOCK + * [5] | 1 = JESD204 deframer interrupt occurred + * [6] | 1 = Tx1 PA protection event + * [7] | 1 = Tx2 PA protection event + * [8] | 1 = Mykonos ARM Watchdog timeout + * [9] | 1 = ARM interrupt occurred + * [15-10] | Reserved for future use + * + * Dependencies + * - device->spiSettings + * + * \param device Pointer to the device settings structure + * \param status parameter to return the IRQ source(s) that caused the GP Interrpt pin to assert. + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_GP_INT_STATUS_NULL_PARAM if null *status pointer is passed + */ +mykonosGpioErr_t MYKONOS_readGpInterruptStatus(mykonosDevice_t *device, uint16_t *status) +{ + uint8_t readStatus1 = 0; + uint8_t readStatus0 = 0; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_readGpInterruptStatus()\n"); +#endif + /* checking for null pointer */ + if (status == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GP_INT_STATUS_NULL_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GP_INT_STATUS_NULL_PARAM)); + return MYKONOS_ERR_GP_INT_STATUS_NULL_PARAM; + } + + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GP_INTERRUPT_READ_1, &readStatus1); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GP_INTERRUPT_READ_0, &readStatus0); + + /* PLL Lock status bits are high when locked, invert to match up with other bits */ + *status = ((((uint16_t)(readStatus1) & 0xE0U) | ((~(uint16_t)(readStatus1)) & 0x1F)) | (((uint16_t)(readStatus0) & 0x0003) << 8)) ; + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Sets the input and output GPIO pin selections for ARM related signals. + * + * The BBP should not have to call this as it will automatically be setup during the + * MYKONOS_loadArmFromBinary() function call. If the BBP wishes to change the GPIO + * assignments this function can be called again to change the configuration while + * the ARM is in the radioOff state. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->auxIo->armGpio : all members in structure + * + * \param device is a pointer to the device settings structure + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_SET_ARMGPIO_INV_POINTER device->auxIo->armGpio pointer is null + * \retval MYKONOS_ERR_SET_ARMGPIO_PINS_INV_SIGNALID Invalid ARM GPIO pin signal ID + * \retval MYKONOS_ERR_SET_ARMGPIO_PINS_INV_GPIOPIN Invalid GPIO pin selected for ARM output (valid 0-15 + output enable in bit[4]) + * \retval MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR ARM returned error setting GPIO pins + */ +mykonosGpioErr_t MYKONOS_setArmGpioPins(mykonosDevice_t *device) +{ + uint8_t i = 0; + uint8_t gpioConfig[3] = {0}; + uint8_t signalId[12] = {ORX_TRIGGER_SIGNALID, ORX_MODE_0_SIGNALID, ORX_MODE_1_SIGNALID, ORX_MODE_2_SIGNALID, RX1_ENABLE_ACK_SIGNALID, + RX2_ENABLE_ACK_SIGNALID, TX1_ENABLE_ACK_SIGNALID, TX2_ENABLE_ACK_SIGNALID, ORX1_ENABLE_ACK_SIGNALID, ORX2_ENABLE_ACK_SIGNALID, + SRX_ENABLE_ACK_SIGNALID, TX_OBS_SELECT_SIGNALID}; + uint32_t timeoutMs = 0; + uint8_t cmdStatusByte = 0; + uint32_t gpioOe = 0; + uint32_t gpioUsedMask = 0; + mykonosGpioErr_t retval = MYKONOS_ERR_GPIO_OK; + + const uint8_t GPIO_CTRL_OBJECTID = 0x60; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setArmGpioPins()\n"); +#endif + + if (device->auxIo->armGpio == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_ARMGPIO_INV_POINTER, + getGpioMykonosErrorMessage(MYKONOS_ERR_SET_ARMGPIO_INV_POINTER)); + return MYKONOS_ERR_SET_ARMGPIO_INV_POINTER; + } + + /* Write ARM set command to setup which ARM signals are using which GPIO pins */ + /* Setup input pins for ORX_MODE[2:0] and ORX_MODE_Trigger if orx is in pin mode */ + for(i = 0; i < sizeof(signalId); i++) + { + gpioConfig[0] = GPIO_CTRL_OBJECTID; + gpioConfig[1] = signalId[i]; + + switch(signalId[i]) + { + case ORX_TRIGGER_SIGNALID: gpioConfig[2] = device->auxIo->armGpio->orxTriggerPin; break; + case ORX_MODE_0_SIGNALID: gpioConfig[2] = device->auxIo->armGpio->orxMode0Pin; break; + case ORX_MODE_1_SIGNALID: gpioConfig[2] = device->auxIo->armGpio->orxMode1Pin; break; + case ORX_MODE_2_SIGNALID: gpioConfig[2] = device->auxIo->armGpio->orxMode2Pin; break; + case RX1_ENABLE_ACK_SIGNALID: gpioConfig[2] = device->auxIo->armGpio->rx1EnableAck; break; + case RX2_ENABLE_ACK_SIGNALID: gpioConfig[2] = device->auxIo->armGpio->rx2EnableAck; break; + case TX1_ENABLE_ACK_SIGNALID: gpioConfig[2] = device->auxIo->armGpio->tx1EnableAck; break; + case TX2_ENABLE_ACK_SIGNALID: gpioConfig[2] = device->auxIo->armGpio->tx2EnableAck; break; + case ORX1_ENABLE_ACK_SIGNALID: gpioConfig[2] = device->auxIo->armGpio->orx1EnableAck; break; + case ORX2_ENABLE_ACK_SIGNALID: gpioConfig[2] = device->auxIo->armGpio->orx2EnableAck; break; + case SRX_ENABLE_ACK_SIGNALID: gpioConfig[2] = device->auxIo->armGpio->srxEnableAck; break; + case TX_OBS_SELECT_SIGNALID: gpioConfig[2] = device->auxIo->armGpio->txObsSelect; break; + default: + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_ARMGPIO_PINS_INV_SIGNALID, + getGpioMykonosErrorMessage(MYKONOS_ERR_SET_ARMGPIO_PINS_INV_SIGNALID)); + return MYKONOS_ERR_SET_ARMGPIO_PINS_INV_SIGNALID; + } + } + + if (gpioConfig[2] > 0x1F) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_ARMGPIO_PINS_INV_GPIOPIN, + getGpioMykonosErrorMessage(MYKONOS_ERR_SET_ARMGPIO_PINS_INV_GPIOPIN)); + return MYKONOS_ERR_SET_ARMGPIO_PINS_INV_GPIOPIN; + } + + /* if output signal */ + if ((signalId[i] >= RX1_ENABLE_ACK_SIGNALID) && (gpioConfig[2] != 0)) + { + gpioOe |= (uint32_t)(((gpioConfig[2] >> 4) & 0x01) << (gpioConfig[2] & 0x0F)); /* 1 = output */ + gpioUsedMask |= (uint32_t)(1 << (gpioConfig[2] & 0x0F)); + } + + /* if input signal and orx Pin mode enabled - currently only input pins are orx pin mode control */ + if ((signalId[i] < RX1_ENABLE_ACK_SIGNALID) && (device->auxIo->armGpio->orxPinMode > 0)) + { + gpioUsedMask |= (1 << (gpioConfig[2] & 0x1F)); + } + + retval = (mykonosGpioErr_t)MYKONOS_sendArmCommand(device, MYKONOS_ARM_SET_OPCODE, &gpioConfig[0], sizeof(gpioConfig)); + if (retval != MYKONOS_ERR_GPIO_OK) + { + return retval; + } + + timeoutMs = 1000; + + if (( retval = (mykonosGpioErr_t)MYKONOS_waitArmCmdStatus(device, MYKONOS_ARM_SET_OPCODE, timeoutMs, &cmdStatusByte)) != MYKONOS_ERR_GPIO_OK) + { + return retval; + } + + if (cmdStatusByte > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR, + getGpioMykonosErrorMessage(MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR)); + return MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR; + } + } + + /* Mykonos SPI regs to set GPIO OE direction only for pins used by ARM */ + if ((retval = MYKONOS_setGpioOe(device, gpioOe, gpioUsedMask)) != MYKONOS_ERR_GPIO_OK) + { + return retval; + } + + /* if any output pins enabled, write GPIO nibble source control. ARM outputs only allowed on GPIO[15:0]*/ + if (gpioOe & 0x000F) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_SOURCE_CONTROL_LOWER_BYTE, 0x09, 0x0F, 0); + } + + if (gpioOe & 0x00F0) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_SOURCE_CONTROL_LOWER_BYTE, 0x09, 0xF0, 4); + } + + if (gpioOe & 0x0F00) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_SOURCE_CONTROL_UPPER_BYTE, 0x09, 0x0F, 0); + } + + if (gpioOe & 0xF000) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_SOURCE_CONTROL_UPPER_BYTE, 0x09, 0xF0, 4); + } + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Sets up the auxiliary ADC + * + * This function configures the AuxADC with the requested decimation. The AuxADC clock is set as close + * as possible to 40MHz. The AuxADC conversion time = (1/40Mhz) * decimation, where the decimation ranges + * from 256 AuxADC clock cycles to 32768 AuxADc clock cycles. + * + * Note: The AuxADC is intended for relative measurements. Two back to back measurements can allow a delta + * measurement with 12bit resolution. If absolute measurements are required, an accurate + * reference should be first measured on AuxADC0 input and used to calibrate the offset/gain error of the AuxADC. + * The reference would need to be measured before each measurement to account for measurement variations caused + * by the transmitter/receiver transients as other circuits in the device are being powered up/down. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device Pointer to the device settings structure + * \param adcDecimation ADC decimation factor (0-7). Decimates by 256 * 2^(adcDecimation) ADC clock cycles. + * \param enable Stop/run ADC (0/1) + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_SETUPAUXADC_INV_VCODIV CLKPLL VCO divider is invalid - Check CLKPLL setup + * \retval MYKONOS_ERR_INV_AUX_ADC_DEC_PARM AuxADC decimation out of range (valid 0-7) + */ +mykonosGpioErr_t MYKONOS_setupAuxAdcs(mykonosDevice_t *device, uint8_t adcDecimation, uint8_t enable) +{ + uint32_t hsDigClk_kHz = 0; + uint32_t auxAdcDiv = 0; + uint32_t auxAdcClk_kHz = 40000; + uint32_t vcoDiv = (uint32_t)device->clocks->clkPllVcoDiv; + uint8_t vcoDivTimes10 = 10; + + const uint8_t AUXADC_POWER_BIT_MASK = 0x80; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setupAuxAdcs()\n"); +#endif + + if (enable == 0) + { + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_0, 0xCF); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AUX_ADC_CFG, 0x01); + + return MYKONOS_ERR_GPIO_OK; + } + else + { + switch(vcoDiv) + { + case VCODIV_1: + vcoDivTimes10 = 10; + break; + case VCODIV_1p5: + vcoDivTimes10 = 15; + break; + case VCODIV_2: + vcoDivTimes10 = 20; + break; + case VCODIV_3: + vcoDivTimes10 = 30; + break; + + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETUPAUXADC_INV_VCODIV, + getGpioMykonosErrorMessage(MYKONOS_ERR_SETUPAUXADC_INV_VCODIV)); + return MYKONOS_ERR_SETUPAUXADC_INV_VCODIV; + } + + hsDigClk_kHz = (device->clocks->clkPllVcoFreq_kHz / vcoDivTimes10 / device->clocks->clkPllHsDiv) * 10; + auxAdcDiv = ((hsDigClk_kHz / 2) / (auxAdcClk_kHz)) - 1; + + if (auxAdcDiv > 63) + { + auxAdcDiv = 63; + } + + if (adcDecimation > 0x07) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AUX_ADC_DEC_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_INV_AUX_ADC_DEC_PARM)); + return MYKONOS_ERR_INV_AUX_ADC_DEC_PARM; + } + + CMB_SPIWriteByte (device->spiSettings, MYKONOS_ADR_AUX_ADC_CLOCK_DIVIDE, (uint8_t)(auxAdcDiv)); + CMB_SPIWriteByte (device->spiSettings, MYKONOS_ADDR_AUX_ADC_CFG, (uint8_t)((adcDecimation << 1))); + CMB_SPIWriteByte (device->spiSettings, MYKONOS_ADDR_AUX_ADC_SEL, 0x00); /* Set AuxADC select to AuxADC0 */ + CMB_SPIWriteField (device->spiSettings, MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_0, 0, AUXADC_POWER_BIT_MASK, 7); + + /* Set Clock enable bit to latch divider */ + CMB_SPIWriteByte (device->spiSettings, MYKONOS_ADR_AUX_ADC_CLOCK_DIVIDE, (uint8_t)(auxAdcDiv | 0x80)); + } + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Sets the selected channel of the auxiliary ADC + * + * After setting the AuxADC channel, wait at least 1 AuxADC conversion time before + * reading back the AuxADC value. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param auxAdcChannel desired Aux ADC input(0-4 and 16 = temperature sensor) + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_INV_AUX_ADC_CHAN_PARM Invalid AuxADC channel (valid 0-4 and 16) + */ +mykonosGpioErr_t MYKONOS_setAuxAdcChannel(mykonosDevice_t *device, mykonosAuxAdcChannels_t auxAdcChannel) +{ + uint8_t currentAuxAdcChan = 0x00; + + const uint8_t CHANNEL_MASK = 0x17; + const uint8_t POWER_UP_AUXADC = 0x00; + const uint8_t POWER_DOWN_AUXADC = 0x01; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setAuxAdcChannel()\n"); +#endif + + if (((uint8_t)auxAdcChannel & ~CHANNEL_MASK) > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_INV_AUX_ADC_CHAN_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_INV_AUX_ADC_CHAN_PARM)); + return MYKONOS_ERR_INV_AUX_ADC_CHAN_PARM; + } + + /* Read current selected channel, if different power down AUXADC and change AUXADC */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_AUX_ADC_SEL, ¤tAuxAdcChan); + if (currentAuxAdcChan != (uint8_t)auxAdcChannel) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AUX_ADC_CFG, POWER_DOWN_AUXADC, 0x01, 0); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AUX_ADC_SEL, ((auxAdcChannel & MYK_AUXADC_0_DIV2) ? 0: auxAdcChannel)); + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AUX_ADC_CFG, POWER_UP_AUXADC, 0x01, 0); + } + + /* Invalid AuxADC channel, the only valid channel for external ref is channel 0 */ + if (auxAdcChannel == MYK_AUXADC_0_DIV2) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_1, 0x01, 0x04, 2); + } + else if (auxAdcChannel == MYK_AUXADC_0) + { + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_1, 0x00, 0x04, 2); + } + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Reads from the selected channel of the auxiliary ADC + * + * Before using this function to read back the AuxADC value of the + * currently selected AuxADC, make sure that at least 1 conversion time + * of the ADC has passed since setting the AuxADC channel. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param adcCode is a pointer for return of the 12bit ADC read value + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_READAUXADC_NULL_PARAM Function parameter adcCode is a NULL pointer + */ +mykonosGpioErr_t MYKONOS_readAuxAdc(mykonosDevice_t *device, uint16_t *adcCode) +{ + uint8_t adcNibble = 0; + + const uint8_t AUXADC_LOCK_BIT_MASK = 0x80; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_readAuxAdcs()\n"); +#endif + + if (adcCode == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READAUXADC_NULL_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_READAUXADC_NULL_PARAM)); + return MYKONOS_ERR_READAUXADC_NULL_PARAM; + } + + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_AUX_ADC_CFG, 1, AUXADC_LOCK_BIT_MASK, 7); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_AUX_ADC_READ_MSB, &adcNibble); + *adcCode = adcNibble << 4; + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_AUX_ADC_READ_LSB, &adcNibble); + *adcCode |= (adcNibble & 0x0F); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Sets up the 10 AuxDACs on the Mykonos device. + * + * This function uses the configuration in the Mykonos device data structure AuxIO substructure to + * setup which of the ten AuxDACs are enabled, their slope, Vref(mid point) and their initial DAC code. + * + * This function can be called any time after MYKONOS_initialize() to reconfigure, enable, disable the + * different AuxDAC outputs. The AuxDACs are used in manual control mode. After calling this setup + * function, it is possible to change a particular AuxDAC code by calling the writeAuxDac() function. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->auxIo->auxDacEnable: 1= enabled, 0 = disabled + * - device->auxIo->auxDacSlope[i]: 0 = 1.404mv/code, 1= 0.702mV/code + * - device->auxIo->auxDacVref: 0 = 1v midpoint, 1 = 1.5v midpoint, 2 = 2v midpoint, 3 = 2.5v midpoint + * - device->auxIo->auxDacValue[i]: 10bit DAC code (0-1023) + * + * \param device is a pointer to the device settings structure + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_SETUPAUXDAC_NULL_PARAM device->auxIo structure has a NULL pointer + * \retval MYKONOS_ERR_SETUPAUXDAC_INV_AUXDACCODE auxDAC code is out of range (valid 0-1023) + */ +mykonosGpioErr_t MYKONOS_setupAuxDacs(mykonosDevice_t *device) +{ + uint8_t i = 0; /* for loop index */ + uint8_t auxDacConfig = 0 ; + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setupAuxDacs()\n"); +#endif + + if (device->auxIo == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETUPAUXDAC_NULL_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_SETUPAUXDAC_NULL_PARAM)); + return MYKONOS_ERR_SETUPAUXDAC_NULL_PARAM; + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_5_0, 0x3F); /* Enable Manual AuxDAC control for all AuxDACs[5:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_9_6, 0x0F); /* Enable Manual AuxDAC control for all AuxDACs[9:6] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_5_0, 0x3F); /* Power down all AuxDACs[5:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_9_6, 0x0F); /* Power down all AuxDACs[9:6] */ + + for (i = 0; i < 10; i++) + { + /* If auxDac enabled, setup AuxDAC configuration */ + if ((device->auxIo->auxDacEnable >> i) & 0x01) + { + if (device->auxIo->auxDacValue[i] > 1023) + { + device->auxIo->auxDacValue[i] = 1023; /* clip value to max */ + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETUPAUXDAC_INV_AUXDACCODE, + getGpioMykonosErrorMessage(MYKONOS_ERR_SETUPAUXDAC_INV_AUXDACCODE)); + error = MYKONOS_ERR_SETUPAUXDAC_INV_AUXDACCODE; /* Complete AuxDAC configuration before returning error code */ + } + + auxDacConfig = 0x00; /* initialize config variable */ + + if (device->auxIo->auxDacSlope[i] > 0) + { + auxDacConfig = 0x40; /* bit [6] sets the slope */ + } + + auxDacConfig |= ((device->auxIo->auxDacVref[i] & 0x03) << 4); + + /* Write AuxDAC config and DAC code */ + CMB_SPIWriteByte(device->spiSettings, (MYKONOS_ADDR_AUXDAC_0_WORD_MSB + (i * 2)), (auxDacConfig | ((device->auxIo->auxDacValue[i] >> 8) & 0x0F))); + CMB_SPIWriteByte(device->spiSettings, (MYKONOS_ADDR_AUXDAC_0_WORD_MSB + (i * 2 ) + 1), (device->auxIo->auxDacValue[i] & 0xFF)); + } + } + + /* Write enable bit to latch DAC codes into DACs */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AUX_DAC_LATCH_CONTROL, 0x01); + + /* Power up selected AuxDacs */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_5_0, (~device->auxIo->auxDacEnable & 0x3F)); /* Power up enabled AuxDACs[5:0] */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_9_6, (((uint16_t)(~device->auxIo->auxDacEnable) >> 6) & 0x0F)); /* Power up enabled AuxDACs[9:6] */ + + return error; +} + +/** + * \brief Writes the current AuxDAC code for a particular AuxDAC + * + * This function updates the 10bit code that controls the AuxDAC output voltage. + * The auxDacCode is updated for the specified auxDAC. Also the auxDacCode is written + * to the device data structure for future reference. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->auxIo->auxDacValue[i] + * + * \param device is a pointer to the device settings structure + * \param auxDacIndex AuxDAC to set the DAC code for (0-9) + * \param auxDacCode DAC code to update the AuxDAC to. Sets the output voltage of the DAC (valid 0-1023) + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACCODE AuxDac code invalid (valid 0-1023) + * \retval MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACINDEX AuxDAC index out of range (valid 0-9) + * \retval MYKONOS_ERR_WRITEAUXDAC_NULL_AUXIO device->auxIo has NULL pointer + */ +mykonosGpioErr_t MYKONOS_writeAuxDac(mykonosDevice_t *device, uint8_t auxDacIndex, uint16_t auxDacCode) +{ + uint16_t auxDacAddr = 0; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_writeAuxDac()\n"); +#endif + + if (auxDacCode > 1023) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACCODE, + getGpioMykonosErrorMessage(MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACCODE)); + return MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACCODE; + } + + if (auxDacIndex > 9) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACINDEX, + getGpioMykonosErrorMessage(MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACINDEX)); + return MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACINDEX; + } + + if (device->auxIo == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_WRITEAUXDAC_NULL_AUXIO, + getGpioMykonosErrorMessage(MYKONOS_ERR_WRITEAUXDAC_NULL_AUXIO)); + return MYKONOS_ERR_WRITEAUXDAC_NULL_AUXIO; + } + + device->auxIo->auxDacValue[auxDacIndex] = auxDacCode; + + auxDacAddr = MYKONOS_ADDR_AUXDAC_0_WORD_MSB + (auxDacIndex * 2); + + /* Write AuxDAC config and DAC code */ + CMB_SPIWriteField(device->spiSettings, auxDacAddr, (auxDacCode >> 8), 0x0F, 0); + CMB_SPIWriteByte(device->spiSettings, (auxDacAddr + 1), (auxDacCode & 0xFF)); + + /* Write enable bit to latch DAC codes into DACs */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_AUX_DAC_LATCH_CONTROL, 0x01); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Sets the Mykonos low voltage GPIO configuration registers + * + * Sets the low voltage GPIO pin direction for each low voltage GPIO pin and + * sets the source control mode (feature) for each group of 4 GPIO pins. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->auxIo->gpio - all members + * + * \param device is a pointer to the device settings structure + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_SET_GPIO_1V8_INV_POINTER device->auxIo->gpio pointer is NULL + * \retval MYKONOS_ERR_SET_GPIO_1V8_INV_MODE gpio structure members have invalid enum value for the GPIO source control mode. + */ +mykonosGpioErr_t MYKONOS_setupGpio(mykonosDevice_t *device) +{ + uint32_t srcWrite = 0x000000; + uint32_t oEnMask = 0x7FFFF; + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setupGpio()\n"); +#endif + + if (device->auxIo->gpio == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_GPIO_1V8_INV_POINTER, + getGpioMykonosErrorMessage(MYKONOS_ERR_SET_GPIO_1V8_INV_POINTER)); + return MYKONOS_ERR_SET_GPIO_1V8_INV_POINTER; + } + + /* write GPIO pin direction registers */ + if ((error = MYKONOS_setGpioOe(device, device->auxIo->gpio->gpioOe, oEnMask)) != MYKONOS_ERR_GPIO_OK) + { + return error; + } + + /* write GPIO source control mode */ + if (((uint8_t)device->auxIo->gpio->gpioSrcCtrl3_0 > 15) || ((uint8_t)device->auxIo->gpio->gpioSrcCtrl7_4 > 15) || + ((uint8_t)device->auxIo->gpio->gpioSrcCtrl11_8 > 15) || ((uint8_t)device->auxIo->gpio->gpioSrcCtrl15_12 > 15) || + ((uint8_t)device->auxIo->gpio->gpioSrcCtrl18_16 > 15)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_GPIO_1V8_INV_MODE, + getGpioMykonosErrorMessage(MYKONOS_ERR_SET_GPIO_1V8_INV_MODE)); + return MYKONOS_ERR_SET_GPIO_1V8_INV_MODE; + } + + srcWrite = (uint32_t)device->auxIo->gpio->gpioSrcCtrl3_0 + ((uint32_t)device->auxIo->gpio->gpioSrcCtrl7_4 << 4) + + ((uint32_t)device->auxIo->gpio->gpioSrcCtrl11_8 << 8) + ((uint32_t)device->auxIo->gpio->gpioSrcCtrl15_12 << 12) + + ((uint32_t)device->auxIo->gpio->gpioSrcCtrl18_16 << 16); + + error = MYKONOS_setGpioSourceCtrl(device, srcWrite); + + return error; +} + +/** + * \brief Sets the Mykonos low voltage GPIO output pins direction + * + * This function will set the GPIO direction given by the passed parameter, + * the direction can be either output or input. The gpioUsedMask parameter + * allows the function to only affect the GPIO pins of interest. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->auxIo->gpio->gpioOe + * + * \param device is a pointer to the device settings structure + * \param gpioOutEn (valid range 0 - 0x07FFFF), bit per GPIO pin, the direction is + * + * gpioOutEn[bit] | GPIO[bit] direction + * ----------------|------------------- + * 0 | input + * 1 | output + * + * \param gpioUsedMask Mask used to control which Oe bits are set/cleared. If + * mask bit =1, that bit will be modified by gpioOutEn bit + * + * \retval MYKONOS_ERR_GPIO_OE_INV_PARAM If the Output enable parameter is invalid + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setGpioOe(mykonosDevice_t *device, uint32_t gpioOutEn, uint32_t gpioUsedMask) +{ + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + + const uint32_t GPIO_OE_MASK = 0x7FFFF; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setGpioOe()\n"); +#endif + + /* Error checking for correct number of GPIOs available. */ + if (gpioOutEn > GPIO_OE_MASK ) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OE_INV_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_OE_INV_PARAM)); + return MYKONOS_ERR_GPIO_OE_INV_PARAM; + } + + /* Mykonos SPI regs to set GPIO OE direction */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_GPIO_DIR_CTL_7_0, (gpioOutEn & 0xFF), (gpioUsedMask & 0xFF), 0); + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_GPIO_DIR_CTL_15_8, ((gpioOutEn >> 8) & 0xFF), ((gpioUsedMask >> 8) & 0xFF), 0); + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_GPIO_DIR_CTL_18_16, ((gpioOutEn >> 16) & 0xFF), ((gpioUsedMask >> 16) & 0xFF), 0); + + /* Updating gpioConfig->gpioSetup->gpioOe output enable */ + if ((error = MYKONOS_getGpioOe(device, &gpioOutEn)) != MYKONOS_ERR_GPIO_OK) + { + return error; + } + + device->auxIo->gpio->gpioOe = gpioOutEn; + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + + +/** + * \brief Gets the Mykonos low voltage GPIO output pins direction + * + * This function will get the GPIO direction currently set in the device, + * the direction can be either output or input. The return gpioOutEn function + * parameter returns a bit per GPIO pin. 1 = output from the Mykonos Device, + * 0 = input into the Mykonos device. + * + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param *gpioOutEn a pointer to the data to be returned with the output enable reading + * + * gpioOutEn[bit] | GPIO[bit] direction + * ----------------|------------------- + * 0 | input + * 1 | output + * + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_GETGPIO_OE_NULL_PARM gpioOutEn function parameter is NULL + */ +mykonosGpioErr_t MYKONOS_getGpioOe(mykonosDevice_t *device, uint32_t *gpioOutEn) +{ + uint8_t readBytes[3] = {0}; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getGpioOe()\n"); +#endif + + if (gpioOutEn == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETGPIO_OE_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETGPIO_OE_NULL_PARM)); + return MYKONOS_ERR_GETGPIO_OE_NULL_PARM; + } + + /* Reading GPIO output enable registers */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_DIR_CTL_7_0, &readBytes[0]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_DIR_CTL_15_8, &readBytes[1]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_DIR_CTL_18_16, &readBytes[2]); + + /* Updating gpioConfig->gpioSetup->gpioOe output enable */ + *gpioOutEn = ((uint32_t)(readBytes[2] & 0x07) << 16) | ((uint32_t)(readBytes[1]) << 8) | (uint32_t)(readBytes[0]); + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + + + +/** + * \brief Sets the Mykonos GPIO source control for different GPIO functionality + * + * This function will only affect the GPIO pins that have their OE direction set to output. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gpioSrcCtrl nibble based source control, this is a 32 bit containing + * 5 nibbles that will be set the source control. + * + * \retval MYKONOS_ERR_GPIO_SRC_PARAM_INV If the source control parameter is invalid + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setGpioSourceCtrl(mykonosDevice_t *device, uint32_t gpioSrcCtrl) +{ + const uint32_t GPIO_SRC_MASK = 0xFFFFF; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setGpioSourceCtrl()\n"); +#endif + + /* writing GPIO configuration registers */ + if (gpioSrcCtrl > GPIO_SRC_MASK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_SRC_PARAM_INV, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_SRC_PARAM_INV)); + return MYKONOS_ERR_GPIO_SRC_PARAM_INV; + } + + /* writing GPIO configuration registers */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SOURCE_CONTROL_LOWER_BYTE, (gpioSrcCtrl & 0xFF)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SOURCE_CONTROL_UPPER_BYTE, ((gpioSrcCtrl >> 8) & 0xFF)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_SOURCE_CONTROL_EXTRA_BITS, ((gpioSrcCtrl >> 16) & 0x0F)); + + /* Updating gpioConfig->gpioSetup source control */ + device->auxIo->gpio->gpioSrcCtrl3_0 = (mykonosGpioMode_t)(gpioSrcCtrl & 0x0F); + device->auxIo->gpio->gpioSrcCtrl7_4 = (mykonosGpioMode_t)((gpioSrcCtrl >> 4) & 0x0F); + device->auxIo->gpio->gpioSrcCtrl11_8 = (mykonosGpioMode_t)((gpioSrcCtrl >> 8) & 0x0F); + device->auxIo->gpio->gpioSrcCtrl15_12 = (mykonosGpioMode_t)((gpioSrcCtrl >> 12) & 0x0F); + device->auxIo->gpio->gpioSrcCtrl18_16 = (mykonosGpioMode_t)((gpioSrcCtrl >> 16) & 0x0F); + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Reads the Mykonos GPIO source control for different GPIO functionality + * + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gpioSrcCtrl nibble based source control, this is a 32 bit containing + * 5 nibbles that will be set the source control. + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getGpioSourceCtrl(mykonosDevice_t *device, uint32_t *gpioSrcCtrl) +{ + uint8_t readBytes[3] = {0}; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getGpioSourceCtrl()\n"); +#endif + + if (gpioSrcCtrl == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GET_GPIO_SOURCE_CONTROL_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GET_GPIO_SOURCE_CONTROL_NULL_PARM)); + return MYKONOS_ERR_GET_GPIO_SOURCE_CONTROL_NULL_PARM; + } + + /* Reading GPIO output enable registers */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_SOURCE_CONTROL_LOWER_BYTE, &readBytes[0]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_SOURCE_CONTROL_UPPER_BYTE, &readBytes[1]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_SOURCE_CONTROL_EXTRA_BITS, &readBytes[2]); + + /* Updating gpioConfig->gpioSetup->gpioOe output enable */ + *gpioSrcCtrl = ((uint32_t)(readBytes[2] & 0x0F) << 16) | ((uint32_t)(readBytes[1]) << 8) | (uint32_t)(readBytes[0]); + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + + + +/** + * \brief Sets the Mykonos 3.3 VDC GPIO configuration registers + * + * This function sets the GPIO 3.3v pin direction (1=output, 0=input) and + * sets the mode of each nibble of GPIO 3.3v pins. See the mykonosGpio3v3Mode_t + * enum for possible modes. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->auxIo->gpio3v3 - all members + * + * \param device is a pointer to the device settings structure + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_SET_GPIO_3V3_INV_POINTER device->auxIo->gpio3v3 pointer is NULL + * \retval MYKONOS_ERR_SET_GPIO_3V3_INV_MODE gpio3v3 members have invalid enum value for the GPIO3v3 source control mode. + */ +mykonosGpioErr_t MYKONOS_setupGpio3v3(mykonosDevice_t *device) +{ + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setupGpio3v3()\n"); +#endif + + if (device->auxIo->gpio3v3 == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_GPIO_3V3_INV_POINTER, + getGpioMykonosErrorMessage(MYKONOS_ERR_SET_GPIO_3V3_INV_POINTER)); + return MYKONOS_ERR_SET_GPIO_3V3_INV_POINTER; + } + else + { + /* write GPIO pin direction registers */ + if ((error = MYKONOS_setGpio3v3Oe(device, device->auxIo->gpio3v3->gpio3v3Oe)) != MYKONOS_ERR_GPIO_OK) + + /* write GPIO3v3 mode */ + if (((uint8_t)device->auxIo->gpio3v3->gpio3v3SrcCtrl3_0 > 15) || + ((uint8_t)device->auxIo->gpio3v3->gpio3v3SrcCtrl7_4 > 15) || + ((uint8_t)device->auxIo->gpio3v3->gpio3v3SrcCtrl11_8 > 15)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_GPIO_3V3_INV_MODE, + getGpioMykonosErrorMessage(MYKONOS_ERR_SET_GPIO_3V3_INV_MODE)); + return MYKONOS_ERR_SET_GPIO_3V3_INV_MODE; + } + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_LSB_SRC_CTL, ((device->auxIo->gpio3v3->gpio3v3SrcCtrl7_4 << 4) | device->auxIo->gpio3v3->gpio3v3SrcCtrl3_0)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_MSB_SRC_CTL, (device->auxIo->gpio3v3->gpio3v3SrcCtrl11_8 & 0x0F)); + + return error; + } +} + +/** + * \brief If the GPIO3v3 pins are setup for BITBANG mode, this function sets + * the output pin levels per pin + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->auxIo->gpio3v3 - all members + * + * \param device is a pointer to the device settings structure + * \param gpio3v3PinLevel Bit per pin to set the level of each GPIO3v3 output pin + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setGpio3v3PinLevel(mykonosDevice_t *device, uint16_t gpio3v3PinLevel) +{ + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setGpio3v3PinLevel()\n"); +#endif + + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_SPI_SRC_7_0, (gpio3v3PinLevel & 0xFF)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_SPI_SRC_15_8, ((gpio3v3PinLevel >> 8) & 0x0F)); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Reads the Mykonos 3.3 VDC GPIO pin output levels for BITBANG mode + * + * This function allows reading the value that the 3.3v GPIO output pins are + * set to drive out the pins. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gpio3v3SetLevel is a unit16_t pointer which contains the level of each GPIO3V3 pin (bit per pin) + * + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_GETGPIO3V3OUT_NULL_PARM gpio3v3SetLevel pointer is NULL in function parameter + */ +mykonosGpioErr_t MYKONOS_getGpio3v3SetLevel(mykonosDevice_t *device, uint16_t *gpio3v3SetLevel) +{ + uint8_t readBytes[2] = {0}; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getGpio3v3SetLevel()\n"); +#endif + + if (gpio3v3SetLevel == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETGPIO3V3OUT_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETGPIO3V3OUT_NULL_PARM)); + return MYKONOS_ERR_GETGPIO3V3OUT_NULL_PARM; + } + + /* reading the registers into two-byte array */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_SPI_SRC_7_0, &readBytes[0]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_SPI_SRC_15_8, &readBytes[1]); + + /* performing concatenation and assigning value to gpio3v3SpiRead */ + *gpio3v3SetLevel = ((uint16_t)(readBytes[1] & 0x0F) << 8) | (uint16_t)(readBytes[0]); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Reads the Mykonos 3.3 VDC GPIO pin levels for BITBANG mode + * + * Note: this function is only capable of reading back pin levels for the + * 3.3v pins set to be inputs. Any pins set to be a GPIO output will read + * back as zero. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gpio3v3PinLevel is a unit16_t pointer which contains the level of each GPIO3V3 pin + * that is defined as an input + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_GETGPIO3V3SPI_NULL_PARM gpio3v3PinLevel pointer is NULL in function parameter + */ +mykonosGpioErr_t MYKONOS_getGpio3v3PinLevel(mykonosDevice_t *device, uint16_t *gpio3v3PinLevel) +{ + uint8_t readBytes[2] = {0}; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getGpio3v3PinLevel()\n"); +#endif + + if (gpio3v3PinLevel == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETGPIO3V3SPI_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETGPIO3V3SPI_NULL_PARM)); + return MYKONOS_ERR_GETGPIO3V3SPI_NULL_PARM; + } + + /* reading the registers for input pin levels */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_SPI_READ_7_0, &readBytes[0]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_SPI_READ_15_8, &readBytes[1]); + + *gpio3v3PinLevel = ((uint16_t)(readBytes[1] & 0x0F) << 8) | (uint16_t)(readBytes[0]); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief This function sets the Pin direction control for the Mykonos 3.3 VDC GPIO. + * + * The bits in gpio3v3OutEn are used to configure each corresponding pin as an input or an output. + * If the bit is set, the pin is configured as an output, and if it is clear the pin is configured as an input. + * For example, setting gpio3v3OutEn = 0x02 will configure GPIO_3p3_2 as an output and the rest pins as inputs. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - device->auxIo->gpio3v3 - all members + * + * \param device is a pointer to the device settings structure + * \param gpio3v3OutEn Bit per pin to set the level of each GPIO3v3 output pin + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setGpio3v3Oe(mykonosDevice_t *device, uint16_t gpio3v3OutEn) +{ + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getGpio3v3Oe()\n"); +#endif + + /* write GPIO pin direction registers */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_DIR_CTL_7_0, (gpio3v3OutEn & 0xFF)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_DIR_CTL_15_8, ((gpio3v3OutEn >> 8) & 0x0F)); + + /* update device->auxIo->gpio3v3 structure */ + device->auxIo->gpio3v3->gpio3v3Oe = gpio3v3OutEn; + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Reads the Mykonos 3.3 VDC GPIO pin direction + * + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gpio3v3OutEn is a unit16_t pointer which will contain the output enable parameter, + * this will be a bit field, if a bit is set then the corresponding GPIO pin is an output, + * if the bit is not set then the corresponding pin is an input + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_GPIO3V3OUTEN_NULL_PARM gpio3v3OutEn pointer is NULL in function parameter + */ +mykonosGpioErr_t MYKONOS_getGpio3v3Oe(mykonosDevice_t *device, uint16_t *gpio3v3OutEn) +{ + uint8_t readBytes[2] = {0}; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getGpio3v3Oe()\n"); +#endif + + /* checking for null parameter */ + if (gpio3v3OutEn == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO3V3OUTEN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO3V3OUTEN_NULL_PARM)); + return MYKONOS_ERR_GPIO3V3OUTEN_NULL_PARM; + } + + /* reading the registers for input pin levels */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_DIR_CTL_7_0, &readBytes[0]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_DIR_CTL_15_8, &readBytes[1]); + + *gpio3v3OutEn = ((uint16_t)(readBytes[1] & 0x0F) << 8) | (uint16_t)(readBytes[0]); + + return MYKONOS_ERR_GPIO_OK; +} + + +/** + * \brief Sets the Mykonos GPIO 3.3 VDC source control for different GPIO fucntionality + * + * This function will only affect the GPIO pins that have their OE direction set to output. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gpio3v3SrcCtrl nibble based source control, this is a 12 bit containing + * 3 nibbles that will be set the source control. + * + * \retval MYKONOS_ERR_SET_GPIO_3V3_INV_SRC_CTRL gpio3v3 members have invalid value for the GPIO3v3 source control mode. + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setGpio3v3SourceCtrl(mykonosDevice_t *device, uint16_t gpio3v3SrcCtrl) +{ + const uint16_t GPIO_SRC_MASK = 0x0FFF; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setGpio3v3SourceCtrl()\n"); +#endif + + /* writing GPIO configuration registers */ + if (gpio3v3SrcCtrl > GPIO_SRC_MASK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SET_GPIO_3V3_INV_SRC_CTRL, + getGpioMykonosErrorMessage(MYKONOS_ERR_SET_GPIO_3V3_INV_SRC_CTRL)); + return MYKONOS_ERR_SET_GPIO_3V3_INV_SRC_CTRL; + } + + /* writing GPIO configuration registers */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_LSB_SRC_CTL, (gpio3v3SrcCtrl & 0xFF)); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_MSB_SRC_CTL, ((gpio3v3SrcCtrl >> 8) & 0xFF)); + + /* Updating gpioConfig->gpioSetup source control */ + device->auxIo->gpio3v3->gpio3v3SrcCtrl3_0 = (mykonosGpio3v3Mode_t)(gpio3v3SrcCtrl & 0x0F); + device->auxIo->gpio3v3->gpio3v3SrcCtrl7_4 = (mykonosGpio3v3Mode_t)(gpio3v3SrcCtrl & 0xF0); + device->auxIo->gpio3v3->gpio3v3SrcCtrl11_8 = (mykonosGpio3v3Mode_t)((gpio3v3SrcCtrl >> 8) & 0x0F); + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Reads the Mykonos 3v3 GPIO source control for different GPIO functionality + * + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gpio3v3SrcCtrl nibble based source control, this is a 12 bit containing + * 3 nibbles that will be set the source control. + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getGpio3v3SourceCtrl(mykonosDevice_t *device, uint16_t *gpio3v3SrcCtrl) +{ + uint8_t readBytes[2] = {0}; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getGpio3v3SourceCtrl()\n"); +#endif + + /* checking for null parameter */ + if (gpio3v3SrcCtrl == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO3V3OUTEN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO3V3OUTEN_NULL_PARM)); + return MYKONOS_ERR_GPIO3V3OUTEN_NULL_PARM; + } + + /* Reading GPIO output enable registers */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_LSB_SRC_CTL, &readBytes[0]); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_GPIO_3V3_MSB_SRC_CTL, &readBytes[1]); + + /* Updating gpioConfig->gpioSetup->gpioOe output enable */ + *gpio3v3SrcCtrl = ((uint16_t)(readBytes[1] & 0xFF) << 8) | ((uint16_t)(readBytes[0])); + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + + +/** + * \brief Gain compensation enable and setup function. + * + * The gain compensation block is a function that compensates for the attenuation in the internal attenuator for the Rx channels. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gainComp which is a mykonosGainComp_t structure. + * \param enable this parameter enables or disables the gain compensation block. + * enable = 1 + * disable = 0 + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_GAINCOMP_SET_NULL_STRUCT gain compensation structure gainComp is not initialised + * \retval MYKONOS_ERR_GAINCOMP_INV_RX1_OFFSET gain compensation structure gainComp->rx1Offset is invalid + * \retval MYKONOS_ERR_GAINCOMP_INV_RX2_OFFSET gain compensation structure gainComp->rx2Offset is invalid + * \retval MYKONOS_ERR_GAINCOMP_INV_STEP gain compensation structure gainComp->compStep is invalid + * \retval MYKONOS_ERR_GAINCOMP_INV_EN enable is not valid + */ +mykonosGpioErr_t MYKONOS_setRxGainCompensation (mykonosDevice_t *device, mykonosGainComp_t *gainComp, uint8_t enable) +{ + uint8_t regWr2 = 0x00; + uint8_t regWr3 = 0x00; + uint8_t regWr4 = 0x00; + + /* Max parameter values for error checking */ + const uint8_t RXOFFSET_RANGE = 0x1F; + const uint8_t STEP_RANGE = 0x07; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setRxGainCompensation()\n"); +#endif + + /* Check for gainComp initialised */ + if (gainComp == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GAINCOMP_SET_NULL_STRUCT, + getGpioMykonosErrorMessage(MYKONOS_ERR_GAINCOMP_SET_NULL_STRUCT)); + return MYKONOS_ERR_GAINCOMP_SET_NULL_STRUCT; + } + + /* Check for enable */ + if (enable > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GAINCOMP_INV_EN, + getGpioMykonosErrorMessage(MYKONOS_ERR_GAINCOMP_INV_EN)); + return MYKONOS_ERR_GAINCOMP_INV_EN; + } + else if (enable == 1) + { + /* Check for gain compensation Rx1 offset range */ + if (gainComp->rx1Offset > RXOFFSET_RANGE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GAINCOMP_INV_RX1_OFFSET, + getGpioMykonosErrorMessage(MYKONOS_ERR_GAINCOMP_INV_RX1_OFFSET)); + return MYKONOS_ERR_GAINCOMP_INV_RX1_OFFSET; + } + + /* Check for gain compensation Rx2 offset range */ + if (gainComp->rx2Offset > RXOFFSET_RANGE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GAINCOMP_INV_RX2_OFFSET, + getGpioMykonosErrorMessage(MYKONOS_ERR_GAINCOMP_INV_RX2_OFFSET)); + return MYKONOS_ERR_GAINCOMP_INV_RX2_OFFSET; + } + + /* Check for gain compensation step range */ + if (gainComp->compStep > STEP_RANGE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GAINCOMP_INV_STEP, + getGpioMykonosErrorMessage(MYKONOS_ERR_GAINCOMP_INV_STEP)); + return MYKONOS_ERR_GAINCOMP_INV_STEP; + } + + /* Enabling gain compensation block */ + regWr4 = 0x88 | gainComp->compStep; + regWr3 = gainComp->rx2Offset; + regWr2 = gainComp->rx1Offset; + } + + /* Write gain compensation setup to device */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX1_GAIN_COMP_OFFSET, regWr2); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX2_GAIN_COMP_OFFSET, regWr3); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX_GAIN_COMP_CFG, regWr4); + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Get gain compensation setup and enabled function. + * + * The gain compensation block is a function that compensates for the attenuation in the internal attenuator for the Rx channels. + * This function will get the current setup and the enable state of the block. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gainComp pointer to a mykonosGainComp_t structure, will held the current device gain compensation settings. + * \param enabled pointer this parameter will contain the enable state of the gain compensation block. + * enabled = 1 + * disabled = 0 + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_GAINCOMP_NULL_STRUCT gain compensation structure gainComp is not initialised + * \retval MYKONOS_ERR_GAINCOMP_EN_NULL_PARM enable is null pointer for the passed parameter + */ +mykonosGpioErr_t MYKONOS_getRxGainCompensation (mykonosDevice_t *device, mykonosGainComp_t *gainComp, uint8_t *enabled) +{ + uint8_t regWr2 = 0x00; + uint8_t regWr3 = 0x00; + uint8_t regWr4 = 0x00; + + /* Mask parameter values populating mykonosGainComp_t structure */ + const uint8_t ENABLED_MASK = 0x80; + const uint8_t STEP_MASK = 0x07; + + /* Shift values for writing gain values */ + const uint8_t ENABLED_SHIFT = 0x07; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getRxGainCompensation()\n"); +#endif + + /* Check for gainComp for Null */ + if (gainComp == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GAINCOMP_NULL_STRUCT, + getGpioMykonosErrorMessage(MYKONOS_ERR_GAINCOMP_NULL_STRUCT)); + return MYKONOS_ERR_GAINCOMP_NULL_STRUCT; + } + + if (enabled == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GAINCOMP_EN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GAINCOMP_EN_NULL_PARM)); + return MYKONOS_ERR_GAINCOMP_EN_NULL_PARM; + } + + /* Read gain compensation setup from device */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_RX1_GAIN_COMP_OFFSET, ®Wr2); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_RX2_GAIN_COMP_OFFSET, ®Wr3); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_RX_GAIN_COMP_CFG, ®Wr4); + + + /* Parsing read data to passed by reference parameters */ + *enabled = (regWr4 & ENABLED_MASK) >> ENABLED_SHIFT; + gainComp->compStep = (regWr4 & STEP_MASK); + gainComp->rx2Offset = regWr3; + gainComp->rx1Offset = regWr2; + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + + +/** + * \brief Gain compensation enable and setup function for the observation channel. + * + * The gain compensation block is a function that compensates for the attenuation in the internal attenuator for the observation channels. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gainComp is a pointer to the mykonosObsRxGainComp_t structure. + * \param enable enables or disables the gain compensation block. + * enable = 1 + * disable = 0 + * + * \retval MYKONOS_ERR_OBS_RX_GAINCOMP_SET_NULL_STRUCT gain compensation structure gainComp is not initialised + * \retval MYKONOS_ERR_OBS_RX_GAINCOMP_INV_OFFSET gain compensation structure gainComp->obsRxOffset is invalid + * \retval MYKONOS_ERR_OBS_RX_GAINCOMP_INV_STEP gain compensation structure gainComp->compStep is invalid + * \retval MYKONOS_ERR_OBS_RX_GAINCOMP_INV_EN enable is not valid + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setObsRxGainCompensation (mykonosDevice_t *device, mykonosObsRxGainComp_t *gainComp, uint8_t enable) +{ + uint8_t regWr2 = 0x00; + uint8_t regWr3 = 0x00; + + /* Max parameter values for error checking */ + const uint8_t RXOFFSET_RANGE = 0x1F; + + /* Shift values for writing gain values */ + const uint8_t STEP_RANGE = 0x07; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setObsRxGainCompensation()\n"); +#endif + + /* Check for gainComp initialised */ + if (gainComp == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBS_RX_GAINCOMP_SET_NULL_STRUCT, + getGpioMykonosErrorMessage(MYKONOS_ERR_OBS_RX_GAINCOMP_SET_NULL_STRUCT)); + return MYKONOS_ERR_OBS_RX_GAINCOMP_SET_NULL_STRUCT; + } + + /* Check for enable */ + if (enable > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBS_RX_GAINCOMP_INV_EN, + getGpioMykonosErrorMessage(MYKONOS_ERR_OBS_RX_GAINCOMP_INV_EN)); + return MYKONOS_ERR_OBS_RX_GAINCOMP_INV_EN; + } + else if (enable == 1) + { + /* Check for gain compensation offset range */ + if (gainComp->obsRxOffset > RXOFFSET_RANGE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBS_RX_GAINCOMP_INV_OFFSET, + getGpioMykonosErrorMessage(MYKONOS_ERR_OBS_RX_GAINCOMP_INV_OFFSET)); + return MYKONOS_ERR_OBS_RX_GAINCOMP_INV_OFFSET; + } + + /* Check for gain compensation step range */ + if (gainComp->compStep > STEP_RANGE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBS_RX_GAINCOMP_INV_STEP, + getGpioMykonosErrorMessage(MYKONOS_ERR_OBS_RX_GAINCOMP_INV_STEP)); + return MYKONOS_ERR_OBS_RX_GAINCOMP_INV_STEP; + } + + /* Enabling gain compensation block */ + regWr3 = 0x88 | gainComp->compStep; + regWr2 = ((gainComp->obsRxOffset & 0x1E) >> 1) | ((gainComp->obsRxOffset & 0x01) << 4); + } + + /* Write gain compensation setup to device */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_OFFSET, regWr2); + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_CFG, regWr3); + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Get gain compensation setup and enabled function for the observation channel. + * + * The gain compensation block is a function that compensates for the attenuation in the internal attenuator for the observation + * channels. + * This function will get the current setup and the enable state of the block. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gainComp pointer to a mykonosObsRxGainComp_t structure, will held the current device gain compensation settings. + * \param enabled pointer this parameter will contain the enable state of the gain compensation block. + * enabled = 1 + * disabled = 0 + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_OBS_RX_GAINCOMP_NULL_STRUCT observation channel gain compensation structure gainComp is not initialised + * \retval MYKONOS_ERR_OBS_RX_GAINCOMP_EN_NULL_PARAM enabled is null pointer for the parameter passed + */ +mykonosGpioErr_t MYKONOS_getObsRxGainCompensation (mykonosDevice_t *device, mykonosObsRxGainComp_t *gainComp, uint8_t *enabled) +{ + uint8_t regRd2 = 0x00; + uint8_t regRd3 = 0x00; + + /* Masks values for populating mykonosObsRxGainComp_t structure */ + const uint8_t ENABLED_MASK = 0x80; + const uint8_t STEP_MASK = 0x07; + + /* Shift values for populating mykonosObsRxGainComp_t structure */ + const uint8_t ENABLED_SHIFT = 0x07; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getObsRxGainCompensation()\n"); +#endif + + /* Check for gainComp for Null */ + if (gainComp == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBS_RX_GAINCOMP_NULL_STRUCT, + getGpioMykonosErrorMessage(MYKONOS_ERR_OBS_RX_GAINCOMP_NULL_STRUCT)); + return MYKONOS_ERR_OBS_RX_GAINCOMP_NULL_STRUCT; + } + + if (enabled == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_OBS_RX_GAINCOMP_EN_NULL_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_OBS_RX_GAINCOMP_EN_NULL_PARAM)); + return MYKONOS_ERR_OBS_RX_GAINCOMP_EN_NULL_PARAM; + } + + /* Read gain compensation setup from device */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_OFFSET, ®Rd2); + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_CFG, ®Rd3); + + + /* Parsing read data to passed by reference parameters */ + *enabled = (regRd3 & ENABLED_MASK) >> ENABLED_SHIFT; + gainComp->compStep = (regRd3 & STEP_MASK); + gainComp->obsRxOffset = ((regRd2 & 0x0F) << 1) | ((regRd2 & 0x10) >> 4); + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Slicer control over GPIO inputs. + * + * The user can control the slicer position via 3 GPIO inputs per channel. + * There are various configurations for the GPIO pins, this configurations are enumerated in the mykonosRxSlicer_t. + * + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - Gain compensation block has to be enabled in order to user the slicer control + * + * \param device is a pointer to the device settings structure + * \param slicerStep configures the step size of the slicer when external pin contol mode is enabled. + * Slicer gain in this mode is determined by multiplying the step size by the input bit code from the BBP. + * Step sizes are as follows: + * sllicerStep | step + * -------------|------------ + * 0 | 1 + * 1 | 2 + * 2 | 3 + * 3 | 4 + * + * \param rx1Pins Rx1 slicer inputs can take values from one of the following combinations that are specified in mykonosRxSlicer_t enum: + * -GPIO_2, GPIO_1, and GPIO_0 + * -GPIO_7, GPIO_6, and GPIO_5 + * -GPIO_10, GPIO_9, and GPIO_8 + * \param rx2Pins Rx2 slicer inputs can take values from one of the following combinations that are specified in mykonosRxSlicer_t enum: + * -GPIO_7, GPIO_6, and GPIO_5 + * -GPIO_13, GPIO_12, and GPIO_11 + * \param enable this parameter enables the external pin control mode so the BBP can control the slicer setting. + * enable = 1 + * disable = 0 + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_SLICER_INV_RX1_SEL invalid RX1 GPIO pin selection for Slicer control + * \retval MYKONOS_ERR_SLICER_INV_RX2_SEL invalid RX2 GPIO pin selection for Slicer control + * \retval MYKONOS_ERR_SLICER_STEP_OUT_OF_RANGE slicer step is out of range + * \retval MYKONOS_ERR_SLICER_EN_INV invalid enable + */ +mykonosGpioErr_t MYKONOS_setRxSlicerCtrl(mykonosDevice_t *device, uint8_t slicerStep, mykonosRxSlicer_t rx1Pins, mykonosRxSlicer_t rx2Pins, uint8_t enable) +{ + uint8_t regWr = 0x00; + + const uint8_t STEP_MASK = 0x03; + const uint8_t STEP_SHIFT = 0x05; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setRxSlicerCtrl()\n"); +#endif + + if (enable > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_EN_INV, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_EN_INV)); + return MYKONOS_ERR_SLICER_EN_INV; + } + else if (enable == 1) + { + /* Enabling Slicer input control */ + regWr = 0x80; + + /* Check for Rx1 Slicer input control */ + switch (rx1Pins) + { + case GPIO_0_1_2: + regWr |= 0x00; + break; + case GPIO_5_6_7: + regWr |= 0x01; + break; + case GPIO_8_9_10: + regWr |= 0x02; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_INV_RX1_SEL, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_INV_RX1_SEL)); + return MYKONOS_ERR_SLICER_INV_RX1_SEL; + } + + /* Check for Rx2 Slicer input control */ + switch (rx2Pins) + { + case GPIO_11_12_13: + regWr |= 0x00; + break; + case GPIO_5_6_7: + regWr |= 0x04; + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_INV_RX2_SEL, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_INV_RX2_SEL)); + return MYKONOS_ERR_SLICER_INV_RX2_SEL; + } + + /* Check for Slicer input step size control */ + if (slicerStep > STEP_MASK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_STEP_OUT_OF_RANGE, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_STEP_OUT_OF_RANGE)); + return MYKONOS_ERR_SLICER_STEP_OUT_OF_RANGE; + } + else + { + regWr |= (uint8_t)(slicerStep << STEP_SHIFT); + } + } + + /* Write to device the slicer configuration */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_RX_SLCR_PIN_CFG, regWr); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief This function will get the programmed Slicer control for Rx1 and Rx2 channels. + * + * The user can control the slicer position via 3 GPIO inputs per channel. + * There are various configurations for the GPIO pins, this configurations are enumerated in the mykonosRxSlicer_t. + * + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param slicerStep will contain the configured step size + * \param rx1Pins will contain the configured GPIO combination for Rx1 + * \param rx2Pins will contain the configured GPIO combination for Rx2 + * \param enable will contain the programmed enable setting + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_SLICER_RX1PIN_NULL_PARM rx1Pins is null pointer for the passed parameter + * \retval MYKONOS_ERR_SLICER_RX2PIN_NULL_PARM rx1Pins is null pointer for the passed parameter + * \retval MYKONOS_ERR_SLICER_STEP_NULL_PARM slicerStep is null pointer for the passed parameter + * \retval MYKONOS_ERR_SLICER_EN_NULL_PARM enable is null pointer for the passed parameter + */ +mykonosGpioErr_t MYKONOS_getRxSlicerCtrl(mykonosDevice_t *device, uint8_t *slicerStep, mykonosRxSlicer_t *rx1Pins, mykonosRxSlicer_t *rx2Pins, uint8_t *enable) +{ + uint8_t regRd = 0x00; + + /* Mask parameter values populating parameters */ + const uint8_t EN_MASK = 0x80; + const uint8_t STEP_MASK = 0x60; + const uint8_t RX1_MASK = 0x03; + const uint8_t RX2_MASK = 0x0C; + + /* Shift values for populating passed parameters */ + const uint8_t EN_SHIFT = 0x07; + const uint8_t STEP_SHIFT = 0x05; + const uint8_t RX1_SHIFT = 0x00; + const uint8_t RX2_SHIFT = 0x02; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getRxSlicerCtrl()\n"); +#endif + + /* Check for Rx1 Slicer input control null parameter */ + if (rx1Pins == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_RX1PIN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_RX1PIN_NULL_PARM)); + return MYKONOS_ERR_SLICER_RX1PIN_NULL_PARM; + } + + /* Check for Rx2 Slicer input control null parameter */ + if (rx2Pins == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_RX2PIN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_RX2PIN_NULL_PARM)); + return MYKONOS_ERR_SLICER_RX2PIN_NULL_PARM; + } + + /* Check for Slicer step control null parameter */ + if (slicerStep == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_STEP_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_STEP_NULL_PARM)); + return MYKONOS_ERR_SLICER_STEP_NULL_PARM; + } + + /* Check for Slicer step control null parameter */ + if (enable == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_EN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_EN_NULL_PARM)); + return MYKONOS_ERR_SLICER_EN_NULL_PARM; + } + + /* Reading SLicer control register */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_RX_SLCR_PIN_CFG, ®Rd); + + /* Parsing values */ + *enable = (regRd & EN_MASK) >> EN_SHIFT; + *slicerStep = (regRd & STEP_MASK) >> STEP_SHIFT; + + /* Map to enum */ + switch ((regRd & RX2_MASK) >> RX2_SHIFT) + { + case 0: + *rx2Pins = GPIO_11_12_13; + break; + case 1: + *rx2Pins = GPIO_5_6_7; + break; + + default: + *rx2Pins = GPIO_11_12_13; + break; + } + + *rx1Pins = (mykonosRxSlicer_t)((regRd & RX1_MASK) >> RX1_SHIFT); + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Slicer control over GPIO inputs for the observation channel. + * + * The user can control the slicer position via 3 GPIO inputs for the observation channel. + * There are various configurations for the GPIO pins, this configurations are enumerated in the mykonosObsRxSlicer_t. + * + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - Gain compensation block has to be enabled in order to user the slicer control + * + * \param device is a pointer to the device settings structure + * \param slicerStep configures the step size of the slicer when external pin contol mode is enabled. + * Slicer gain in this mode is determined by multiplying the step size by the input bit code from the BBP. + * Step sizes are as follows: + * sllicerStep | step + * -------------|------------ + * 0 | 1 + * 1 | 2 + * 2 | 3 + * 3 | 4 + * + * \param obsRxPins observation slicer inputs can take values from one of the following combinations that are specified in mykonosObsRxSlicer_t enum: + * -GPIO_18, GPIO_17 and GPIO_16 + * -GPIO_16, GPIO_15 and GPIO_14 + * \param enable enables the external pin control mode so the BBP can control the slicer setting. + * enable = 1 + * disable = 0 + * + * \retval MYKONOS_ERR_SLICER_INV_OBS_RX_SEL invalid observation channel GPIO pin selection for Slicer control + * \retval MYKONOS_ERR_SLICER_OBS_RX_STEP_OUT_OF_RANGE slicer step is out of range + * \retval MYKONOS_ERR_SLICER_OBS_RX_EN_INV invalid enable + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setObsRxSlicerCtrl(mykonosDevice_t *device, uint8_t slicerStep, mykonosObsRxSlicer_t obsRxPins, uint8_t enable) +{ + uint8_t regWr = 0x00; + + const uint8_t STEP_MASK = 0x03; + const uint8_t STEP_SHIFT = 0x05; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setObsRxSlicerCtrl()\n"); +#endif + + if (enable > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_OBS_RX_EN_INV, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_OBS_RX_EN_INV)); + return MYKONOS_ERR_SLICER_OBS_RX_EN_INV; + } + else if (enable == 1) + { + /* Enabling Slicer input control */ + regWr = 0x80; + + /* Check for Rx1 Slicer input control */ + switch (obsRxPins) + { + case GPIO_18_17_16: + regWr |= 0x00; + break; + case GPIO_16_15_14: + regWr |= 0x01; + break; + + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_INV_OBS_RX_SEL, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_INV_OBS_RX_SEL)); + return MYKONOS_ERR_SLICER_INV_OBS_RX_SEL; + } + + /* Check for Slicer input step size control */ + if (slicerStep & ~STEP_MASK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_OBS_RX_STEP_OUT_OF_RANGE, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_OBS_RX_STEP_OUT_OF_RANGE)); + return MYKONOS_ERR_SLICER_OBS_RX_STEP_OUT_OF_RANGE; + } + else + { + regWr |= (uint8_t)((slicerStep << STEP_SHIFT)); + } + } + + /* Write to device the slicer configuration */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_DPD_SNF_RX_SLCR_PIN_CFG, regWr); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief This function will get the programmed Slicer control for observation channel. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param slicerStep will contain the configured step size + * \param obsRxPins will contain the configured GPIO combination + * \param enable will contain the programmed enable setting + * + * \retval MYKONOS_ERR_SLICER_OBS_RXPIN_NULL_PARM obsRxPins is null pointer for the passed parameter + * \retval MYKONOS_ERR_SLICER_OBS_RX_STEP_NULL_PARM slicerStep is null pointer for the passed parameter + * \retval MYKONOS_ERR_SLICER_OBS_RX_EN_NULL_PARM, enable is null pointer for the passed parameter + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getObsRxSlicerCtrl(mykonosDevice_t *device, uint8_t *slicerStep, mykonosObsRxSlicer_t *obsRxPins, uint8_t *enable) +{ + uint8_t regRd = 0x00; + + /* Mask parameter values populating slicer parameters */ + const uint8_t EN_MASK = 0x80; + const uint8_t STEP_MASK = 0x60; + const uint8_t OBS_RX_MASK = 0x03; + + /* Shift values for writing slicer parameters */ + const uint8_t EN_SHIFT = 0x07; + const uint8_t STEP_SHIFT = 0x05; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getObsRxSlicerCtrl()\n"); +#endif + + /* Check for Rx1 Slicer input control null parameter */ + if (obsRxPins == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_OBS_RXPIN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_OBS_RXPIN_NULL_PARM)); + return MYKONOS_ERR_SLICER_OBS_RXPIN_NULL_PARM; + } + + /* Check for Slicer step control null parameter */ + if (slicerStep == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_OBS_RX_STEP_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_OBS_RX_STEP_NULL_PARM)); + return MYKONOS_ERR_SLICER_OBS_RX_STEP_NULL_PARM; + } + + /* Check for Slicer step control null parameter */ + if (enable == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SLICER_OBS_RX_EN_NULL_PARM, + getGpioMykonosErrorMessage(MYKONOS_ERR_SLICER_OBS_RX_EN_NULL_PARM)); + return MYKONOS_ERR_SLICER_OBS_RX_EN_NULL_PARM; + } + + /* Reading Slicer control register */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_DPD_SNF_RX_SLCR_PIN_CFG, ®Rd); + + /* Parsing values */ + *enable = (regRd & EN_MASK) >> EN_SHIFT; + *slicerStep = (regRd & STEP_MASK) >> STEP_SHIFT; + + /* Map to enum */ + switch (regRd & OBS_RX_MASK) + { + case 0: + *obsRxPins = GPIO_18_17_16; + break; + case 1: + *obsRxPins = GPIO_16_15_14; + break; + + default: + *obsRxPins = (mykonosObsRxSlicer_t)0; + break; + } + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + + +/** + * \brief Floating point formatter enable and setup function. + * + * The floating point formatter block is a function that works in conjunction with the gain + * compensating block, as the gain compensation requires increased dynamic range (total gain range on AD9371 is 42dB) + * which increases the bitwidth in the digital datapath. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - Gain compensation block has to be enabled in order to user floating point formatter + * + * \param device is a pointer to the device settings structure + * \param floatFrmt which is a mykonosFloatPntFrmt_t structure. + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_FLOATFRMT_SET_NULL_STRUCT floating point formatter structure floatFrmt not initialized + * \retval MYKONOS_ERR_FLOATFRMT_INV_ROUND_MODE floating point formatter structure floatFrmt.roundMode not valid parameter + * \retval MYKONOS_ERR_FLOATFRMT_INV_DATA_FORMAT floating point formatter structure floatFrmt.dataFormat not valid parameter + * \retval MYKONOS_ERR_FLOATFRMT_INV_ENC_NAN floating point formatter structure floatFrmt.encNan not valid parameter + * \retval MYKONOS_ERR_FLOATFRMT_INV_EXP_BITS floating point formatter structure floatFrmt.expBits not valid parameter + * \retval MYKONOS_ERR_FLOATFRMT_INV_LEADING floating point formatter structure floatFrmt.leading not valid parameter + */ +mykonosGpioErr_t MYKONOS_setFloatPointFrmt (mykonosDevice_t *device, mykonosFloatPntFrmt_t *floatFrmt) +{ + uint8_t regWr1 = 0x00; + + /* Max parameter values for error checking */ + const uint8_t ROUND_RANGE = 0x04; + const uint8_t DATA_FRMT_RANGE = 0x01; + const uint8_t ENCODE_RANGE = 0x01; + const uint8_t EXPBITS_RANGE = 0x03; + const uint8_t LEADING_RANGE = 0x01; + + /* Shift values for writing mykonosFloatPntFrmt_t values */ + const uint8_t ROUND_SHIFT = 0x05; + const uint8_t DATA_FRMT_SHIFT = 0x04; + const uint8_t ENCODE_SHIFT = 0x03; + const uint8_t EXPBITS_SHIFT = 0x01; + const uint8_t LEADING_SHIFT = 0x00; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setFloatPointFrmt()\n"); +#endif + + /* Check for gainComp initialised */ + if (floatFrmt == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_SET_NULL_STRUCT, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_SET_NULL_STRUCT)); + return MYKONOS_ERR_FLOATFRMT_SET_NULL_STRUCT; + } + + /* Check for floating point round mode */ + if (floatFrmt->roundMode > ROUND_RANGE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_INV_ROUND_MODE, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_INV_ROUND_MODE)); + return MYKONOS_ERR_FLOATFRMT_INV_ROUND_MODE; + } + + /* Check for floating point data format */ + if (floatFrmt->dataFormat > DATA_FRMT_RANGE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_INV_DATA_FORMAT, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_INV_DATA_FORMAT)); + return MYKONOS_ERR_FLOATFRMT_INV_DATA_FORMAT; + } + + /* Check for floating point encode NaN */ + if (floatFrmt->encNan > ENCODE_RANGE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_INV_ENC_NAN, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_INV_ENC_NAN)); + return MYKONOS_ERR_FLOATFRMT_INV_ENC_NAN; + } + + /* Check for floating point exponent bits range */ + if (floatFrmt->expBits > EXPBITS_RANGE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_INV_EXP_BITS, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_INV_EXP_BITS)); + return MYKONOS_ERR_FLOATFRMT_INV_EXP_BITS; + } + + /* Check for floating point hide leading ones */ + if (floatFrmt->leading > LEADING_RANGE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_INV_LEADING, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_INV_LEADING)); + return MYKONOS_ERR_FLOATFRMT_INV_LEADING; + } + + regWr1 = (uint8_t)((floatFrmt->roundMode << ROUND_SHIFT) | (floatFrmt->dataFormat << DATA_FRMT_SHIFT) | + (floatFrmt->encNan << ENCODE_SHIFT) | (floatFrmt->expBits << EXPBITS_SHIFT) | + (floatFrmt->leading << LEADING_SHIFT)); + + + /* Write gain compensation setup to device */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FLOATING_POINT_CFG, regWr1); + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Floating point formatter setup function. + * + * The floating point formatter block is a function that works in conjunction with the gain + * compensating block, as the gain compensation requires increased dynamic range + * which increases the bit-width in the digital data-path. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - Gain compensation block has to be enabled in order to user floating point formatter + * + * \param device is a pointer to the device settings structure + * \param floatFrmt which is a mykonosFloatPntFrmt_t structure. + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_FLOATFRMT_NULL_STRUCT floating point formatter structure floatFrmt not initialized + * + */ +mykonosGpioErr_t MYKONOS_getFloatPointFrmt (mykonosDevice_t *device, mykonosFloatPntFrmt_t *floatFrmt) +{ + uint8_t regRd1 = 0x00; + + /* Mask parameter values populating mykonosGainComp_t structure */ + const uint8_t ROUND_MASK = 0xE0; + const uint8_t DATA_FRMT_MASK = 0x10; + const uint8_t ENCODE_MASK = 0x08; + const uint8_t EXPBITS_MASK = 0x06; + const uint8_t LEADING_MASK = 0x01; + + /* Shift values for writing gain values */ + const uint8_t ROUND_SHIFT = 0x05; + const uint8_t DATA_FRMT_SHIFT = 0x04; + const uint8_t ENCODE_SHIFT = 0x03; + const uint8_t EXPBITS_SHIFT = 0x01; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getFloatPointFrmt()\n"); +#endif + + /* Check floatFrmt for Null */ + if (floatFrmt == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_NULL_STRUCT, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_NULL_STRUCT)); + return MYKONOS_ERR_FLOATFRMT_NULL_STRUCT; + } + + /* Read gain compensation setup from device */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_FLOATING_POINT_CFG, ®Rd1); + + /* Parsing read data to passed by reference parameters */ + floatFrmt->roundMode = (regRd1 & ROUND_MASK) >> ROUND_SHIFT; + floatFrmt->dataFormat = (regRd1 & DATA_FRMT_MASK) >> DATA_FRMT_SHIFT; + floatFrmt->encNan = (regRd1 & ENCODE_MASK) >> ENCODE_SHIFT; + floatFrmt->expBits = (regRd1 & EXPBITS_MASK) >> EXPBITS_SHIFT; + floatFrmt->leading = regRd1 & LEADING_MASK; + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Floating point formatter enable/disable Rx1 and Rx2 function. + * + * The floating point formatter block is a function that works in conjunction with the gain + * compensating block, as the gain compensation requires increased dynamic range + * which increases the bit-width in the digital data-path. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * - Gain compensation block has to be enabled in order to user floating point formatter + * + * \param device is a pointer to the device settings structure + * \param rx1Att this parameter sets the integer data attenuation for the Rx1 channel in 6dB steps + * to enable the entire data range to be represented in the selected floating point format. + * \param rx2Att this parameter sets the integer data attenuation for the Rx2 channel in 6dB steps + * to enable the entire data range to be represented in the selected floating point format. + * \param enable this parameter enables or disables the gain compensation block. + * enable = 1 + * disable = 0 + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_FLOATFRMT_SET_INV_RX1ATT not valid rx1 attenuation parameter passed in MYKONOS_setRxEnFloatPntFrmt() + * \retval MYKONOS_ERR_FLOATFRMT_SET_INV_RX2ATT not valid rx2 attenuation parameter passed in MYKONOS_setRxEnFloatPntFrmt() + * \retval MYKONOS_ERR_FLOATFRMT_SET_INV_EN not valid enable parameter passed in MYKONOS_setRxEnFloatPntFrmt() + */ +mykonosGpioErr_t MYKONOS_setRxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t rx1Att, uint8_t rx2Att, uint8_t enable) +{ + uint8_t regWr = 0x00; + + const uint8_t RXATT_RANGE = 0x07; + const uint8_t RX1ATT_SHIFT = 0x01; + const uint8_t RX2ATT_SHIFT = 0x05; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setRxEnFloatPntFrmt()\n"); +#endif + + if (enable > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_SET_INV_EN, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_SET_INV_EN)); + return MYKONOS_ERR_FLOATFRMT_SET_INV_EN; + } + else if (enable == 1) + { + /* Check for rx1Att range */ + if (rx1Att > RXATT_RANGE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_SET_INV_RX1ATT, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_SET_INV_RX1ATT)); + return MYKONOS_ERR_FLOATFRMT_SET_INV_RX1ATT; + } + + /* Check for rx2Att range */ + if (rx2Att > RXATT_RANGE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_SET_INV_RX2ATT, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_SET_INV_RX2ATT)); + return MYKONOS_ERR_FLOATFRMT_SET_INV_RX2ATT; + } + + /* Enabling floating point formatter for Rx1 and Rx2 */ + regWr = 0x11; + regWr |= (uint8_t)((rx1Att << RX1ATT_SHIFT) | (rx2Att << RX2ATT_SHIFT)); + } + + /* Writing floating point formatter enables for Rx1 and Rx2 */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FLOATING_POINT_RX_CTRL, regWr); + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Floating point formatter setup function. + * + * The floating point formatter block is a function that works in conjunction with the gain + * compensating block, as the gain compensation requires increased dynamic range (total gain range on AD9371 is 42dB) + * which increases the bitwidth in the digital datapath. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param rx1Att this parameter sets the integer data attenuation for the Rx1 channel in 6dB steps + * to enable the entire data range to be represented in the selected floating point format. + * \param rx2Att this parameter sets the integer data attenuation for the Rx2 channel in 6dB steps + * to enable the entire data range to be represented in the selected floating point format. + * \param enable this parameter enables or disables the gain compensation block. + * enable = 1 + * disable = 0 + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_FLOATFRMT_NULL_RX1ATT null pointer passed for rx1 attenuation in MYKONOS_setRxEnFloatPntFrmt() + * \retval MYKONOS_ERR_FLOATFRMT_NULL_RX2ATT null pointer passed for rx2 attenuation in MYKONOS_setRxEnFloatPntFrmt() + * \retval MYKONOS_ERR_FLOATFRMT_NULL_ENABLE null pointer passed for enable in MYKONOS_setRxEnFloatPntFrmt() + */ +mykonosGpioErr_t MYKONOS_getRxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t *rx1Att, uint8_t *rx2Att, uint8_t *enable) +{ + uint8_t regRd = 0x00; + + const uint8_t EN_MASK = 0x11; + const uint8_t RX1ATT_MASK = 0x0E; + const uint8_t RX1ATT_SHIFT = 0x01; + const uint8_t RX2ATT_MASK = 0xE0; + const uint8_t RX2ATT_SHIFT = 0x05; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getRxEnFloatPntFrmt()\n"); +#endif + + /* Check for rx1Att NULL parameter */ + if (rx1Att == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_NULL_RX1ATT, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_NULL_RX1ATT)); + return MYKONOS_ERR_FLOATFRMT_NULL_RX1ATT; + } + + /* Check for rx2Att NULL parameter */ + if (rx2Att == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_NULL_RX2ATT, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_NULL_RX2ATT)); + return MYKONOS_ERR_FLOATFRMT_NULL_RX2ATT; + } + + /* Check for enable NULL parameter */ + if (enable == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_NULL_ENABLE, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_NULL_ENABLE)); + return MYKONOS_ERR_FLOATFRMT_NULL_ENABLE; + } + + /* Read Rx1 and Rx2 floating point enables */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_FLOATING_POINT_RX_CTRL, ®Rd); + + *rx1Att = (regRd & RX1ATT_MASK) >> RX1ATT_SHIFT; + *rx2Att = (regRd & RX2ATT_MASK) >> RX2ATT_SHIFT ; + *enable = (regRd & EN_MASK) ? 1 : 0; + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + + + +/** + * \brief Floating point formatter enable function for ORx channel. + * + * The floating point formatter block is a function that works in conjunction with the gain + * compensating block, as the gain compensation requires increased dynamic range + * which increases the bit-width in the digital data-path. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param orxAtt this parameter sets the integer data attenuation for the ORx channel in 6dB steps + * to enable the entire data range to be represented in the selected floating point format. + * * \param enable this parameter enables or disables the gain compensation block. + * enable = 1 + * disable = 0 + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_FLOATFRMT_INV_ORXATT not valid Orx attenuation parameter passed in MYKONOS_setOrxEnFloatPntFrmt() + * \retval MYKONOS_ERR_FLOATFRMT_INV_ORXEN not valid enable parameter passed in MYKONOS_setOrxEnFloatPntFrmt() + */ +mykonosGpioErr_t MYKONOS_setOrxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t orxAtt, uint8_t enable) +{ + uint8_t regWr = 0x00; + + const uint8_t ORXATT_RANGE = 0x07; + const uint8_t ORXATT_SHIFT = 0x01; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setOrxEnFloatPntFrmt()\n"); +#endif + + /* Check for enable */ + if (enable > 1) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_INV_ORXEN, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_INV_ORXEN)); + return MYKONOS_ERR_FLOATFRMT_INV_ORXEN; + } + else if (enable == 1) + { + /* Check for rx1Att range */ + if (orxAtt > ORXATT_RANGE) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_INV_ORXATT, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_INV_ORXATT)); + return MYKONOS_ERR_FLOATFRMT_INV_ORXATT; + } + + /* Enabling floating point formatter for Rx1 and Rx2 */ + regWr = 0x01; + regWr |= (uint8_t)(orxAtt << ORXATT_SHIFT); + } + + /* Writing floating point formatter enable for ORX channel */ + CMB_SPIWriteByte(device->spiSettings, MYKONOS_ADDR_FLOATING_POINT_ORX_CTRL, regWr); + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + + +/** + * \brief Floating point formatter enable and setup function. + * + * The floating point formatter block is a function that works in conjunction with the gain + * compensating block, as the gain compensation requires increased dynamic range (total gain range on AD9371 is 42dB) + * which increases the bitwidth in the digital datapath. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param orxAtt this parameter sets the integer data attenuation for the ORx channel in 6dB steps + * to enable the entire data range to be represented in the selected floating point format. + * \param enable this parameter enables or disables the gain compensation block. + * enable = 1 + * disable = 0 + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_FLOATFRMT_NULL_ORXATT null pointer passed for orxAtt + * \retval MYKONOS_ERR_FLOATFRMT_NULL_ORXENABLE null pointer passed for enable + */ +mykonosGpioErr_t MYKONOS_getOrxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t *orxAtt, uint8_t *enable) +{ + uint8_t regRd = 0x00; + + const uint8_t EN_MASK = 0x01; + const uint8_t ORXATT_MASK = 0x0E; + const uint8_t ORXATT_SHIFT = 0x01; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getOrxEnFloatPntFrmt()\n"); +#endif + + /* Check for orxAtt NULL parameter */ + if (orxAtt == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_NULL_ORXATT, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_NULL_ORXATT)); + return MYKONOS_ERR_FLOATFRMT_NULL_ORXATT; + } + + /* Check for enable NULL parameter */ + if (enable == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_FLOATFRMT_NULL_ORXENABLE, + getGpioMykonosErrorMessage(MYKONOS_ERR_FLOATFRMT_NULL_ORXENABLE)); + return MYKONOS_ERR_FLOATFRMT_NULL_ORXENABLE; + } + + /* Read Rx1 and Rx2 floating point enables */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_FLOATING_POINT_ORX_CTRL, ®Rd); + + *orxAtt = (regRd & ORXATT_MASK) >> ORXATT_SHIFT; + *enable = (regRd & EN_MASK) ? 1 : 0; + + /* Return */ + return MYKONOS_ERR_GPIO_OK; +} + + +/** + * \brief Sets up the Temperature Sensor + * + * Before using this function to set up the temp sensor, + * make sure that you call the MYKONOS_setupAuxADC() function + * to ensure that the AuxADC clock is setup and running correctly at 40 MHz, + * and that the structure mykonosTempSensorConfig_t tempSensor is populated. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param tempSensor is a pointer to the mykonosTempSensorConfig_t which holds + * the configuration settings for the temperature sensor + * + * \retval MYKONOS_ERR_SETUPTEMPSENSOR_NULL_PARAM Function parameter tempSensor is a NULL pointer + * \retval MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPDECIMATION tempDecimation value out of range (0-7) + * \retval MYKONOS_ERR_SETUPTEMPSENSOR_INV_OFFSET offset value out of range (0-255) + * \retval MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPWINDOW tempWindow out of range (0-15) + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setupTempSensor(mykonosDevice_t *device, mykonosTempSensorConfig_t *tempSensor) +{ + uint8_t offsetFromDevice = 0; + + const uint8_t OFFSET_API = 0x43; +/* const uint8_t TEMP_OFFSET_MASK = 0xFF;*/ + const uint8_t TEMP_WINDOW_MASK = 0xF0; + const uint8_t TEMP_WINDOW_CHECK = 0x0F; + const uint8_t TEMP_DEC_MASK = 0x07; + const uint8_t OFFSET_OVERRIDE_MASK = 0x10; + +#ifdef MYKONOS_VERBOSE + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setupTempSensor()\n"); +#endif + + /* Check for structure initialisation mykonosTempSensorConfig_t */ + if (tempSensor == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETUPTEMPSENSOR_NULL_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_SETUPTEMPSENSOR_NULL_PARAM)); + return MYKONOS_ERR_SETUPTEMPSENSOR_NULL_PARAM; + } + + /* Check Temperature sensor decimation range */ + if ((tempSensor->tempDecimation & ~TEMP_DEC_MASK) > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPDECIMATION, + getGpioMykonosErrorMessage(MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPDECIMATION)); + return MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPDECIMATION; + } + + /* Override fused offset */ + if (tempSensor->overrideFusedOffset > 0) + { + /* Check Temperature sensor offset range */ +/* if (tempSensor->offset & ~TEMP_OFFSET_MASK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETUPTEMPSENSOR_INV_OFFSET, + getGpioMykonosErrorMessage(MYKONOS_ERR_SETUPTEMPSENSOR_INV_OFFSET)); + return MYKONOS_ERR_SETUPTEMPSENSOR_INV_OFFSET; + }*/ + + CMB_SPIWriteField (device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_CONFIG, 1, OFFSET_OVERRIDE_MASK, 4); + CMB_SPIWriteByte (device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_OFFSET, tempSensor->offset); + } + else + { + /* If manual override was not requested, read back device offset value. + * If factory fused it is non-zero; else API adds a typical offset value */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_OFFSET, &(offsetFromDevice)); + if (offsetFromDevice == 0) + { + CMB_SPIWriteByte (device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_OFFSET, OFFSET_API); + } + } + + /* Check Temperature sensor window range */ + if ((tempSensor->tempWindow & ~TEMP_WINDOW_CHECK) > 0) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPWINDOW, + getGpioMykonosErrorMessage(MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPWINDOW)); + return MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPWINDOW; + } + else + { + CMB_SPIWriteField (device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_CONTROL_LSB, tempSensor->tempWindow, TEMP_WINDOW_MASK, 4); + } + + /* Single shot setup */ + CMB_SPIWriteByte (device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_CONTROL_MSB, 0x00); + + /* Write decimation factor for the Temperature sensor */ + CMB_SPIWriteField (device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_CONFIG, tempSensor->tempDecimation, TEMP_DEC_MASK, 0); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Reads from the Temperature Sensor registers and populates device data structure + * + * After this function is executed, the tempSensor parameter holds updated values + * from the device registers. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param tempSensor is a pointer to the mykonosTempSensorConfig_t which holds + * the configuration settings for the tempSensor + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_GETTEMPSENSORCONFIG_NULL_PARAM Function parameter tempSensor is a NULL pointer + */ +mykonosGpioErr_t MYKONOS_getTempSensorConfig(mykonosDevice_t *device, mykonosTempSensorConfig_t *tempSensor) +{ + uint8_t tempConfig = 0; + + const uint8_t TEMP_WINDOW_MASK = 0xF0; + const uint8_t TEMP_FUSE_MASK = 0x10; + const uint8_t TEMP_DECIMATION_MASK = 0x07; + const uint8_t TEMP_FUSE_SHIFT = 0x04; + +#ifdef MYKONOS_VERBOSE + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getTempSensorConfig()\n"); +#endif + + /* Check tempSensor null parameter passed */ + if (tempSensor == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETTEMPSENSORCFG_NULL_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETTEMPSENSORCFG_NULL_PARAM)); + return MYKONOS_ERR_GETTEMPSENSORCFG_NULL_PARAM; + } + + /* Read back factory offset, if fused; else manual offset value */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_OFFSET, &(tempSensor->offset)); + + /* Read back Decimation and override Offset Temperature sensor parameters */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_CONFIG, &tempConfig); + tempSensor->overrideFusedOffset = (tempConfig & TEMP_FUSE_MASK) >> TEMP_FUSE_SHIFT; + tempSensor->tempDecimation = (tempConfig & TEMP_DECIMATION_MASK); + + /* Read back tempWindow */ + CMB_SPIReadField(device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_CONTROL_LSB, &tempConfig, TEMP_WINDOW_MASK, 4); + tempSensor->tempWindow = tempConfig; + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Initiates temperature measurement + * + * This function will initiate the Temperature sensor measurement. + * + * \pre + * MYKONOS_setupTempSensor() function to set the temperature sensor. + * MYKONOS_setAuxAdcChannel() function with the AuxADC setting for Temperature sensor channel MYK_TEMPSENSOR + * from the enum type mykonosAuxAdcChannels_t. + * + * \post + * Internal temperature sensor will perform measurement and updated register values, + * read back using MYKONOS_readTempSensor() function. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_startTempMeasurement(mykonosDevice_t *device) +{ + const uint8_t TEMP_LOCK_MASK = 0x80; + const uint8_t TEMP_LOCK_BIT = 0x01; + const uint8_t MEASUREMENT_MASK = 0x01; + +#ifdef MYKONOS_VERBOSE + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_startTempMeasurement()\n"); +#endif + + /* Write the lock bit to ensure that a valid measurement is achieved */ + CMB_SPIWriteField (device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_CONFIG, TEMP_LOCK_BIT, TEMP_LOCK_MASK, 7); + + /* Initiate Temperature measurement */ + CMB_SPIWriteField (device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_CONTROL_LSB, 1, MEASUREMENT_MASK, 0); + CMB_SPIWriteField (device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_CONTROL_LSB, 0, MEASUREMENT_MASK, 0); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief Reads temperature code and statuses from the Temperature Sensor registers + * + * This function reads the temperature sensor's statuses and temperature code. + * Allow at least one computation period to elapse. + * The temperature sensor computation period is as 6 times the AuxADC conversion time. + * AuxADC conversion time = (1/40Mhz) * (256 * 2^(tempDecimation)) + * + * Before using this function to read back the temperature, make sure that temperature sensor + * is setup using the MYKONOS_setupTempSensor() function. + * + * \pre Before using this function to read back the sensor value: + * MYKONOS_setupTempSensor() function is needed in order to set up the Temperature sensor. + * MYKONOS_setAuxAdcChannel() function has to be called in order to set the proper AuxADC + * channel. AuxADC channel MYK_TEMPSENSOR is used for the Temperature sensor. + * MYKONOS_startTempMeasurement() this function will start the Temperature sensor, this + * function is needed to be called for every reading that needs to be performed. + * + * \post "tempStatus" structure will contain the status information and the temperature + * code. + * If a valid measurement is achieved then tempStatus->tempValid will be set and + * tempStatus->tempCode will contain the actual reading. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param tempStatus is a pointer to the mykonosTempSensorStatus_t structure which will be updated + * with the temp sensor readings + * + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + * \retval MYKONOS_ERR_READTEMPSENSOR_NULL_PARAM Function parameter tempSensor is a NULL pointer + * \retval MYKONOS_ERR_READTEMPSENSOR_NOT_LOCKED temperature sensor reading is not locked + */ +mykonosGpioErr_t MYKONOS_readTempSensor(mykonosDevice_t *device, mykonosTempSensorStatus_t *tempStatus) +{ + int16_t temperature = 0; + uint8_t statusWord = 0; + uint8_t rgRd = 0x00; + + const uint8_t CODE_TO_DEGREE_CELSIUS = 0x67; + const uint8_t TEMP_VALID_MASK = 0x02; + const uint8_t WINDOW_EXCEED_MASK = 0x08; + const uint8_t WINDOW_HI_LO_MASK = 0x04; + const uint8_t TEMP_LOCK = 0x80; + +#ifdef MYKONOS_VERBOSE + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_readTempSensor()\n"); +#endif + + if (tempStatus == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READTEMPSENSOR_NULL_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_READTEMPSENSOR_NULL_PARAM)); + return MYKONOS_ERR_READTEMPSENSOR_NULL_PARAM; + } + + /* Check for temperature sensor value lock */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_CONFIG, &rgRd); + if ((rgRd & TEMP_LOCK) == TEMP_LOCK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_READTEMPSENSOR_NOT_LOCKED, + getGpioMykonosErrorMessage(MYKONOS_ERR_READTEMPSENSOR_NOT_LOCKED)); + return MYKONOS_ERR_READTEMPSENSOR_NOT_LOCKED; + } + + /* Perform temperature status reading */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_CONTROL_LSB, &statusWord); + tempStatus->windowExceeded = (statusWord & WINDOW_EXCEED_MASK) >> 3; + tempStatus->windowHiLo = (statusWord & WINDOW_HI_LO_MASK) >> 2; + tempStatus->tempValid = (0x01 & ~((statusWord & TEMP_VALID_MASK) >> 1)); + + /* Perform temperature reading */ + CMB_SPIReadByte(device->spiSettings, MYKONOS_ADDR_TEMP_SENSOR_READ, &rgRd); + temperature = rgRd - CODE_TO_DEGREE_CELSIUS; + tempStatus->tempCode = temperature; + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief This function sets the drive strength for the required GPIOs. + * + * This function will set the required drive strength, the settings for GPIO drive strength are normal drive and double drive. + * + * GPIO pins that can be assigned independent drive strength are: + * -MYKGPIO0 to MYKGPIO7 and MYKGPIO18 + * + * The rest of GPIOs are paired as: + * -MYKGPIO17 and MYKGPIO16 + * -MYKGPIO8 and MYKGPIO15 + * -MYKGPIO14 and MYKGPIO13 + * -MYKGPIO10 and MYKGPIO9 + * -MYKGPIO12 and MYKGPIO11 + * + * This means that if it is required to double the drive strength for MYKGPIO17 then the drive strength will also be doubled for MYKGPIO16. + * + * If the particular bitfield for gpioDrv is set then the drive strength will be doubled. Note that multiple GPIOs can be set at a time. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gpioDrv GPIO drive strength setup, valid range is from 0x00000 to 0x7FFFF. + * + * \retval MYKONOS_ERR_GPIO_DRV_INV_PARAM GPIO out of range- valid GPIOs are in the range 0x00000 to 0x7FFFF. + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setGpioDrv(mykonosDevice_t *device, uint32_t gpioDrv) +{ + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + uint8_t reg0 = 0x00; + uint8_t reg1 = 0x00; + + const uint32_t GPIO_MASK = 0x7FFFF; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setGpioDrv()\n"); +#endif + + /* Error checking for correct number of GPIOs. */ + if (gpioDrv > GPIO_MASK ) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_DRV_INV_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_DRV_INV_PARAM)); + return MYKONOS_ERR_GPIO_DRV_INV_PARAM; + } + + CMB_SPIReadByte(device->spiSettings, MYKONOS_GPIO_DRV_CTL_0, ®0); + CMB_SPIReadByte(device->spiSettings, MYKONOS_GPIO_DRV_CTL_1, ®1); + + reg1 = reg1 & 0xC0; + + if (gpioDrv & 0xFF) + { + reg0 = (uint8_t)(gpioDrv & 0xFF); + } + else + { + reg0 = 0x00; + } + + if (gpioDrv & (uint32_t)MYKGPIO18) + { + reg1 |= 0x01; + } + + if ((gpioDrv & (uint32_t)MYKGPIO17) || (gpioDrv & (uint32_t)MYKGPIO16)) + { + reg1 |= 0x02; + } + + if ((gpioDrv & (uint32_t)MYKGPIO15) || (gpioDrv & (uint32_t)MYKGPIO8)) + { + reg1 |= 0x04; + } + + if ((gpioDrv & (uint32_t)MYKGPIO14) || (gpioDrv & (uint32_t)MYKGPIO13)) + { + reg1 |= 0x08; + } + + if ((gpioDrv & (uint32_t)MYKGPIO10) || (gpioDrv & (uint32_t)MYKGPIO9)) + { + reg1 |= 0x10; + } + + if ((gpioDrv & (uint32_t)MYKGPIO12) || (gpioDrv & (uint32_t)MYKGPIO11)) + { + reg1 |= 0x20; + } + + CMB_SPIWriteByte (device->spiSettings, MYKONOS_GPIO_DRV_CTL_0, reg0); + CMB_SPIWriteByte (device->spiSettings, MYKONOS_GPIO_DRV_CTL_1, reg1); + + return error; +} + + +/** + * \brief This function gets the GPIOs drive strength. + * + * This function will get the programmed drive strength for all the GPIOs + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure. + * \param gpioDrv will contain the current GPIOs drive strength setting. + * + * \retval MYKONOS_ERR_GETGPIODRV_NULL_PARAM null parameter passed to the function. + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getGpioDrv(mykonosDevice_t *device, uint32_t *gpioDrv) +{ + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + uint8_t reg0 = 0x00; + uint8_t reg1 = 0x00; + uint32_t gpioDrvRd = 0x00; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getGpioDrv()\n"); +#endif + + /* Error checking for correct number of GPIOs. */ + if (gpioDrv == NULL ) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GETGPIODRV_NULL_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GETGPIODRV_NULL_PARAM)); + return MYKONOS_ERR_GETGPIODRV_NULL_PARAM; + } + + CMB_SPIReadByte(device->spiSettings, MYKONOS_GPIO_DRV_CTL_0, ®0); + CMB_SPIReadByte(device->spiSettings, MYKONOS_GPIO_DRV_CTL_1, ®1); + + gpioDrvRd = (uint32_t)reg0 & 0xFF; + + if (reg1 & 0x01) + { + gpioDrvRd |= (uint32_t)MYKGPIO18; + } + + if (reg1 & 0x02) + { + gpioDrvRd |= (uint32_t)MYKGPIO17 | (uint32_t)MYKGPIO16; + } + + if (reg1 & 0x04) + { + gpioDrvRd |= (uint32_t)MYKGPIO8 | (uint32_t)MYKGPIO15; + } + + if (reg1 & 0x08) + { + gpioDrvRd |= (uint32_t)MYKGPIO14 | (uint32_t)MYKGPIO13; + } + + if (reg1 & 0x10) + { + gpioDrvRd |= (uint32_t)MYKGPIO10 | (uint32_t)MYKGPIO9; + } + + if (reg1 & 0x20) + { + gpioDrvRd |= (uint32_t)MYKGPIO12 | (uint32_t)MYKGPIO11; + } + + *gpioDrv = (mykonosGpioSelect_t)gpioDrvRd; + + return error; +} + +/** + * \brief This function sets the slew rate for the required GPIOs. + * + * This function will set the required slew rate, the settings for GPIO slew rate are given by the enumeration type mykonosGpioSlewRate_t. + * + * GPIO pins that can be assigned independent slew rate are: + * -MYKGPIO0 to MYKGPIO7 and MYKGPIO18 + * + * The rest of GPIOs are paired as: + * -MYKGPIO17 and MYKGPIO16 + * -MYKGPIO8 and MYKGPIO15 + * -MYKGPIO14 and MYKGPIO13 + * -MYKGPIO10 and MYKGPIO9 + * -MYKGPIO12 and MYKGPIO11 + * + * This means that if it is required to set the slew rate for MYKGPIO17 then the same slew rate will be applied for MYKGPIO16. + * + * If the particular bitfield for gpioSelect is set then slewRate will be set for that GPIO. Note that multiple GPIOs can be set at a time. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param gpioSelect GPIO for which the slew rate will be changed, valid range 0x00000 to 0x7FFFF. + * \param slewRate slew rate setting, valid slew rate settings are given by the enumeration type mykonosGpioSlewRate_t + * + * \retval MYKONOS_ERR_GPIO_SLEW_RATE_INV_PARAM GPIO out of range- valid GPIOs are in the range 0x00000 to 0x7FFFF. + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setGpioSlewRate(mykonosDevice_t *device, mykonosGpioSelect_t gpioSelect, mykonosGpioSlewRate_t slewRate) +{ + mykonosGpioErr_t error = MYKONOS_ERR_GPIO_OK; + uint8_t reg0 = 0x00; + uint8_t reg1 = 0x00; + uint8_t reg2 = 0x00; + uint8_t reg3 = 0x00; + + const uint32_t GPIO_MASK = 0x7FFFF; + const uint8_t SLEWRATE_MASK = 0x03; + const uint32_t SHIFT4NIBLE = 0x06; + const uint32_t SHIFT3NIBLE = 0x04; + const uint32_t SHIFT2NIBLE = 0x02; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setGpioSlewRate()\n"); +#endif + + /* Error checking for correct number of GPIOs. */ + if (((uint32_t)gpioSelect > GPIO_MASK) || ((uint8_t)slewRate > SLEWRATE_MASK)) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_SLEW_RATE_INV_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_SLEW_RATE_INV_PARAM)); + return MYKONOS_ERR_GPIO_SLEW_RATE_INV_PARAM; + } + + CMB_SPIReadByte(device->spiSettings, MYKONOS_GPIO_SLEW_CTL_0, ®0); + CMB_SPIReadByte(device->spiSettings, MYKONOS_GPIO_SLEW_CTL_1, ®1); + CMB_SPIReadByte(device->spiSettings, MYKONOS_GPIO_SLEW_CTL_2, ®2); + CMB_SPIReadByte(device->spiSettings, MYKONOS_GPIO_SLEW_CTL_3, ®3); + + if ((uint32_t)gpioSelect & (uint32_t)MYKGPIO18) + { + reg0 = (reg0 & ~(SLEWRATE_MASK << SHIFT4NIBLE)) | ((uint8_t)slewRate << SHIFT4NIBLE); + } + if (((uint32_t)gpioSelect & (uint32_t)MYKGPIO17) || ((uint32_t)gpioSelect & (uint32_t)MYKGPIO16)) + { + reg0 = (reg0 & ~(SLEWRATE_MASK << SHIFT3NIBLE)) | ((uint8_t)slewRate << SHIFT3NIBLE); + } + if (((uint32_t)gpioSelect & (uint32_t)MYKGPIO15) || ((uint32_t)gpioSelect & (uint32_t)MYKGPIO8)) + { + reg0 = (reg0 & ~(SLEWRATE_MASK << SHIFT2NIBLE)) | ((uint8_t)slewRate << SHIFT2NIBLE); + } + if (((uint32_t)gpioSelect & (uint32_t)MYKGPIO14) || ((uint32_t)gpioSelect & (uint32_t)MYKGPIO13)) + { + reg0 = (reg0 & ~(SLEWRATE_MASK)) | (uint8_t)slewRate; + } + if (((uint32_t)gpioSelect & (uint32_t)MYKGPIO11) || ((uint32_t)gpioSelect & (uint32_t)MYKGPIO12)) + { + reg1 = (reg1 & ~(SLEWRATE_MASK << SHIFT4NIBLE)) | ((uint8_t)slewRate << SHIFT4NIBLE); + } + if (((uint32_t)gpioSelect & (uint32_t)MYKGPIO9) || ((uint32_t)gpioSelect & (uint32_t)MYKGPIO10)) + { + reg1 = (reg1 & ~(SLEWRATE_MASK << SHIFT3NIBLE)) | ((uint8_t)slewRate << SHIFT3NIBLE); + } + if ((uint32_t)gpioSelect & (uint32_t)MYKGPIO7) + { + reg1 = (reg1 & ~(SLEWRATE_MASK << SHIFT2NIBLE)) | ((uint8_t)slewRate << SHIFT2NIBLE); + } + if ((uint32_t)gpioSelect & (uint32_t)MYKGPIO6) + { + reg1 = (reg1 & ~(SLEWRATE_MASK)) | (uint8_t)slewRate; + } + if ((uint32_t)gpioSelect & (uint32_t)MYKGPIO5) + { + reg2 = (reg2 & ~(SLEWRATE_MASK << SHIFT4NIBLE)) | ((uint8_t)slewRate << SHIFT4NIBLE); + } + if ((uint32_t)gpioSelect & (uint32_t)MYKGPIO4) + { + reg2 = (reg2 & ~(SLEWRATE_MASK << SHIFT3NIBLE)) | ((uint8_t)slewRate << SHIFT3NIBLE); + } + if ((uint32_t)gpioSelect & (uint32_t)MYKGPIO3) + { + reg2 = (reg2 & ~(SLEWRATE_MASK << SHIFT2NIBLE)) | ((uint8_t)slewRate << SHIFT2NIBLE); + } + if ((uint32_t)gpioSelect & (uint32_t)MYKGPIO2) + { + reg2 = (reg2 & ~(SLEWRATE_MASK)) | (uint8_t)slewRate; + } + if ((uint32_t)gpioSelect & (uint32_t)MYKGPIO1) + { + reg3 = (reg3 & ~(SLEWRATE_MASK << SHIFT2NIBLE)) | ((uint8_t)slewRate << SHIFT2NIBLE); + } + if ((uint32_t)gpioSelect & (uint32_t)MYKGPIO0) + { + reg3 = (reg3 & ~(SLEWRATE_MASK)) | (uint8_t)slewRate; + } + + /* Prepare registers */ + CMB_SPIWriteByte (device->spiSettings, MYKONOS_GPIO_SLEW_CTL_0, reg0); + CMB_SPIWriteByte (device->spiSettings, MYKONOS_GPIO_SLEW_CTL_1, reg1); + CMB_SPIWriteByte (device->spiSettings, MYKONOS_GPIO_SLEW_CTL_2, reg2); + CMB_SPIWriteByte (device->spiSettings, MYKONOS_GPIO_SLEW_CTL_3, reg3); + + return error; +} + + +/** + * \brief This function gets the GPIO slew rate setting. + * + * This function will get the programmed slew rate for the GPIO given by slewRateGpio. + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure. + * \param gpioSelect GPIO selection for getting the slew rate setting. + * \param slewRate will contain the GPIO slew rate setting. + * + * \retval MYKONOS_ERR_GPIO_GETSLEW_NULL_PARAM null parameter passed to the function. + * \retval MYKONOS_ERR_GPIO_SLEW_RATE_INV_PARAM GPIO out of range- valid GPIOs are in the range 0x00000 to 0x7FFFF. + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getGpioSlewRate(mykonosDevice_t *device, mykonosGpioSelect_t gpioSelect, mykonosGpioSlewRate_t *slewRate) +{ + uint8_t reg0 = 0x00; + uint8_t reg1 = 0x00; + uint8_t reg2 = 0x00; + uint8_t reg3 = 0x00; + mykonosGpioSlewRate_t slewSetting = MYK_SLEWRATE_NONE; + + const uint32_t SLEWRATE_MASK = 0x03; + const uint32_t SHIFT4NIBLE = 0x06; + const uint32_t SHIFT3NIBLE = 0x04; + const uint32_t SHIFT2NIBLE = 0x02; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getGpioSlewRate()\n"); +#endif + + /* Error checking for NULL parameter. */ + if (slewRate == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_GETSLEW_NULL_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_GETSLEW_NULL_PARAM)); + return MYKONOS_ERR_GPIO_GETSLEW_NULL_PARAM; + } + + CMB_SPIReadByte(device->spiSettings, MYKONOS_GPIO_SLEW_CTL_0, ®0); + CMB_SPIReadByte(device->spiSettings, MYKONOS_GPIO_SLEW_CTL_1, ®1); + CMB_SPIReadByte(device->spiSettings, MYKONOS_GPIO_SLEW_CTL_2, ®2); + CMB_SPIReadByte(device->spiSettings, MYKONOS_GPIO_SLEW_CTL_3, ®3); + + switch (gpioSelect) + { + case MYKGPIO18: + slewSetting = (mykonosGpioSlewRate_t)((reg0 & (SLEWRATE_MASK << SHIFT4NIBLE)) >> SHIFT4NIBLE); + break; + case MYKGPIO17: + case MYKGPIO16: + slewSetting = (mykonosGpioSlewRate_t)((reg0 & (SLEWRATE_MASK << SHIFT3NIBLE)) >> SHIFT3NIBLE); + break; + case MYKGPIO15: + case MYKGPIO8: + slewSetting = (mykonosGpioSlewRate_t)((reg0 & (SLEWRATE_MASK << SHIFT2NIBLE)) >> SHIFT2NIBLE); + break; + case MYKGPIO14: + case MYKGPIO13: + slewSetting = (mykonosGpioSlewRate_t)(reg0 & (SLEWRATE_MASK)); + break; + case MYKGPIO11: + case MYKGPIO12: + slewSetting = (mykonosGpioSlewRate_t)((reg1 & (SLEWRATE_MASK << SHIFT4NIBLE)) >> SHIFT4NIBLE); + break; + case MYKGPIO9: + case MYKGPIO10: + slewSetting = (mykonosGpioSlewRate_t)((reg1 & (SLEWRATE_MASK << SHIFT3NIBLE)) >> SHIFT3NIBLE); + break; + case MYKGPIO7: + slewSetting = (mykonosGpioSlewRate_t)((reg1 & (SLEWRATE_MASK << SHIFT2NIBLE)) >> SHIFT2NIBLE); + break; + case MYKGPIO6: + slewSetting = (mykonosGpioSlewRate_t)(reg1 & (SLEWRATE_MASK)); + break; + case MYKGPIO5: + slewSetting = (mykonosGpioSlewRate_t)((reg2 & (SLEWRATE_MASK << SHIFT4NIBLE)) >> SHIFT4NIBLE); + break; + case MYKGPIO4: + slewSetting = (mykonosGpioSlewRate_t)((reg2 & (SLEWRATE_MASK << SHIFT3NIBLE)) >> SHIFT3NIBLE); + break; + case MYKGPIO3: + slewSetting = (mykonosGpioSlewRate_t)((reg2 & (SLEWRATE_MASK << SHIFT2NIBLE)) >> SHIFT2NIBLE); + break; + case MYKGPIO2: + slewSetting = (mykonosGpioSlewRate_t)(reg2 & (SLEWRATE_MASK)); + break; + case MYKGPIO1: + slewSetting = (mykonosGpioSlewRate_t)((reg3 & (SLEWRATE_MASK << SHIFT2NIBLE)) >> SHIFT2NIBLE); + break; + case MYKGPIO0: + slewSetting = (mykonosGpioSlewRate_t)(reg3 & (SLEWRATE_MASK)); + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_SLEW_RATE_INV_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_GPIO_SLEW_RATE_INV_PARAM)); + return MYKONOS_ERR_GPIO_SLEW_RATE_INV_PARAM; + } + + *slewRate = slewSetting; + + return MYKONOS_ERR_GPIO_OK; +} + + +/** + * \brief This function sets the CMOS output driver. + * + * This function sets the CMOS output driver to increase pad drive strength for the SPI_DIO and GP_INTERRUPT pads + * according to the following settings of the enumeration type mykonosCmosPadDrvStr_t + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param cmosDrv drive for the CMOS output driver + * + * \retval MYKONOS_ERR_CMOS_DRV_INV_PARAM invalid drive strength, valid settings are given by mykonosCmosPadDrvStr_t + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_setCmosDrv(mykonosDevice_t *device, mykonosCmosPadDrvStr_t cmosDrv) +{ + const uint8_t CMOS_DRV_MASK = 0x0F; + const uint8_t CMOS_DRV_SHIFT = 0x04; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_setCmosDrv()\n"); +#endif + + /* Error checking for correct drive */ + switch (cmosDrv) + { /* fall through since this is only checking */ + case MYK_CMOSPAD_DRV_1X: + case MYK_CMOSPAD_DRV_2X: + case MYK_CMOSPAD_DRV_3X: + case MYK_CMOSPAD_DRV_4X: + case MYK_CMOSPAD_DRV_5X: + break; + default: + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CMOS_DRV_INV_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_CMOS_DRV_INV_PARAM)); + return MYKONOS_ERR_CMOS_DRV_INV_PARAM; + } + + CMB_SPIWriteField(device->spiSettings, MYKONOS_GPIO_SLEW_CTL_3, cmosDrv, (~CMOS_DRV_MASK), CMOS_DRV_SHIFT); + + return MYKONOS_ERR_GPIO_OK; +} + +/** + * \brief This function gets the programmed CMOS output driver + * + * + * Dependencies + * - device->spiSettings->chipSelectIndex + * + * \param device is a pointer to the device settings structure + * \param cmosDrv will be the programmed drive for the CMOS output driver + * + * \retval MYKONOS_ERR_CMOS_DRV_NULL_PARAM Null parameter passed to the function + * \retval MYKONOS_ERR_GPIO_OK Function completed successfully + */ +mykonosGpioErr_t MYKONOS_getCmosDrv(mykonosDevice_t *device, mykonosCmosPadDrvStr_t *cmosDrv) +{ + uint8_t regRd = 0x00; + + const uint8_t CMOS_DRV_MASK = 0xF0; + const uint8_t CMOS_DRV_SHIFT = 0x04; + +#if MYKONOS_VERBOSE == 1 + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_getCmosDrv()\n"); +#endif + + if (cmosDrv == NULL) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_CMOS_DRV_NULL_PARAM, + getGpioMykonosErrorMessage(MYKONOS_ERR_CMOS_DRV_NULL_PARAM)); + return MYKONOS_ERR_CMOS_DRV_NULL_PARAM; + } + + CMB_SPIReadByte(device->spiSettings, MYKONOS_GPIO_SLEW_CTL_3, ®Rd); + + *cmosDrv = (mykonosCmosPadDrvStr_t)((regRd & CMOS_DRV_MASK) >> CMOS_DRV_SHIFT); + + return MYKONOS_ERR_GPIO_OK; +} + +/** +* \brief This API function configures and enables the secondary SPI port. +* +* This port allows control compatibility with BBPs that employ dual SPI ports. +* The GPIO mapping for the SPI2 is fixed: +* SPI signal | GPIO +* -------------|------------------- +* CSB_2 | GPIO 3 +* SCLK_2 | GPIO 2 +* SDO_2 | GPIO 1 +* SDO_2/SDI2 | GPIO 0 +* +* The secondary SPI port only has a small subset of registers that affect the +* attenuation of the TX channels. It uses a fifth GPIO pin in order to decide +* which TxAttenuation word is active. The Tx Attenuation words in the 2nd SPI +* port are different than the first SPI port. On the 2nd SPI port, each +* transmitter has two Tx Attenuation words (an active word and an inactive +* word). The BBIC should write to the inactive TxAttenuation word. Then the +* fifth GPIO pin should be asserted to make the inactive TxAttenuation word +* active. This allows the BBIC to tightly control in real time when the +* TxAttenuation updates. +* +* Dependencies +* - device->spiSettings +* - device->spiSettings->chipSelectIndex +* +* \param device is a pointer to the device settings structure +* \param enable This is parameter will enable the secondary SPI port: 1 = enable, 0 = disable +* \param updateTxAttenPinSelect This parameter set the GPIO pin to be toggle for using the inactive attenuation words for both channels +* tx update | GPIO +* ------------|------------------- +* 0x00 | GPIO 4 +* 0x01 | GPIO 8 +* 0x02 | GPIO 14 +* 0x03 | none selected +* +* \retval MYKONOS_ERR_SPI2_INV_GPIO if an invalid GPIO pin configuration is passed +* \retval MYKONOS_ERR_HAL_LAYER if HAL function error is passed +* \retval MYKONOS_ERR_OK Function completed successfully +*/ +mykonosGpioErr_t MYKONOS_spi2GpioSetup(mykonosDevice_t *device, uint8_t enable, uint8_t updateTxAttenPinSelect) +{ + uint8_t regWrite = 0; + uint8_t enableBit = 0; + + const uint32_t SPI2_PIN_MASK = 0x03; + +#ifdef MYKONOS_VERBOSE + CMB_writeToLog(ADIHAL_LOG_MESSAGE, device->spiSettings->chipSelectIndex, MYKONOS_ERR_GPIO_OK, "MYKONOS_spi2GpioSetup()\n"); +#endif + + /* Error checking for correctness of GPIO to control attenuation word. */ + if (updateTxAttenPinSelect & ~SPI2_PIN_MASK) + { + CMB_writeToLog(ADIHAL_LOG_ERROR, device->spiSettings->chipSelectIndex, MYKONOS_ERR_SPI2_INV_GPIO, + getGpioMykonosErrorMessage(MYKONOS_ERR_SPI2_INV_GPIO)); + return MYKONOS_ERR_SPI2_INV_GPIO; + } + + /* masking the enable bit and the required pin */ + enableBit = (enable > 0) ? 1 : 0; + regWrite = (uint8_t)((updateTxAttenPinSelect << 4) | (enableBit << 3)); + + /* Set the SPI2 enable and the GPIO pin associated. */ + CMB_SPIWriteField(device->spiSettings, MYKONOS_ADDR_CONFIGURATION_CONTROL_1, regWrite, 0x38, 0); + + return MYKONOS_ERR_GPIO_OK; +} + diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_gpio.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_gpio.h new file mode 100644 index 00000000..f69ec745 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_gpio.h @@ -0,0 +1,172 @@ +/*! + * \file mykonos_gpio.h + * \brief Contains macro definitions and function prototypes for mykonos_gpio.c + * + * Mykonos API version: 1.5.2.3566 + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#ifndef MYKONOSGPIO_H_ +#define MYKONOSGPIO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "t_mykonos.h" +#include "t_mykonos_gpio.h" + +/* + ***************************************************************************** + * GPIO functions + ***************************************************************************** + */ + +/* GPIO CMOS and SPI setting Functions */ +mykonosGpioErr_t MYKONOS_setGpioDrv(mykonosDevice_t *device, uint32_t gpioDrv); +mykonosGpioErr_t MYKONOS_getGpioDrv(mykonosDevice_t *device, uint32_t *gpioDrv); + +mykonosGpioErr_t MYKONOS_setGpioSlewRate(mykonosDevice_t *device, mykonosGpioSelect_t gpioSelect, mykonosGpioSlewRate_t slewRate); +mykonosGpioErr_t MYKONOS_getGpioSlewRate(mykonosDevice_t *device, mykonosGpioSelect_t gpioSelect, mykonosGpioSlewRate_t *slewRate); + +mykonosGpioErr_t MYKONOS_setCmosDrv(mykonosDevice_t *device, mykonosCmosPadDrvStr_t spiDrv); +mykonosGpioErr_t MYKONOS_getCmosDrv(mykonosDevice_t *device, mykonosCmosPadDrvStr_t *spiDrv); + + +/* Monitor output Functions */ +mykonosGpioErr_t MYKONOS_setGpioMonitorOut(mykonosDevice_t *device, uint8_t monitorIndex, uint8_t monitorMask); +mykonosGpioErr_t MYKONOS_getGpioMonitorOut(mykonosDevice_t *device, uint8_t *monitorIndex, uint8_t *monitorMask); + +/* RX GPIO Functions */ +mykonosGpioErr_t MYKONOS_setRx1GainCtrlPin(mykonosDevice_t *device, uint8_t incStep, uint8_t decStep, mykonosGpioSelect_t rx1GainIncPin, mykonosGpioSelect_t rx1GainDecPin, uint8_t enable); +mykonosGpioErr_t MYKONOS_setRx2GainCtrlPin(mykonosDevice_t *device, uint8_t incStep, uint8_t decStep, mykonosGpioSelect_t rx2GainIncPin, mykonosGpioSelect_t rx2GainDecPin, uint8_t enable); +mykonosGpioErr_t MYKONOS_getRx1GainCtrlPin(mykonosDevice_t *device, uint8_t *incStep, uint8_t *decStep, mykonosGpioSelect_t *rx1GainIncPin, mykonosGpioSelect_t *rx1GainDecPin, uint8_t *enable); +mykonosGpioErr_t MYKONOS_getRx2GainCtrlPin(mykonosDevice_t *device, uint8_t *incStep, uint8_t *decStep, mykonosGpioSelect_t *rx2GainIncPin, mykonosGpioSelect_t *rx2GainDecPin, uint8_t *enable); + +mykonosGpioErr_t MYKONOS_setRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t rx1GainChangePin, mykonosGpioSelect_t rx2GainChangePin); +mykonosGpioErr_t MYKONOS_getRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t *rx1GainChangePin, mykonosGpioSelect_t *rx2GainChangePin); +mykonosGpioErr_t MYKONOS_setObsRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t obsRxGainChangePin); +mykonosGpioErr_t MYKONOS_getObsRxHybridGainChangePin(mykonosDevice_t *device, mykonosGpioSelect_t *obsRxGainChangePin); + +mykonosGpioErr_t MYKONOS_setRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t rx1AgcSyncPin, mykonosGpioSelect_t rx2AgcSyncPin); +mykonosGpioErr_t MYKONOS_getRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t *rx1AgcSyncPin, mykonosGpioSelect_t *rx2AgcSyncPin); +mykonosGpioErr_t MYKONOS_setObsRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t obsRxAgcSyncPin); +mykonosGpioErr_t MYKONOS_getObsRxAgcEnSyncPin(mykonosDevice_t *device, mykonosGpioSelect_t *obsRxAgcSyncPin); + +/* TX GPIO Functions */ +mykonosGpioErr_t MYKONOS_setTx1AttenCtrlPin(mykonosDevice_t *device, uint8_t stepSize, mykonosGpioSelect_t tx1AttenIncPin, mykonosGpioSelect_t tx1AttenDecPin, uint8_t enable, uint8_t useTx1ForTx2); +mykonosGpioErr_t MYKONOS_setTx2AttenCtrlPin(mykonosDevice_t *device, uint8_t stepSize, mykonosGpioSelect_t tx2AttenIncPin, mykonosGpioSelect_t tx2AttenDecPin, uint8_t enable); +mykonosGpioErr_t MYKONOS_getTx1AttenCtrlPin(mykonosDevice_t *device, uint8_t *stepSize, mykonosGpioSelect_t *tx1AttenIncPin, mykonosGpioSelect_t *tx1AttenDecPin, uint8_t *enable, uint8_t *useTx1ForTx2); +mykonosGpioErr_t MYKONOS_getTx2AttenCtrlPin(mykonosDevice_t *device, uint8_t *stepSize, mykonosGpioSelect_t *tx2AttenIncPin, mykonosGpioSelect_t *tx2AttenDecPin, uint8_t *enable, uint8_t *useTx1ForTx2); + +mykonosGpioErr_t MYKONOS_spi2GpioSetup(mykonosDevice_t *device, uint8_t enable, uint8_t updateTxAttenPinSelect); + +/* GPIO memory source Functions */ +mykonosGpioErr_t MYKONOS_setGpioPinLevel(mykonosDevice_t *device, uint32_t gpioPinLevel); +mykonosGpioErr_t MYKONOS_getGpioPinLevel(mykonosDevice_t *device, uint32_t *gpioPinLevel); +mykonosGpioErr_t MYKONOS_getGpioSetLevel(mykonosDevice_t *device, uint32_t *gpioPinSetLevel); + +/* Gain Compensation Functions */ +mykonosGpioErr_t MYKONOS_setRxGainCompensation (mykonosDevice_t *device, mykonosGainComp_t *gainComp, uint8_t enable); +mykonosGpioErr_t MYKONOS_getRxGainCompensation (mykonosDevice_t *device, mykonosGainComp_t *gainComp, uint8_t *enabled); + +mykonosGpioErr_t MYKONOS_setObsRxGainCompensation (mykonosDevice_t *device, mykonosObsRxGainComp_t *gainComp, uint8_t enable); +mykonosGpioErr_t MYKONOS_getObsRxGainCompensation (mykonosDevice_t *device, mykonosObsRxGainComp_t *gainComp, uint8_t *enabled); + +/* SLICER Functions */ +mykonosGpioErr_t MYKONOS_setRxSlicerCtrl(mykonosDevice_t *device, uint8_t slicerStep, mykonosRxSlicer_t rx1Pins, mykonosRxSlicer_t rx2Pins, uint8_t enable); +mykonosGpioErr_t MYKONOS_getRxSlicerCtrl(mykonosDevice_t *device, uint8_t *slicerStep, mykonosRxSlicer_t *rx1Pins, mykonosRxSlicer_t *rx2Pins, uint8_t *enable); + +mykonosGpioErr_t MYKONOS_setObsRxSlicerCtrl(mykonosDevice_t *device, uint8_t slicerStep, mykonosObsRxSlicer_t obsRxPins, uint8_t enable); +mykonosGpioErr_t MYKONOS_getObsRxSlicerCtrl(mykonosDevice_t *device, uint8_t *slicerStep, mykonosObsRxSlicer_t *obsRxPins, uint8_t *enable); + +/* Floating Point Formatter Functions */ +mykonosGpioErr_t MYKONOS_setFloatPointFrmt (mykonosDevice_t *device, mykonosFloatPntFrmt_t *floatFrmt); +mykonosGpioErr_t MYKONOS_getFloatPointFrmt (mykonosDevice_t *device, mykonosFloatPntFrmt_t *floatFrmt); + +mykonosGpioErr_t MYKONOS_setRxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t rx1Att, uint8_t rx2Att, uint8_t enable); +mykonosGpioErr_t MYKONOS_getRxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t *rx1Att, uint8_t *rx2Att, uint8_t *enable); + +mykonosGpioErr_t MYKONOS_setOrxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t orxAtt, uint8_t enable); +mykonosGpioErr_t MYKONOS_getOrxEnFloatPntFrmt (mykonosDevice_t *device, uint8_t *orxAtt, uint8_t *enable); + +/* + ***************************************************************************** + * General Purpose Interrupt functions + ***************************************************************************** + */ +mykonosGpioErr_t MYKONOS_configGpInterrupt(mykonosDevice_t *device, uint16_t gpMask); +mykonosGpioErr_t MYKONOS_readGpInterruptStatus(mykonosDevice_t *device, uint16_t *status); + +/* + ***************************************************************************** + * ARM GPIO usage functions + ***************************************************************************** + */ +mykonosGpioErr_t MYKONOS_setArmGpioPins(mykonosDevice_t *device); + +/* + ***************************************************************************** + * AuxADC/AuxDAC functions + ***************************************************************************** + */ +mykonosGpioErr_t MYKONOS_setupAuxAdcs(mykonosDevice_t *device, uint8_t adcDecimation, uint8_t enable); +mykonosGpioErr_t MYKONOS_setAuxAdcChannel(mykonosDevice_t *device, mykonosAuxAdcChannels_t auxAdcChannel); +mykonosGpioErr_t MYKONOS_readAuxAdc(mykonosDevice_t *device, uint16_t *adcCode); +mykonosGpioErr_t MYKONOS_setupAuxDacs(mykonosDevice_t *device); +mykonosGpioErr_t MYKONOS_writeAuxDac(mykonosDevice_t *device, uint8_t auxDacIndex, uint16_t auxDacCode); + +/* + ***************************************************************************** + * GPIO3v3 functions + ***************************************************************************** + */ +mykonosGpioErr_t MYKONOS_setupGpio3v3(mykonosDevice_t *device); + +mykonosGpioErr_t MYKONOS_setGpio3v3PinLevel(mykonosDevice_t *device, uint16_t gpio3v3PinLevel); +mykonosGpioErr_t MYKONOS_getGpio3v3SetLevel(mykonosDevice_t *device, uint16_t *gpio3v3SetLevel); + +mykonosGpioErr_t MYKONOS_getGpio3v3PinLevel(mykonosDevice_t *device, uint16_t *gpio3v3PinLevel); + +mykonosGpioErr_t MYKONOS_setGpio3v3Oe(mykonosDevice_t *device, uint16_t gpio3v3OutEn); +mykonosGpioErr_t MYKONOS_getGpio3v3Oe(mykonosDevice_t *device, uint16_t *gpio3v3OutEn); + +mykonosGpioErr_t MYKONOS_setGpio3v3SourceCtrl(mykonosDevice_t *device, uint16_t gpio3v3SrcCtrl); +mykonosGpioErr_t MYKONOS_getGpio3v3SourceCtrl(mykonosDevice_t *device, uint16_t *gpio3v3SrcCtrl); + +/* + ***************************************************************************** + * GPIO helper functions + ***************************************************************************** + */ +mykonosGpioErr_t MYKONOS_setupGpio(mykonosDevice_t *device); +mykonosGpioErr_t MYKONOS_setGpioOe(mykonosDevice_t *device, uint32_t gpioOutEn, uint32_t gpioUsedMask); +mykonosGpioErr_t MYKONOS_getGpioOe(mykonosDevice_t *device, uint32_t *gpioOutEn); + +mykonosGpioErr_t MYKONOS_setGpioSourceCtrl(mykonosDevice_t *device, uint32_t gpioSrcCtrl); +mykonosGpioErr_t MYKONOS_getGpioSourceCtrl(mykonosDevice_t *device, uint32_t *gpioSrcCtrl); + +/* + ***************************************************************************** + * Temperature Sensor functions + ***************************************************************************** + */ +mykonosGpioErr_t MYKONOS_setupTempSensor(mykonosDevice_t *device, mykonosTempSensorConfig_t *tempSensor); +mykonosGpioErr_t MYKONOS_getTempSensorConfig(mykonosDevice_t *device, mykonosTempSensorConfig_t *tempSensor); + +mykonosGpioErr_t MYKONOS_startTempMeasurement(mykonosDevice_t *device); +mykonosGpioErr_t MYKONOS_readTempSensor(mykonosDevice_t *device, mykonosTempSensorStatus_t *tempStatus); + +const char* getGpioMykonosErrorMessage(mykonosGpioErr_t errorCode); + +#ifdef __cplusplus +} +#endif + +#endif /* MYKONOSGPIO_H_ */ diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_macros.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_macros.h new file mode 100644 index 00000000..354f5617 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_macros.h @@ -0,0 +1,707 @@ +/** + * \file mykonos_macros.h + * \brief Contains address and miscellaneous macro definitions for Mykonos API + * + * Mykonos API version: 1.5.2.3566 + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#ifndef CLEMENTE_TDD_MACROS_H +#define CLEMENTE_TDD_MACROS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define MYKONOS_ADDR_CONFIGURATION_CONTROL_0 0x000 +#define MYKONOS_ADDR_SPI_CONFIGURATION_CONTROL_1 0x001 +#define MYKONOS_ADDR_PRODUCT_ID 0x004 +#define MYKONOS_GPIO_DRV_CTL_0 0x020 +#define MYKONOS_GPIO_DRV_CTL_1 0x021 +#define MYKONOS_GPIO_SLEW_CTL_0 0x022 +#define MYKONOS_GPIO_SLEW_CTL_1 0x023 +#define MYKONOS_GPIO_SLEW_CTL_2 0x024 +#define MYKONOS_GPIO_SLEW_CTL_3 0x025 + +#define MYKONOS_ADDR_DIGITAL_IO_CONTROL 0x028 + +#define MYKONOS_ADDR_SYSREF_PAD_CONFIG 0x040 +#define MYKONOS_ADDR_TX1_SYNC_PAD_CONFIG 0x041 +#define MYKONOS_ADDR_TX2_SYNC_PAD_CONFIG 0x042 +#define MYKONOS_ADDR_RX1_SYNC_CONFIG 0x043 +#define MYKONOS_ADDR_RX2_SYNC_CONFIG 0x044 + +/* Mykonos Framer Registers */ +#define MYKONOS_ADDR_FRAMER_RESET 0x059 +#define MYKONOS_ADDR_FRAMER_CLK_EN 0x05A +#define MYKONOS_ADDR_FRAMER_ADDR 0x05B +#define MYKONOS_ADDR_FRAMER_DATA 0x05C +#define MYKONOS_ADDR_FRAMER_WRITE_EN 0x05D +#define MYKONOS_ADDR_FRAMER_SYSREF_FIFO_EN 0x05E +#define MYKONOS_ADDR_FRAMER_CONFIG_F 0x05F +#define MYKONOS_ADDR_FRAMER_LANE_CTL 0x060 +#define MYKONOS_ADDR_FRAMER_ADC_XBAR_SEL 0x061 +#define MYKONOS_ADDR_FRAMER_LANE_XBAR_SEL 0x062 +#define MYKONOS_ADDR_FRAMER_CONFIG_LOOPBACK_XBAR_REV 0x063 +#define MYKONOS_ADDR_FRAMER_SYNCN_FILT 0x064 +#define MYKONOS_ADDR_FRAMER_LMFC_F_OFFSET 0x065 +#define MYKONOS_ADDR_FRAMER_LMFC_K_OFFSET 0x066 +#define MYKONOS_ADDR_FRAMER_TEST_CNTR_CTL 0x067 +#define MYKONOS_ADDR_FRAMER_STATUS_STRB 0x068 +#define MYKONOS_ADDR_FRAMER_STATUS 0x069 +#define MYKONOS_ADDR_FRAMER_SYSREF_TO_LMFC_CNTR_STAT 0x06A +#define MYKONOS_ADDR_FRAMER_SYSREF_TO_LMFC_ERR_MARGIN 0x06B +#define MYKONOS_ADDR_FRAMER_LANE_FIFO_STRB 0x06C +#define MYKONOS_ADDR_FRAMER_LANE0_FIFO_RDWR_ADDR 0x06D +#define MYKONOS_ADDR_FRAMER_LANE1_FIFO_RDWR_ADDR 0x06E +#define MYKONOS_ADDR_FRAMER_LANE2_FIFO_RDWR_ADDR 0x06F +#define MYKONOS_ADDR_FRAMER_LANE3_FIFO_RDWR_ADDR 0x070 +#define MYKONOS_ADDR_FRAMER_PRBS10_CTL 0x071 +#define MYKONOS_ADDR_FRAMER_PRBS20_CTL 0x072 +#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_EN 0x073 +#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_7_TO_0 0x074 +#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_15_TO_8 0x075 +#define MYKONOS_ADDR_FRAMER_PATTERN_GEN_19_TO_16 0x076 +#define MYKONOS_ADDR_FRAMER_CONFIG_JTX_GEN 0x077 +#define MYKONOS_ADDR_FRAMER_LANE_DATA_CTL 0x078 +#define MYKONOS_ADDR_FRAMER_DATA_SAMPLE_CTL 0x079 + +/* Mykonos Deframer Sub Address Map */ +#define MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_RECVD 0x00 +#define MYKONOS_SUBADDR_DEFRAMER_LANE0_ILAS_CFG 0x50 + +/* Mykonos Deframer Registers */ +#define MYKONOS_ADDR_DEFRAMER_RESET 0x07A +#define MYKONOS_ADDR_DEFRAMER_CLK_EN 0x07B +#define MYKONOS_ADDR_DEFRAMER_ADDR 0x07C +#define MYKONOS_ADDR_DEFRAMER_DATA 0x07D +#define MYKONOS_ADDR_DEFRAMER_WR_EN 0x07E +#define MYKONOS_ADDR_DEFRAMER_SYSREF_FIFO_EN 0x07F +#define MYKONOS_ADDR_DEFRAMER_CONFIG_F 0x080 +#define MYKONOS_ADDR_DEFRAMER_LANE_FIFO_CTL 0x081 +#define MYKONOS_ADDR_DEFRAMER_DAC_XBAR_SEL 0x082 +#define MYKONOS_ADDR_DEFRAMER_LANE_XBAR_SEL 0x083 +#define MYKONOS_ADDR_DEFRAMER_LMFC_F_OFFSET 0x084 +#define MYKONOS_ADDR_DEFRAMER_LMFC_K_OFFSET 0x085 +#define MYKONOS_ADDR_DEFRAMER_CONFIG_SYNC_USER_DATA_CTL 0x086 +#define MYKONOS_ADDR_DEFRAMER_SYNC_REQ_RETIME 0x087 +#define MYKONOS_ADDR_DEFRAMER_TEST 0x088 +#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_STRT_DAC_XBAR_REV 0x089 +#define MYKONOS_ADDR_DEFRAMER_STAT_STRB 0x08A +#define MYKONOS_ADDR_DEFRAMER_STAT 0x08B +#define MYKONOS_ADDR_DEFRAMER_TEST_ERR_CNT_STAT 0x08C +#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_RD_ADDR 0x08D +#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_WR_ADDR 0x08E +#define MYKONOS_ADDR_DEFRAMER_QBLMFC_VS_EXTLMFC_CNTR_STAT 0x08F +#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_STAT 0x090 +#define MYKONOS_ADDR_DEFRAMER_STRT_RD_DEL_STOP_WR 0x091 +#define MYKONOS_ADDR_DEFRAMER_FIFO_SAMPLE_SPI_ADDR_RD 0x092 +#define MYKONOS_ADDR_DEFRAMER_FIFO_BYTE_SPI_ADDR_RD 0x093 +#define MYKONOS_ADDR_DEFRAMER_FIFO_BYTE_SPI_DATA_RD 0x094 +#define MYKONOS_ADDR_DEFRAMER_SAMPLE0_7_TO_0 0x095 +#define MYKONOS_ADDR_DEFRAMER_SAMPLE0_15_TO_8 0x096 +#define MYKONOS_ADDR_DEFRAMER_SAMPLE1_7_TO_0 0x097 +#define MYKONOS_ADDR_DEFRAMER_SAMPLE1_15_TO_8 0x098 +#define MYKONOS_ADDR_DEFRAMER_SAMPLE2_7_TO_0 0x099 +#define MYKONOS_ADDR_DEFRAMER_SAMPLE2_15_TO_8 0x09A +#define MYKONOS_ADDR_DEFRAMER_SAMPLE3_7_TO_0 0x09B +#define MYKONOS_ADDR_DEFRAMER_SAMPLE3_15_TO_8 0x09C +#define MYKONOS_ADDR_DEFRAMER_LANE_FIFO_STRB 0x09D +#define MYKONOS_ADDR_DEFRAMER_LANE0_FIFO_RDWR_ADDR 0x09E +#define MYKONOS_ADDR_DEFRAMER_LANE1_FIFO_RDWR_ADDR 0x09F +#define MYKONOS_ADDR_DEFRAMER_LANE2_FIFO_RDWR_ADDR 0x0A0 +#define MYKONOS_ADDR_DEFRAMER_LANE3_FIFO_RDWR_ADDR 0x0A1 +#define MYKONOS_ADDR_DEFRAMER_SYSREF_TO_LMFC_CNTR_STAT 0x0A2 +#define MYKONOS_ADDR_DEFRAMER_SYSREF_TO_LMFC_ERR_MARGIN 0x0A3 +#define MYKONOS_ADDR_DEFRAMER_PRBS10_CTL 0x0A4 +#define MYKONOS_ADDR_DEFRAMER_PRBS20_CTL 0x0A5 +#define MYKONOS_ADDR_DEFRAMER_PRBS20_STRB_CHKSUM_TYPE 0x0A6 +#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_7_TO_0 0x0A7 +#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_15_TO_8 0x0A8 +#define MYKONOS_ADDR_DEFRAMER_PRBS20_ERR_CNTR_23_TO_16 0x0A9 +#define MYKONOS_ADDR_DEFRAMER_LANE_DATA_CTL 0x0AA +#define MYKONOS_ADDR_DEFRAMER_STATUS_2 0x0AB +#define MYKONOS_ADDR_DEFRAMER_DET_FIFO_PHASE 0x0AC + +/* Mykonos Serializer Registers */ +#define MYKONOS_ADDR_SERIALIZER_CTL_0 0x0B0 +#define MYKONOS_ADDR_SERIALIZER_CTL_1 0x0B1 +#define MYKONOS_ADDR_SERIALIZER_CTL_2 0x0B2 +#define MYKONOS_ADDR_SERIALIZER_CTL_3 0x0B3 +#define MYKONOS_ADDR_SERIALIZER_HS_DIV_TXSER_CLK_EN 0x0B4 +#define MYKONOS_ADDR_SERIALIZER_SPECIAL 0x0B5 + +/* Mykonos Deserializer Registers */ +#define MYKONOS_ADDR_DESERIALIZER_PDET_CTL 0x0BC +#define MYKONOS_ADDR_DESERIALIZER_CTL_0 0x0BD +#define MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_0 0x0BE +#define MYKONOS_ADDR_DESERIALIZER_SIN_SHAPE_1 0x0BF +#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_0 0x0C1 +#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1 0x0C2 +#define MYKONOS_ADDR_DESERIALIZER_MISC_CTL 0x0C3 +#define MYKONOS_ADDR_DESERIALIZER_EQ_HP_EN 0x0C4 +#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_1_TO_0 0x0C5 +#define MYKONOS_ADDR_DESERIALIZER_EQ_CTL_3_TO_2 0x0C6 +#define MYKONOS_ADDR_DESERIALIZER_HS_DIV_RXCDR_CLK_EN 0x0CD +#define MYKONOS_ADDR_DESERIALIZER_SPECIAL 0x0CE +#define MYKONOS_ADDR_DESERIALIZER_CDR_CAL_CTL 0x0D0 + +#define MYKONOS_ADDR_CONFIGURATION_CONTROL_1 0x100 +#define MYKONOS_ADDR_CONFIGURATION_CONTROL_2 0x101 +#define MYKONOS_ADDR_CONFIGURATION_CONTROL_4 0x102 +#define MYKONOS_ADDR_CONFIGURATION_CONTROL_5 0x103 +#define MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_1 0x104 +#define MYKONOS_ADDR_DPD_SNIFFER_CONFIGURATION_CONTROL_2 0x105 +#define MYKONOS_ADDR_DPD_SNIFFER_GPIO_SELECT 0x106 +#define MYKONOS_ADDR_SNIFFER_CONFIGURATION_CONTROL 0x107 +#define MYKONOS_ADDR_DPD_CONFIGURATION_CONTROL 0x108 +#define MYKONOS_ADDR_LOOPBACK_CONFIGURATION_CONTROL 0x109 + +#define MYKONOS_ADDR_CLOCK_CONTROL_0 0x117 +#define MYKONOS_ADDR_CLOCK_CONTROL_1 0x118 +#define MYKONOS_ADDR_CLOCK_CONTROL_2 0x119 +#define MYKONOS_ADDR_CLOCK_CONTROL_3 0x11A +#define MYKONOS_ADDR_CLOCK_CONTROL_4 0x11B +#define MYKONOS_ADDR_CLOCK_CONTROL_5 0x11C + +#define MYKONOS_ADDR_MCS_CONTROL 0x120 +#define MYKONOS_ADDR_MCS_STATUS 0x121 + +/* CLK PLL Registers */ +#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE0 0x141 +#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_INT_BYTE1 0x142 +#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE0 0x143 +#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE1 0x144 +#define MYKONOS_ADDR_CLK_SYNTH_DIVIDER_FRAC_BYTE2 0x145 +#define MYKONOS_ADDR_CLK_SYNTH_F_VCOTN_BYTE1 0x148 +#define MYKONOS_ADDR_CLK_SYNTH_BYTE1 0x149 +#define MYKONOS_ADDR_CLK_SYNTH_BYTE2 0x14A +#define MYKONOS_ADDR_CLK_SYNTH_BYTE3 0x14B +#define MYKONOS_ADDR_CLK_SYNTH_BYTE5 0x14D +#define MYKONOS_ADDR_CLK_SYNTH_BYTE6 0x14E +#define MYKONOS_ADDR_CLK_SYNTH_BYTE7 0x14F +#define MYKONOS_ADDR_CLK_SYNTH_LF_R3 0x150 +#define MYKONOS_ADDR_CLK_SYNTH_BYTE9 0x152 +#define MYKONOS_ADDR_CLK_SYNTH_CAL_STAT 0x154 +#define MYKONOS_ADDR_CLK_SYNTH_VCO_CAL_REF 0x155 +#define MYKONOS_ADDR_CLK_SYNTH_VCO_BAND_BYTE1 0x157 +#define MYKONOS_ADDR_CLK_SYNTH_CAL_CONTROL 0x159 +#define MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL1 0x15E +#define MYKONOS_ADDR_CLK_SYNTH_VCO_VAR_CTL2 0x15F + +/* DPD Registers */ +#define MYKONOS_ADDR_TX1_DPD_MODEL_INDIRECT_PTR 0x178 +#define MYKONOS_ADDR_TX2_DPD_MODEL_INDIRECT_PTR 0x17C +#define MYKONOS_ADDR_DPD_RMS_BUF_SIZE 0x180 +#define MYKONOS_ADDR_TX1_DPD_MODEL_WORKING_PTR 0x188 +#define MYKONOS_ADDR_TX2_DPD_MODEL_WORKING_PTR 0x18C + +/* Rx NCO Control registers */ +#define MYKONOS_ADDR_CALPLL_SDM_CONTROL 0x17F +#define MYKONOS_ADDR_RX_NCO_CONTROL 0x190 +#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_3 0x191 +#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_2 0x192 +#define MYKONOS_ADDR_RX_NCO_CH1_FTW_BYTE_1 0x193 +#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_3 0x194 +#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_2 0x195 +#define MYKONOS_ADDR_RX_NCO_CH2_FTW_BYTE_1 0x196 +#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_3 0x197 +#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_2 0x198 +#define MYKONOS_ADDR_RX_NCO_DPD_SNIFFER_FTW_BYTE_1 0x199 + +#define MYKONOS_ADDR_ENSM_CONFIG_7_0 0x1B0 +#define MYKONOS_ADDR_CALIBRATION_CONTROL 0x1B2 +#define MYKONOS_ADDR_ENSM_MANUAL_GAIN_LOCK_GPIO_SELECT 0x1B5 +#define MYKONOS_ADDR_REFERENCE_CLOCK_CYCLES 0x1C0 +#define MYKONOS_ADDR_TX_PD_OVERIDE_7_0 0x209 +#define MYKONOS_ADDR_RCAL_CONTROL 0x224 +#define MYKONOS_ADDR_REF_PAD_CONFIG1 0x230 +#define MYKONOS_ADDR_REF_PAD_CONFIG2 0x231 + +#define MYKONOS_ADDR_RXSYNTH_CP_CAL_STAT 0x254 +#define MYKONOS_ADDR_RXSYNTH_VCO_BAND_BYTE1 0x257 +#define MYKONOS_ADDR_TXSYNTH_CP_CAL_STAT 0x2C4 +#define MYKONOS_ADDR_TXSYNTH_VCO_BAND_BYTE1 0x2C7 +#define MYKONOS_ADDR_SNIFF_RXSYNTH_CP_CAL_STAT 0x354 +#define MYKONOS_ADDR_SNIFF_RXSYNTH_VCO_BAND_BYTE1 0x357 +#define MYKONOS_ADDR_SNIFF_RXLOGEN_BYTE1 0x380 + +#define MYKONOS_ADDR_RX_FILTER_CONFIGURATION 0x410 +#define MYKONOS_ADDR_RX_FILTER_GAIN 0x411 +#define MYKONOS_ADDR_DPD_SNIFFER_RX_FILTER_GAIN 0x412 + +/* Mykonos Temperature Gain Compensation Registers */ +#define MYKONOS_ADDR_RX1_TEMP_GAIN_COMP 0x420 +#define MYKONOS_ADDR_RX2_TEMP_GAIN_COMP 0x421 +#define MYKONOS_ADDR_OBS_TEMP_GAIN_COMP 0x422 + +/* Mykonos AGC General Registers */ +#define MYKONOS_ADDR_AGC_CFG_1 0x42E +#define MYKONOS_ADDR_AGC_CFG_2 0x42F +#define MYKONOS_ADDR_AGC_GAIN_CHANGE_GPIO_SEL 0x430 +#define MYKONOS_ADDR_AGC_RX1_MAX_GAIN_INDEX 0x431 +#define MYKONOS_ADDR_AGC_RX1_MIN_GAIN_INDEX 0x432 +#define MYKONOS_ADDR_AGC_MANUAL_GAIN_CFG 0x433 +#define MYKONOS_ADDR_AGC_MANUAL_GAIN_GPIO_SEL 0x434 +#define MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_1 0x435 +#define MYKONOS_ADDR_AGC_MANUAL_GAIN_INDEX_CH_2 0x436 +#define MYKONOS_ADDR_AGC_LOCK_LEVEL 0x437 +#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_1 0x438 +#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_2 0x439 +#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_3 0x43A +#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_4 0x43B +#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_5 0x43C +#define MYKONOS_ADDR_AGC_OVRG_GAIN_STEP_6 0x43D +#define MYKONOS_ADDR_AGC_RX1_GAIN_LOCK_DELAY 0x43E +#define MYKONOS_ADDR_AGC_RX2_GAIN_LOCK_DELAY 0x43F +#define MYKONOS_ADDR_AGC_RX1_ATTACK_DELAY 0x440 +#define MYKONOS_ADDR_AGC_RX2_ATTACK_DELAY 0x441 +#define MYKONOS_ADDR_AGC_ULB_THRSH 0x442 +#define MYKONOS_ADDR_AGC_LLB_THRSH 0x443 +#define MYKONOS_ADDR_AGC_RX_BLOCK_DET_DECAY 0x444 +#define MYKONOS_ADDR_AGC_RESET_PD_HIGH_CNT 0x445 +#define MYKONOS_ADDR_AGC_RX2_MAX_GAIN_INDEX 0x446 +#define MYKONOS_ADDR_AGC_RX2_MIN_GAIN_INDEX 0x447 +#define MYKONOS_ADDR_AGC_ORX_SNRX_CFG_1 0x448 +#define MYKONOS_ADDR_AGC_ORX_SNRX_CFG_2 0x449 +#define MYKONOS_ADDR_AGC_ORX_SNRX_MAX_GAIN_INDEX 0x44A +#define MYKONOS_ADDR_AGC_ORX_SNRX_MIN_GAIN_INDEX 0x44B +#define MYKONOS_ADDR_AGC_ORX_SNRX_MANUAL_GAIN_CFG 0x44C +#define MYKONOS_ADDR_AGC_ORX_SNRX_GPIO_SEL 0x44D +#define MYKONOS_ADDR_AGC_ORX_SNRX_LOCK_LEVEL 0x44E +#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_1 0x44F +#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_2 0x450 +#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_3 0x451 +#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_4 0x452 +#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_5 0x453 +#define MYKONOS_ADDR_AGC_ORX_SNRX_OVRG_GAIN_STEP_6 0x454 +#define MYKONOS_ADDR_AGC_ORX_SNRX_GAIN_LOCK_DELAY 0x455 +#define MYKONOS_ADDR_AGC_ORX_SNRX_ATTACK_DELAY 0x456 +#define MYKONOS_ADDR_AGC_ORX_SNRX_ULB_THRSH 0x457 +#define MYKONOS_ADDR_AGC_ORX_SNRX_LLB_THRSH 0x458 +#define MYKONOS_ADDR_AGC_ORX_SNRX_BLOCK_DET_DECAY 0x459 +#define MYKONOS_ADDR_AGC_ORX_SNRX_RESET_PD_HIGH_CNT 0x45A +#define MYKONOS_ADDR_AGC_ORX1_MANUAL_GAIN_INDEX 0x45B +#define MYKONOS_ADDR_AGC_ORX2_MANUAL_GAIN_INDEX 0x45C +#define MYKONOS_ADDR_AGC_SNRX_MANUAL_GAIN_INDEX 0x45D +#define MYKONOS_ADDR_AGC_LOOPBACK1_MANUAL_GAIN_INDEX 0x45E +#define MYKONOS_ADDR_AGC_LOOPBACK2_MANUAL_GAIN_INDEX 0x45F +#define MYKONOS_ADDR_AGC_ORX_SNRX_ACTIVE 0x460 + +/* Mykonos Fast Attack AGC Registers */ +#define MYKONOS_ADDR_AGC_FAST_CFG_1 0x468 +#define MYKONOS_ADDR_AGC_FAST_CFG_2 0x469 +#define MYKONOS_ADDR_AGC_FAST_ENRGY_LOST_THRSH 0x46A +#define MYKONOS_ADDR_AGC_FAST_STRONG_SIG_THRSH 0x46B +#define MYKONOS_ADDR_AGC_FAST_SETTING_DELAY 0x46C +#define MYKONOS_ADDR_AGC_FAST_OPT_MAX_GAIN 0x46D +#define MYKONOS_ADDR_AGC_FAST_ENRGY_DET_CNT 0x46E +#define MYKONOS_ADDR_AGC_FAST_AGCLL_UPPER_LIMIT 0x46F +#define MYKONOS_ADDR_AGC_FAST_GAIN_LOCK_EXIT_CNT 0x470 +#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_CFG_1 0x471 +#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_CFG_2 0x472 +#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_ENRGY_LOST_THRSH 0x473 +#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_STRONG_SIG_THRSH 0x474 +#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_SET_DELAY 0x475 +#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_OPT_MAX_GAIN 0x476 +#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_ENRGY_DET_CNT 0x477 +#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_AGCLL_UPPER_LIMIT 0x478 +#define MYKONOS_ADDR_AGC_FAST_ORX_SNRX_GAIN_LOCK_EXIT_CNT 0x479 + +/* Mykonos Slow Loop - Hybrid AGC Registers */ +#define MYKONOS_ADDR_AGC_SLOW_LOCK_LEV_THRSH 0x480 +#define MYKONOS_ADDR_AGC_SLOW_ULB_CNT_THRSH 0x481 +#define MYKONOS_ADDR_AGC_SLOW_LLB_CNT_THRSH 0x482 +#define MYKONOS_ADDR_AGC_SLOW_HIGH_OVRG_CNT_THRSH 0x483 +#define MYKONOS_ADDR_AGC_SLOW_LOW_OVRG_CNT_THRSH 0x484 +#define MYKONOS_ADDR_AGC_SLOW_VERYLOW_OVRG_CNT_THRSH 0x485 +#define MYKONOS_ADDR_AGC_SLOW_DIG_SAT_CNT_THRSH 0x486 +#define MYKONOS_ADDR_AGC_SLOW_UPPER0_THRSH_GAIN_STEP 0x487 +#define MYKONOS_ADDR_AGC_SLOW_LOWER0_THRSH_GAIN_STEP 0x488 +#define MYKONOS_ADDR_AGC_SLOW_UPPER1_THRSH_GAIN_STEP 0x489 +#define MYKONOS_ADDR_AGC_SLOW_LOWER1_THRSH_GAIN_STEP 0x48A +#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_1 0x48B +#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_2 0x48C +#define MYKONOS_ADDR_AGC_SLOW_GAIN_UPDATE_CNT_3 0x48D +#define MYKONOS_ADDR_AGC_SLOW_LOOP_CFG 0x48E +#define MYKONOS_ADDR_AGC_SLOW_POWER_THRSH 0x48F +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOCK_LEV_THRSH 0x490 + +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ULB_CNT_THRSH 0x491 +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LLB_CNT_THRSH 0x492 +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_HIGH_OVRG_CNT_THRSH 0x493 +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_LOW_OVRG_CNT_THRSH 0x494 +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_ADC_VERYLOW_OVRG_CNT_THRSH 0x495 + +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_DIG_SAT_CNT_THRSH 0x496 +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER0_THRSH_GAIN_STEP 0x497 +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER0_THRSH_GAIN_STEP 0x498 +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UPPER1_THRSH_GAIN_STEP 0x499 +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOWER1_THRSH_GAIN_STEP 0x49A +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_1 0x49B +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_2 0x49C +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_GAIN_UPDATE_CTR_3 0x49D +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_LOOP_CFG 0x49E +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_POWER_THRSH 0x49F +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DEL_1 0x4A0 +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DEL_2 0x4A1 +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DUR_1 0x4A2 +#define MYKONOS_ADDR_AGC_SLOW_ORX_SNRX_UL_SIG_POW_MEAS_DUR_2 0x4A3 + +/* Mykonos Gain Control Read Registers */ +#define MYKONOS_ADDR_GAIN_CTL_CHANNEL_1 0x4B0 +#define MYKONOS_ADDR_GAIN_CTL_FAST_ATTK_STATE 0x4B1 +#define MYKONOS_ADDR_GAIN_CTL_SLOW_LOOP_STATE 0x4B2 +#define MYKONOS_ADDR_GAIN_CTL_CHANNEL_2 0x4B3 +#define MYKONOS_ADDR_GAIN_CTL_OVRG_SIGS_CHANNEL_1 0x4B4 +#define MYKONOS_ADDR_GAIN_CTL_OVRG_SIGS_CHANNEL_2 0x4B5 +#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_GAIN 0x4B6 +#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_LOOP_STATE 0x4B7 +#define MYKONOS_ADDR_GAIN_CTL_ORX_SNRX_OVRG_SIGS 0x4B8 + +/* Mykonos Rx Data Path Overrange Registers */ +#define MYKONOS_ADDR_RX_OVRG_DATAPATH_OVRFLW 0x4B9 +#define MYKONOS_ADDR_RX_OVRG_ORX_SNRX_DATAPATH_OVRFLW 0x4BA + +/* Mykonos RSSI Measurement Registers and Dec Power Measurement Registers*/ +#define MYKONOS_ADDR_RSSI_MEAS_DURATION_0_1 0x4C0 +#define MYKONOS_ADDR_RSSI_MEAS_DURATION_2_3 0x4C1 +#define MYKONOS_ADDR_RSSI_CFG 0x4C6 +#define MYKONOS_DEC_POWER_CONFIG_1 0x4C7 +#define MYKONOS_DEC_POWER_CONFIG_2 0x4C8 +#define MYKONOS_ADDR_DPD_SNF_RSSI_CFG 0x4CF +#define MYKONOS_ADDR_DPD_RSSI_CFG 0x4D6 +#define MYKONOS_SNIFFER_DEC_POWER_CONFIG_1 0x4D7 +#define MYKONOS_SNIFFER_DEC_POWER_CONFIG_2 0x4D8 +#define MYKONOS_CH1_DECIMATED_PWR 0x4DE +#define MYKONOS_CH2_DECIMATED_PWR 0x4DF +#define MYKONOS_SNIFFER_DECIMATED_PWR 0x4E6 + +#define MYKONOS_ADDR_DIGITAL_GAIN_CONFIG 0x4F0 +#define MYKONOS_ADDR_DPD_SNIFFER_DIGITAL_GAIN_CONFIG 0x4F1 +#define MYKONOS_ADDR_GAIN_TABLE_ADDR 0x500 +#define MYKONOS_ADDR_GAIN_TABLE_RX1_FE_GAIN 0x501 +#define MYKONOS_ADDR_GAIN_TABLE_RX1_EXT_CTL 0x502 +#define MYKONOS_ADDR_GAIN_TABLE_RX1_DIG_GAIN 0x503 +#define MYKONOS_ADDR_GAIN_TABLE_RX2_FE_GAIN 0x504 +#define MYKONOS_ADDR_GAIN_TABLE_RX2_EXT_CTL 0x505 +#define MYKONOS_ADDR_GAIN_TABLE_RX2_DIG_GAIN 0x506 +#define MYKONOS_ADDR_GAIN_TABLE_RX3_FE_GAIN 0x507 +#define MYKONOS_ADDR_GAIN_TABLE_RX3_LNA_ENAB 0x508 +#define MYKONOS_ADDR_GAIN_TABLE_RX3_DIG_GAIN 0x509 +#define MYKONOS_ADDR_GAIN_TABLE_CONFIGURATION 0x516 +#define MYKONOS_ADDR_CH3_GAIN_TABLE_CONFIGURATION 0x517 +#define MYKONOS_ADDR_RXFE1_LOCM 0x520 +#define MYKONOS_ADDR_RXFE2_LOCM 0x521 +#define MYKONOS_ADDR_RXLOOPBACK1_CNTRL_1 0x540 +#define MYKONOS_ADDR_RXLOOPBACK2_CNTRL_1 0x541 +#define MYKONOS_ADDR_RX_LOOPBACK1_CNTRL_4 0x546 +#define MYKONOS_ADDR_RX_LOOPBACK2_CNTRL_4 0x547 + +/* Mykonos Overload/Peak Detection Registers */ +#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_CFG 0x580 +#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_UPPER_THRSH 0x581 +#define MYKONOS_ADDR_OVRLD_ADC_OVRLD_LOWER_THRSH 0x582 + +#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_CFG 0x583 +#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_UPPER_THRSH 0x584 +#define MYKONOS_ADDR_OVRLD_PD_DEC_OVRLD_LOWER_THRSH 0x585 +#define MYKONOS_ADDR_OVRLD_PD_DEC_VERYLOW_THRSH 0x586 +#define MYKONOS_ADDR_ORX_SNRX_OVRLD_ADC_OVRLD_CFG 0x587 +#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_CFG 0x58A +#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_UPPER_THRSH 0x58B +#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_LOWER_THRSH 0x58C +#define MYKONOS_ADDR_ORX_SNRX_OVRLD_PD_DEC_OVRLD_VERYLOW_THRSH 0x58D + +#define MYKONOS_ADDR_RX_ADC_FLASH_DELAY 0x5B6 +#define MYKONOS_ADDR_RX_ADC_FLASH_CTRL 0x5B7 +#define MYKONOS_ADDR_RX_ADC1_PRFL 0x5DD +#define MYKONOS_ADDR_RX_ADC2_PRFL 0x5DE +#define MYKONOS_ADDR_ORX_ADC_PRFL 0x5DF + +#define MYKONOS_ADDR_RFDC_MEASURE_COUNT_1 0x631 +#define MYKONOS_ADDR_RFDC_MEASURE_COUNT_2 0x632 +#define MYKONOS_ADDR_RFDC_PROGRAM_SHIFT 0x635 +#define MYKONOS_ADDR_RFDC_CONFIG2 0x636 +#define MYKONOS_DPD_Sniffer_RFDC_CAL_TRACK_EN 0x642 +#define MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_1 0x644 +#define MYKONOS_ADDR_RFDC_SNF_MEASURE_COUNT_2 0x645 +#define MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_1 0x650 +#define MYKONOS_ADDR_RFDC_ORX_MEASURE_COUNT_2 0x651 +#define MYKONOS_ADDR_DIGITAL_DC_MIN_CAL_IDX 0x63A +#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_SHIFT 0x674 +#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_CONFIG 0x676 +#define MYKONOS_DIGITAL_DC_OFFSET_CH3_TRACKING 0x67A +#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_SNF 0x67C +#define MYKONOS_ADDR_DIGITAL_DC_OFFSET_CH3_DPD_M_SHIFT 0x67D + +#define MYKONOS_ADDR_RX_GAIN_COMP_DELAY 0x710 +#define MYKONOS_ADDR_RX1_GAIN_COMP_OFFSET 0x711 +#define MYKONOS_ADDR_RX2_GAIN_COMP_OFFSET 0x712 +#define MYKONOS_ADDR_RX_GAIN_COMP_CFG 0x713 +#define MYKONOS_ADDR_RX_SLCR_PIN_CFG 0x714 +#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_DELAY 0x715 +#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_OFFSET 0x716 +#define MYKONOS_ADDR_DPD_SNF_RX_GAIN_COMP_CFG 0x717 +#define MYKONOS_ADDR_DPD_SNF_RX_SLCR_PIN_CFG 0x718 + +#define MYKONOS_ADDR_FLOATING_POINT_CFG 0x750 +#define MYKONOS_ADDR_FLOATING_POINT_RX_CTRL 0x751 +#define MYKONOS_ADDR_FLOATING_POINT_ORX_CTRL 0x752 + + +#define MYKONOS_ADDR_SNRX_LNA_BIAS_C 0x81B + + +#define MYKONOS_ADDR_ORX_ADC_FLASH_DELAY 0x846 +#define MYKONOS_ADDR_ORX_ADC_FLASH_CTRL 0x847 + +#define MYKONOS_ADDR_TX_FILTER_CONFIGURATION 0x910 +#define MYKONOS_ADDR_TX1_ATTENUATION_0_READBACK 0x940 +#define MYKONOS_ADDR_TX1_ATTENUATION_1_READBACK 0x941 +#define MYKONOS_ADDR_TX2_ATTENUATION_0_READBACK 0x942 +#define MYKONOS_ADDR_TX2_ATTENUATION_1_READBACK 0x943 +#define MYKONOS_ADDR_TX_FILTER_OVERFLOW 0x950 + +/* Mykonos PA Protection Block Registers */ +#define MYKONOS_ADDR_PA_PROTECTION_CONFIGURATION 0x955 +#define MYKONOS_ADDR_PA_PROTECTION_ATTEN_CONTROL 0x956 +#define MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_LSB 0x957 +#define MYKONOS_ADDR_PA_PROTECTION_THRESHOLD_MSB 0x958 +#define MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_LSB 0x959 +#define MYKONOS_ADDR_PA_PROTECTION_POWER_READBACK_MSB 0x95A +#define MYKONOS_ADDR_TX1_ATTENUATION_0 0x960 +#define MYKONOS_ADDR_TX1_ATTENUATION_1 0x961 +#define MYKONOS_ADDR_TX2_ATTENUATION_0 0x962 +#define MYKONOS_ADDR_TX2_ATTENUATION_1 0x963 +#define MYKONOS_ADDR_TX1_GAIN_0 0x967 +#define MYKONOS_ADDR_TX1_GAIN_1 0x968 +#define MYKONOS_ADDR_TX1_GAIN_2 0x969 +#define MYKONOS_ADDR_TX2_GAIN_0 0x96A +#define MYKONOS_ADDR_TX2_GAIN_1 0x96B +#define MYKONOS_ADDR_TX2_GAIN_2 0x96C +#define MYKONOS_ADDR_TX_INCR_DECR_WORD 0x96D +#define MYKONOS_ADDR_TX_TPC_CONFIG 0x96E +#define MYKONOS_ADDR_TX_TPC_GPIO_CFG 0x96F + +#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_MSB 0x9CB +#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_I_LSB 0x9CC +#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_MSB 0x9CD +#define MYKONOS_ADDR_TX_ABBF_FREQ_CAL_NCO_Q_LSB 0x9CE + +/* Mykonos GPIO Registers */ +#define MYKONOS_ADDR_GPIO_3V3_DIR_CTL_7_0 0xB00 +#define MYKONOS_ADDR_GPIO_3V3_DIR_CTL_15_8 0xB01 +#define MYKONOS_ADDR_GPIO_3V3_SPI_SRC_7_0 0xB02 +#define MYKONOS_ADDR_GPIO_3V3_SPI_SRC_15_8 0xB03 +#define MYKONOS_ADDR_GPIO_3V3_SPI_READ_7_0 0xB04 +#define MYKONOS_ADDR_GPIO_3V3_SPI_READ_15_8 0xB05 +#define MYKONOS_ADDR_GPIO_3V3_LSB_SRC_CTL 0xB06 +#define MYKONOS_ADDR_GPIO_3V3_MSB_SRC_CTL 0xB07 + +#define MYKONOS_ADDR_GPIO_DIR_CTL_7_0 0xB20 +#define MYKONOS_ADDR_GPIO_DIR_CTL_15_8 0xB21 +#define MYKONOS_ADDR_GPIO_DIR_CTL_18_16 0xB22 +#define MYKONOS_ADDR_GPIO_SPI_SRC_7_0 0xB23 +#define MYKONOS_ADDR_GPIO_SPI_SRC_15_8 0xB24 +#define MYKONOS_ADDR_GPIO_SPI_SRC_18_16 0xB25 +#define MYKONOS_ADDR_GPIO_SPI_READ_7_0 0xB26 +#define MYKONOS_ADDR_GPIO_SPI_READ_15_8 0xB27 +#define MYKONOS_ADDR_GPIO_SPI_READ_18_16 0xB28 +#define MYKONOS_ADDR_SOURCE_CONTROL_LOWER_BYTE 0xB29 +#define MYKONOS_ADDR_SOURCE_CONTROL_UPPER_BYTE 0xB2A +#define MYKONOS_ADDR_SOURCE_CONTROL_EXTRA_BITS 0xB2B + +#define MYKONOS_ADDR_GPIO_MONITOR_INDEX 0xB40 +#define MYKONOS_ADDR_GPIO_MONITOR_ENABLE 0xB41 + +#define MYKONOS_ADDR_GP_INTERRUPT_MASK_1 0xB42 +#define MYKONOS_ADDR_GP_INTERRUPT_MASK_0 0xB43 +#define MYKONOS_ADDR_GP_INTERRUPT_READ_1 0xB44 +#define MYKONOS_ADDR_GP_INTERRUPT_READ_0 0xB45 + +#define MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_5_0 0xB73 +#define MYKONOS_ADDR_PDAUXDAC_MANUAL_CONTROL_9_6 0xB74 +#define MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_5_0 0xB75 +#define MYKONOS_ADDR_PDAUXDAC_MANUAL_IN_9_6 0xB76 +#define MYKONOS_ADDR_AUX_DAC_LATCH_CONTROL 0xB9F +#define MYKONOS_ADDR_AUXDAC_0_WORD_MSB 0xBA0 + +#define MYKONOS_ADR_AUX_ADC_CLOCK_DIVIDE 0xBC0 +#define MYKONOS_ADDR_AUX_ADC_CFG 0xBC1 +#define MYKONOS_ADDR_AUX_ADC_READ_MSB 0xBC2 +#define MYKONOS_ADDR_AUX_ADC_READ_LSB 0xBC3 +#define MYKONOS_ADDR_AUX_ADC_SEL 0xBC4 +#define MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_0 0xBC5 +#define MYKONOS_ADDR_AUX_ADC_BUFFER_CONFIG_1 0xBC6 + +#define MYKONOS_ADDR_TEMP_SENSOR_OFFSET 0xBE0 +#define MYKONOS_ADDR_TEMP_SENSOR_CONTROL_LSB 0xBE1 +#define MYKONOS_ADDR_TEMP_SENSOR_CONTROL_MSB 0xBE2 +#define MYKONOS_ADDR_TEMP_SENSOR_READ 0xBE3 +#define MYKONOS_ADDR_TEMP_SENSOR_CONFIG 0xBE4 + +#define MYKONOS_ADDR_DIGITAL_TEST_BYTE_0 0xC40 + +/* ARM subsystem registers */ +#define MYKONOS_ADDR_ARM_CTL_1 0xD00 +#define MYKONOS_ADDR_ARM_CTL_2 0xD01 +#define MYKONOS_ADDR_ARM_ADDR_BYTE_0 0xD02 +#define MYKONOS_ADDR_ARM_ADDR_BYTE_1 0xD03 +#define MYKONOS_ADDR_ARM_DATA_BYTE_0 0xD04 +#define MYKONOS_ADDR_ARM_DATA_BYTE_1 0xD05 +#define MYKONOS_ADDR_ARM_DATA_BYTE_2 0xD06 +#define MYKONOS_ADDR_ARM_DATA_BYTE_3 0xD07 +#define MYKONOS_ADDR_ARM_CLK_CTL 0xD08 +#define MYKONOS_ADDR_AHB_SPI_BRIDGE 0xD09 +#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_0 0xD0A +#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_1 0xD0B +#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_2 0xD0C +#define MYKONOS_ADDR_ARM_BOOT_ADDR_BYTE_3 0xD0D +#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_0 0xD0E +#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_1 0xD0F +#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_2 0xD10 +#define MYKONOS_ADDR_ARM_STACK_PTR_BYTE_3 0xD11 +#define MYKONOS_ADDR_ARM_BRIDGE_CLK_CTL 0xD14 + +/* ARM mailbox registers */ +#define MYKONOS_ADDR_ARM_CMD 0xD30 +#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_1 0xD31 +#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_2 0xD32 +#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_3 0xD33 +#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_4 0xD34 +#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_5 0xD35 +#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_6 0xD36 +#define MYKONOS_ADDR_ARM_EXT_CMD_BYTE_7 0xD37 +#define MYKONOS_ADDR_ARM_CMD_STATUS_0 0xD38 +#define MYKONOS_ADDR_ARM_CMD_STATUS_1 0xD39 +#define MYKONOS_ADDR_ARM_CMD_STATUS_2 0xD3A +#define MYKONOS_ADDR_ARM_CMD_STATUS_3 0xD3B +#define MYKONOS_ADDR_ARM_CMD_STATUS_4 0xD3C +#define MYKONOS_ADDR_ARM_CMD_STATUS_5 0xD3D +#define MYKONOS_ADDR_ARM_CMD_STATUS_6 0xD3E +#define MYKONOS_ADDR_ARM_CMD_STATUS_7 0xD3F + +#define MYKONOS_ADDR_ARM_OPCODE_STATE_0 0xD40 +#define MYKONOS_ADDR_ARM_OPCODE_STATE_1 0xD41 +#define MYKONOS_ADDR_ARM_OPCODE_STATE_2 0xD42 +#define MYKONOS_ADDR_ARM_OPCODE_STATE_3 0xD43 +#define MYKONOS_ADDR_ARM_OPCODE_STATE_4 0xD44 +#define MYKONOS_ADDR_ARM_OPCODE_STATE_5 0xD45 +#define MYKONOS_ADDR_ARM_OPCODE_STATE_6 0xD46 +#define MYKONOS_ADDR_ARM_OPCODE_STATE_7 0xD47 + +/* Mykonos Power-Down Override Control Registers */ +#define MYKONOS_ADDR_TX_PD_OVERRIDE_CONTROL_7_0 0xD89 + +/* Mykonos Observation Framer Registers */ +#define MYKONOS_ADDR_OBS_FRAMER_RESET 0xDC0 +#define MYKONOS_ADDR_OBS_FRAMER_CLK_EN 0xDC1 +#define MYKONOS_ADDR_OBS_FRAMER_ADDR 0xDC2 +#define MYKONOS_ADDR_OBS_FRAMER_DATA 0xDC3 +#define MYKONOS_ADDR_OBS_FRAMER_WRITE_EN 0xDC4 +#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_FIFO_EN 0xDC5 +#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_F 0xDC6 +#define MYKONOS_ADDR_OBS_FRAMER_LANE_CTL 0xDC7 +#define MYKONOS_ADDR_OBS_FRAMER_ADC_XBAR_SEL 0xDC8 +#define MYKONOS_ADDR_OBS_FRAMER_LANE_XBAR_SEL 0xDC9 +#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_LOOPBACK_XBAR_REV 0xDCA +#define MYKONOS_ADDR_OBS_FRAMER_SYNCN_FILT 0xDCB +#define MYKONOS_ADDR_OBS_FRAMER_LMFC_F_OFFSET 0xDCC +#define MYKONOS_ADDR_OBS_FRAMER_LMFC_K_OFFSET 0xDCD +#define MYKONOS_ADDR_OBS_FRAMER_TEST_CNTR_CTL 0xDCE +#define MYKONOS_ADDR_OBS_FRAMER_STATUS_STRB 0xDCF +#define MYKONOS_ADDR_OBS_FRAMER_STATUS 0xDD0 +#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_TO_LMFC_CNTR_STAT 0xDD1 +#define MYKONOS_ADDR_OBS_FRAMER_SYSREF_TO_LMFC_ERR_MARGIN 0xDD2 +#define MYKONOS_ADDR_OBS_FRAMER_LANE_FIFO_STRB 0xDD3 +#define MYKONOS_ADDR_OBS_FRAMER_LANE0_FIFO_RDWR_ADDR 0xDD4 +#define MYKONOS_ADDR_OBS_FRAMER_LANE1_FIFO_RDWR_ADDR 0xDD5 +#define MYKONOS_ADDR_OBS_FRAMER_LANE2_FIFO_RDWR_ADDR 0xDD6 +#define MYKONOS_ADDR_OBS_FRAMER_LANE3_FIFO_RDWR_ADDR 0xDD7 +#define MYKONOS_ADDR_OBS_FRAMER_PRBS10_CTL 0xDD8 +#define MYKONOS_ADDR_OBS_FRAMER_PRBS20_CTL 0xDD9 +#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_EN 0xDDA +#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_7_TO_0 0xDDB +#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_15_TO_8 0xDDC +#define MYKONOS_ADDR_OBS_FRAMER_PATTERN_GEN_19_TO_16 0xDDD +#define MYKONOS_ADDR_OBS_FRAMER_CONFIG_JTX_GEN 0xDDE +#define MYKONOS_ADDR_OBS_FRAMER_LANE_DATA_CTL 0xDDF +#define MYKONOS_ADDR_OBS_FRAMER_DATA_SAMPLE_CTL 0xDE0 + +#define MYKONOS_ADDR_PFIR_COEFF_CTL 0xDFF +#define MYKONOS_ADDR_PFIR_COEFF_DATA 0xE00 +#define MYKONOS_ADDR_PFIR_COEFF_ADDR 0xE01 + +/* ARM memory */ +#define MYKONOS_ADDR_ARM_START_PROG_ADDR 0x01000000 +#define MYKONOS_ADDR_ARM_END_PROG_ADDR 0x01017FFF +#define MYKONOS_ADDR_ARM_START_DATA_ADDR 0x20000000 +#define MYKONOS_ADDR_ARM_END_DATA_ADDR 0x2000FFFF +#define MYKONOS_ADDR_ARM_BUILD_CHKSUM_ADDR 0x01017FE0 +#define MYKONOS_ADDR_ARM_CALC_CHKSUM_ADDR 0x01017FE4 +#define MYKONOS_ADDR_ARM_VERSION 0x01000128 +#define MYKONOS_ARM_ABORT_OPCODE 0x00 +#define MYKONOS_ARM_RUNINIT_OPCODE 0x02 +#define MYKONOS_ARM_RADIOON_OPCODE 0x04 +#define MYKONOS_ARM_WRITECFG_OPCODE 0x06 +#define MYKONOS_ARM_READCFG_OPCODE 0x08 +#define MYKONOS_ARM_SET_OPCODE 0x0A +#define MYKONOS_ARM_GET_OPCODE 0x0C + +#define MYKONOS_ARM_OBJECTID_DPDINIT_CONFIG 0x0F +#define MYKONOS_ARM_OBJECTID_CLGCINIT_CONFIG 0x10 +#define MYKONOS_ARM_OBJECTID_VSWRINIT_CONFIG 0x11 +#define MYKONOS_ARM_OBJECTID_DPDCONFIG 0x24 +#define MYKONOS_ARM_DPD_RESET 0x02 +#define MYKONOS_ARM_OBJECTID_GS_TRACKCALS 0x66 +#define MYKONOS_ARM_OBJECTID_RXQEC_TRACKING 0x20 +#define MYKONOS_ARM_OBJECTID_ORXQEC_TRACKING 0x21 +#define MYKONOS_ARM_OBJECTID_TXLOL_TRACKING 0x22 +#define MYKONOS_ARM_OBJECTID_TXQEC_TRACKING 0x23 +#define MYKONOS_ARM_OBJECTID_CLGCCONFIG 0x25 +#define MYKONOS_ARM_OBJECTID_VSWRCONFIG 0x26 +#define MYKONOS_ARM_OBJECTID_CAL_STATUS 0x42 +#define MYKONOS_ARM_OBJECTID_INIT_CAL_DONE 0x43 +#define MYKONOS_ARM_OBJECTID_ORX_MODE 0x61 +#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_SUSPEND_RESUME 0x65 +#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_CONTROL 0x66 +#define MYKONOS_ARM_OBJECTID_TRACKING_CAL_PENDING 0x67 +#define MYKONOS_ARM_OBJECTID_RADIO_CONTROL 0x81 +#define MYKONOS_ARM_OBJECTID_CALSCHEDULER 0x83 + +#define MYKONOS_ARM_SYSTEMSTATE_POWERUP 0x00 +#define MYKONOS_ARM_SYSTEMSTATE_READY 0x01 +#define MYKONOS_ARM_SYSTEMSTATE_IDLE 0x02 +#define MYKONOS_ARM_SYSTEMSTATE_RADIO_ON 0x03 + +#define ORX_TRIGGER_SIGNALID 0x00 +#define ORX_MODE_0_SIGNALID 0x01 +#define ORX_MODE_1_SIGNALID 0x02 +#define ORX_MODE_2_SIGNALID 0x03 +#define RX1_ENABLE_ACK_SIGNALID 0x04 +#define RX2_ENABLE_ACK_SIGNALID 0x05 +#define TX1_ENABLE_ACK_SIGNALID 0x06 +#define TX2_ENABLE_ACK_SIGNALID 0x07 +#define ORX1_ENABLE_ACK_SIGNALID 0x08 +#define ORX2_ENABLE_ACK_SIGNALID 0x09 +#define SRX_ENABLE_ACK_SIGNALID 0x0A +#define TX_OBS_SELECT_SIGNALID 0x0B + +#define DISABLE_DPD_ACTUATOR 0x03 +#define ENABLE_DPD_ACTUATOR 0x04 +#define SET_CLGC_DESIRED_GAIN_1 0x05 +#define SET_CLGC_DESIRED_GAIN_2 0x06 +#define SET_PATH_DELAY 0x08 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_user.c b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_user.c new file mode 100644 index 00000000..5cedb579 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_user.c @@ -0,0 +1,176 @@ +/** + * \file mykonos_user.c + * \brief Contains Mykonos default gain table values for Rx, ObsRx, and SnRx + * + * Mykonos API version: 1.5.2.3566 + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#include +#include "t_mykonos.h" +#include "mykonos_user.h" + +/** + * \brief Default Rx gain table settings + */ +uint8_t RxGainTable [61][4] = +{ + /* Order: {FE table, External Ctl, Digital Gain/Atten, Enable Atten} */ + {0, 0, 0, 0}, /* Gain index 255 */ + {3, 0, 2, 1}, /* Gain index 254 */ + {6, 0, 3, 1}, /* Gain index 253 */ + {10, 0, 0, 0}, /* Gain index 252 */ + {13, 0, 1, 1}, /* Gain index 251 */ + {16, 0, 0, 0}, /* Gain index 250 */ + {18, 0, 3, 1}, /* Gain index 249 */ + {21, 0, 1, 1}, /* Gain index 248 */ + {23, 0, 3, 1}, /* Gain index 247 */ + {25, 0, 4, 1}, /* Gain index 246 */ + {28, 0, 0, 0}, /* Gain index 245 */ + {30, 0, 0, 0}, /* Gain index 244 */ + {31, 0, 5, 1}, /* Gain index 243 */ + {33, 0, 4, 1}, /* Gain index 242 */ + {35, 0, 2, 1}, /* Gain index 241 */ + {37, 0, 0, 0}, /* Gain index 240 */ + {38, 0, 4, 1}, /* Gain index 239 */ + {39, 0, 7, 1}, /* Gain index 238 */ + {41, 0, 2, 1}, /* Gain index 237 */ + {42, 0, 4, 1}, /* Gain index 236 */ + {43, 0, 6, 1}, /* Gain index 235 */ + {44, 0, 8, 1}, /* Gain index 234 */ + {45, 0, 9, 1}, /* Gain index 233 */ + {46, 0, 10, 1}, /* Gain index 232 */ + {47, 0, 10, 1}, /* Gain index 231 */ + {48, 0, 9, 1}, /* Gain index 230 */ + {49, 0, 8, 1}, /* Gain index 229 */ + {50, 0, 6, 1}, /* Gain index 228 */ + {51, 0, 3, 1}, /* Gain index 227 */ + {51, 0, 13, 1}, /* Gain index 226 */ + {52, 0, 9, 1}, /* Gain index 225 */ + {53, 0, 5, 1}, /* Gain index 224 */ + {53, 0, 15, 1}, /* Gain index 223 */ + {54, 0, 9, 1}, /* Gain index 222 */ + {54, 0, 19, 1}, /* Gain index 221 */ + {55, 0, 11, 1}, /* Gain index 220 */ + {55, 0, 21, 1}, /* Gain index 219 */ + {56, 0, 11, 1}, /* Gain index 218 */ + {56, 0, 21, 1}, /* Gain index 217 */ + {57, 0, 9, 1}, /* Gain index 216 */ + {57, 0, 19, 1}, /* Gain index 215 */ + {57, 0, 29, 1}, /* Gain index 214 */ + {58, 0, 12, 1}, /* Gain index 213 */ + {58, 0, 22, 1}, /* Gain index 212 */ + {58, 0, 32, 1}, /* Gain index 211 */ + {59, 0, 11, 1}, /* Gain index 210 */ + {59, 0, 21, 1}, /* Gain index 209 */ + {59, 0, 31, 1}, /* Gain index 208 */ + {59, 0, 41, 1}, /* Gain index 207 */ + {60, 0, 13, 1}, /* Gain index 206 */ + {60, 0, 23, 1}, /* Gain index 205 */ + {60, 0, 33, 1}, /* Gain index 204 */ + {60, 0, 43, 1}, /* Gain index 203 */ + {60, 0, 53, 1}, /* Gain index 202 */ + {61, 0, 14, 1}, /* Gain index 201 */ + {61, 0, 24, 1}, /* Gain index 200 */ + {61, 0, 34, 1}, /* Gain index 199 */ + {61, 0, 44, 1}, /* Gain index 198 */ + {61, 0, 54, 1}, /* Gain index 197 */ + {61, 0, 64, 1}, /* Gain index 196 */ + {61, 0, 74, 1}, /* Gain index 195 */ +}; + +/** + * \brief Default ORx gain table settings + */ +uint8_t ORxGainTable [19][4] = +{ + /* Order: {FE table, External Ctl, Digital Gain/Atten, Enable Atten} */ + {0, 0, 0, 0}, /* Gain index 255 */ + {7, 0, 0, 0}, /* Gain index 254 */ + {13, 0, 1, 1}, /* Gain index 253 */ + {18, 0, 3, 1}, /* Gain index 252 */ + {23, 0, 3, 1}, /* Gain index 251 */ + {28, 0, 0, 0}, /* Gain index 250 */ + {32, 0, 0, 0}, /* Gain index 249 */ + {35, 0, 2, 1}, /* Gain index 248 */ + {38, 0, 4, 1}, /* Gain index 247 */ + {41, 0, 2, 1}, /* Gain index 246 */ + {43, 0, 6, 1}, /* Gain index 245 */ + {46, 0, 0, 0}, /* Gain index 244 */ + {47, 0, 10, 1}, /* Gain index 243 */ + {49, 0, 8, 1}, /* Gain index 242 */ + {51, 0, 3, 1}, /* Gain index 241 */ + {52, 0, 9, 1}, /* Gain index 240 */ + {53, 0, 14, 1}, /* Gain index 239 */ + {54, 0, 18, 1}, /* Gain index 238 */ + {56, 0, 0, 0} /* Gain index 237 */ + +}; + +/** + * \brief Default SnRx gain table settings + */ +uint8_t SnRxGainTable [53][4] = +{ + /* Order: {FE table, LNA Bypass, Digital Gain/Atten, Enable Atten} */ + {0, 0, 0, 0}, /* Gain index 255 */ + {1, 0, 7, 1}, /* Gain index 254 */ + {3, 0, 1, 0}, /* Gain index 253 */ + {3, 0, 15, 1}, /* Gain index 252 */ + {5, 0, 0, 0}, /* Gain index 251 */ + {6, 0, 2, 1}, /* Gain index 250 */ + {7, 0, 2, 1}, /* Gain index 249 */ + {8, 0, 12, 1}, /* Gain index 248 */ + {9, 0, 7, 1}, /* Gain index 247 */ + {11, 0, 1, 0}, /* Gain index 246 */ + {11, 0, 15, 1},/* Gain index 245 */ + {13, 0, 1, 0}, /* Gain index 244 */ + {14, 0, 2, 0}, /* Gain index 243 */ + {14, 0, 10, 1},/* Gain index 242 */ + {15, 0, 0, 0}, /* Gain index 241 */ + {15, 0, 20, 1},/* Gain index 240 */ + {16, 0, 2, 1}, /* Gain index 239 */ + {16, 0, 22, 1},/* Gain index 238 */ + {17, 0, 1, 0}, /* Gain index 237 */ + {17, 0, 15, 1},/* Gain index 236 */ + {17, 0, 35, 1},/* Gain index 235 */ + {17, 0, 55, 1},/* Gain index 234 */ + {18, 0, 7, 1}, /* Gain index 233 */ + {18, 0, 27, 1},/* Gain index 232 */ + { 6, 1, 7, 1}, /* Gain index 231 */ + { 7, 1, 7, 1}, /* Gain index 230 */ + { 8, 1, 17, 1}, /* Gain index 229 */ + { 9, 1, 12, 1}, /* Gain index 228 */ + {11, 1, 0, 0}, /* Gain index 227 */ + {12, 1, 3, 1}, /* Gain index 226 */ + {13, 1, 0, 0}, /* Gain index 225 */ + {14, 1, 1, 0}, /* Gain index 224 */ + {14, 1, 15, 1},/* Gain index 223 */ + {15, 1, 5, 1}, /* Gain index 222 */ + {15, 1, 25, 1},/* Gain index 221 */ + {16, 1, 7, 1}, /* Gain index 220 */ + {16, 1, 27, 1},/* Gain index 219 */ + {17, 1, 0, 0}, /* Gain index 218 */ + {17, 1, 20, 1},/* Gain index 217 */ + {17, 1, 40, 1},/* Gain index 216 */ + {17, 1, 60, 1},/* Gain index 215 */ + {18, 1, 12, 1},/* Gain index 214 */ + {18, 1, 32, 1},/* Gain index 213 */ + {18, 1, 52, 1},/* Gain index 212 */ + {18, 1, 72, 1},/* Gain index 211 */ + {18, 1, 92, 1},/* Gain index 210 */ + {19, 1, 1, 0}, /* Gain index 209 */ + {19, 1, 15, 1},/* Gain index 208 */ + {19, 1, 35, 1},/* Gain index 207 */ + {19, 1, 55, 1},/* Gain index 206 */ + {19, 1, 75, 1},/* Gain index 205 */ + {19, 1, 95, 1},/* Gain index 204 */ + {19, 1, 115, 1}/* Gain index 203 */ +}; + diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_user.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_user.h new file mode 100644 index 00000000..2875837b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_user.h @@ -0,0 +1,85 @@ +/** + * \file mykonos_user.h + * + * \brief Contains macro definitions and global structure declarations for mykonos_user.c + * + * Mykonos API version: 1.5.2.3566 + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#ifndef _MYKONOSPROFILES_H_ +#define _MYKONOSPROFILES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* turns verbose messaging on */ +#define MYKONOS_VERBOSE 1 +#define MYK_ENABLE_SPIWRITEARRAY 1 + +/* 3 Bytes per SPI transaction * 341 transactions = ~1024 byte buffer size */ +/* Minimum MYK_SPIWRITEARRAY_BUFFERSIZE = 27 */ +#define MYK_SPIWRITEARRAY_BUFFERSIZE 341 +/* + ***************************************** + * Rx, ObsRx, and Sniffer gain tables + ****************************************** + */ +#define MAX_GAIN_TABLE_INDEX 255 + +#define START_RX_GAIN_INDEX 255 +#define MAX_RX_GAIN_TABLE_NUMINDEXES (START_RX_GAIN_INDEX + 1) +#define MIN_RX_GAIN_TABLE_INDEX 0 + +#define START_ORX_GAIN_INDEX 47 +#define MAX_ORX_GAIN_TABLE_NUMINDEXES (START_ORX_GAIN_INDEX + 1) +#define MIN_ORX_GAIN_TABLE_INDEX (MAX_GAIN_TABLE_INDEX - START_ORX_GAIN_INDEX) + +#define START_SNRX_GAIN_INDEX 127 +#define MAX_SNRX_GAIN_TABLE_NUMINDEXES (START_SNRX_GAIN_INDEX + 1) +#define MIN_SNRX_GAIN_TABLE_INDEX (MAX_GAIN_TABLE_INDEX - START_SNRX_GAIN_INDEX) + +#define START_LOOPBACK_GAIN_INDEX 47 +#define MAX_LOOPBACK_GAIN_TABLE_NUMINDEXES (START_LOOPBACK_GAIN_INDEX + 1) +#define MIN_LOOPBACK_GAIN_TABLE_INDEX (MAX_GAIN_TABLE_INDEX - START_SNRX_GAIN_INDEX) + +extern uint8_t RxGainTable [61][4]; +extern uint8_t ORxGainTable [19][4]; +extern uint8_t SnRxGainTable [53][4]; + + +/* + ******************************************** + * Rx, Sniffer, ObsRx and Tx Profiles limits + ******************************************** + */ +#define MIN_RX_IQRATE_KHZ 15000 /*!< Mykonos minimum IQ rate for the Rx channel, expressed in KHz */ +#define MAX_RX_IQRATE_KHZ 320000 /*!< Mykonos maximum IQ rate for the Rx channel, expressed in KHz */ + +#define MIN_TX_IQRATE_KHZ 15000 /*!< Mykonos minimum IQ rate for the Tx channel, expressed in KHz */ +#define MAX_TX_IQRATE_KHZ 492000 /*!< Mykonos maximum IQ rate for the Tx channel, expressed in KHz */ + +#define MIN_SNIFFER_RFBW_HZ 5000000 /*!< Mykonos minimum Sniffer channel bandwidth expressed in Hz */ +#define MAX_SNIFFER_RFBW_HZ 20000000 /*!< Mykonos maximum Sniffer channel bandwidth expressed in Hz */ + +#define MIN_ORX_RFBW_HZ 5000000 /*!< Mykonos minimum Observation channel bandwidth expressed in Hz */ +#define MAX_ORX_RFBW_HZ 250000000 /*!< Mykonos maximum Observation channel bandwidth expressed in Hz */ + +#define MIN_RX_RFBW_HZ 5000000 /*!< Mykonos minimum Rx channel bandwidth expressed in Hz */ +#define MAX_RX_RFBW_HZ 100000000 /*!< Mykonos maximum Rx channel bandwidth expressed in Hz */ + +#define MIN_TX_RFBW_HZ 20000000 /*!< Mykonos minimum Tx channel bandwidth expressed in Hz */ +#define MAX_TX_RFBW_HZ 250000000 /*!< Mykonos maximum Tx channel bandwidth expressed in Hz */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_version.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_version.h new file mode 100644 index 00000000..c7f58d22 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/mykonos_version.h @@ -0,0 +1,31 @@ +/** + * \file mykonos_version.h + * \brief Contains the version number for the Mykonos API + * + * Mykonos API version: 1.5.2.3566 + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in * this zip file. +* +*/ + +#ifndef MYKONOS_VERSION_H_ +#define MYKONOS_VERSION_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define MYKONOS_CURRENT_SI_VERSION 1 /*!< Mykonos current silicon version */ +#define MYKONOS_CURRENT_MAJOR_VERSION 5 /*!< Mykonos current ARM major version */ +#define MYKONOS_CURRENT_MINOR_VERSION 2 /*!< Mykonos current ARM minor version */ +#define MYKONOS_CURRENT_BUILD_VERSION 3566 /*!< Mykonos current API build version */ + +#ifdef __cplusplus +} +#endif + +#endif /* MYKONOS_VERSION_H_ */ diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/t_ad9528.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/t_ad9528.h new file mode 100644 index 00000000..02cd2781 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/t_ad9528.h @@ -0,0 +1,194 @@ +/** + * \file t_ad9528.h + * \brief Contains enum and structure data types for all AD9528 function calls + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#ifndef _AD9528_TYPES_H_ +#define _AD9528_TYPES_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "../common.h" + +/* AD9528 SPI Address defines */ +#define AD9528_ADDR_ADI_SPI_CONFIG_A 0x000 +#define AD9528_ADDR_ADI_SPI_CONFIG_B 0x001 +#define AD9528_ADDR_IO_UPDATE 0x00F + +#define AD9528_ADDR_REF_A_DIVIDER_LSB 0x100 +#define AD9528_ADDR_REF_A_DIVIDER_MSB 0x101 +#define AD9528_ADDR_REF_B_DIVIDER_LSB 0x102 +#define AD9528_ADDR_REF_B_DIVIDER_MSB 0x103 +#define AD9528_ADDR_PLL1_N_DIV_LSB 0x104 +#define AD9528_ADDR_PLL1_N_DIV_MSB 0x105 +#define AD9528_ADDR_PLL1_CHARGEPUMP 0x106 +#define AD9528_ADDR_PLL1_CP_CTRL2 0x107 +#define AD9528_ADDR_INPUT_RECEIVERS1 0x108 +#define AD9528_ADDR_INPUT_RECEIVERS2 0x109 +#define AD9528_ADDR_INPUT_RECEIVERS3 0x10A +#define AD9528_ADDR_PLL1_FASTLOCK 0x10B + +#define AD9528_ADDR_PLL2_CHARGEPUMP 0x200 +#define AD9528_ADDR_PLL2_N_DIV 0x201 +#define AD9528_ADDR_PLL2_CTRL 0x202 +#define AD9528_ADDR_PLL2_VCO_CTRL 0x203 +#define AD9528_ADDR_PLL2_VCO_DIV 0x204 +#define AD9528_ADDR_PLL2_LF_CTRL1 0x205 +#define AD9528_ADDR_PLL2_LF_CTRL2 0x206 +#define AD9528_ADDR_PLL2_RDIV 0x207 +#define AD9528_ADDR_PLL2_REPLICA_CHDIV 0x208 +#define AD9528_ADDR_PLL2_REPLICA_DIV_PHASE 0x209 + +#define AD9528_ADDR_CH_OUT0_CTRL1 0x300 +#define AD9528_ADDR_CH_OUT0_CTRL2 0x301 +#define AD9528_ADDR_CH_OUT0_CHDIV 0x302 +#define AD9528_ADDR_OUTPUT_SYNC 0x32A +#define AD9528_ADDR_MASK_SYNC1 0x32B +#define AD9528_ADDR_MASK_SYNC2 0x32C +#define AD9528_ADDR_EN_OUTPUT_PATH_SEL1 0x32D +#define AD9528_ADDR_EN_OUTPUT_PATH_SEL2 0x32E + +#define AD9528_ADDR_SYSERF_DIV_LSB 0x400 +#define AD9528_ADDR_SYSERF_DIV_MSB 0x401 +#define AD9528_ADDR_SYSREF_CTRL3 0x402 +#define AD9528_ADDR_SYSREF_CTRL4 0x403 +#define AD9528_ADDR_SYSREF_CTRL5 0x404 + +#define AD9528_ADDR_POWERDOWN_CTRL 0x500 +#define AD9528_ADDR_CH_POWERDOWN1 0x501 +#define AD9528_ADDR_CH_POWERDOWN2 0x502 +#define AD9528_ADDR_LDO_ENABLES1 0x503 +#define AD9528_ADDR_LDO_ENABLES2 0x504 +#define AD9528_ADDR_STATUS0_CTRL 0x505 +#define AD9528_ADDR_STATUS1_CTRL 0x506 +#define AD9528_ADDR_STATUS_OE 0x507 +#define AD9528_ADDR_STATUS_READBACK0 0x508 +#define AD9528_ADDR_STATUS_READBACK1 0x509 + + + +///Enum to select what source outputs from each AD9528 output channel +typedef enum +{ + CHANNEL_DIV = 0, PLL1_OUTPUT = 1, //VCXO frequency + SYSREF = 2, + INV_PLL1_OUTPUT = 5 //VCXO inverted +} ad9528outSourceSel_t; + +///Enum to select what output buffer standard is used for the clock outputs +typedef enum +{ + LVDS = 0, LVDS_BOOST = 1, HSTL = 2 +} ad9528outBufferControl_t; + +///Enum to select the clock input buffer mode. +typedef enum +{ + DISABLED = 0, SINGLE_ENDED, NEG_SINGLE_ENDED, DIFFERENTIAL +} ad9528RefBuffer_t; + +/// Structure to hold AD9528 PLL1 settings +typedef struct +{ + uint32_t refA_Frequency_Hz; + uint16_t refA_Divider; + ad9528RefBuffer_t refA_bufferCtrl; + + uint32_t refB_Frequency_Hz; + uint16_t refB_Divider; + ad9528RefBuffer_t refB_bufferCtrl; + + uint32_t vcxo_Frequency_Hz; + ad9528RefBuffer_t vcxoBufferCtrl; + + uint16_t nDivider; + uint8_t bypassPll1; +} ad9528pll1Settings_t; + +/// Structure to hold AD9528 PLL2 settings +typedef struct +{ + uint8_t rfDivider; //VCO divider: Valid range (3,4,5) + uint8_t n2Divider; //PLL2 N2 Divider + uint8_t totalNdiv; //NDiv = 4*Bdiv + Adiv //Bdiv valid range (3 to 63), Adiv valid range (0-3) +} ad9528pll2Settings_t; + +/// Structure to hold AD9528 Output Clock settings +typedef struct +{ + uint16_t outPowerDown; //bit per output, if 1 power down that output. + ad9528outSourceSel_t outSource[14]; //CHANNEL_DIV, PLL1_OUTPUT, SYSREF, INV_PLL1_OUTPUT + ad9528outBufferControl_t outBufferCtrl[14]; //LVDS, LVDS_BOOST, HSTL + uint8_t outAnalogDelay[14]; //5 bits + uint8_t outDigitalDelay[14]; //6 bits, 1/2 clock resolution @ channel div input frequency + uint8_t outChannelDiv[14]; //8 bit channel divider + uint32_t outFrequency_Hz[14]; //output clock frequency per clock output +} ad9528outputSettings_t; + +///Enum to select the SYSREF output source +typedef enum +{ + EXTERNAL = 0, EXT_RESAMPLED = 1, INTERNAL = 2 +} sysrefSourceSelection_t; + +///Enum to choose the SYSREF pattern mode. +typedef enum +{ + NSHOT = 0, CONTINUOUS = 1, PRBS = 2, STOP = 3 +} sysrefPatternMode_t; + +///Enum to select the SYSREF input pin mode. +typedef enum +{ + LEVEL_ACTIVE_HIGH = 0, LEVEL_ACTIVE_LOW = 1, RISING_EDGE = 2, FALLING_EDGE = 3 +} sysrefPinEdgeMode_t; + +///Enum to select the SYSREF output # of pulses for NSHOT mode. +typedef enum +{ + ONE_PULSE = 0, TWO_PULSES = 2, FOUR_PULSES = 3, SIX_PULSES = 4, EIGHT_PULSES = 5 +} sysrefNshotMode_t; + +//Enum to select how a SYSREF is requested. +typedef enum +{ + SPI = 0, PIN = 1 +} sysrefRequestMethod_t; + +/// Structure to hold AD9528 SYSREF output settings +typedef struct +{ + sysrefRequestMethod_t sysrefRequestMethod; + sysrefSourceSelection_t sysrefSource; + sysrefPinEdgeMode_t sysrefPinEdgeMode; + ad9528RefBuffer_t sysrefPinBufferMode; + sysrefPatternMode_t sysrefPatternMode; + sysrefNshotMode_t sysrefNshotMode; + uint16_t sysrefDivide; + +} ad9528sysrefSettings_t; + +/// Structure to hold AD9528 settings +typedef struct +{ + spiSettings_t *spiSettings; + ad9528pll1Settings_t *pll1Settings; + ad9528pll2Settings_t *pll2Settings; + ad9528outputSettings_t *outputSettings; + ad9528sysrefSettings_t *sysrefSettings; +} ad9528Device_t; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/t_mykonos.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/t_mykonos.h new file mode 100644 index 00000000..66db0d7b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/t_mykonos.h @@ -0,0 +1,1710 @@ +/*! + * \file t_mykonos.h + * \brief Contains type definitions for Mykonos API + * + * Mykonos API version: 1.5.2.3566 + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#ifndef _T_MYKONOS_LIB_H_ +#define _T_MYKONOS_LIB_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "../common.h" + + +/** + * \brief Enum of unique error codes from the Mykonos API functions. + * Each error condition in the library should get its own enum value to allow + * easy debug of errors. + */ +typedef enum +{ + MYKONOS_ERR_OK=0, + MYKONOS_ERR_HAL_LAYER, + MYKONOS_ERR_INV_PARM, + MYKONOS_ERR_FAILED, + MYKONOS_ERR_WAITFOREVENT_INV_PARM, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT, + MYKONOS_ERR_SETENSM_INVALID_NEWSTATE_WAIT, + MYKONOS_ERR_SETENSM_INVALID_NEWSTATE_ALERT, + MYKONOS_ERR_SETENSM_INVALID_NEWSTATE_TXRX, + MYKONOS_ERR_SETENSM_INVALIDSTATE, + MYKONOS_ERR_PU_RXPATH_INV_PARAM, + MYKONOS_ERR_PU_TXPATH_INV_PARAM, + MYKONOS_ERR_PU_OBSRXPATH_INV_PARAM, + MYKONOS_ERR_INIT_INV_ORXCHAN, + MYKONOS_ERR_INIT_INV_RXSYNCB_ORXSYNCB_MODE, + MYKONOS_ERR_INIT_INV_TXFIR_INTERPOLATION, + MYKONOS_ERR_INIT_INV_TXHB2_INTERPOLATION, + MYKONOS_ERR_INIT_INV_TXHB1_INTERPOLATION, + MYKONOS_ERR_INIT_INV_RXFIR_DECIMATION, + MYKONOS_ERR_INIT_INV_RXDEC5_DECIMATION, + MYKONOS_ERR_INIT_INV_RXHB1_DECIMATION, + MYKONOS_ERR_INIT_INV_SNIFFER_RHB1, + MYKONOS_ERR_INIT_INV_SNIFFER_RFIR_DEC, + MYKONOS_ERR_INIT_INV_ORX_RHB1, + MYKONOS_ERR_INIT_INV_ORX_RFIR_DEC, + MYKONOS_ERR_INIT_INV_ADCDIV, + MYKONOS_ERR_INIT_INV_DACDIV, + MYKONOS_ERR_INIT_INV_OBSRX_ADCDIV, + MYKONOS_ERR_CLKPLL_INV_HSDIV, + MYKONOS_ERR_CLKPLL_INV_VCODIV, + MYKONOS_ERR_CLKPLL_INV_RXTXPROFILES, + MYKONOS_ERR_SETCLKPLL_INV_VCOINDEX, + MYKONOS_ERR_SETCLKPLL_INV_FRACWORD, + MYKONOS_ERR_SETRFPLL_INV_PLLNAME, + MYKONOS_ERR_SETRFPLL_INV_LO_PARM, + MYKONOS_ERR_INV_SCALEDDEVCLK_PARAM, + MYKONOS_ERR_NULL_DEVICE_PARAM, + MYKONOS_ERR_CALCDEVCLK_NULLPARAM, + MYKONOS_ERR_SETRFPLL_INV_VCOINDEX, + MYKONOS_ERR_SETRFPLL_INV_REFCLK, + MYKONOS_ERR_SETORXGAIN_INV_CHANNEL, + MYKONOS_ERR_SETORXGAIN_INV_GAIN, + MYKONOS_ERR_GETORX1GAIN_INV_POINTER, + MYKONOS_ERR_GETORX2GAIN_INV_POINTER, + MYKONOS_ERR_GETSNIFFGAIN_INV_POINTER, + MYKONOS_ERR_GETOBSRXGAIN_CH_DISABLED, + MYKONOS_ERR_SETTX1ATTEN_INV_PARM, + MYKONOS_ERR_SETTX1ATTEN_INV_STEPSIZE_PARM, + MYKONOS_ERR_SETTX2ATTEN_INV_PARM, + MYKONOS_ERR_SETTX2ATTEN_INV_STEPSIZE_PARM, + MYKONOS_ERR_PROGRAMFIR_INV_NUMTAPS_PARM, + MYKONOS_ERR_PROGRAMFIR_INV_FIRNAME_PARM, + MYKONOS_ERR_RXFIR_INV_GAIN_PARM, + MYKONOS_ERR_OBSRXFIR_INV_GAIN_PARM, + MYKONOS_ERR_SRXFIR_INV_GAIN_PARM, + MYKONOS_ERR_TXFIR_INV_GAIN_PARM, + MYKONOS_ERR_READFIR_NULL_PARM, + MYKONOS_ERR_READFIR_COEFS_NULL, + MYKONOS_ERR_READFIR_INV_FIRNAME_PARM, + MYKONOS_ERR_READFIR_INV_NUMTAPS_PARM, + MYKONOS_ERR_SETRX1GAIN_INV_GAIN_PARM, + MYKONOS_ERR_SETRX2GAIN_INV_GAIN_PARM, + MYKONOS_ERR_INITSER_INV_VCODIV_PARM, + MYKONOS_ERR_INITSER_INV_VCODIV1_HSCLK_PARM, + MYKONOS_ERR_INITSER_INV_VCODIV1P5_HSCLK_PARM, + MYKONOS_ERR_INITDES_INV_VCODIV_PARM, + MYKONOS_ERR_SER_INV_M_PARM, + MYKONOS_ERR_SER_INV_L_PARM, + MYKONOS_ERR_SER_INV_LANERATE_PARM, + MYKONOS_ERR_SER_INV_LANEEN_PARM, + MYKONOS_ERR_SER_INV_AMP_PARM, + MYKONOS_ERR_SER_INV_PREEMP_PARM, + MYKONOS_ERR_SER_INV_LANEPN_PARM, + MYKONOS_ERR_SER_LANE_CONFLICT_PARM, + MYKONOS_ERR_SER_INV_TXSER_DIV_PARM, + MYKONOS_ERR_SER_LANE_RATE_CONFLICT_PARM, + MYKONOS_ERR_SER_INV_REAL_IF_DATA_PARM, + MYKONOS_ERR_HS_AND_LANE_RATE_NOT_INTEGER_MULT, + MYKONOS_ERR_DES_HS_AND_LANE_RATE_NOT_INTEGER_MULT, + MYKONOS_ERR_DESER_INV_M_PARM, + MYKONOS_ERR_DESER_INV_L_PARM, + MYKONOS_ERR_DESER_INV_HSCLK_PARM, + MYKONOS_ERR_DESER_INV_LANERATE_PARM, + MYKONOS_ERR_DESER_INV_LANEEN_PARM, + MYKONOS_ERR_DESER_INV_EQ_PARM, + MYKONOS_ERR_DESER_INV_LANEPN_PARM, + MYKONOS_ERR_FRAMER_INV_M_PARM, + MYKONOS_ERR_FRAMER_INV_BANKID_PARM, + MYKONOS_ERR_FRAMER_INV_LANEID_PARM, + MYKONOS_ERR_FRAMER_INV_K_OFFSET_PARAM, + MYKONOS_ERR_FRAMER_INV_REAL_IF_DATA_PARM, + MYKONOS_ERR_OBSRX_FRAMER_INV_M_PARM, + MYKONOS_ERR_OBSRX_FRAMER_INV_BANKID_PARM, + MYKONOS_ERR_OBSRX_FRAMER_INV_LANEID_PARM, + MYKONOS_ERR_OBSRX_FRAMER_INV_K_OFFSET_PARAM, + MYKONOS_ERR_OBSRX_FRAMER_INV_REAL_IF_DATA_PARM, + MYKONOS_ERR_DEFRAMER_INV_M_PARM, + MYKONOS_ERR_DEFRAMER_INV_BANKID_PARM, + MYKONOS_ERR_ERR_DEFRAMER_INV_LANEID_PARM, + MYKONOS_ERR_DEFRAMER_INV_K_OFFSET_PARAM, + MYKONOS_ERR_DEFRAMER_INV_K_PARAM, + MYKONOS_ERR_DEFRAMER_INV_FK_PARAM, + MYKONOS_ERR_RX_FRAMER_INV_PRBS_POLYORDER_PARAM, + MYKONOS_ERR_OBSRX_FRAMER_INV_PRBS_POLYORDER_PARAM, + MYKONOS_ERR_DEFRAMER_INV_PRBS_ENABLE_PARAM, + MYKONOS_ERR_DEFRAMER_INV_PRBS_POLYORDER_PARAM, + MYKONOS_ERR_DEFRAMER_INV_PRBS_CNTR_SEL_PARAM, + MYKONOS_ERR_INITARM_INV_DATARATE_PARM, + MYKONOS_ERR_INITARM_INV_REGCLK, + MYKONOS_ERR_INITARM_INV_ARMCLK_PARAM, + MYKONOS_ERR_LOADHEX_INV_CHARCOUNT, + MYKONOS_ERR_LOADHEX_INVALID_FIRSTCHAR, + MYKONOS_ERR_LOADHEX_INVALID_CHKSUM, + MYKONOS_ERR_LOADBIN_INVALID_BYTECOUNT, + MYKONOS_ERR_ARM_INVALID_BUILDCHKSUM, + MYKONOS_ERR_READARMMEM_INV_ADDR_PARM, + MYKONOS_ERR_WRITEARMMEM_INV_ADDR_PARM, + MYKONOS_ERR_ARMCMD_INV_OPCODE_PARM, + MYKONOS_ERR_ARMCMD_INV_NUMBYTES_PARM, + MYKONOS_ERR_ARMCMDSTATUS_INV_OPCODE_PARM, + MYKONOS_ERR_CHECKDEVSTRUCT_SPI, + MYKONOS_ERR_CHECKDEVSTRUCT_RX, + MYKONOS_ERR_CHECKDEVSTRUCT_RXSUB, + MYKONOS_ERR_CHECKDEVSTRUCT_RXFIR, + MYKONOS_ERR_CHECKDEVSTRUCT_TX, + MYKONOS_ERR_CHECKDEVSTRUCT_TXSUB, + MYKONOS_ERR_CHECKDEVSTRUCT_TXFIR, + MYKONOS_ERR_CHECKDEVSTRUCT_OBSRX, + MYKONOS_ERR_CHECKDEVSTRUCT_OBSRXSUB, + MYKONOS_ERR_CHECKDEVSTRUCT_SNIFFERFIR, + MYKONOS_ERR_CHECKDEVSTRUCT_ORXFIR, + MYKONOS_ERR_CHECKDEVSTRUCT_ORXGAINCTRL, + MYKONOS_ERR_CHECKDEVSTRUCT_SNIFFERGAINCTRL, + MYKONOS_ERR_CHECKDEVSTRUCT_OBSRXFRAMER, + MYKONOS_ERR_INITSER_INV_PROFILE, + MYKONOS_ERR_INITDES_INV_TXPROFILE, + MYKONOS_ERR_JESD204B_ILAS_MISMATCH, + MYKONOS_ERR_RXGAINTABLE_INV_CHANNEL, + MYKONOS_ERR_RXGAINTABLE_INV_GAIN_INDEX_RANGE, + MYKONOS_ERR_WRITE_CFG_MEMORY_FAILED, + MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM, + MYKONOS_ERR_RXFRAMER_INV_FK_PARAM, + MYKONOS_ERR_OBSRXFRAMER_INV_FK_PARAM, + MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM, + MYKONOS_ERR_PU_OBSRXPATH_INV_LOSOURCE_PARAM, + MYKONOS_ERR_ARM_RADIOON_FAILED, + MYKONOS_ERR_INV_RX_GAIN_MODE_PARM, + MYKONOS_ERR_INV_ORX_GAIN_MODE_PARM, + MYKONOS_ERR_INV_AGC_RX_STRUCT_INIT, + MYKONOS_ERR_INV_AGC_RX_APD_THRESH_DIFF_VS_ATTACK_GAIN_STEP, + MYKONOS_ERR_INV_AGC_RX_PEAK_WAIT_TIME_PARM, + MYKONOS_ERR_INV_AGC_RX_GAIN_UPDATE_TIME_PARM, + MYKONOS_ERR_INV_AGC_RX_APD_HIGH_THRESH_PARM, + MYKONOS_ERR_INV_AGC_RX_APD_LOW_THRESH_PARM, + MYKONOS_ERR_INV_AGC_RX_BLOCK_DET_DECAY_PARM, + MYKONOS_ERR_INV_AGC_RX_APD_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_RX_HB2_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_RX_RECOVERY_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_PMD_MEAS_CONFIG, + MYKONOS_ERR_INV_AGC_PMD_MEAS_DURATION, + MYKONOS_ERR_INV_AGC_RX_ENABLE_SYNC_PULSE_GAIN_COUNTER, + MYKONOS_ERR_INV_AGC_RX_LOW_THS_PREV_GAIN_INC, + MYKONOS_ERR_INV_AGC_RX_PEAK_STRUCT_INIT, + MYKONOS_ERR_INV_AGC_RX_PEAK_THRESH_MODE, + MYKONOS_ERR_INV_AGC_RX_PWR_STRUCT_INIT, + MYKONOS_ERR_INV_AGC_RX_RESET_ON_RX_ENABLE, + MYKONOS_ERR_INV_AGC_RX_SLOW_LOOP_SETTLING_DELAY, + MYKONOS_ERR_INV_AGC_RX1_MAX_GAIN_INDEX, + MYKONOS_ERR_INV_AGC_RX1_MIN_GAIN_INDEX, + MYKONOS_ERR_INV_AGC_RX2_MAX_GAIN_INDEX, + MYKONOS_ERR_INV_AGC_RX2_MIN_GAIN_INDEX, + MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_HIGH_THRESH, + MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_THRESH, + MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_THRESH, + MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_THRESH, + MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_LOW_GAIN_STEP, + MYKONOS_ERR_INV_AGC_RX_PMD_LOWER_HIGH_GAIN_STEP, + MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_LOW_GAIN_STEP, + MYKONOS_ERR_INV_AGC_RX_PMD_UPPER_HIGH_GAIN_STEP, + MYKONOS_ERR_INV_AGC_RX_APD_HIGH_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_RX_APD_LOW_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_RX_HB2_HIGH_THRESH_PARM, + MYKONOS_ERR_INV_AGC_RX_HB2_LOW_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_RX_HB2_LOW_THRESH_PARM, + MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_RX_HB2_VERY_LOW_THRESH_PARM, + MYKONOS_ERR_INV_AGC_RX_PKDET_FAST_ATTACK_VALUE, + MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_ENABLE, + MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_DUR_CNT, + MYKONOS_ERR_INV_AGC_RX_HB2_OVLD_THRESH_CNT, + MYKONOS_ERR_INV_AGC_OBSRX_STRUCT_INIT, + MYKONOS_ERR_INV_AGC_OBSRX_APD_THRESH_DIFF_VS_ATTACK_GAIN_STEP, + MYKONOS_ERR_INV_AGC_OBSRX_PEAK_WAIT_TIME_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_GAIN_UPDATE_TIME_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_THRESH_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_THRESH_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_BLOCK_DET_DECAY_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_APD_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_HB2_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_RECOVERY_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_MAX_GAIN_INDEX, + MYKONOS_ERR_INV_AGC_OBSRX_MIN_GAIN_INDEX, + MYKONOS_ERR_INV_AGC_OBSRX_SELECT, + MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_CONFIG, + MYKONOS_ERR_INV_AGC_OBSRX_PMD_MEAS_DURATION, + MYKONOS_ERR_INV_AGC_OBSRX_ENABLE_SYNC_PULSE_GAIN_COUNTER, + MYKONOS_ERR_INV_AGC_OBSRX_LOW_THS_PREV_GAIN_INC, + MYKONOS_ERR_INV_AGC_OBSRX_PEAK_STRUCT_INIT, + MYKONOS_ERR_INV_AGC_OBSRX_PEAK_THRESH_MODE, + MYKONOS_ERR_INV_AGC_OBSRX_PWR_STRUCT_INIT, + MYKONOS_ERR_INV_AGC_OBSRX_RESET_ON_RX_ENABLE, + MYKONOS_ERR_INV_AGC_OBSRX_SLOW_LOOP_SETTLING_DELAY, + MYKONOS_ERR_INV_AGC_OBSRX1_MAX_GAIN_INDEX, + MYKONOS_ERR_INV_AGC_OBSRX1_MIN_GAIN_INDEX, + MYKONOS_ERR_INV_AGC_OBSRX2_MAX_GAIN_INDEX, + MYKONOS_ERR_INV_AGC_OBSRX2_MIN_GAIN_INDEX, + MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_THRESH, + MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_THRESH, + MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_THRESH, + MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_THRESH, + MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_LOW_GAIN_STEP, + MYKONOS_ERR_INV_AGC_OBSRX_PMD_LOWER_HIGH_GAIN_STEP, + MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_LOW_GAIN_STEP, + MYKONOS_ERR_INV_AGC_OBSRX_PMD_UPPER_HIGH_GAIN_STEP, + MYKONOS_ERR_INV_AGC_OBSRX_APD_HIGH_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_APD_LOW_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_HB2_HIGH_THRESH_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_HB2_LOW_THRESH_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_GAIN_STEP_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_HB2_VERY_LOW_THRESH_PARM, + MYKONOS_ERR_INV_AGC_OBSRX_PKDET_FAST_ATTACK_VALUE, + MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_ENABLE, + MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_DUR_CNT, + MYKONOS_ERR_INV_AGC_OBSRX_HB2_OVLD_THRESH_CNT, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_CALPLL_LOCK, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_CLKPLLCP, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_CLKPLL_LOCK, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RXPLLCP, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RXPLL_LOCK, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_TXPLLCP, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_TXPLL_LOCK, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_SNIFFPLLCP, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_SNIFFPLL_LOCK, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RXBBFCALDONE, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_TXBBFCALDONE, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RFDCCALDONE, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_ADCTUNECALDONE, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RX1ADCPROFILE, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RX2ADCPROFILE, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_ORXADCPROFILE, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_RCALDONE, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_ARMBUSY, + MYKONOS_ERR_WAITFOREVENT_TIMEDOUT_INITARMDONE, + MYKONOS_ERR_TIMEDOUT_ARMMAILBOXBUSY, + MYKONOS_ERR_PU_OBSRXPATH_ARMERROR, + MYKONOS_ERR_EN_TRACKING_CALS_ARMSTATE_ERROR, + MYKONOS_ERR_SET_RADIOCTRL_PINS_ARMERROR, + MYKONOS_ERR_EN_TRACKING_CALS_ARMERROR, + MYKONOS_ERR_SETRFPLL_ARMERROR, + MYKONOS_ERR_INIT_INV_TXINPUTHB_PARM, + MYKONOS_ERR_LOAD_ADCPROFILE_INV_VCODIV, + MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_RXREQUIRED, + MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_ORXREQUIRED, + MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_SNRXREQUIRED, + MYKONOS_ERR_SETUP_PA_PROT_INV_AVG_DURATION, + MYKONOS_ERR_SETUP_PA_PROT_INV_STICKY_ENABLE, + MYKONOS_ERR_SETUP_PA_PROT_INV_ATTEN_STEP, + MYKONOS_ERR_SETUP_PA_PROT_INV_ATTEN_ENABLE, + MYKONOS_ERR_SETUP_PA_PROT_INV_POWER_THRESH, + MYKONOS_ERR_SETUP_PA_PROT_INV_TX_CHANNEL, + MYKONOS_ERR_GET_DAC_PWR_INV_POINTER, + MYKONOS_ERR_GET_PA_FLAG_STATUS_INV_POINTER, + MYKONOS_ERR_GET_OBSRX_OVERLOADS_NULL_PARM, + MYKONOS_ERR_GET_RX1_OVERLOADS_NULL_PARM, + MYKONOS_ERR_GET_RX2_OVERLOADS_NULL_PARM, + MYKONOS_ERR_GETRADIOSTATE_NULL_PARAM, + MYKONOS_ERR_ABORT_INITCALS_NULL_PARAM, + MYKONOS_ERR_ARM_RADIOOFF_FAILED, + MYKONOS_ERR_WAIT_INITCALS_NULL_PARAM, + MYKONOS_ERR_WAIT_INITCALS_CALFAILED, + MYKONOS_ERR_WAIT_INITCALS_ARMERROR, + MYKONOS_ERR_CHECK_PLL_LOCK_NULL_PARM, + MYKONOS_ERR_GET_TXFILTEROVRG_NULL_PARM, + MYKONOS_ERR_PROGRAM_RXGAIN_TABLE_NULL_PARM, + MYKONOS_ERR_PROGRAMFIR_NULL_PARM, + MYKONOS_ERR_PROGRAMFIR_COEFS_NULL, + MYKONOS_ERR_READ_DEFRAMERSTATUS_NULL_PARAM, + MYKONOS_ERR_READ_DEFRAMERPRBS_NULL_PARAM, + MYKONOS_ERR_READ_ORXFRAMERSTATUS_NULL_PARAM, + MYKONOS_ERR_READ_RXFRAMERSTATUS_NULL_PARAM, + MYKONOS_ERR_ARMCMDSTATUS_NULL_PARM, + MYKONOS_ERR_READARMCMDSTATUS_INV_OPCODE_PARM, + MYKONOS_ERR_READARMCMDSTATUS_NULL_PARM, + MYKONOS_ERR_READARMCMDSTATUSBYTE_NULL_PARM, + MYKONOS_ERR_ARMCMD_NULL_PARM, + MYKONOS_ERR_WRITEARMMEM_NULL_PARM, + MYKONOS_ERR_LOADBIN_NULL_PARAM, + MYKONOS_ERR_ARM_INV_ADDR_PARM, + MYKONOS_ERR_LOADARMCON_INVALID_BYTECOUNT, + MYKONOS_ERR_LOADARMCON_NULL_PARAM, + MYKONOS_ERR_GETTX1ATTEN_NULL_PARM, + MYKONOS_ERR_GETTX2ATTEN_NULL_PARM, + MYKONOS_ERR_ENFRAMERLINK_INV_LANESEN_PARM, + MYKONOS_ERR_ENOBSFRAMERLINK_INV_LANESEN_PARM, + MYKONOS_ERR_ENTXNCO_TXPROFILE_INVALID, + MYKONOS_ERR_ENTXNCO_TX1_FREQ_INVALID, + MYKONOS_ERR_ENTXNCO_TX2_FREQ_INVALID, + MYKONOS_ERR_JESD204B_ILAS_MISMATCH_NULLPARAM, + MYKONOS_ERR_LOAD_LBADCPROFILE_ARMMEM_FAILED, + MYKONOS_ERR_LOAD_SNRXADCPROFILE_ARMMEM_FAILED, + MYKONOS_ERR_LOAD_ADCPROFILE_SNRX_ADCDIV_ZERO, + MYKONOS_ERR_LOAD_ORXADCPROFILE_ARMMEM_FAILED, + MYKONOS_ERR_LOAD_ADCPROFILE_ORXADCDIV_ZERO, + MYKONOS_ERR_LOAD_RXADCPROFILE_ARMMEM_FAILED, + MYKONOS_ERR_LOAD_ADCPROFILE_RXADCDIV_ZERO, + MYKONOS_ERR_LOAD_ADCPROFILE_CUSTOM_LBREQUIRED, + MYKONOS_ERR_LOAD_ADCPROFILE_MISSING_ORX_PROFILE, + MYKONOS_ERR_GETRFPLL_INV_PLLNAME, + MYKONOS_ERR_GETRFPLL_ARMERROR, + MYKONOS_ERR_GETRFPLL_NULLPARAM, + MYKONOS_ERR_INITARM_INV_VCODIV, + MYKONOS_ERR_GET_PLLFREQ_INV_HSDIV, + MYKONOS_ERR_GET_PLLFREQ_INV_VCODIV, + MYKONOS_ERR_GET_PLLFREQ_INV_REFCLKDIV, + MYKONOS_ERR_SETORXGAIN_INV_ORX1GAIN, + MYKONOS_ERR_SETORXGAIN_INV_ORX2GAIN, + MYKONOS_ERR_SETORXGAIN_INV_SNRXGAIN, + MYKONOS_ERR_GET_RX1_DEC_POWER_NUM_SAMPLES, + MYKONOS_ERR_GET_RX1_DEC_POWER_NULL_PARM, + MYKONOS_ERR_GET_RX2_DEC_POWER_NUM_SAMPLES, + MYKONOS_ERR_GET_RX2_DEC_POWER_NULL_PARM, + MYKONOS_ERR_GET_OBSRX_DEC_POWER_NUM_SAMPLES, + MYKONOS_ERR_GET_OBSRX_DEC_POWER_NULL_PARM, + MYKONOS_ERR_GETARMVER_NULL_PARM, + MYKONOS_ERR_EN_CLGCTRACKING_ARMSTATE_ERROR, + MYKONOS_ERR_EN_DPDTRACKING_ARMSTATE_ERROR, + MYKONOS_ERR_RESTDPDMOD_WRONGBUFFERSIZE, + MYKONOS_ERR_RESTDPDMOD_ARMSTATE, + MYKONOS_ERR_RESTDPDMOD_INVALID_TXCHANNEL, + MYKONOS_ERR_RESTDPDMOD_ARMERRFLAG, + MYKONOS_ERR_SAVDPDMOD_WRONGBUFFERSIZE, + MYKONOS_ERR_SAVDPDMOD_ARMSTATE, + MYKONOS_ERR_SAVDPDMOD_INVALID_TXCHANNEL, + MYKONOS_ERR_SAVDPDMOD_ARMERRFLAG, + MYKONOS_ERR_WRITEARMCFG_ARMERRFLAG, + MYKONOS_ERR_CFGDPD_TXORX_PROFILE_INV, + MYKONOS_ERR_CFGDPD_NULL_DPDCFGSTRUCT, + MYKONOS_ERR_CFGDPD_INV_DPDDAMPING, + MYKONOS_ERR_CFGDPD_INV_DPDSAMPLES, + MYKONOS_ERR_CFGDPD_INV_DPDOUTLIERTHRESH, + MYKONOS_ERR_CFGDPD_INV_DPDPRIORWEIGHT, + MYKONOS_ERR_CFGCLGC_INV_DESIREDGAIN, + MYKONOS_ERR_CFGCLGC_INV_TXATTENLIMIT, + MYKONOS_ERR_CFGCLGC_INV_CLGC_CTRLRATIO, + MYKONOS_ERR_SETCLGCGAIN_INV_DESIREDGAIN, + MYKONOS_ERR_SETCLGCGAIN_INV_TXCHANNEL, + MYKONOS_ERR_SETCLGCGAIN_TRACK_ARMERRFLAG, + MYKONOS_ERR_CFGDPD_INV_DPD_ADDDELAY, + MYKONOS_ERR_CFGDPD_INV_PNSEQLEVEL, + MYKONOS_ERR_READARMCFG_ARMERRFLAG, + MYKONOS_ERR_GETPENDTRKCALS_NULL_PARAM, + MYKONOS_ERR_ARMCMDSTATUS_ARMERROR, + MYKONOS_ERR_WAITARMCMDSTATUS_TIMEOUT, + MYKONOS_ERR_PU_GETOBSRXPATH_ARMERROR, + MYKONOS_ERR_GETDPDCFG_NULL_DPDCFGSTRUCT, + MYKONOS_ERR_GETDPDCFG_TXORX_PROFILE_INV, + MYKONOS_ERR_GETDPDSTATUS_ARMERRFLAG, + MYKONOS_ERR_GETDPDSTATUS_NULLPARAM, + MYKONOS_ERR_SETDEFOBSRXPATH_NULL_OBSRX_STRUCT, + MYKONOS_ERR_SETDEFOBSRXPATH_NULL_DEF_OBSRX_STRUCT, + MYKONOS_ERR_GETCLGCSTATUS_NULLPARAM, + MYKONOS_ERR_GETCLGCSTATUS_ARMERRFLAG, + MYKONOS_ERR_CHECKDEVSTRUCT_NULLDEVPOINTER, + MYKONOS_ERR_READ_DEFFIFODEPTH_NULL_PARAM, + MYKONOS_ERR_READ_DEFFIFODEPTH_LMFCCOUNT_NULL_PARAM, + MYKONOS_ERR_GETDPDSTATUS_INV_CH, + MYKONOS_ERR_GETCLGCSTATUS_INV_CH, + MYKONOS_ERR_INIT_INV_TXINPUTHB_INV_RATE, + MYKONOS_ERR_INIT_INV_TXINPUTHB0_INV_RATE, + MYKONOS_ERR_TXFIR_TAPSEXCEEDED, + MYKONOS_ERR_TXFIR_INV_NUMROWS, + MYKONOS_ERR_TXFIR_INV_NUMTAPS_PARM, + MYKONOS_ERR_RXFIR_TAPSEXCEEDED, + MYKONOS_ERR_ORXFIR_TAPSEXCEEDED, + MYKONOS_ERR_SNRXFIR_TAPSEXCEEDED, + MYKONOS_ERR_GETINITCALSTATUS_NULL_PARAM, + MYKONOS_ERR_GETINITCALSTATUS_ARMERROR, + MYKONOS_ERR_CFGDPD_INV_NUMWEIGHTS, + MYKONOS_ERR_CFGDPD_INV_MODELVERSION, + MYKONOS_ERR_SETDPDACT_INV_TXCHANNEL, + MYKONOS_ERR_SETDPDACT_INV_STATE, + MYKONOS_ERR_SETDPDACT_ARMERRFLAG, + MYKONOS_ERR_CFGCLGC_TXORX_PROFILE_INV, + MYKONOS_ERR_CFGCLGC_NULL_CLGCCFGSTRUCT, + MYKONOS_ERR_GETCLGCCFG_TXORX_PROFILE_INV, + MYKONOS_ERR_GETCLGCCFG_NULL_CFGSTRUCT, + MYKONOS_ERR_CALCDIGCLK_NULLDEV_PARAM, + MYKONOS_ERR_CALCDIGCLK_NULL_CLKSTRUCT, + MYKONOS_ERR_CFGCLGC_INV_CLGC_ADDDELAY, + MYKONOS_ERR_CFGCLGC_INV_PNSEQLEVEL, + MYKONOS_ERR_CFGVSWR_TXORX_PROFILE_INV, + MYKONOS_ERR_CFGVSWR_ARMSTATE_ERROR, + MYKONOS_ERR_CFGVSWR_INV_3P3GPIOPIN, + MYKONOS_ERR_CFGVSWR_INV_PNSEQLEVEL, + MYKONOS_ERR_CFGVSWR_INV_VSWR_ADDDELAY, + MYKONOS_ERR_CFGVSWR_NULL_VSWRCFGSTRUCT, + MYKONOS_ERR_GETVSWRCFG_NULL_CFGSTRUCT, + MYKONOS_ERR_GETVSWRCFG_TXORX_PROFILE_INV, + MYKONOS_ERR_GETVSWRSTATUS_ARMERRFLAG, + MYKONOS_ERR_GETVSWRSTATUS_INV_CH, + MYKONOS_ERR_GETVSWRSTATUS_NULLPARAM, + MYKONOS_ERR_SET_RX_MAX_GAIN_INDEX, + MYKONOS_ERR_SET_RX_MIN_GAIN_INDEX, + MYKONOS_ERR_AGC_MIN_MAX_RX_CHANNEL, + MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX_CHANNEL, + MYKONOS_ERR_SET_ORX_MAX_GAIN_INDEX, + MYKONOS_ERR_SET_ORX_MIN_GAIN_INDEX, + MYKONOS_ERR_AGC_MIN_MAX_ORX_CHANNEL, + MYKONOS_ERR_RX1_TEMP_GAIN_COMP_RANGE, + MYKONOS_ERR_RX2_TEMP_GAIN_COMP_RANGE, + MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_RANGE, + MYKONOS_ERR_RX1_TEMP_GAIN_COMP_STEP, + MYKONOS_ERR_RX2_TEMP_GAIN_COMP_STEP, + MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_STEP, + MYKONOS_ERR_RX1_TEMP_GAIN_COMP_NULL, + MYKONOS_ERR_RX2_TEMP_GAIN_COMP_NULL, + MYKONOS_ERR_OBS_RX_TEMP_GAIN_COMP_NULL, + MYKONOS_ERR_GETTXLOLSTATUS_NULLPARAM, + MYKONOS_ERR_GETTXLOLSTATUS_INV_CH, + MYKONOS_ERR_GETTXLOLSTATUS_ARMERRFLAG, + MYKONOS_ERR_GETTXQECSTATUS_NULLPARAM, + MYKONOS_ERR_GETTXQECSTATUS_INV_CH, + MYKONOS_ERR_GETTXQECSTATUS_ARMERRFLAG, + MYKONOS_ERR_GETRXQECSTATUS_NULLPARAM, + MYKONOS_ERR_GETRXQECSTATUS_INV_CH, + MYKONOS_ERR_GETRXQECSTATUS_ARMERRFLAG, + MYKONOS_ERR_GETORXQECSTATUS_NULLPARAM, + MYKONOS_ERR_GETORXQECSTATUS_INV_CH, + MYKONOS_ERR_GETORXQECSTATUS_ARMERRFLAG, + MYKONOS_ERR_RESCHEDULE_TRACK_CAL_INV, + MYKONOS_ERR_RESCHEDULE_TRACK_ARMERRFLAG, + + MYKONOS_ERR_SETSTATEALL_TRACK_CAL_INV, + MYKONOS_ERR_SETSTATEALL_TRACK_ARMERRFLAG, + + MYKONOS_ERR_GETSTATEALL_TRACK_NULL_PARAM, + MYKONOS_ERR_GETSTATEALL_TRACK_ARMERRFLAG, + MYKONOS_ERR_GETSTATEALL_TRACK_ARMERROR, + + MYKONOS_ERR_SETSTATE_TRACK_CAL_INV, + MYKONOS_ERR_SETSTATE_TRACK_ARMERRFLAG, + + MYKONOS_ERR_GETSTATE_TRACK_NULL_PARAM, + MYKONOS_ERR_GETSTATE_TRACK_ARMERRFLAG, + MYKONOS_ERR_GETSTATE_TRACK_ARMERROR, + + MYKONOS_ERR_ARMSTATE_PROFILE_ERROR, + MYKONOS_ERR_ARMSTATE_CAL_ERROR, + MYKONOS_ERR_ARMSTATE_EXCEPTION, + MYKONOS_ERR_WAITARMCSTATE_TIMEOUT, + + MYKONOS_ERR_GETPRODUCTID_NULL_PARAM, + MYKONOS_ERR_GET_API_VERSION_NULL_PARAM, + + MYKONOS_ERR_PROFILES_HSDIGCLK, + MYKONOS_ERR_RXPROFILE_RXCHANNEL, + MYKONOS_ERR_RXPROFILE_IQRATE, + MYKONOS_ERR_RXPROFILE_RFBW, + MYKONOS_ERR_RXPROFILE_FILTER_DECIMATION, + MYKONOS_ERR_RXPROFILE_FIR_COEFS, + MYKONOS_ERR_RXPROFILE_ADCDIV, + MYKONOS_ERR_TXPROFILE_IQRATE, + MYKONOS_ERR_TXPROFILE_RFBW, + MYKONOS_ERR_TXPROFILE_FILTER_INTERPOLATION, + MYKONOS_ERR_TXPROFILE_FIR_COEFS, + MYKONOS_ERR_TXPROFILE_DACDIV, + MYKONOS_ERR_RESET_TXLOL_INV_PARAM, + MYKONOS_ERR_RESET_TXLOL_ARMERROR, + MYKONOS_ERR_SETRFPLL_LF_INV_STABILITY, + MYKONOS_ERR_SETRFPLL_LF_PLLNAME, + MYKONOS_ERR_SETRFPLL_LF_INV_TXRX_LOOPBANDWIDTH, + MYKONOS_ERR_SETRFPLL_LF_INV_SNF_LOOPBANDWIDTH, + MYKONOS_ERR_SETRFPLL_LF_ARMERROR, + MYKONOS_ERR_GETRFPLL_LF_ARMERROR, + MYKONOS_ERR_GETRFPLL_LF_NULLPARAM, + MYKONOS_ERR_GETRFPLL_LF_INV_PLLNAME, + MYKONOS_ERR_DC_OFFSET_INV_CHAN, + MYKONOS_ERR_SET_RF_DC_OFFSET_INV_MEASURECNT, + MYKONOS_ERR_SET_RF_DC_OFFSET_MEASURECNT_MIN_LIMIT, + MYKONOS_ERR_GET_RF_DC_OFFSET_NULL_MEASURECNT, + MYKONOS_ERR_RF_DC_OFFSET_INV_ENABLE_MASK, + MYKONOS_ERR_RF_DC_OFFSET_NULL_ENABLE_MASK, + MYKONOS_ERR_SET_DIG_DC_OFFSET_INV_MSHIFT, + MYKONOS_ERR_GET_DIG_DC_OFFSET_NULL_MSHIFT, + MYKONOS_ERR_DIG_DC_OFFSET_INV_ENABLE_MASK, + MYKONOS_ERR_DIG_DC_OFFSET_NULL_ENABLE_MASK, + MYKONOS_ERR_CFGCLGC_INV_THRESHOLD, + MYKONOS_ERR_RESETDPD_INV_TXCHANNEL, + MYKONOS_ERR_RESETDPD_ARMERRFLAG, + MYKONOS_ERR_RESETDPD_WRONG_PARAM, + MYKONOS_WRN_RADIO_ON_NOT_MODIFIABLE, + MYKONOS_ERR_SET_PATH_DELAY_NULL_PARAM, + MYKONOS_ERR_SET_PATH_DELAY_PARAM_OUT_OF_RANGE, + MYKONOS_ERR_GET_PATH_DELAY_NULL_PARAM, + MYKONOS_ERR_GET_PATH_DELAY_INVALID_SELECTION, + MYKONOS_ERR_GET_PATH_DELAY_ARMERRFLAG, + + + MYKONOS_ERR_GETDPD_ERROR_CNT_NULLPARAM, + MYKONOS_ERR_GETDPD_ERROR_CNT_INV_CH, + MYKONOS_ERR_GETDPD_ERROR_CNT_ARMERRFLAG, + + MYKONOS_ERR_SETDPDACT_NULL_ACTSTRUCT, + MYKONOS_ERR_SETDPDACT_INV_ACTMODE, + MYKONOS_ERR_SETDPDACT_INV_LEVEL, + MYKONOS_ERR_GETDPDACT_NULL_ACTSTRUCT, + + MYKONOS_ERR_SETDPDACTCHECK_NULL_ACTSTRUCT, + MYKONOS_ERR_SETDPDACTCHECK_INV_ACTMODE, + MYKONOS_ERR_SETDPDACTCHECK_INV_LEVEL, + MYKONOS_ERR_GETDPDACTCHECK_NULL_ACTSTRUCT, + + MYKONOS_ERR_CLGCATTENTUNCFG_NULL_ATTRANGECFGSTRUCT, + MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_MODE, + MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_PRESET, + MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_RANGE, + MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX1_SETTINGS, + MYKONOS_ERR_CLGCATTENTUNCFG_INVALID_TX2_SETTINGS, + + MYKONOS_ERR_CLGCATTENTUNCFGGET_NULL_ATTRANGECFGSTRUCT, + + MYKONOS_ERR_END +} mykonosErr_t; + +/** + * \brief Enum for Mykonos low voltage GPIO available pins + */ +typedef enum +{ + MYKGPIONAN = 0x00, + MYKGPIO0 = 0x1, + MYKGPIO1 = 0x2, + MYKGPIO2 = 0x4, + MYKGPIO3 = 0x8, + MYKGPIO4 = 0x10, + MYKGPIO5 = 0x20, + MYKGPIO6 = 0x40, + MYKGPIO7 = 0x80, + MYKGPIO8 = 0x100, + MYKGPIO9 = 0x200, + MYKGPIO10 = 0x400, + MYKGPIO11 = 0x800, + MYKGPIO12 = 0x1000, + MYKGPIO13 = 0x2000, + MYKGPIO14 = 0x4000, + MYKGPIO15 = 0x8000, + MYKGPIO16 = 0x10000, + MYKGPIO17 = 0x20000, + MYKGPIO18 = 0x40000 +} mykonosGpioSelect_t; + + +/** + * \brief Enum of valid Mykonos Enable State Machine (ENSM) states + */ +typedef enum +{ + WAIT = 0, /*!< Mykonos ENSM state upon which a power up in the WAIT/SLEEP state occurs */ + INIT = 1, /*!< Mykonos ENSM state upon which a power up delay state ocurrs to allow clocks to stabilize */ + WAITCALS = 2, /*!< Mykonos ENSM state upon which calibrations are initializing */ + ALERTCALS = 3, /*!< Mykonos ENSM state upon which calibrations are occurring */ + ALERTLDS = 4, /*!< Mykonos ENSM state upon which a delay state is occurring when moving from WAIT to ALERT to allow internal circuits to power up */ + ALERT = 5, /*!< Mykonos ENSM state upon which the internal RF synth is powered up, and TX and RX data paths are still powered down */ + TX_RX = 6, /*!< Mykonos ENSM state upon which the ability to power up data paths depending on the TxEnable/RxEnable pins or SPI bits */ + FLUSH = 7 /*!< Mykonos ENSM state upon which the data paths are cleared when exiting the TX_RX state */ +} mykonosEnsmState_t; + + +/** + * \brief Enum of possible Tx channels + */ +typedef enum +{ + TXOFF = 0, + TX1 = 1, + TX2 = 2, + TX1_TX2 = 3 +} mykonosTxChannels_t; + +/** + * \brief Enum of possible Rx channels + */ +typedef enum +{ + RXOFF = 0, + RX1 = 1, + RX2 = 2, + RX1_RX2 = 3 +} mykonosRxChannels_t; + +/** + * \brief Enum of possible Observation Rx channels + */ +typedef enum +{ + OBS_RXOFF = 0, + OBS_RX1_TXLO = 1, + OBS_RX2_TXLO = 2, + OBS_INTERNALCALS = 3, + OBS_SNIFFER = 4, + OBS_RX1_SNIFFERLO = 5, + OBS_RX2_SNIFFERLO = 6, + OBS_SNIFFER_A = 0x14, + OBS_SNIFFER_B = 0x24, + OBS_SNIFFER_C = 0x34 +} mykonosObsRxChannels_t; + +/** + * \brief Enum of possible Sniffer Rx channels + */ +typedef enum +{ + SNIFFER_A = 1, + SNIFFER_B = 2, + SNIFFER_C = 3 +} mykonosSnifferChannel_t; + +/** + * \brief Enum of possible Observation Rx channels to enable and run calibrations for during init. + * Choose ENUM value that enables all channels that will be used in the system. During system use, + * only one channel can be used at a time. This is also used to alert the ARM processor + * which observation channels are valid for the current desired system setup. + */ +typedef enum +{ + MYK_OBS_RXOFF = 0x00, + MYK_ORX1 = 0x01, + MYK_ORX2 = 0x02, + MYK_ORX1_ORX2 = 0x03, + MYK_SNRXA = 0x04, + MYK_SNRXB = 0x08, + MYK_SNRXC = 0x10, + MYK_SNRXA_B_C = 0x1C +} mykonosObsRxChannelsEn_t; + +/** + * \brief Enum of possible DAC divider settings (2x, 2.5x, 4x) + */ +typedef enum +{ + DACDIV_2, + DACDIV_2p5, + DACDIV_4 +} mykonosDacDiv_t; + +/** + * \brief Enum of possible VCO divider settings (1x, 1.5x, 2x, 3x) + */ +typedef enum +{ + VCODIV_1 = 0, + VCODIV_1p5 = 1, + VCODIV_2 = 2, + VCODIV_3 = 3 +} mykonosVcoDiv_t; + +/** + * \brief Enum of possible PRBS pattern settings + */ +typedef enum +{ + MYK_PRBS7 = 0, + MYK_PRBS15 = 1, + MYK_PRBS31 = 2 +} mykonosPrbsOrder_t; + +/** + * \brief Enum of RF PLL names + */ +typedef enum +{ + CLK_PLL, + RX_PLL, + TX_PLL, + SNIFFER_PLL +} mykonosRfPllName_t; + +/** + * \brief Enum of Rx profile types + */ +typedef enum +{ + MYK_RX_PROFILE, + MYK_OBS_PROFILE, + MYK_SNIFFER_PROFILE +} mykonosRxProfType_t; + +/** + * \brief Enum of ORx PLL names + */ +typedef enum +{ + OBSLO_TX_PLL, + OBSLO_SNIFFER_PLL +} mykonosObsRxLoSource_t; + +/** + * \brief Enum of possible wait events to use with MYKONOS_waitForEvent() + */ +typedef enum +{ + CALPLL_LOCK, + CLKPLLCP, + CLKPLL_LOCK, + RF_RXPLLCP, + RF_RXPLL_LOCK, + RF_TXPLLCP, + RF_TXPLL_LOCK, + RF_SNIFFERPLLCP, + RF_SNIFFERPLL_LOCK, + RXBBF_CALDONE, + TXBBF_CALDONE, + RX_RFDC_CALDONE, + RX_ADCTUNER_CALDONE, + RX1_ADCPROFILE, + RX2_ADCPROFILE, + ORX_ADCPROFILE, + RCAL_CALDONE, + ARMBUSY, + INITARM_DONE +} waitEvent_t; + +/** + * \brief Enum to set the desired FIR filter type for related functions + */ +typedef enum +{ + TX1_FIR = 1, + TX2_FIR = 2, + TX1TX2_FIR = 3, + RX1_FIR = 4, + RX2_FIR = 8, + RX1RX2_FIR = 12, + OBSRX_A_FIR = 16, + OBSRX_B_FIR = 32 +} mykonosfirName_t; + +/** + * \brief Enum to set the desired Rx gain table channel + */ +typedef enum +{ + RX1_GT = 1, + RX2_GT, + RX1_RX2_GT, + ORX_GT, + SNRX_GT, + LOOPBACK_GT +}mykonosGainTable_t; + +/** + * \brief Enum to set the Rx Gain control mode + */ +typedef enum +{ + MGC = 0, /*!< Manual Gain Control */ + AGC = 2, /*!< Automatic Gain Control (AGC) */ + HYBRID = 3 /*!< Hybrid AGC Gain Control */ + +} mykonosGainMode_t; + +/** + * \brief Enum to set the Tx Atenuation step size + */ +typedef enum +{ + TXATTEN_0P05_DB = 0, /*!< Tx attenuation 0.05dB step size */ + TXATTEN_0P1_DB = 1, /*!< Tx attenuation 0.1dB step size */ + TXATTEN_0P2_DB = 2, /*!< Tx attenuation 0.2dB step size */ + TXATTEN_0P4_DB = 3 /*!< Tx attenuation 0.4dB step size */ +} mykonosTxAttenStepSize_t; + +/** + * \brief Enum to help set the init calibration mask + */ +typedef enum +{ + TX_BB_FILTER = 0x0001, + ADC_TUNER = 0x0002, + TIA_3DB_CORNER = 0x0004, + DC_OFFSET = 0x0008, + TX_ATTENUATION_DELAY = 0x0010, + RX_GAIN_DELAY = 0x0020, + FLASH_CAL = 0x0040, + PATH_DELAY = 0x0080, + TX_LO_LEAKAGE_INTERNAL = 0x0100, + TX_LO_LEAKAGE_EXTERNAL = 0x0200, + TX_QEC_INIT = 0x0400, + LOOPBACK_RX_LO_DELAY = 0x0800, + LOOPBACK_RX_RX_QEC_INIT = 0x1000, + RX_LO_DELAY = 0x2000, + RX_QEC_INIT = 0x4000, + DPD_INIT = 0x8000, + CLGC_INIT = 0x10000, + VSWR_INIT = 0x20000 +} mykonosInitCalibrations_t; + +/** + * \brief Enum to help set the tracking calibration mask + */ +typedef enum +{ + TRACK_RX1_QEC = 0x00001, + TRACK_RX2_QEC = 0x00002, + TRACK_ORX1_QEC = 0x00004, + TRACK_ORX2_QEC = 0x00008, + TRACK_TX1_LOL = 0x00010, + TRACK_TX2_LOL = 0x00020, + TRACK_TX1_QEC = 0x00040, + TRACK_TX2_QEC = 0x00080, + TRACK_TX1_DPD = 0x00100, + TRACK_TX2_DPD = 0x00200, + TRACK_TX1_CLGC = 0x00400, + TRACK_TX2_CLGC = 0x00800, + TRACK_TX1_VSWR = 0x01000, + TRACK_TX2_VSWR = 0x02000, + TRACK_ORX1_QEC_SNLO = 0x10000, + TRACK_ORX2_QEC_SNLO = 0x20000, + TRACK_SRX_QEC = 0x40000 +} mykonosTrackingCalibrations_t; + + +/** + * \brief Enum to select the desired status calibration path delay read back + */ +typedef enum +{ + MYK_DPD_PATH_DELAY = 0, + MYK_CLGC_PATH_DELAY = 1, + MYK_VSWR_PATH_DELAY = 2 +} mykonosPathDelaySel_t; + +/** + * \brief Enum to set the GPIO3v3 mode + */ +typedef enum +{ + GPIO3V3_LEVELTRANSLATE_MODE = 1, /*!< Level translate mode, signal level on low voltage GPIO output on GPIO3v3 pins */ + GPIO3V3_INVLEVELTRANSLATE_MODE = 2, /*!< Inverted Level translate mode, inverse of signal level on low voltage GPIO output on GPIO3v3 pins */ + GPIO3V3_BITBANG_MODE = 3, /*!< Manual mode, API function sets output pin levels and reads input pin levels */ + GPIO3V3_EXTATTEN_LUT_MODE = 4 /*!< GPIO3v3 output level follows Rx1/Rx2 gain table external control 6bit field. */ +} mykonosGpio3v3Mode_t; + +/** + * \brief Enum to set the low voltage GPIO mode + */ +typedef enum +{ + GPIO_MONITOR_MODE = 0, /*!< Allows a choice of debug signals to output from Mykonos to monitor the state of the device */ + GPIO_BITBANG_MODE = 3, /*!< Manual mode, API function sets output pin levels and reads input pin levels */ + GPIO_ARM_OUT_MODE = 9, /*!< Allows internal ARM processor to output on GPIO pins */ + GPIO_SLICER_OUT_MODE = 10 /*!< Allows Slicer active configuration to the GPIO output pins */ +} mykonosGpioMode_t; + +/** + * \brief Enum for ARM states + */ +typedef enum +{ + MYK_ARM_POWERUP = 0x00, /*!< ARM is powered up and ready to be programmed */ + MYK_ARM_READY = 0x01, /*!< ARM enter this state once the boot up sequence is completed */ + MYK_ARM_IDLE = 0x02, /*!< ARM enter this state after initial calibrations are completed */ + MYK_ARM_RADIO_ON = 0x04, /*!< ARM has moved from MYKONOS_ARM_IDLE state into MYKONOS_ARM_RADIO_ON after the proper command, an abort command will move back to MYKONOS_ARM_IDLE state */ + MYK_ARM_PROFILE_ERROR = 0x08, /*!< ARM has detected an illegal profile */ + MYK_ARM_CAL_ERROR = 0x40, /*!< ARM has detected an error in the tracking calibrations */ + MYK_ARM_EXCEPTION = 0x80 /*!< ARM system problem has been detected */ +} mykonosArmState_t; + +/** + * \brief Enum for channel selection for DC offset settings. + */ +typedef enum +{ + MYK_DC_OFFSET_RX_CHN = 0x01, /*!< Select Rx channel */ + MYK_DC_OFFSET_ORX_CHN = 0x02, /*!< Select ORx channel */ + MYK_DC_OFFSET_SNF_CHN = 0x04 /*!< Select Sniffer channel */ +}mykonosDcOffsetChannels_t; + +/** + * \brief Enum of Rx channels for configuring (Enable /disable) DC offsets. + */ +typedef enum +{ + MYK_DC_OFFSET_ALL_OFF = 0x00, /*!< Disable all the channels */ + MYK_DC_OFFSET_RX1 = 0x01, /*!< Enables Rx1 */ + MYK_DC_OFFSET_RX2 = 0x02, /*!< Enables Rx2 */ + MYK_DC_OFFSET_SNF = 0x04, /*!< Enables Sniffer */ + MYK_DC_OFFSET_ORX = 0x08, /*!< Enables ORx */ + MYK_DC_OFFSET_AVAILABLE = 0x0F /*!< Enables all the channels */ +}mykonosRxDcOffsettEn_t; + +/** + * \brief Enum of build type + */ +typedef enum +{ + MYK_BUILD_RELEASE = 0X00, + MYK_BUILD_DEBUG = 0x01, + MYK_BUILD_TEST_OBJECT = 0x04 +}mykonosBuild_t; + +/** + * \brief Enum for DPD error codes + */ +typedef enum +{ + MYK_NO_ERROR = 0, /*!< No Error */ + MYK_ORX_DISABLED = 1, /*!< ORX_DISABLED */ + MYK_TX_DISABLED = 2, /*!< TX_DISABLED */ + MYK_PATHDELAY_NOT_SETUP = 3, /*!< PATHDELAY_NOT_SETUP */ + MYK_DPD_INIT_NOT_RUN = 4, /*!< DPD_INIT_NOT_RUN */ + MYK_ORX_SIG_TOO_LOW = 5, /*!< ORX_SIG_TOO_LOW */ + MYK_ORX_SIG_SATURATED = 6, /*!< ORX_SIG_SATURATED */ + MYK_TX_SIG_TOO_LOW = 7, /*!< TX_SIG_TOO_LOW */ + MYK_TX_SIG_SATURATED = 8, /*!< TX_SIG_SATURATED */ + MYK_MODEL_ERROR_HIGH = 9, /*!< MODEL_ERROR_HIGH */ + MYK_AM_AM_OUTLIERS = 10, /*!< AM_AM_OUTLIERS */ + MYK_INVALID_TX_PROFILE = 11, /*!< INVALID_TX_PROFILE */ + MYK_ORX_TRACKING_DISABLED = 12, /*!< ORX_TRACKING_DISABLED ORx tracking must be enabled */ + MYK_ERR_RESERVED_13 = 13, /*!< Reserved DPD error */ + MYK_ERR_BAD_ACTUATOR_MODEL = 14, /*!< DPD actuator model is in bad state */ + MYK_ERR_LOW_POWER_ACTUATOR_BYPASS = 15, /*!< DPD actuator bypassed due to low input power */ + + MYK_DPD_ERROR_END +} mykonosDpdErrors_t; + +/** + * \brief Enum for DPD reset modes + */ +typedef enum +{ + MYK_DPD_NO_ACTION = 0, /*!< DPD no Action error */ + MYK_DPD_RESET_FULL = 1, /*!< Full DPD reset */ + MYK_DPD_RESET_PRIOR = 4, /*!< Reset only prior model */ + MYK_DPD_RESET_CORRELATOR = 8, /*!< Reset correlator only */ + + MYK_DPD_RESET_END +} mykonosDpdResetMode_t; + + +/** + * \brief Enum for CLGC Tx attenuation tuning range modes + */ +typedef enum +{ + MYK_CLGC_ATTEN_TUNING_PRESET = 0, /*!< Set attenuation to the tx[]AttenTuningPreset */ + MYK_CLGC_ATTEN_DISCARD = 1, /*!< Ignore calculated attenuation level and keep the existing one */ + MYK_CLGC_ATTEN_UPDATE = 2, /*!< Set attenuation to tx[]AttenTuningPreset + tx[]AttenTuningRange if calculated attenuation is above this level + Set attenuation to tx[]AttenTuningPreset - tx[]AttenTuningRange if calculated attenuation is below this level*/ + + MYK_CLGC_ATTEN_END +} mykonosClgcAttenTuningMode_t; + +/** + * \brief Data structure to hold 3.3 VDC GPIO settings + */ +typedef struct +{ + uint16_t gpio3v3Oe; /*!< Pin direction: bit per 3.3v GPIO, 0=Input, 1=Output from Mykonos device */ + mykonosGpio3v3Mode_t gpio3v3SrcCtrl3_0; /*!< Mode for GPIO3v3[3:0] pins */ + mykonosGpio3v3Mode_t gpio3v3SrcCtrl7_4; /*!< Mode for GPIO3v3[7:4] pins */ + mykonosGpio3v3Mode_t gpio3v3SrcCtrl11_8; /*!< Mode for GPIO3v3[11:8] pins */ +} mykonosGpio3v3_t; + +/** + * \brief Data structure to hold low voltage GPIO settings + */ +typedef struct +{ + uint32_t gpioOe; /*!< Output Enable per low voltage GPIO pin (1=output, 0=input) */ + mykonosGpioMode_t gpioSrcCtrl3_0; /*!< Mode for low voltage GPIO[3:0] pins */ + mykonosGpioMode_t gpioSrcCtrl7_4; /*!< Mode for low voltage GPIO[7:4] pins */ + mykonosGpioMode_t gpioSrcCtrl11_8; /*!< Mode for low voltage GPIO[11:8] pins */ + mykonosGpioMode_t gpioSrcCtrl15_12; /*!< Mode for low voltage GPIO[15:12] pins */ + mykonosGpioMode_t gpioSrcCtrl18_16; /*!< Mode for low voltage GPIO[18:16] pins */ +} mykonosGpioLowVoltage_t; + +/** + * \brief Structure used within the DPD config structure to hold a int8_t complex number + */ +typedef struct{ + int8_t real; /*!< real part of the complex number */ + int8_t imag; /*!< imaginary part of the complex number */ +} int8_cpx; + +/** + * \brief Structure to configure DPD (Only valid for a DPD-enabled transceiver) + * \deprecated robustModeling member of this structure is no longer in use. + * This information is loaded into the ARM memory using the + * MYKONOS_configDpd() function before running the DPD init or tracking + * calibrations. These values can only be changed when the ARM is in the + * radioOff state. + */ +typedef struct +{ + uint8_t damping; /*!< 1/2^(damping + 8) fraction of previous model 'forgotten' per adaptation (default: 5 = '1/8192' , valid 0 to 15), 0 = infinite damping */ + uint8_t numWeights; /*!< number of weights to use for int8_cpx weights weights member of this structure (default = 1) */ + uint8_t modelVersion; /*!< DPD model version: one of four different generalized polynomial models: 0 = same as R0 silicon, 1-3 are new and the best one depends on the PA (default: 2) */ + uint8_t highPowerModelUpdate; /*!< 1 = Update saved model whenever peak Tx digital RMS is within 1dB of historical peak Tx RMS */ + uint8_t modelPriorWeight; /*!< Determines how much weight the loaded prior model has on DPD modeling (Valid 0 - 32, default 20) */ + uint8_t robustModeling; /*!< This is deprecated and no longer in use */ + uint16_t samples; /*!< number of samples to capture (default: 512, valid 64 - 32768) */ + uint16_t outlierThreshold; /*!< threshold for sample in AM-AM plot outside of 1:1 line to be thrown out. (default: 50% = 8192/2, valid 8192 to 1) */ + int16_t additionalDelayOffset; /*!< 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64) */ + uint16_t pathDelayPnSeqLevel; /*!< Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to 8191) */ + int8_cpx weights[3]; /*!< DPD model error weighting (real/imag valid from -128 to 127) */ +} mykonosDpdConfig_t; + +/** + * \brief Structure to configure the feature to bypass DPD actuator when signal power below a threshold + * + */ +typedef struct +{ + uint8_t bypassActuatorEn; /*!< Enable/Disable feature to bypass actuator when input power below a certain threshold */ + mykonosDpdResetMode_t bypassActuatorMode; /*!< Follows reset DPD enum */ + uint16_t bypassActuatorLevel; /*!< Tx RMS level below which actuator is bypassed. P_dBFS = 20*log10(bypassActuatorLevel/8192) */ +} mykonosDpdBypassConfig_t; + + + +/** + * \brief Structure to configure the DPD actuator gain check + * + */ +typedef struct +{ + uint8_t actuatorGainCheckEn; /*!< Enable Gain check for DPD actuator */ + mykonosDpdResetMode_t actuatorGainCheckMode; /*!< Follows reset DPD enum */ + uint16_t actuatorGainCheckLevel; /*!< If the gain difference before and after the actuator exceeds this value an error will be issued + and the actuator will reset depending on the actuatorGainCheckMode, in 0.01dB, where a value of 200 => 2dB*/ +} mykonosDpdActuatorCheck_t; + +/** + * \brief Structure to configure CLGC (Closed Loop Gain Control) (Only valid for a DPD-enabled transceiver) + * + * This information is loaded into the ARM memory using the + * MYKONOS_configClgc() function before running the CLGC init or tracking + * calibrations. + * These values can be changed when the ARM is in the radioOff or radioOn states. + */ +typedef struct +{ + int16_t tx1DesiredGain; /*!< (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx1 output to ORx1 input in (dB * 100) */ + int16_t tx2DesiredGain; /*!< (value = 100 * dB (valid range -32768 to 32767) - total gain and attenuation from Mykonos Tx2 output to ORx2 input in (dB * 100) */ + uint16_t tx1AttenLimit; /*!< (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx1Atten is not reduced below the limit */ + uint16_t tx2AttenLimit; /*!< (valid range 0 - 40dB), no default, depends on PA, Protects PA by making sure Tx2Atten is not reduced below the limit */ + uint16_t tx1ControlRatio; /*!< valid range 1-100, default 45 */ + uint16_t tx2ControlRatio; /*!< valid range 1-100, default 45 */ + uint8_t allowTx1AttenUpdates; /*!< 0= allow CLGC to run, but Tx1Atten will not be updated. User can still read back power measurements. 1=CLGC runs, and Tx1Atten automatically updated */ + uint8_t allowTx2AttenUpdates; /*!< 0= allow CLGC to run, but Tx2Atten will not be updated. User can still read back power measurements. 1=CLGC runs, and Tx2Atten automatically updated */ + + int16_t additionalDelayOffset; /*!< 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64) */ + uint16_t pathDelayPnSeqLevel; /*!< Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to 8191) */ + + uint16_t tx1RelThreshold; /*!< Threshold for Tx1 in order to stop tracking, value = 100 * dB, default 6db then value = 600 */ + uint16_t tx2RelThreshold; /*!< Threshold for Tx2 in order to stop tracking, value = 100 * dB, default 6db then value = 600 */ + uint8_t tx1RelThresholdEn; /*!< Threshold feature enable for Tx1, 0 = disable, 1 = enable, default = 0 */ + uint8_t tx2RelThresholdEn; /*!< Threshold feature enable for Tx2, 0 = disable, 1 = enable, default = 0 */ +} mykonosClgcConfig_t; + +/** + * \brief Structure to configure the CLGC attenuation tuning range + */ +typedef struct +{ + mykonosClgcAttenTuningMode_t tx1AttenTuningLimitMode; /*!< Tx1 CLGC Attenuation tuning mode */ + mykonosClgcAttenTuningMode_t tx2AttenTuningLimitMode; /*!< Tx2 CLGC Attenuation tuning mode */ + uint16_t tx1AttenTuningPreset; /*!< Tx1 CLGC nominal attenuation, valid range is 0 to 839 with a 0.05dB*/ + uint16_t tx2AttenTuningPreset; /*!< Tx2 CLGC nominal attenuation, valid range is 0 to 839 with a 0.05dB*/ + uint16_t tx1AttenTuningRange; /*!< Tx1 CLGC relative attenuation range around nominal attenuation, valid range is 0 to 420 with a 0.05dB*/ + uint16_t tx2AttenTuningRange; /*!< Tx2 CLGC relative attenuation range around nominal attenuation, valid range is 0 to 420 with a 0.05dB*/ +} mykonosClgcAttenTuningConfig_t; + +/** + * \brief Structure to configure VSWR (Only valid for a DPD-enabled transceiver) + * + * This information is loaded into the ARM memory using the + * MYKONOS_configVswr() function before running the VSWR init or tracking + * calibrations. + * These values can be changed when the ARM is in the radioOff states. + */ +typedef struct +{ + /* VSWR init cal parameters */ + int16_t additionalDelayOffset; /*!< 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64) */ + uint16_t pathDelayPnSeqLevel; /*!< Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to 8191) */ + + /* VSWR tracking cal parameters */ + uint8_t tx1VswrSwitchGpio3p3Pin; /*!< 3p3V GPIO pin to use to control VSWR switch for Tx1 (valid 0-11) (output from Mykonos) */ + uint8_t tx2VswrSwitchGpio3p3Pin; /*!< 3p3V GPIO pin to use to control VSWR switch for Tx2 (valid 0-11) (output from Mykonos) */ + uint8_t tx1VswrSwitchPolarity; /*!< 3p3v GPIO pin polarity for forward path of Tx1, opposite used for reflection path (1 = high level, 0 = low level) */ + uint8_t tx2VswrSwitchPolarity; /*!< 3p3v GPIO pin polarity for forward path of Tx2, opposite used for reflection path (1 = high level, 0 = low level) */ + uint8_t tx1VswrSwitchDelay_us; /*!< Delay for Tx1 after flipping the VSWR switch until measurement is made. In us resolution with a range from 0 to 255us */ + uint8_t tx2VswrSwitchDelay_us; /*!< Delay for Tx2 after flipping the VSWR switch until measurement is made. In us resolution with a range from 0 to 255us */ +} mykonosVswrConfig_t; + +typedef struct +{ + /** + * errorStatus(decimal) | Description + * ---------------------|----------------------- + * 0 | NO ERROR (Tracking success) + * 1 | Tx data path not enabled + * 2 | ORX data path is not enabled + * 3 | Loopback switch closed + * 4 | VSWR init cal was not run + * 5 | Path delay not setup + * 6 | Data measurement was aborted + * 7 | VSWR disabled + * 8 | If set, entered cal but not finished + * 9 | No GPIO configured in single ORx configuration + * 10 | Tx is not observable with any of the ORx Channels + * 11 | ORX_TRACKING_DISABLED ORx tracking must be enabled + * + */ + uint32_t errorStatus; + uint32_t trackCount; /*!< Number of times VSWR tracking has run since last reset */ + int32_t forwardGainRms_dB; /*!< Forward RMS gain measured from Tx to ORx path (1 = 0.01 dB Gain) */ + int32_t forwardGainReal; /*!< Real part of the forward path complex gain (1 = 0.01 linear Gain) */ + int32_t forwardGainImag; /*!< Imaginary part of the forward path complex gain (1 = 0.01 linear Gain) */ + int32_t reflectedGainRms_dB; /*!< Measured reflection path gain in RMS (1 = 0.01 dB Gain) */ + int32_t reflectedGainReal; /*!< Real part of the reflection path complex gain (1 = 0.01 linear Gain) */ + int32_t reflectedGainImag; /*!< Imaginary part of the reflection path complex gain (1 = 0.01 linear Gain) */ + int32_t vswr_forward_tx_rms; /*!< Forward RMS measured from Tx path (1 = 0.01 dBFS) */ + int32_t vswr_forward_orx_rms; /*!< Forward RMS measured from ORx path (1 = 0.01 dBFS) */ + int32_t vswr_reflection_tx_rms; /*!< Reflected RMS measured from Tx path (1 = 0.01 dBFS) */ + int32_t vswr_reflection_orx_rms; /*!< Reflected RMS measured from ORx path (1 = 0.01 dBFS) */ +} mykonosVswrStatus_t; + +/** + * \brief Data structure to hold Mykonos FIR filter settings + */ +typedef struct +{ + int8_t gain_dB; /*!< Filter gain in dB*/ + uint8_t numFirCoefs; /*!< Number of coefficients in the FIR filter */ + int16_t *coefs; /*!< A pointer to an array of filter coefficients */ +} mykonosFir_t; + +/** + * \brief Data structure to hold Mykonos JESD204b Framer configuration settings + */ +typedef struct +{ + uint8_t bankId; /*!< JESD204B Configuration Bank ID extension to Device ID. Range is 0..15 */ + uint8_t deviceId; /*!< JESD204B Configuration Device ID link identification number. Range is 0..255 */ + uint8_t lane0Id; /*!< JESD204B Configuration starting Lane ID. If more than one lane is used, each lane will increment from the Lane0 ID. Range is 0..31 */ + uint8_t M; /*!< Number of ADCs (0, 2, or 4) where 2 ADCs are required per receive chain (I and Q) */ + uint8_t K; /*!< Number of frames in a multiframe. Default = 32, F*K must be modulo 4. Where, F=2*M/numberOfLanes */ + uint8_t scramble; /*!< Scrambling off if framerScramble = 0, if framerScramble > 0 scrambling is enabled */ + uint8_t externalSysref; /*!< External SYSREF select. 0 = use internal SYSREF, 1 = use external SYSREF */ + uint8_t serializerLanesEnabled; /*!< Serializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ + uint8_t serializerLaneCrossbar; /*!< Lane crossbar to map framer lane outputs to physical lanes */ + uint8_t serializerAmplitude; /*!< Serializer amplitude setting. Default = 22. Range is 0..31 */ + uint8_t preEmphasis; /*!< Serializer pre-emphasis setting. Default = 4 Range is 0..7 */ + uint8_t invertLanePolarity; /*!< Lane inversion select. Default = 0. Where, bit[0] = 0 will invert lane [0], bit[1] = 0 will invert lane 1, etc. */ + uint8_t lmfcOffset; /*!< LMFC offset value for deterministic latency setting. Range is 0..31 */ + uint8_t newSysrefOnRelink; /*!< Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, 0 = not set */ + uint8_t enableAutoChanXbar; /*!< Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set */ + uint8_t obsRxSyncbSelect; /*!< Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use OBSRX_SYNCB for this framer */ + uint8_t rxSyncbMode; /*!< Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS */ + uint8_t overSample; /*!< Selects framer bit repeat or oversampling mode for lane rate matching. Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane rate between ObsRx framer and Rx framer and oversamples the ADC samples) */ + uint8_t enableManualLaneXbar; /*!< Flag for determining if API will calculate the appropriate settings for framer lane outputs to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in serializerLaneCrossbar will be used */ +} mykonosJesd204bFramerConfig_t; + +/* NO Doxygen content required for this data structure as this is used internally */ +/// @cond +typedef struct +{ + uint8_t DID; /*!< JESD204B Configuration Device ID for ILAS check */ + uint8_t BID; /*!< JESD204B Configuration Bank ID for ILAS check */ + uint8_t LID0; /*!< JESD204B Configuration starting Lane ID for ILAS check */ + uint8_t L; /*!< JESD204B Configuration L = lanes per data converter for ILAS check */ + uint8_t SCR; /*!< JESD204B Configuration scramble setting for ILAS check */ + uint8_t F; /*!< JESD204B Configuration F = octets per frame for ILAS check */ + uint8_t K; /*!< JESD204B Configuration K = frames per multiframe for ILAS check */ + uint8_t M; /*!< JESD204B Configuration M = number of data converters for ILAS check */ + uint8_t N; /*!< JESD204B Configuration N = data converter sample resolution for ILAS check */ + uint8_t CS; /*!< JESD204B Configuration CS = number of control bits transferred per sample per frame for ILAS check */ + uint8_t NP; /*!< JESD204B Configuration NP = JESD204B word size based on the highest resolution of the data converter for ILAS check */ + uint8_t S; /*!< JESD204B Configuration S = number of samples/data converter/frame for ILAS check */ + uint8_t CF; /*!< JESD204B Configuration CF = '0' = control bits appended to each sample, '1' = appended to end of frame for ILAS check */ + uint8_t HD; /*!< JESD204B Configuration HD = high density bit - samples are contained within lane (0) or divided over more than one lane (1) for ILAS check */ + uint8_t FCHK0; /*!< JESD204B Configuration checksum for ILAS check */ +} mykonosJesd204bLane0Config_t; +/// @endcond + +/** +* \brief Data structure to hold the settings for the deserializer and deframer configuration +* +* EQ Settings | 3GHz Loss (dB) |6GHz Loss (dB) | max FR408HR Length (in) | max FR4 Length (in) +*-------------|----------------|---------------|-------------------------|--------------------- +* 0 | 6.5 | 14 | 20 | 12 +* 1 | 11.5 | 21 | 30 | 20 +* 2 | 18 | 31 | 46 | 32 +* 3 | 21.5 | 38 | 56 | 40 +* 4 | 22 | 39 | 60 | 43 +*/ +typedef struct +{ + uint8_t bankId; /*!< Extension to Device ID. Range is 0..15 */ + uint8_t deviceId; /*!< Link identification number. Range is 0..255 */ + uint8_t lane0Id; /*!< Lane0 ID. Range is 0..31 */ + uint8_t M; /*!< Number of DACs (0, 2, or 4) - 2 DACs per transmit chain (I and Q) */ + uint8_t K; /*!< Number of frames in a multiframe. Default = 32, F*K = modulo 4. Where, F=2*M/numberOfLanes */ + uint8_t scramble; /*!< Scrambling off if scramble = 0, if framerScramble > 0 scrambling is enabled */ + uint8_t externalSysref; /*!< External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF */ + uint8_t deserializerLanesEnabled; /*!< Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1 enabled, etc */ + uint8_t deserializerLaneCrossbar; /*!< Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc */ + uint8_t EQSetting; /*!< Equalizer setting. Applied to all deserializer lanes. Range is 0..4 */ + uint8_t invertLanePolarity; /*!< PN inversion per each lane. bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert PN of Lane 1, etc */ + uint8_t lmfcOffset; /*!< LMFC offset value to adjust deterministic latency. Range is 0..31 */ + uint8_t newSysrefOnRelink; /*!< Flag for determining if SYSREF on relink should be set. Where, if > 0 = set, '0' = not set */ + uint8_t enableAutoChanXbar; /*!< Flag for determining if auto channel select for the xbar should be set. Where, if > 0 = set, '0' = not set */ + uint8_t txSyncbMode; /*!< Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 = CMOS, '0' = LVDS */ + uint8_t enableManualLaneXbar; /*!< Flag for determining if API will calculate the appropriate settings for deframer lane in to physical lanes. Where, if '0' = API will set automatic lane crossbar, '1' = set to manual mode and the value in deserializerLaneCrossbar will be used */ +} mykonosJesd204bDeframerConfig_t; + +/** + * \brief Data structure to hold settings for the current Rx specific use case profile + */ +typedef struct +{ + uint8_t adcDiv; /*!< The divider used to generate the ADC clock (Valid: 1,2) */ + mykonosFir_t *rxFir; /*!< Pointer to Rx FIR filter structure */ + uint8_t rxFirDecimation; /*!< Rx FIR decimation (1,2,4) */ + uint8_t rxDec5Decimation; /*!< Decimation of Dec5 or Dec4 filter (5,4) */ + uint8_t enHighRejDec5; /*!< If set, and DEC5 filter used, will use a higher rejection DEC5 FIR filter. Where, 1 = enabled, 0 = disabled */ + uint8_t rhb1Decimation; /*!< RX Halfband1 (HB1) decimation. Can be either 1 or 2 */ + uint32_t iqRate_kHz; /*!< Rx IQ data rate in kHz */ + uint32_t rfBandwidth_Hz; /*!< Rx RF passband bandwidth for the profile */ + uint32_t rxBbf3dBCorner_kHz; /*!< Rx BBF (TIA) 3dB corner in kHz */ + uint16_t *customAdcProfile; /*!< Custom ADC profile to set the bandwidth of the ADC response */ +} mykonosRxProfile_t; + +/** + * \brief Data structure to hold settings for the current Tx specific use case profile + */ +typedef struct +{ + mykonosDacDiv_t dacDiv; /*!< The divider used to generate the DAC clock (ENUM Values)*/ + mykonosFir_t *txFir; /*!< Pointer to Tx FIR filter structure */ + uint8_t txFirInterpolation; /*!< The TX digital FIR filter interpolation (1,2,4) */ + uint8_t thb1Interpolation; /*!< Tx Halfband1 (HB1) filter interpolation (1,2) */ + uint8_t thb2Interpolation; /*!< Tx Halfband2 (HB2) filter interpolation (1,2) */ + uint8_t txInputHbInterpolation; /*!< Interpolation of half band filter before the programmable FIR (valid 1,2,4) */ + uint32_t iqRate_kHz; /*!< Tx IQ data rate in kHz */ + uint32_t primarySigBandwidth_Hz; /*!< Tx primary signal BW */ + uint32_t rfBandwidth_Hz; /*!< Tx RF passband bandwidth for the profile */ + uint32_t txDac3dBCorner_kHz; /*!< DAC filter 3dB corner in kHz */ + uint32_t txBbf3dBCorner_kHz; /*!< Tx BBF 3dB corner in kHz */ + uint8_t enableDpdDataPath; /*!< Enable Tx Dynamic pre distortion - only valid for a DPD-enabled transceiver */ +} mykonosTxProfile_t; + +/** + * \brief Data structure to hold SnRx gain control settings for initialization and during use + */ +typedef struct +{ + mykonosGainMode_t gainMode; /*!< Current Sniffer gain control mode setting */ + uint8_t gainIndex; /*!< Current Sniffer gain index. Can be used differently for Manual Gain control/AGC */ + uint8_t maxGainIndex; /*!< Max gain index for the currently loaded Sniffer Gain table */ + uint8_t minGainIndex; /*!< Min gain index for the currently loaded Sniffer Gain table */ +} mykonosSnifferGainControl_t; + +/** + * \brief Data structure to hold ORx gain control settings for initialization and during use + */ +typedef struct +{ + mykonosGainMode_t gainMode; /*!< Current ORx gain control mode setting */ + uint8_t orx1GainIndex; /*!< ORx1 Gain Index, can be used in different ways for manual and AGC gain control */ + uint8_t orx2GainIndex; /*!< ORx2 Gain Index, can be used in different ways for manual and AGC gain control */ + uint8_t maxGainIndex; /*!< Max gain index for the currently loaded ORx Gain table */ + uint8_t minGainIndex; /*!< Min gain index for the currently loaded ORx Gain table */ +} mykonosORxGainControl_t; + +/** + * \brief Data structure to hold Rx gain control settings for initialization and during use + */ +typedef struct +{ + mykonosGainMode_t gainMode; /*!< Current Rx gain control mode setting */ + uint8_t rx1GainIndex; /*!< Rx1 Gain Index, can be used in different ways for manual and AGC gain control */ + uint8_t rx2GainIndex; /*!< Rx2 Gain Index, can be used in different ways for manual and AGC gain control */ + uint8_t rx1MaxGainIndex; /*!< Max gain index for the currently loaded Rx1 Gain table */ + uint8_t rx1MinGainIndex; /*!< Min gain index for the currently loaded Rx1 Gain table */ + uint8_t rx2MaxGainIndex; /*!< Max gain index for the currently loaded Rx2 Gain table */ + uint8_t rx2MinGainIndex; /*!< Min gain index for the currently loaded Rx2 Gain table */ + uint8_t rx1Rssi; /*!< Stores Rx1 RSSI value read back from the Mykonos */ + uint8_t rx2Rssi; /*!< Stores Rx2 RSSI value read back from the Mykonos */ +} mykonosRxGainControl_t; + +/** + * \brief Data structure to hold peak detector settings for the AGC + */ +typedef struct +{ + /* Threshold Settings */ + uint8_t apdHighThresh; /*!< APD high threshold. Must be greater than apdLowThresh. Min = apdLowThresh, Max = 0x3F. 6-bit field. */ + uint8_t apdLowThresh; /*!< APD low threshold. Must be less than apdHighThresh. Min = 0, Max = apdHighThresh. 6-bit field. */ + uint8_t hb2HighThresh; /*!< HB2 high threshold. Must be greater than hb2LowThresh. Min = hb2LowThresh, Max = 0xFF. 8-bit field. */ + uint8_t hb2LowThresh; /*!< HB2 low threshold. Must be less than hb2HighThresh. Min = 0, Max = hb2HighThresh. 8-bit field. */ + uint8_t hb2VeryLowThresh; /*!< HB2 very low threshold. Must be less than hb2LowThresh. Min = 0, Max = hb2LowThresh. 8-bit field. */ + + /* Threshold Counter Settings */ + uint8_t apdHighThreshExceededCnt; /*!< APD high threshold exceeded counter. Sets number of peaks to detect above apdHighThresh to cause gain decrement according to apdHighGainStepAttack. 8-bit field. */ + uint8_t apdLowThreshExceededCnt; /*!< APD low threshold exceeded counter. Sets number of peaks to detect below apdLowThresh to cause gain increment according to apdLowGainStepRecovery. 8-bit field. */ + uint8_t hb2HighThreshExceededCnt; /*!< HB2 high threshold exceeded counter. Sets number of overloads to detect above hb2HighThresh to cause gain decrement according to hb2HighGainStepAttack. 8-bit field. */ + uint8_t hb2LowThreshExceededCnt; /*!< HB2 low threshold exceeded counter. Sets number of peaks to detect below hb2LowThresh to cause gain increment according to hb2LowGainStepRecovery. 8-bit field. */ + uint8_t hb2VeryLowThreshExceededCnt; /*!< HB2 very low threshold exceeded counter. Sets number of peaks to detect below hb2VeryLowThresh to cause gain increment according to hb2VeryLowGainStepRecovery. 8-bit field. */ + + /* Gain Step Settings */ + uint8_t apdHighGainStepAttack; /*!< Number of gain indices to decrement gain when apdHighThreshExceededCnt is exceeded. 5-bit field. */ + uint8_t apdLowGainStepRecovery; /*!< Number of gain indices to increment gain when apdLowThreshExceededCnt is exceeded. 5-bit field */ + uint8_t hb2HighGainStepAttack; /*!< Number of gain indices to decrement gain when hb2HighThreshExceededCnt is exceeded. 5-bit field */ + uint8_t hb2LowGainStepRecovery; /*!< Number of gain indices to increment gain when hb2LowThreshExceededCnt is exceeded. 5-bit field*/ + uint8_t hb2VeryLowGainStepRecovery; /*!< Number of gain indices to increment gain when hb2VeryLowThreshExceededCnt is exceeded. 5-bit field */ + + /* Fast Attack Settings */ + uint8_t apdFastAttack; /*!< [1] Enables APD fast attack mode - gain decrements immediately when apdHighThreshExceededCnt is exceeded. [0] disables APD fast attack mode - gain decrements at the expiry of agcGainUpdateCounter. 1-bit field. */ + uint8_t hb2FastAttack; /*!< [1] Enables HB2 fast attack mode - gain decrements immediately when hb2HighThreshExceededCnt is exceeded. [0] disables HB2 fast attack mode - gain decrements at the expiry of agcGainUpdateCounter. 1-bit field. */ + + /* HB2 Configuration Settings */ + uint8_t hb2OverloadDetectEnable; /*!< [1] Enables the HB2 overload detector. [0] Disables the HB2 overload detector. 1-bit field. */ + uint8_t hb2OverloadDurationCnt; /*!< Sets the samples size window of the HB2 overload detector. If hb2OverloadThreshCnt number of overloads are detected, the hb2xxxThreshExceededCnt increments. 3-bit field. [001]=1, [001]=4, [010]=8, [011]=12, [100]=16, [101]=24, [110]=32, [111]=INVALID */ + uint8_t hb2OverloadThreshCnt; /*!< Sets the number of individual overloads necessary within hb2OverloadDurationCnt samples to increment the hb2xxxThreshExceededCnt */ +} mykonosPeakDetAgcCfg_t; + +/** + * \brief Data structure to hold power measurement settings for the AGC + */ +typedef struct +{ + /* Threshold Settings */ + uint8_t pmdUpperHighThresh; /*!< Power measurement upper band, high threshold . This value is a positive offset to the pmdUpperLowThresh threshold. 4-bit field */ + uint8_t pmdUpperLowThresh; /*!< Power measurement upper band, low threshold. This value sets the threshold in (negative) -dBFS. Byte value must be less than pmdLowerHighThresh. 7-bit field */ + uint8_t pmdLowerHighThresh; /*!< Power measurement lower band, high threshold. This value sets the threshold in (negative) -dBFS. Byte value must be greater than pmdUpperLowThresh. 7-bit field */ + uint8_t pmdLowerLowThresh; /*!< Power measurement lower band, low threshold. This value is a negative offset to the pmdLowerHighThresh threshold. 4-bit field */ + + /* Gain Step Settings */ + uint8_t pmdUpperHighGainStepAttack; /*!< Number of gain indices to decrement gain if pmdUpperHighThresh is exceeded by the end of the agcGainUpdateCounter. 5-bit field */ + uint8_t pmdUpperLowGainStepAttack; /*!< Number of gain indices to decrement gain if pmdUpperLowThresh is exceeded by the end of the agcGainUpdateCounter. 5-bit field */ + uint8_t pmdLowerHighGainStepRecovery; /*!< Number of gain indices to increment gain if pmdLowerHighThresh is not exceeded by the end of the agcGainUpdateCounter. 5-bit field */ + uint8_t pmdLowerLowGainStepRecovery; /*!< Number of gain indices to increment gain if pmdLowerLowThresh is not exceeded by the end of the agcGainUpdateCounter. 5-bit field */ + + /* PMD Configuration Settings */ + uint8_t pmdMeasDuration; /*!< Number of samples to measure power on. The number of samples corresponding to the 4-bit word is 8*2^(pmdMeasDuration[3:0]). This value must be less than agcGainUpdateCounter */ + uint8_t pmdMeasConfig; /*!< Power measurement configuration. 2-bit field. [00]=PMD disabled, [01]=PMD Enabled at HB2 output, [10]=Enabled at RFIR output (recommended), [11]=PMD Enabled at BBDC2 */ +} mykonosPowerMeasAgcCfg_t; + +/** + * \brief Data structure to hold general AGC settings for initialization and during use + */ +typedef struct +{ + /* Gain Table Settings */ + uint8_t agcRx1MaxGainIndex; /*!< Maximum Rx1 gain index allowed in AGC mode. Must be greater than agcRx1MinGainIndex and valid gain index. 8-bit field */ + uint8_t agcRx1MinGainIndex; /*!< Minimum Rx1 gain index allowed in AGC mode. Must be less than agcRx1MinGainIndex and valid gain index. 8-bit field */ + uint8_t agcRx2MaxGainIndex; /*!< Maximum Rx2 gain index allowed in AGC mode. Must be greater than agcRx2MinGainIndex and valid gain index. 8-bit field */ + uint8_t agcRx2MinGainIndex; /*!< Minimum Rx2 gain index allowed in AGC mode. Must be less than agcRx2MinGainIndex and valid gain index. 8-bit field */ + uint8_t agcObsRxMaxGainIndex; /*!< Maximum ObsRx gain index allowed in AGC mode. Must be greater than agcObsRxMinGainIndex and valid gain index. 8-bit field */ + uint8_t agcObsRxMinGainIndex; /*!< Minimum ObsRx gain index allowed in AGC mode. Must be less than agcObsRxMaxGainIndex and valid gain index. 8-bit field */ + uint8_t agcObsRxSelect; /*!< Sniffer or ObsRx AGC channel select. [1] = SnRx */ + + /* AGC Mode Selection */ + uint8_t agcPeakThresholdMode; /*!< [1] = Peak Threshold Mode, power based gain changes are disabled. [0] = Peak and overload detectors are ignored for gain changes */ + uint8_t agcLowThsPreventGainIncrease; /*!< [1] PMD based gain increments are ignored if apd/hb2LowThreshExceedCnt is high [0] apdLowThreshExceededCnt and hb2LowThreshExceededCnt are "Don't cares" to the AGC gain recovery */ + + /* AGC General Settings */ + uint32_t agcGainUpdateCounter; /*!< Number of samples for the AGC gain update counter. Counter operates on the IQ data rate. 22-bit field. Min = 0x000001, Max = 0x3FFFFF */ + uint8_t agcSlowLoopSettlingDelay; /*!< Number of IQ data rate clock cycles to wait after a gain change before peak/power measurements resume. 7-bit field */ + uint8_t agcPeakWaitTime; /*!< Number of IQ data rate clock cycles to wait to enable peak/overload detectors after AGC is enabled. 5-bit field. Min = 0x02. Max = 0x1F */ + uint8_t agcResetOnRxEnable; /*!< [1] = Performs a reset of the AGC slow loop state machine when Rx is disabled. [0] = AGC slow loop state machine maintains its state when Rx is disabled. */ + uint8_t agcEnableSyncPulseForGainCounter; /*!< [1] = Allows sync of agcGainUpdateCounter to the time-slot boundary. GPIO setup required. [0] = agcGainUpdateCounter functions as normal */ + + mykonosPeakDetAgcCfg_t *peakAgc; /*!< pointer to structure for Peak AGC */ + mykonosPowerMeasAgcCfg_t *powerAgc; /*!< pointer to structure for Power AGC */ +} mykonosAgcCfg_t; + +/** + * \brief Data structure to hold Tx data path settings + */ +typedef struct +{ + mykonosTxProfile_t *txProfile; /*!< Tx datapath profile, 3dB corner frequencies, and digital filter enables */ + mykonosJesd204bDeframerConfig_t *deframer; /*!< Mykonos JESD204b deframer config for the Tx data path */ + mykonosTxChannels_t txChannels; /*!< The desired Tx channels to enable during initialization */ + uint8_t txPllUseExternalLo; /*!< Internal LO=0, external LO*2 if =1 */ + uint64_t txPllLoFrequency_Hz; /*!< Tx PLL LO frequency (internal or external LO) */ + mykonosTxAttenStepSize_t txAttenStepSize; /*!< Tx Attenuation step size */ + uint16_t tx1Atten_mdB; /*!< Initial and current Tx1 Attenuation */ + uint16_t tx2Atten_mdB; /*!< Initial and current Tx2 Attenuation */ + mykonosDpdConfig_t *dpdConfig; /*!< DPD settings. Only valid for a DPD-enabled transceiver, set pointer to NULL otherwise */ + mykonosClgcConfig_t *clgcConfig; /*!< CLGC settings. Only valid for a DPD-enabled transceiver, set pointer to NULL otherwise */ + mykonosVswrConfig_t *vswrConfig; /*!< VSWR settings. Only valid for a DPD-enabled transceiver, set pointer to NULL otherwise */ +} mykonosTxSettings_t; + +/** + * \brief Data structure to hold Rx data path settings + */ +typedef struct +{ + mykonosRxProfile_t *rxProfile; /*!< Rx datapath profile, 3dB corner frequencies, and digital filter enables */ + mykonosJesd204bFramerConfig_t *framer; /*!< Rx JESD204b framer configuration structure */ + mykonosRxGainControl_t *rxGainCtrl; /*!< Rx Gain control settings structure */ + mykonosAgcCfg_t *rxAgcCtrl; /*!< Rx AGC control settings structure */ + mykonosRxChannels_t rxChannels; /*!< The desired Rx Channels to enable during initialization */ + uint8_t rxPllUseExternalLo; /*!< Internal LO = 0, external LO*2 = 1 */ + uint64_t rxPllLoFrequency_Hz; /*!< Rx PLL LO Frequency (internal or external LO) */ + uint8_t realIfData; /*!< Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where, if > 0 = real IF data, '0' = zero IF (IQ) data*/ +} mykonosRxSettings_t; + +/** + * \brief Data structure to hold ORx data path settings + */ +typedef struct +{ + mykonosRxProfile_t *orxProfile; /*!< ORx datapath profile, 3dB corner frequencies, and digital filter enables. */ + mykonosORxGainControl_t *orxGainCtrl; /*!< ObsRx gain control settings structure */ + mykonosAgcCfg_t *orxAgcCtrl; /*!< ORx AGC control settings structure */ + mykonosRxProfile_t *snifferProfile; /*!< Sniffer datapath profile, 3dB corner frequencies, and digital filter enables. */ + mykonosSnifferGainControl_t *snifferGainCtrl; /*!< SnRx gain control settings structure */ + mykonosJesd204bFramerConfig_t *framer; /*!< ObsRx JESD204b framer configuration structure */ + mykonosObsRxChannelsEn_t obsRxChannelsEnable; /*!< The desired ObsRx channels to configure/calibrate during initialization */ + mykonosObsRxLoSource_t obsRxLoSource; /*!< The sniffer/ORx mixers can use the TX_PLL or SNIFFER_PLL */ + uint64_t snifferPllLoFrequency_Hz; /*!< SnRx PLL LO frequency in Hz */ + uint8_t realIfData; /*!< Flag to choose if complex baseband or real IF data are selected for Rx and ObsRx paths. Where if > 0 = real IF data, '0' = complex data */ + uint16_t *customLoopbackAdcProfile; /*!< Custom Loopback ADC profile to set the bandwidth of the ADC response */ + mykonosObsRxChannels_t defaultObsRxChannel; /*!< Default ObsRx channel to enter when radioOn called */ +} mykonosObsRxSettings_t; + + +/** + * \brief Data structure to hold ARM GPIO pin assignments for each ARM input/output pin. + */ +typedef struct +{ + uint8_t useRx2EnablePin; /*!< 0= RX1_ENABLE controls RX1 and RX2, 1 = separate RX1_ENABLE/RX2_ENABLE pins */ + uint8_t useTx2EnablePin; /*!< 0= TX1_ENABLE controls TX1 and TX2, 1 = separate TX1_ENABLE/TX2_ENABLE pins */ + uint8_t txRxPinMode; /*!< 0= ARM command mode, 1 = Pin mode to power up Tx/Rx chains */ + uint8_t orxPinMode; /*!< 0= ARM command mode, 1 = Pin mode to power up ObsRx receiver*/ + + /* Mykonos ARM input GPIO pins -- Only valid if orxPinMode = 1 */ + uint8_t orxTriggerPin; /*!< Select desired GPIO pin (valid 4-15) */ + uint8_t orxMode2Pin; /*!< Select desired GPIO pin (valid 0-18) */ + uint8_t orxMode1Pin; /*!< Select desired GPIO pin (valid 0-18) */ + uint8_t orxMode0Pin; /*!< Select desired GPIO pin (valid 0-18) */ + + /* Mykonos ARM output GPIO pins -- always available, even when pin mode not enabled*/ + uint8_t rx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + uint8_t rx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + uint8_t tx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + uint8_t tx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + uint8_t orx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + uint8_t orx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + uint8_t srxEnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + uint8_t txObsSelect; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */ + /* When 2Tx are used with only 1 ORx input, this GPIO tells the BBIC which Tx channel is */ + /* active for calibrations, so BBIC can route correct RF Tx path into the single ORx input */ +} mykonosArmGpioConfig_t; + +/** + * \brief Data structure to hold auxiliary IO settings (AuxDAC, ARM GPIO, GPIO3.3v, low voltage GPIO, HSCP, etc) + */ +typedef struct +{ + uint16_t auxDacEnable; /*!< Aux DAC enable. One bit per Aux DAC. Where bit[0] = Aux DAC 0, bit[1] = Aux DAC 1, etc */ + uint16_t auxDacValue[10]; /*!< Aux DAC value */ + uint8_t auxDacSlope[10]; /*!< Aux DAC slope */ + uint8_t auxDacVref[10]; /*!< Aux DAC voltage reference value */ + + mykonosGpio3v3_t *gpio3v3; /*!< GPIO 3.3 VDC settings data structure pointer */ + mykonosGpioLowVoltage_t *gpio; /*!< Low voltage GPIO settings data structure pointer */ + mykonosArmGpioConfig_t *armGpio; /*!< Mykonos ARM GPIO settings*/ +} mykonosAuxIo_t; + +/** + * \brief Data structure to hold digital clock settings + */ +typedef struct +{ + uint32_t deviceClock_kHz; /*!< CLKPLL and device reference clock frequency in kHz */ + uint32_t clkPllVcoFreq_kHz; /*!< CLKPLL VCO frequency in kHz */ + mykonosVcoDiv_t clkPllVcoDiv; /*!< CLKPLL VCO divider */ + uint8_t clkPllHsDiv; /*!< CLKPLL high speed clock divider */ +} mykonosDigClocks_t; + + +/** + * \brief Data structure used to read back the Init Calibration Status + */ +typedef struct +{ + uint32_t calsDoneLastRun; /*!< Init cals that completed in the last call to MYKONOS_runInitCals() */ + uint32_t calsDoneLifetime; /*!< Init cals that have completed successfully since loading of the ARM processor */ + uint32_t calsMinimum; /*!< Minimum set of init cals that must complete before device can move to radioOn state */ + uint8_t initErrCal; /*!< If an init cal had an error, this represents the opcode of the init cal that reported an error */ + uint8_t initErrCode; /*!< If an init cal had an error, this represents the ARM error code describing the failure */ +} mykonosInitCalStatus_t; + +/** + * \brief Data structure used to read back DPD calibration status + */ +typedef struct +{ + /** + * dpdErrorStatus (decimal) | Description + * --------------------------|----------------------- + * 0 | No Error + * 1 | ORX_DISABLED + * 2 | TX_DISABLED + * 3 | PATHDELAY_NOT_SETUP + * 4 | DPD_INIT_NOT_RUN + * 5 | ORX_SIG_TOO_LOW + * 6 | ORX_SIG_SATURATED + * 7 | TX_SIG_TOO_LOW + * 8 | TX_SIG_SATURATED + * 9 | MODEL_ERROR_HIGH + * 10 | AM_AM_OUTLIERS + * 11 | INVALID_TX_PROFILE + * 12 | ORX_TRACKING_DISABLED ORx tracking must be enabled + * 13 | Cal suspended + * 14 | Reserved + * 15 | Reserved + * 16 | Reserved + * 17 | Reserved + * 18 | Reserved + */ + uint32_t dpdErrorStatus; + uint32_t dpdTrackCount; /*!< Number of times DPD tracking has run since last reset */ + uint32_t dpdModelErrorPercent; /*!< Percent Error of PA model * 10 to include 1 decimal place */ + uint32_t dpdExtPathDelay; /*!< External path delay from Tx output to ORx input, at 1/16 sample resolution of ORx sample rate */ + uint16_t dpdMaxAdaptationCurrent; /*!< max amplitude of current adaptation */ + uint16_t dpdMaxAdaptation; /*!< max amplitude of adaptation since DPD started*/ + uint32_t dpdIterCount; /*!< number of times DPD tracking has run since last reset*/ +} mykonosDpdStatus_t; + +/** + * \brief Data structure used to read back CLGC calibration status + */ +typedef struct +{ + /** + * clgcErrorStatus(decimal) | Description + * -------------------------|----------------------- + * 0 | NO ERROR + * 1 | TX Disabled + * 2 | ORx is disabled + * 3 | Loopback switch is clo + * 4 | Data measurement aborted during capture + * 5 | No initial calibration was done + * 6 | Path delay not setup + * 7 | No apply control is possible + * 8 | Control value is out of range + * 9 | CLGC feature is disabled + * 10 | TX attenuation is capped + * 11 | Gain measurement + * 12 | No GPIO configured in single ORx configuration + * 13 | Tx is not observable with any of the ORx Channels + * 14 | ORX_TRACKING_DISABLED ORx tracking must be enabled + * 15 | PA Protection Activated + * 16 | Relative Threshold Violated + * 17 | RESERVED + * 18 | Tx power too low + * 19 | ORx power too low + */ + uint32_t errorStatus; + uint32_t trackCount; /*!< Number of times CLGC tracking has run since last reset */ + int32_t desiredGain; /*!< Desired gain/attenuation from Tx output to ORx input of Mykonos device. 0.01 dB resolution */ + int32_t currentGain; /*!< Current measured gain in 0.01 dB resolution. */ + uint32_t txGain; /*!< Current TxAttenuation setting, same as MYKONOS_getTx1/2Attenuation(), in 0.05dB resolution */ + int32_t txRms; /*!< Tx digital sample power measured at DPD block input (0.01 dB resolution) */ + int32_t orxRms; /*!< ORx digital sample power measured at ORx port (0.01 dB resolution) */ +} mykonosClgcStatus_t; + +/** + * \brief Data structure to hold Tx LOL Status + */ +typedef struct +{ + uint32_t errorCode; /*!< error code from Tx LOL */ + uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ + uint32_t performanceMetric; /*!< Variance of the corrections, and gives an indication in dB on how much LO leakage is corrected on an average tracking pass. */ + uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ + uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ +} mykonosTxLolStatus_t; + +/** + * \brief This structure contains the internal path delay + * + */ +typedef struct +{ + uint32_t forwardPathDelayCh1; /*!< Forward path delay for Channel 1 valid range is from 0 to 4095 at 1/16 sample resolution of ORx sample rate */ + uint32_t reversePathDelayCh1; /*!< Reverse path delay for Channel 1 valid range is from 0 to 4095 at 1/16 sample resolution of ORx sample rate */ + uint32_t forwardPathDelayCh2; /*!< Forward path delay for Channel 2 valid range is from 0 to 4095 at 1/16 sample resolution of ORx sample rate */ + uint32_t reversePathDelayCh2; /*!< Reverse path delay for Channel 2 valid range is from 0 to 4095 at 1/16 sample resolution of ORx sample rate */ +} mykonosPathdelay_t; + +/** + * \brief This structure contains the DPD error status counters for the different errors + * + */ +typedef struct +{ + uint32_t dpdErrorCount; /*!< DPD total error count */ + uint32_t errorCounter[MYK_DPD_ERROR_END]; /*!< array for individual error counters corresponding to ::mykonosDpdErrors_t */ +} mykonosDpdErrorCounters_t; + +/** + * \brief Data structure to hold Tx QEC Status + */ +typedef struct +{ + uint32_t errorCode; /*!< error code from Tx QEC */ + uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ + uint32_t performanceMetric; /*!< Number of codes adjusted which is the number of codes of correction made last time which can be converted to an IRR power metric as with Rx QEC, if desired. */ + uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ + uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ +} mykonosTxQecStatus_t; + +/** + * \brief Data structure to hold Rx QEC Status + */ +typedef struct +{ + uint32_t errorCode; /*!< error code from Rx QEC */ + uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ + uint32_t selfcheckIrrDb; /*!< selfCheckIrrdDb - Power-weighted average Image Rejection Ratio (IRR) in dBc. */ + uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ + uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ +} mykonosRxQecStatus_t; + +/** + * \brief Data structure to hold Orx QEC Status + */ +typedef struct +{ + uint32_t errorCode; /*!< error code from Orx QEC */ + uint32_t percentComplete; /*!< percent of required data collected for the current cal. Range 0 to 100 */ + uint32_t selfcheckIrrDb; /*!< selfCheckIrrdDb - Power-weighted average Image Rejection Ratio (IRR) in dBc. */ + uint32_t iterCount; /*!< running counter that increments each time the cal runs to completion */ + uint32_t updateCount; /*!< running counter that increments each time the cal updates the correction/actuator hardware */ +} mykonosOrxQecStatus_t; + +/** + * \brief Data structure to hold Mykonos device settings + */ +typedef struct +{ + spiSettings_t *spiSettings; /*!< SPI settings data structure pointer */ + mykonosRxSettings_t *rx; /*!< Rx settings data structure pointer */ + mykonosTxSettings_t *tx; /*!< Tx settings data structure pointer */ + mykonosObsRxSettings_t *obsRx; /*!< ObsRx settings data structure pointer */ + mykonosAuxIo_t *auxIo; /*!< Auxiliary IO settings data structure pointer */ + mykonosDigClocks_t *clocks; /*!< Holds settings for CLKPLL and reference clock */ + uint8_t profilesValid; /*!< Mykonos initialize function uses this as an output to remember which profile data structure pointers are valid */ +} mykonosDevice_t; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/t_mykonos_gpio.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/t_mykonos_gpio.h new file mode 100644 index 00000000..71f2cf91 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/mykonos/t_mykonos_gpio.h @@ -0,0 +1,375 @@ +/*! + * \file t_mykonos_gpio.h + * \brief Mykonos GPIO error handling and type defines + * + * Mykonos API version: 1.5.2.3566 + */ + +/** +* \page Disclaimer Legal Disclaimer +* Copyright 2015-2017 Analog Devices Inc. +* Released under the AD9371 API license, for more information see the "LICENSE.txt" file in this zip file. +* +*/ + +#ifndef T_MYKONOSGPIO_H_ +#define T_MYKONOSGPIO_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +#include "../common.h" + +/** + * \brief Enum of unique error codes from the Mykonos GPIO API functions. + * Each error condition in the library should get its own enum value to allow + * easy debug of errors. + */ +typedef enum +{ + MYKONOS_ERR_GPIO_OK = 0, + MYKONOS_ERR_EN_MONITOR_OUT_NOT_ENABLED, + MYKONOS_ERR_EN_MONITOR_OUT_SRC_CTRL, + MYKONOS_ERR_MONITOR_OUT_INDEX_RANGE, + MYKONOS_ERR_GETGPIOMON_INDEX_NULL_PARM, + MYKONOS_ERR_GETGPIOMON_MONITORMASK_NULL_PARM, + + MYKONOS_ERR_MGCRX2_GPIO_DECPIN_INV_PARAM, + MYKONOS_ERR_MGCRX2_GPIO_INCPIN_INV_PARAM, + MYKONOS_ERR_MGCRX2_SOURCE_CONFIG, + MYKONOS_ERR_MGCRX2_STEP_INV_PARAM, + MYKONOS_ERR_MGCRX1_GPIO_DECPIN_INV_PARAM, + MYKONOS_ERR_MGCRX1_GPIO_INCPIN_INV_PARAM, + MYKONOS_ERR_MGCRX1_STEP_INV_PARAM, + MYKONOS_ERR_GETRX2PIN_INCSTEP_NULL_PARM, + MYKONOS_ERR_GETRX2PIN_DECSTEP_NULL_PARM, + MYKONOS_ERR_GETRX2PIN_INCPIN_NULL_PARM, + MYKONOS_ERR_GETRX2PIN_DECPIN_NULL_PARM, + MYKONOS_ERR_GETRX2PIN_EN_NULL_PARM, + MYKONOS_ERR_GETRX1PIN_INCSTEP_NULL_PARM, + MYKONOS_ERR_GETRX1PIN_DECSTEP_NULL_PARM, + MYKONOS_ERR_GETRX1PIN_INCPIN_NULL_PARM, + MYKONOS_ERR_GETRX1PIN_DECPIN_NULL_PARM, + MYKONOS_ERR_GETRX1PIN_EN_NULL_PARM, + + MYKONOS_ERR_TPCTX2_GPIO_DECPIN_INV_PARAM, + MYKONOS_ERR_TPCTX2_GPIO_INCPIN_INV_PARAM, + MYKONOS_ERR_TPCTX2_GPIO_STEP_INV_PARAM, + MYKONOS_ERR_TPCTX1_GPIO_DECPIN_INV_PARAM, + MYKONOS_ERR_TPCTX1_GPIO_INCPIN_INV_PARAM, + MYKONOS_ERR_TPCTX1_GPIO_STEP_INV_PARAM, + MYKONOS_ERR_GETTX2PIN_STEP_NULL_PARM, + MYKONOS_ERR_GETTX2PIN_INC_NULL_PARM, + MYKONOS_ERR_GETTX2PIN_DEC_NULL_PARM, + MYKONOS_ERR_GETTX2PIN_EN_NULL_PARM, + MYKONOS_ERR_GETTX2PIN_TX1TX2_NULL_PARM, + MYKONOS_ERR_GETTX1PIN_STEP_NULL_PARM, + MYKONOS_ERR_GETTX1PIN_INC_NULL_PARM, + MYKONOS_ERR_GETTX1PIN_DEC_NULL_PARM, + MYKONOS_ERR_GETTX1PIN_EN_NULL_PARM, + MYKONOS_ERR_GETTX1PIN_TX1TX2_NULL_PARM, + + MYKONOS_ERR_SPI2_INV_GPIO, + MYKONOS_ERR_SPI2_INV_SETUP, + + MYKONOS_ERR_SET_GPIO_1V8_INV_POINTER, + + MYKONOS_ERR_GETGPIOSETLEVEL_NULL_PARM, + MYKONOS_ERR_READGPIOSPI_NULL_PARM, + MYKONOS_ERR_SET_GPIO_1V8_INV_MODE, + MYKONOS_ERR_GETGPIO_OE_NULL_PARM, + MYKONOS_ERR_GPIO_OE_INV_PARAM, + MYKONOS_ERR_GPIO_SRC_PARAM_INV, + MYKONOS_ERR_GET_GPIO_SOURCE_CONTROL_NULL_PARM, + + MYKONOS_ERR_INV_GP_INT_MASK_PARM, + MYKONOS_ERR_GP_INT_STATUS_NULL_PARAM, + + MYKONOS_ERR_GETGPIO3V3OUT_NULL_PARM, + MYKONOS_ERR_SET_GPIO_3V3_INV_POINTER, + MYKONOS_ERR_GETGPIO3V3SPI_NULL_PARM, + MYKONOS_ERR_GPIO3V3OUTEN_NULL_PARM, + MYKONOS_ERR_SET_GPIO_3V3_INV_MODE, + MYKONOS_ERR_SET_GPIO_3V3_INV_SRC_CTRL, + + MYKONOS_ERR_SET_ARMGPIO_INV_POINTER, + MYKONOS_ERR_SET_ARMGPIO_PINS_ARMERROR, + MYKONOS_ERR_SET_ARMGPIO_PINS_INV_SIGNALID, + MYKONOS_ERR_SET_ARMGPIO_PINS_INV_GPIOPIN, + + MYKONOS_ERR_SETUPAUXDAC_NULL_PARAM, + MYKONOS_ERR_WRITEAUXDAC_NULL_AUXIO, + MYKONOS_ERR_READAUXADC_NULL_PARAM, + MYKONOS_ERR_SETUPAUXDAC_INV_AUXDACCODE, + MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACCODE, + MYKONOS_ERR_WRITEAUXDAC_INV_AUXDACINDEX, + MYKONOS_ERR_INV_AUX_ADC_CHAN_PARM, + MYKONOS_ERR_SETUPAUXADC_INV_VCODIV, + MYKONOS_ERR_INV_AUX_ADC_DEC_PARM, + + MYKONOS_ERR_GAINCOMP_NULL_STRUCT, + MYKONOS_ERR_GAINCOMP_EN_NULL_PARM, + MYKONOS_ERR_GAINCOMP_SET_NULL_STRUCT, + MYKONOS_ERR_GAINCOMP_INV_RX1_OFFSET, + MYKONOS_ERR_GAINCOMP_INV_RX2_OFFSET, + MYKONOS_ERR_GAINCOMP_INV_STEP, + MYKONOS_ERR_GAINCOMP_INV_EN, + + MYKONOS_ERR_OBS_RX_GAINCOMP_SET_NULL_STRUCT, + MYKONOS_ERR_OBS_RX_GAINCOMP_EN_NULL_PARAM, + MYKONOS_ERR_OBS_RX_GAINCOMP_INV_EN, + MYKONOS_ERR_OBS_RX_GAINCOMP_INV_OFFSET, + MYKONOS_ERR_OBS_RX_GAINCOMP_INV_STEP, + MYKONOS_ERR_OBS_RX_GAINCOMP_NULL_STRUCT, + + MYKONOS_ERR_SLICER_STEP_OUT_OF_RANGE, + MYKONOS_ERR_SLICER_INV_RX1_SEL, + MYKONOS_ERR_SLICER_INV_RX2_SEL, + MYKONOS_ERR_SLICER_EN_INV, + + MYKONOS_ERR_SLICER_RX1PIN_NULL_PARM, + MYKONOS_ERR_SLICER_RX2PIN_NULL_PARM, + MYKONOS_ERR_SLICER_STEP_NULL_PARM, + MYKONOS_ERR_SLICER_EN_NULL_PARM, + + MYKONOS_ERR_SLICER_INV_OBS_RX_SEL, + MYKONOS_ERR_SLICER_OBS_RX_STEP_OUT_OF_RANGE, + MYKONOS_ERR_SLICER_OBS_RX_EN_INV, + MYKONOS_ERR_SLICER_OBS_RX_EN_NULL_PARM, + MYKONOS_ERR_SLICER_OBS_RX_STEP_NULL_PARM, + MYKONOS_ERR_SLICER_OBS_RXPIN_NULL_PARM, + + MYKONOS_ERR_FLOATFRMT_NULL_STRUCT, + MYKONOS_ERR_FLOATFRMT_SET_NULL_STRUCT, + MYKONOS_ERR_FLOATFRMT_INV_ROUND_MODE, + MYKONOS_ERR_FLOATFRMT_INV_DATA_FORMAT, + MYKONOS_ERR_FLOATFRMT_INV_ENC_NAN, + MYKONOS_ERR_FLOATFRMT_INV_EXP_BITS, + MYKONOS_ERR_FLOATFRMT_INV_LEADING, + MYKONOS_ERR_FLOATFRMT_INV_RX1ATT, + MYKONOS_ERR_FLOATFRMT_INV_RX2ATT, + MYKONOS_ERR_FLOATFRMT_INV_EN, + MYKONOS_ERR_FLOATFRMT_NULL_RX1ATT, + MYKONOS_ERR_FLOATFRMT_NULL_RX2ATT, + MYKONOS_ERR_FLOATFRMT_NULL_ENABLE, + MYKONOS_ERR_FLOATFRMT_SET_INV_EN, + MYKONOS_ERR_FLOATFRMT_SET_INV_RX1ATT, + MYKONOS_ERR_FLOATFRMT_SET_INV_RX2ATT, + + MYKONOS_ERR_FLOATFRMT_INV_ORXATT, + MYKONOS_ERR_FLOATFRMT_INV_ORXEN, + MYKONOS_ERR_FLOATFRMT_NULL_ORXATT, + MYKONOS_ERR_FLOATFRMT_NULL_ORXENABLE, + + MYKONOS_ERR_SETUPTEMPSENSOR_NULL_PARAM, + MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPDECIMATION, + MYKONOS_ERR_SETUPTEMPSENSOR_INV_OFFSET, + MYKONOS_ERR_SETUPTEMPSENSOR_INV_TEMPWINDOW, + MYKONOS_ERR_GETTEMPSENSORCFG_NULL_PARAM, + MYKONOS_ERR_READTEMPSENSOR_NULL_PARAM, + MYKONOS_ERR_READTEMPSENSOR_NOT_LOCKED, + + MYKONOS_ERR_GAIN_CONTROL_NOT_HYBRID, + MYKONOS_ERR_GPIO_HYBRID_RX1_PIN, + MYKONOS_ERR_GPIO_HYBRID_RX2_PIN, + MYKONOS_ERR_GPIO_HYBRID_RX1_PIN_NULL_PARM, + MYKONOS_ERR_GPIO_HYBRID_RX2_PIN_NULL_PARM, + MYKONOS_ERR_GPIO_HYBRID_RX1_PIN_READ, + MYKONOS_ERR_GPIO_HYBRID_RX2_PIN_READ, + MYKONOS_ERR_AGC_OBS_NOT_IN_HYBRID, + MYKONOS_ERR_GPIO_HYBRID_ORX_PIN, + MYKONOS_ERR_GPIO_HYBRID_ORX_PIN_NULL_PARM, + + MYKONOS_ERR_GAIN_CONTROL_NOT_AGC, + MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN, + MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN, + MYKONOS_ERR_GPIO_AGC_SYNC_RX1_PIN_NULL_PARM, + MYKONOS_ERR_GPIO_AGC_SYNC_RX2_PIN_NULL_PARM, + MYKONOS_ERR_OBS_GAIN_CONTROL_NOT_AGC, + MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN, + MYKONOS_ERR_GPIO_AGC_SYNC_ORX_PIN_NULL_PARM, + + MYKONOS_ERR_GETGPIODRV_NULL_PARAM, + MYKONOS_ERR_GPIO_DRV_INV_PARAM, + + MYKONOS_ERR_GPIO_SLEW_RATE_INV_PARAM, + MYKONOS_ERR_GPIO_GETSLEW_NULL_PARAM, + + MYKONOS_ERR_CMOS_DRV_INV_PARAM, + MYKONOS_ERR_CMOS_DRV_NULL_PARAM +} mykonosGpioErr_t; + +/** + * \brief Enum of possible Rx Slicer pin combinations + */ +typedef enum +{ + GPIO_0_1_2 = 0, /*!< GPIO combination for RX1 */ + GPIO_5_6_7 = 1, /*!< GPIO combination for RX1 or RX2 */ + GPIO_8_9_10 = 2, /*!< GPIO combination for RX1 */ + GPIO_11_12_13 = 3 /*!< GPIO combination for RX2 */ +} mykonosRxSlicer_t; + +/** + * \brief Enum of possible observation channel Slicer pin combinations + */ +typedef enum +{ + GPIO_18_17_16 = 0, /*!< GPIO combination for observation channel */ + GPIO_16_15_14 = 1 /*!< GPIO combination for observation channel */ +} mykonosObsRxSlicer_t; + +/** + * \brief Enum of possible GPIO slew rate settings + */ +typedef enum +{ + MYK_SLEWRATE_NONE = 0, /*!< Lower slew rate for the GPIO */ + MYK_SLEWRATE_LOW = 1, /*!< Low slew rate for the GPIO */ + MYK_SLEWRATE_MEDIUM = 2, /*!< Medium slew rate for the GPIO */ + MYK_SLEWRATE_HIGH = 3 /*!< High slew rate for the GPIO */ +} mykonosGpioSlewRate_t; + +/** + * \brief Enumerated list of CMOS pads drive strength options + */ +typedef enum +{ + MYK_CMOSPAD_DRV_1X = 0x00, /*!< 2.5pF load @ 65MHz */ + MYK_CMOSPAD_DRV_2X = 0x01, /*!< 5pF load @ 65MHz */ + MYK_CMOSPAD_DRV_3X = 0x03, /*!< 7.5pF load @ 65MHz */ + MYK_CMOSPAD_DRV_4X = 0x07, /*!< 10pF load @ 65MHz */ + MYK_CMOSPAD_DRV_5X = 0x0F /*!< 12.5pF load @ 65MHz */ +} mykonosCmosPadDrvStr_t; + + +/** + * \brief Enumerated list for Aux ADCs + */ +typedef enum +{ + MYK_AUXADC_0 = 0x00, /*!< Aux ADC channel 0 */ + MYK_AUXADC_1 = 0x01, /*!< Aux ADC channel 1 */ + MYK_AUXADC_2 = 0x02, /*!< Aux ADC channel 2 */ + MYK_AUXADC_3 = 0x03, /*!< Aux ADC channel 3 */ + MYK_AUXADC_0_DIV2 = 0x04, /*!< Aux ADC channel 0 with the divider by 2 set */ + MYK_TEMPSENSOR = 0x10 /*!< Temperature sensor channel */ +} mykonosAuxAdcChannels_t; + + +/** + * \brief Data structure to hold Gain compensation settings for the main receive channels + **/ +typedef struct +{ + uint8_t rx1Offset; /*!< These parameter contains the Rx1 offset word used for the gain compensation + when the gain index is at its maximum setting. + It has a range of 0 to 0x1F with a resolution is 0.5dB per LSB. */ + uint8_t rx2Offset; /*!< These parameter contains the Rx2 offset word used for the gain compensation + when the gain index is at its maximum setting. + It has a range of 0 to 0x1F with a resolution is 0.5dB per LSB. */ + uint8_t compStep; /*!< These bits contains the value in dB that the total Rx gain changes + when there is an LSB change in the gain index according to the following settings: + compStep | dB ramp + ---------|------------ + 0 | 0.25dB + 1 | 0.5dB + 2 | 1.0dB + 3 | 2.0dB + 4 | 3.0dB + 5 | 4.0dB + 6 | 6.0dB + 7 | Not valid defaulted to 0.25dB */ +} mykonosGainComp_t; + +/** + * \brief Data structure to hold Gain compensation settings for the observation channel + **/ +typedef struct +{ + uint8_t obsRxOffset; /*!< These parameter contains the Rx1 offset word used for the gain compensation + when the gain index is at its maximum setting. + It has a range of 0 to 0x1F with a resolution is 0.5dB per LSB. */ + uint8_t compStep; /*!< These bits contains the value in dB that the total Rx gain changes + when there is an LSB change in the gain index according to the following settings: + compStep | dB ramp + ---------|------------ + 0 | 0.25dB + 1 | 0.5dB + 2 | 1.0dB + 3 | 2.0dB + 4 | 3.0dB + 5 | 4.0dB + 6 | 6.0dB + 7 | Not valid defaulted to 0.25dB */ +} mykonosObsRxGainComp_t; + +/** + * \brief Data structure to hold floating point formatter settings for the floating point + * number generation + **/ +typedef struct +{ + uint8_t roundMode; /*! +#include +#include "platform_drivers.h" + +/******************************************************************************/ +/************************ Functions Definitions *******************************/ +/******************************************************************************/ + +/** + * @brief Initialize the I2C communication peripheral. + * @param desc - The I2C descriptor. + * @param init_param - The structure that contains the I2C parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t i2c_init(struct i2c_desc **desc, + const struct i2c_init_param *param) +{ + if (desc) { + // Unused variable - fix compiler warning + } + + if (param->type) { + // Unused variable - fix compiler warning + } + + return SUCCESS; +} + +/** + * @brief Free the resources allocated by i2c_init(). + * @param desc - The I2C descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t i2c_remove(struct i2c_desc *desc) +{ + if (desc) { + // Unused variable - fix compiler warning + } + + return SUCCESS; +} + +/** + * @brief Write data to a slave device. + * @param desc - The I2C descriptor. + * @param data - Buffer that stores the transmission data. + * @param bytes_number - Number of bytes to write. + * @param stop_bit - Stop condition control. + * Example: 0 - A stop condition will not be generated; + * 1 - A stop condition will be generated. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t i2c_write(struct i2c_desc *desc, + uint8_t *data, + uint8_t bytes_number, + uint8_t stop_bit) +{ + if (desc) { + // Unused variable - fix compiler warning + } + + if (data) { + // Unused variable - fix compiler warning + } + + if (bytes_number) { + // Unused variable - fix compiler warning + } + + if (stop_bit) { + // Unused variable - fix compiler warning + } + + return SUCCESS; +} + +/** + * @brief Read data from a slave device. + * @param desc - The I2C descriptor. + * @param data - Buffer that will store the received data. + * @param bytes_number - Number of bytes to read. + * @param stop_bit - Stop condition control. + * Example: 0 - A stop condition will not be generated; + * 1 - A stop condition will be generated. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t i2c_read(struct i2c_desc *desc, + uint8_t *data, + uint8_t bytes_number, + uint8_t stop_bit) +{ + if (desc) { + // Unused variable - fix compiler warning + } + + if (data) { + // Unused variable - fix compiler warning + } + + if (bytes_number) { + // Unused variable - fix compiler warning + } + + if (stop_bit) { + // Unused variable - fix compiler warning + } + + return SUCCESS; +} + +/** + * @brief Initialize the SPI communication peripheral. + * @param desc - The SPI descriptor. + * @param init_param - The structure that contains the SPI parameters. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_init(struct spi_desc **desc, + const struct spi_init_param *param) +{ + spi_desc *descriptor; + int32_t ret; + + descriptor = (struct spi_desc *) calloc(1, sizeof(*descriptor)); + if (!descriptor) + return FAILURE; + + descriptor->mode = param->mode; + descriptor->chip_select = param->chip_select; + descriptor->flags = param->flags; + +#ifdef _XPARAMETERS_PS_H_ + descriptor->config = XSpiPs_LookupConfig(param->id); + if (descriptor->config == NULL) + goto error; + + ret = XSpiPs_CfgInitialize(&descriptor->instance, + descriptor->config, descriptor->config->BaseAddress); + if (ret != 0) + goto error; + + XSpiPs_SetOptions(&descriptor->instance, + XSPIPS_MASTER_OPTION | + ((descriptor->flags & SPI_CS_DECODE) ? + XSPIPS_DECODE_SSELECT_OPTION : 0) | + XSPIPS_FORCE_SSELECT_OPTION | + ((descriptor->mode & SPI_CPOL) ? + XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) | + ((descriptor->mode & SPI_CPHA) ? + XSPIPS_CLK_PHASE_1_OPTION : 0)); + + XSpiPs_SetClkPrescaler(&descriptor->instance, + XSPIPS_CLK_PRESCALE_64); + + XSpiPs_SetSlaveSelect(&descriptor->instance, 0xf); +#else + ret = XSpi_Initialize(&descriptor->instance, param->id); + if (ret != 0) + goto error; + + XSpi_SetOptions(&descriptor->instance, + XSP_MASTER_OPTION | + ((descriptor->mode & SPI_CPOL) ? + XSP_CLK_ACTIVE_LOW_OPTION : 0) | + ((descriptor->mode & SPI_CPHA) ? + XSP_CLK_PHASE_1_OPTION : 0)); + + XSpi_Start(&descriptor->instance); + + XSpi_IntrGlobalDisable(&descriptor->instance); +#endif + + *desc = descriptor; + + return SUCCESS; + +error: + free(descriptor); + + return FAILURE; +} + +/** + * @brief Free the resources allocated by spi_init(). + * @param desc - The SPI descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t spi_remove(struct spi_desc *desc) +{ + if (desc) { + // Unused variable - fix compiler warning + } + + return SUCCESS; +} + +/** + * @brief Write and read data to/from SPI. + * @param desc - The SPI descriptor. + * @param data - The buffer with the transmitted/received data. + * @param bytes_number - Number of bytes to write/read. + * @return SUCCESS in case of success, FAILURE otherwise. + */ + +int32_t spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint8_t bytes_number) +{ +#ifdef _XPARAMETERS_PS_H_ + XSpiPs_SetOptions(&desc->instance, + XSPIPS_MASTER_OPTION | + ((desc->flags & SPI_CS_DECODE) ? + XSPIPS_DECODE_SSELECT_OPTION : 0) | + XSPIPS_FORCE_SSELECT_OPTION | + ((desc->mode & SPI_CPOL) ? + XSPIPS_CLK_ACTIVE_LOW_OPTION : 0) | + ((desc->mode & SPI_CPHA) ? + XSPIPS_CLK_PHASE_1_OPTION : 0)); + + XSpiPs_SetSlaveSelect(&desc->instance, desc->chip_select); + // 0xf & ~desc->chip_select); + XSpiPs_PolledTransfer(&desc->instance, + data, data, bytes_number); +#else + XSpi_SetOptions(&desc->instance, + XSP_MASTER_OPTION | + ((desc->mode & SPI_CPOL) ? + XSP_CLK_ACTIVE_LOW_OPTION : 0) | + ((desc->mode & SPI_CPHA) ? + XSP_CLK_PHASE_1_OPTION : 0)); + + XSpi_SetSlaveSelect(&desc->instance, + desc->chip_select); + + XSpi_Transfer(&desc->instance, + data, data, bytes_number); +#endif + return 0; +} + +/** + * @brief Obtain the GPIO decriptor. + * @param desc - The GPIO descriptor. + * @param gpio_number - The number of the GPIO. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get(struct gpio_desc **desc, + uint8_t gpio_number) +{ + gpio_desc *descriptor; + int32_t ret; + + descriptor = (struct gpio_desc *) malloc(sizeof(*descriptor)); + if (!descriptor) + return FAILURE; + +#ifdef _XPARAMETERS_PS_H_ + descriptor->config = XGpioPs_LookupConfig(0); + if (descriptor->config == NULL) + goto error; + + ret = XGpioPs_CfgInitialize(&descriptor->instance, + descriptor->config, descriptor->config->BaseAddr); + if (ret != 0) + goto error; +#else + ret = XGpio_Initialize(&descriptor->instance, 0); + if (ret != 0) + goto error; +#endif + + descriptor->number = gpio_number; + + *desc = descriptor; + + return SUCCESS; + +error: + free(descriptor); + + return FAILURE; +} + +/** + * @brief Free the resources allocated by gpio_get(). + * @param desc - The SPI descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_remove(struct gpio_desc *desc) +{ + if (desc) { + // Unused variable - fix compiler warning + } + + return SUCCESS; +} + +/** + * @brief Enable the input direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_direction_input(struct gpio_desc *desc) +{ + if (desc) { + // Unused variable - fix compiler warning + } + + return 0; +} + +/** + * @brief Enable the output direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_direction_output(struct gpio_desc *desc, + uint8_t value) +{ +#ifdef _XPARAMETERS_PS_H_ + XGpioPs_SetDirectionPin(&desc->instance, desc->number, 1); + + XGpioPs_SetOutputEnablePin(&desc->instance, desc->number, 1); + + XGpioPs_WritePin(&desc->instance, desc->number, value); +#else + uint8_t pin = desc->number; + uint8_t channel; + uint32_t reg_val; + + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + + reg_val = XGpio_GetDataDirection(&desc->instance, channel); + reg_val &= ~(1 << pin); + XGpio_SetDataDirection(&desc->instance, channel, reg_val); + + reg_val = XGpio_DiscreteRead(&desc->instance, channel); + if(value) + reg_val |= (1 << pin); + else + reg_val &= ~(1 << pin); + XGpio_DiscreteWrite(&desc->instance, channel, reg_val); +#endif + + return SUCCESS; +} + +/** + * @brief Get the direction of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param direction - The direction. + * Example: GPIO_OUT + * GPIO_IN + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get_direction(struct gpio_desc *desc, + uint8_t *direction) +{ + if (desc) { + // Unused variable - fix compiler warning + } + + if (direction) { + // Unused variable - fix compiler warning + } + + return 0; +} + +/** + * @brief Set the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_set_value(struct gpio_desc *desc, + uint8_t value) +{ +#ifdef _XPARAMETERS_PS_H_ + XGpioPs_WritePin(&desc->instance, desc->number, value); +#else + uint8_t pin = desc->number; + uint8_t channel; + uint32_t reg_val; + + if (pin >= 32) { + channel = 2; + pin -= 32; + } else + channel = 1; + + reg_val = XGpio_DiscreteRead(&desc->instance, channel); + if(value) + reg_val |= (1 << pin); + else + reg_val &= ~(1 << pin); + XGpio_DiscreteWrite(&desc->instance, channel, reg_val); +#endif + + return 0; +} + +/** + * @brief Get the value of the specified GPIO. + * @param desc - The GPIO descriptor. + * @param value - The value. + * Example: GPIO_HIGH + * GPIO_LOW + * @return SUCCESS in case of success, FAILURE otherwise. + */ +int32_t gpio_get_value(struct gpio_desc *desc, + uint8_t *value) +{ + if (desc) { + // Unused variable - fix compiler warning + } + + if (value) { + // Unused variable - fix compiler warning + } + + return 0; +} + +/** + * @brief Generate microseconds delay. + * @param usecs - Delay in microseconds. + * @return None. + */ +void udelay(uint32_t usecs) +{ + usleep(usecs); +} + +/** + * @brief Generate miliseconds delay. + * @param msecs - Delay in miliseconds. + * @return None. + */ +void mdelay(uint32_t msecs) +{ +#ifdef _XPARAMETERS_PS_H_ + usleep(msecs * 1000); +#else + usleep(msecs * 50); // FIXME +#endif +} diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/platform_drivers.h b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/platform_drivers.h new file mode 100644 index 00000000..5a744b94 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/hardware/platform_drivers.h @@ -0,0 +1,223 @@ +/***************************************************************************//** + * @file platform_drivers.h + * @brief Header file of Xilinx Platform Drivers. + * @author DBogdan (dragos.bogdan@analog.com) +******************************************************************************** + * Copyright 2018(c) Analog Devices, Inc. + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * - Neither the name of Analog Devices, Inc. nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * - The use of this software may or may not infringe the patent rights + * of one or more patent holders. This license does not release you + * from the requirement that you obtain separate licenses from these + * patent holders to use this software. + * - Use of the software either in source or binary form, must be run + * on or directly connected to an Analog Devices Inc. component. + * + * THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*******************************************************************************/ + +#ifndef PLATFORM_DRIVERS_H_ +#define PLATFORM_DRIVERS_H_ + +/******************************************************************************/ +/***************************** Include Files **********************************/ +/******************************************************************************/ +#include +#include +#ifdef _XPARAMETERS_PS_H_ +#include +#include +#else +#include +#include +#endif + +/******************************************************************************/ +/********************** Macros and Constants Definitions **********************/ +/******************************************************************************/ + +#define SUCCESS 0 +#define FAILURE -1 + +#define SPI_CPHA 0x01 +#define SPI_CPOL 0x02 + +#define SPI_CS_DECODE 0x01 +#define SPI_CS_DECODE_DISABLE 0x00 + +#define GPIO_OUT 0x01 +#define GPIO_IN 0x00 + +#define GPIO_HIGH 0x01 +#define GPIO_LOW 0x00 + +/******************************************************************************/ +/*************************** Types Declarations *******************************/ +/******************************************************************************/ + +typedef enum i2c_type { + XILINX_I2C +} i2c_type; + +typedef struct i2c_init_param { + enum i2c_type type; + uint32_t id; + uint32_t max_speed_hz; + uint8_t slave_address; +} i2c_init_param; + +typedef struct i2c_desc { + enum i2c_type type; + uint32_t id; + uint32_t max_speed_hz; + uint8_t slave_address; +} i2c_desc; + +typedef enum spi_type { + XILINX_SPI +} spi_type; + +/** + * @enum spi_mode + * @brief SPI configuration for clock phase and polarity. + */ +typedef enum spi_mode { + /** Data on rising, shift out on falling */ + SPI_MODE_0 = (0 | 0), + /** Data on falling, shift out on rising */ + SPI_MODE_1 = (0 | SPI_CPHA), + /** Data on falling, shift out on rising */ + SPI_MODE_2 = (SPI_CPOL | 0), + /** Data on rising, shift out on falling */ + SPI_MODE_3 = (SPI_CPOL | SPI_CPHA) +} spi_mode; + +typedef struct spi_init_param { + enum spi_type type; + uint32_t id; + uint32_t max_speed_hz; + enum spi_mode mode; + uint8_t chip_select; + uint32_t flags; +} spi_init_param; + +typedef struct spi_desc { + enum spi_type type; + uint32_t id; + uint32_t max_speed_hz; + enum spi_mode mode; + uint8_t chip_select; + uint32_t flags; +#ifdef _XPARAMETERS_PS_H_ + XSpiPs_Config *config; + XSpiPs instance; +#else + XSpi instance; +#endif +} spi_desc; + +typedef enum gpio_type { + XILINX_GPIO +} gpio_type; + +typedef struct gpio_desc { + enum gpio_type type; + uint32_t id; + uint8_t number; +#ifdef _XPARAMETERS_PS_H_ + XGpioPs_Config *config; + XGpioPs instance; +#else + XGpio instance; +#endif +} gpio_desc; + +/******************************************************************************/ +/************************ Functions Declarations ******************************/ +/******************************************************************************/ + +/* Initialize the I2C communication peripheral. */ +int32_t i2c_init(struct i2c_desc **desc, + const struct i2c_init_param *param); + +/* Free the resources allocated by i2c_init(). */ +int32_t i2c_remove(struct i2c_desc *desc); + +/* Write data to a slave device. */ +int32_t i2c_write(struct i2c_desc *desc, + uint8_t *data, + uint8_t bytes_number, + uint8_t stop_bit); + +/* Read data from a slave device. */ +int32_t i2c_read(struct i2c_desc *desc, + uint8_t *data, + uint8_t bytes_number, + uint8_t stop_bit); + +/* Initialize the SPI communication peripheral. */ +int32_t spi_init(struct spi_desc **desc, + const struct spi_init_param *param); + +/* Free the resources allocated by spi_init() */ +int32_t spi_remove(struct spi_desc *desc); + +/* Write and read data to/from SPI. */ +int32_t spi_write_and_read(struct spi_desc *desc, + uint8_t *data, + uint8_t bytes_number); + +/* Obtain the GPIO decriptor. */ +int32_t gpio_get(struct gpio_desc **desc, + uint8_t gpio_number); + +/* Free the resources allocated by gpio_get() */ +int32_t gpio_remove(struct gpio_desc *desc); + +/* Enable the input direction of the specified GPIO. */ +int32_t gpio_direction_input(struct gpio_desc *desc); + +/* Enable the output direction of the specified GPIO. */ +int32_t gpio_direction_output(struct gpio_desc *desc, + uint8_t value); + +/* Get the direction of the specified GPIO. */ +int32_t gpio_get_direction(struct gpio_desc *desc, + uint8_t *direction); + +/* Set the value of the specified GPIO. */ +int32_t gpio_set_value(struct gpio_desc *desc, + uint8_t value); + +/* Get the value of the specified GPIO. */ +int32_t gpio_get_value(struct gpio_desc *desc, + uint8_t *value); + +/* Generate microseconds delay. */ +void udelay(uint32_t usecs); + +/* Generate miliseconds delay. */ +void mdelay(uint32_t msecs); + +#endif // PLATFORM_DRIVERS_H_ diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/lscript.ld b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/lscript.ld new file mode 100644 index 00000000..8066126a --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/lscript.ld @@ -0,0 +1,288 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: 2019.1.3 */ +/* */ +/* Copyright (c) 2010-2016 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : Cortex-A9 Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000; + +_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024; +_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048; +_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024; +_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024; +_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024; + +/* Define Memories in the system */ + +MEMORY +{ + ps7_ddr_0 : ORIGIN = 0x100000, LENGTH = 0x1FF00000 + ps7_qspi_linear_0 : ORIGIN = 0xFC000000, LENGTH = 0x1000000 + ps7_ram_0 : ORIGIN = 0x0, LENGTH = 0x30000 + ps7_ram_1 : ORIGIN = 0xFFFF0000, LENGTH = 0xFE00 +} + +/* Specify the default entry point to the program */ + +ENTRY(_vector_table) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.text : { + KEEP (*(.vectors)) + *(.boot) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.plt) + *(.gnu_warning) + *(.gcc_execpt_table) + *(.glue_7) + *(.glue_7t) + *(.vfp11_veneer) + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) +} > ps7_ddr_0 + +.init : { + KEEP (*(.init)) +} > ps7_ddr_0 + +.fini : { + KEEP (*(.fini)) +} > ps7_ddr_0 + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > ps7_ddr_0 + +.rodata1 : { + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > ps7_ddr_0 + +.sdata2 : { + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + __sdata2_end = .; +} > ps7_ddr_0 + +.sbss2 : { + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > ps7_ddr_0 + +.data : { + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.jcr) + *(.got) + *(.got.plt) + __data_end = .; +} > ps7_ddr_0 + +.data1 : { + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > ps7_ddr_0 + +.got : { + *(.got) +} > ps7_ddr_0 + +.ctors : { + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > ps7_ddr_0 + +.dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > ps7_ddr_0 + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > ps7_ddr_0 + +.eh_frame : { + *(.eh_frame) +} > ps7_ddr_0 + +.eh_framehdr : { + __eh_framehdr_start = .; + *(.eh_framehdr) + __eh_framehdr_end = .; +} > ps7_ddr_0 + +.gcc_except_table : { + *(.gcc_except_table) +} > ps7_ddr_0 + +.mmu_tbl (ALIGN(16384)) : { + __mmu_tbl_start = .; + *(.mmu_tbl) + __mmu_tbl_end = .; +} > ps7_ddr_0 + +.ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidix.*.*) + __exidx_end = .; +} > ps7_ddr_0 + +.preinit_array : { + __preinit_array_start = .; + KEEP (*(SORT(.preinit_array.*))) + KEEP (*(.preinit_array)) + __preinit_array_end = .; +} > ps7_ddr_0 + +.init_array : { + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; +} > ps7_ddr_0 + +.fini_array : { + __fini_array_start = .; + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array)) + __fini_array_end = .; +} > ps7_ddr_0 + +.ARM.attributes : { + __ARM.attributes_start = .; + *(.ARM.attributes) + __ARM.attributes_end = .; +} > ps7_ddr_0 + +.sdata : { + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > ps7_ddr_0 + +.sbss (NOLOAD) : { + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + __sbss_end = .; +} > ps7_ddr_0 + +.tdata : { + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > ps7_ddr_0 + +.tbss : { + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > ps7_ddr_0 + +.bss (NOLOAD) : { + __bss_start = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + __bss_end = .; +} > ps7_ddr_0 + +_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); + +_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); + +/* Generate Stack and Heap definitions */ + +.heap (NOLOAD) : { + . = ALIGN(16); + _heap = .; + HeapBase = .; + _heap_start = .; + . += _HEAP_SIZE; + _heap_end = .; + HeapLimit = .; +} > ps7_ddr_0 + +.stack (NOLOAD) : { + . = ALIGN(16); + _stack_end = .; + . += _STACK_SIZE; + . = ALIGN(16); + _stack = .; + __stack = _stack; + . = ALIGN(16); + _irq_stack_end = .; + . += _IRQ_STACK_SIZE; + . = ALIGN(16); + __irq_stack = .; + _supervisor_stack_end = .; + . += _SUPERVISOR_STACK_SIZE; + . = ALIGN(16); + __supervisor_stack = .; + _abort_stack_end = .; + . += _ABORT_STACK_SIZE; + . = ALIGN(16); + __abort_stack = .; + _fiq_stack_end = .; + . += _FIQ_STACK_SIZE; + . = ALIGN(16); + __fiq_stack = .; + _undef_stack_end = .; + . += _UNDEF_STACK_SIZE; + . = ALIGN(16); + __undef_stack = .; +} > ps7_ddr_0 + +_end = .; +} + diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/main.c b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/main.c new file mode 100644 index 00000000..a310c080 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj/src/main.c @@ -0,0 +1,60 @@ +/*****************************************************************************/ +/** + * Description: main.c + * + * Author: Fan Hao + * Date: 2021-11-13 13:19 + * Last Editors: Fan Hao + * Last Edit Time: [2022-03-28 20:32] + * + * Revisions: Rev 0.0 + * History: + * [2021-11-13]: Initial edition. + * [2022-03-28]: Add bit error test mode. + * + * Copyright(c) 2021 Beijing Institute of Technology. + * Lab of Communication and Networking + * + ******************************************************************************/ + +/***************************** Include Files *********************************/ +#include +#include "xscugic.h" // The generic interrupt controller driver component +#include "xil_exception.h" // ARM Cortex A9 specific exception related APIs +#include "sleep.h" // Sleep APIs for Cortex A9 +#include "xil_cache.h" +#include "hardware/headless.h" + +/************************** Constant Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/*********************** Driver Instance Definitions **************************/ + + +/*****************************************************************************/ +/** + * @brief Main function, initialize all the device needed, initialize + * interrupt system, halt in while(1) wait for event interrupt. + * + * @param None. + * + * @return + * + ******************************************************************************/ +int main(void) { + int Status; + Xil_ICacheEnable(); + Xil_DCacheDisable(); + + Status = HARDWARE_initialize(); + + if (Status == SUCCESS) { + xil_printf("Hardware Init SUCCESS! \r\n"); + } + else { + xil_printf("Hardware Init FAILED! \r\n"); + } + + return Status; +} // main diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/.cproject b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/.cproject new file mode 100644 index 00000000..ba6066b1 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/.cproject @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/.project b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/.project new file mode 100644 index 00000000..3b5a76f8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/.project @@ -0,0 +1,75 @@ + + + dl814_dj_bsp + Created by SDK v2019.1 + + + + + org.eclipse.cdt.make.core.makeBuilder + + + org.eclipse.cdt.core.errorOutputParser + org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser; + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.build.arguments + + + + org.eclipse.cdt.make.core.build.command + make + + + org.eclipse.cdt.make.core.build.target.auto + all + + + org.eclipse.cdt.make.core.build.target.clean + clean + + + org.eclipse.cdt.make.core.build.target.inc + all + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.enabledIncrementalBuild + true + + + org.eclipse.cdt.make.core.environment + + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + + com.xilinx.sdk.sw.SwProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.make.core.makeNature + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/.sdkproject b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/.sdkproject new file mode 100644 index 00000000..7e04c35b --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/.sdkproject @@ -0,0 +1,4 @@ +THIRPARTY=false +HW_PROJECT_REFERENCE=system_top_hw_platform_0 +PROCESSOR=ps7_cortexa9_0 +MSS_FILE=system.mss diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/Makefile b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/Makefile new file mode 100644 index 00000000..1e68922c --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/Makefile @@ -0,0 +1,35 @@ +# Makefile generated by Xilinx. + +PROCESSOR = ps7_cortexa9_0 +LIBRARIES = ${PROCESSOR}/lib/libxil.a +BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) +SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) + +ifneq (,$(findstring win,$(RDI_PLATFORM))) + SHELL = CMD +endif + +all: libs + @echo 'Finished building libraries' + +include: $(addsuffix /make.include,$(SUBDIRS)) + +libs: $(addsuffix /make.libs,$(SUBDIRS)) + +clean: $(addsuffix /make.clean,$(SUBDIRS)) + +$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a + cp -f $< $@ + +%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) + @echo "Running Make include in $(subst /make.include,,$@)" + $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra" + +%/make.libs: include + @echo "Running Make libs in $(subst /make.libs,,$@)" + $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra" + +%/make.clean: + $(MAKE) -C $(subst /make.clean,,$@) -s clean +clean: + rm -f ${PROCESSOR}/lib/libxil.a diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/system.mss b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/system.mss new file mode 100644 index 00000000..234222b3 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/dl814_dj_bsp/system.mss @@ -0,0 +1,225 @@ + + PARAMETER VERSION = 2.2.0 + + +BEGIN OS + PARAMETER OS_NAME = standalone + PARAMETER OS_VER = 7.0 + PARAMETER PROC_INSTANCE = ps7_cortexa9_0 + PARAMETER stdin = ps7_uart_1 + PARAMETER stdout = ps7_uart_1 +END + + +BEGIN PROCESSOR + PARAMETER DRIVER_NAME = cpu_cortexa9 + PARAMETER DRIVER_VER = 2.7 + PARAMETER HW_INSTANCE = ps7_cortexa9_0 +END + + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = jesd204b_jesd204_phy +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = jesd204b_jesd204_rx +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = jesd204b_jesd204_tx +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_afi_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_afi_1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_afi_2 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_afi_3 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = coresightps_dcc + PARAMETER DRIVER_VER = 1.5 + PARAMETER HW_INSTANCE = ps7_coresight_comp_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = ddrps + PARAMETER DRIVER_VER = 1.0 + PARAMETER HW_INSTANCE = ps7_ddr_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_ddrc_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = devcfg + PARAMETER DRIVER_VER = 3.5 + PARAMETER HW_INSTANCE = ps7_dev_cfg_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = dmaps + PARAMETER DRIVER_VER = 2.4 + PARAMETER HW_INSTANCE = ps7_dma_ns +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = dmaps + PARAMETER DRIVER_VER = 2.4 + PARAMETER HW_INSTANCE = ps7_dma_s +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_globaltimer_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = gpiops + PARAMETER DRIVER_VER = 3.5 + PARAMETER HW_INSTANCE = ps7_gpio_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_gpv_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_intc_dist_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_iop_bus_config_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_l2cachec_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_ocmc_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_pl310_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_pmu_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = qspips + PARAMETER DRIVER_VER = 3.6 + PARAMETER HW_INSTANCE = ps7_qspi_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_qspi_linear_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_ram_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_ram_1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_scuc_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = scugic + PARAMETER DRIVER_VER = 4.0 + PARAMETER HW_INSTANCE = ps7_scugic_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = scutimer + PARAMETER DRIVER_VER = 2.1 + PARAMETER HW_INSTANCE = ps7_scutimer_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = scuwdt + PARAMETER DRIVER_VER = 2.1 + PARAMETER HW_INSTANCE = ps7_scuwdt_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = ps7_slcr_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = spips + PARAMETER DRIVER_VER = 3.2 + PARAMETER HW_INSTANCE = ps7_spi_0 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = uartps + PARAMETER DRIVER_VER = 3.7 + PARAMETER HW_INSTANCE = ps7_uart_1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = xadcps + PARAMETER DRIVER_VER = 2.3 + PARAMETER HW_INSTANCE = ps7_xadc_0 +END + + diff --git a/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/system_top.hdf b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/system_top.hdf new file mode 100644 index 00000000..17ea33c4 Binary files /dev/null and b/projects/dl814_dj/dl814_dj_new_48m/project/project.sdk/system_top.hdf differ diff --git a/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_auto_switch_freq.v b/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_auto_switch_freq.v new file mode 100644 index 00000000..be7e9207 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_auto_switch_freq.v @@ -0,0 +1,211 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/05/06 15:37:29 +// Design Name: +// Module Name: rf_auto_switch_freq +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module rf_auto_switch_freq( + input clk , + input rst , + // vio control + input start , // rise-edge active, if start, change freq word to the first + input auto_test_enable , // rise-edge active + input rf_ctrl_mode , // 1 : auto switch, 0 : manual switch + input switch_next_freq , // rise-edge active + input switch_last_freq , // rise-edge active + input [31:0] cnt_valid_to_switch , // clock number from valid to switch + input [31:0] test_slot_length , + // input + input [11:0] freq_hop_words_vio , + input hop_words_valid_vio , + input freq_hop_switch_vio , + // output + output reg [11:0] freq_hop_words_auto = 12'd0 , + output reg hop_words_valid_auto = 1'd0 , + output reg freq_hop_switch_auto = 1'd0 , + output reg sync_signal = 1'b0 // sync signal from DJ to JD +); + +//************************* rise-edge detect *********************************** +reg start_d1 = 1'b0; +reg start_d2 = 1'b0; +reg start_pulse = 1'b0; +reg switch_next_freq_d1 = 1'b0; +reg switch_next_freq_d2 = 1'b0; +reg [9:0] switch_next_freq_pulse = 10'd0; +reg switch_last_freq_d1 = 1'b0; +reg switch_last_freq_d2 = 1'b0; +reg [9:0] switch_last_freq_pulse = 10'd0; +reg auto_test_enable_d1 = 1'b0; +reg auto_test_enable_d2 = 1'b0; +reg auto_test_enable_pulse = 1'b0; +always @ (posedge clk) + if(rst) begin + start_d1 <= 1'b0; + start_d2 <= 1'b0; + start_pulse <= 1'b0; + switch_next_freq_d1 <= 1'b0; + switch_next_freq_d2 <= 1'b0; + switch_next_freq_pulse <= 10'd0; + switch_last_freq_d1 <= 1'b0; + switch_last_freq_d2 <= 1'b0; + switch_last_freq_pulse <= 10'd0; + auto_test_enable_d1 <= 1'b0; + auto_test_enable_d2 <= 1'b0; + auto_test_enable_pulse <= 1'b0; + end else begin + start_d1 <= start; + start_d2 <= start_d1; + start_pulse <= start_d1 & ~start_d2; + switch_next_freq_d1 <= switch_next_freq; + switch_next_freq_d2 <= switch_next_freq_d1; + switch_next_freq_pulse[0] <= switch_next_freq_d1 & ~switch_next_freq_d2; + switch_next_freq_pulse[9:1] <= switch_next_freq_pulse[8:0]; + switch_last_freq_d1 <= switch_last_freq; + switch_last_freq_d2 <= switch_last_freq_d1; + switch_last_freq_pulse[0] <= switch_last_freq_d1 & ~switch_last_freq_d2; + switch_last_freq_pulse[9:1] <= switch_last_freq_pulse[8:0]; + auto_test_enable_d1 <= auto_test_enable; + auto_test_enable_d2 <= auto_test_enable_d1; + auto_test_enable_pulse <= auto_test_enable_d1 & ~auto_test_enable_d2; + end + +//************************ auto test logic ************************************* +reg auto_test_enable_reg = 1'b0; +reg [31:0] auto_test_cnt = 32'd0; +reg [7:0] freq_word_cnt = 8'd0; // range 0 -> 80 +always @ (posedge clk) + if(rst | start_pulse) + auto_test_enable_reg <= 1'b0; + else if(auto_test_enable_pulse && ~auto_test_enable_reg) + auto_test_enable_reg <= 1'b1; + else if(auto_test_cnt == test_slot_length && freq_word_cnt == 8'd80) + auto_test_enable_reg <= 1'b0; + +always @ (posedge clk) + if(rst | start_pulse) + auto_test_cnt <= 32'd0; + else if(auto_test_cnt == test_slot_length) + auto_test_cnt <= 32'd0; + else if(auto_test_enable_reg) + auto_test_cnt <= auto_test_cnt + 1'b1; + +//******************** local freq word control ********************************* +reg [11:0] local_freq_word = 12'd0; +reg local_freq_word_valid = 1'b0; +reg local_freq_word_switch = 1'b0; +wire [10:0] rom_freq_word_dout; +// 2 clock latency +rom_freq_word rom_freq_word_inst( + .clka (clk ), + .addra (freq_word_cnt[6:0] ), + .douta (rom_freq_word_dout ) +); + +always @ (posedge clk) + if(rst | start_pulse) + freq_word_cnt <= 8'd0; + else if(freq_word_cnt == 8'd80 && switch_next_freq_pulse[0]) + freq_word_cnt <= 8'd0; + else if(freq_word_cnt == 8'd80 && auto_test_cnt == test_slot_length) + freq_word_cnt <= 8'd0; + else if(freq_word_cnt == 8'd0 && switch_last_freq_pulse[0]) + freq_word_cnt <= 8'd80; + else if(auto_test_cnt == test_slot_length) + freq_word_cnt <= freq_word_cnt + 1'b1; + else if(switch_next_freq_pulse[0]) + freq_word_cnt <= freq_word_cnt + 1'b1; + else if(switch_last_freq_pulse[0]) + freq_word_cnt <= freq_word_cnt - 1'b1; + else + freq_word_cnt <= freq_word_cnt; + +always @ (posedge clk) + if(rst | start_pulse) + local_freq_word_valid <= 1'b0; + else if(switch_next_freq_pulse[4] | switch_last_freq_pulse[4] | auto_test_cnt == 32'd4) + local_freq_word_valid <= 1'b1; + else if(auto_test_cnt == 32'd104) + local_freq_word_valid <= 1'b0; + +reg [31:0] freq_word_valid_cnt = 32'd0; +always @ (posedge clk) + if(rst | start_pulse) + freq_word_valid_cnt <= 32'd0; + else if(freq_word_valid_cnt == cnt_valid_to_switch) + freq_word_valid_cnt <= 32'd0; + else if(local_freq_word_valid) + freq_word_valid_cnt <= freq_word_valid_cnt + 1'b1; + else if(freq_word_valid_cnt != 32'd0) + freq_word_valid_cnt <= freq_word_valid_cnt + 1'b1; + else + freq_word_valid_cnt <= freq_word_valid_cnt; + +always @ (posedge clk) + if(rst | start_pulse) + local_freq_word_switch <= 1'b0; + else if(freq_word_valid_cnt == cnt_valid_to_switch - 32'd100) + local_freq_word_switch <= 1'b1; + else if(freq_word_valid_cnt == cnt_valid_to_switch) + local_freq_word_switch <= 1'b0; + + + +always @ (posedge clk) + if(rst | start_pulse) + local_freq_word <= 12'd0; + else + local_freq_word <= rom_freq_word_dout; + +//******************** output freq switch signal ******************************* +// freq_hop_words_auto +always @ (posedge clk) + if(rst | start_pulse) + freq_hop_words_auto <= 12'd0; + else if(rf_ctrl_mode) + freq_hop_words_auto <= local_freq_word; + else + freq_hop_words_auto <= freq_hop_words_vio; + +// hop_words_valid_auto +always @ (posedge clk) + if(rst | start_pulse) + hop_words_valid_auto <= 1'b0; + else if(rf_ctrl_mode) + hop_words_valid_auto <= local_freq_word_valid; + else + hop_words_valid_auto <= hop_words_valid_vio; + +// freq_hop_switch_auto +always @ (posedge clk) + if(rst | start_pulse) + freq_hop_switch_auto <= 1'b0; + else if(rf_ctrl_mode) + freq_hop_switch_auto <= local_freq_word_switch; + else + freq_hop_switch_auto <= freq_hop_switch_vio; + +// sync_signal +always @ (posedge clk) + if(rst | start_pulse) + sync_signal <= 1'b0; + else if(~freq_hop_switch_auto & local_freq_word_switch) + sync_signal <= ~sync_signal; + +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_control.v b/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_control.v new file mode 100644 index 00000000..871af678 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/rtl/rf_control.v @@ -0,0 +1,457 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2022/01/13 12:04:17 +// Design Name: +// Module Name: rf_control +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module rf_control( + input clk , //192Mclk + input rst , + + input [5:0] tx_gain_manual , //发射增益输入 + input [5:0] rx_gain_manual , //接收增益输入 + + input gain_on_vio , //vio设置参数or自动切换 + input [1:0] rf_txrx_vio , //发射通道或者接收通道 + input [1:0] rf_txrx_net , //受网络层控制 + + input rf_vio_set , //vio设置参数or自动切换 + + input [11:0] tx_freq_hop_words , //tx跳频频率控制字 + input tx_hop_words_valid , //tx跳频频率控制字有效脉冲 + input tx_freq_hop_switch , //tx频点切换脉冲 + + input [11:0] rx_freq_hop_words , //rx跳频频率控制字 + input rx_hop_words_valid , //rx跳频频率控制字有效脉冲 + input rx_freq_hop_switch , //rx频点切换脉冲 + + input [11:0] freq_hop_words_vio , //vio设置跳频频率控制字 + input hop_words_valid_vio , //vio设置跳频频率控制字有效脉冲 + input freq_hop_switch_vio , //vio设置频点切换脉冲 + + // 新增4个引脚 + output reg clk_12M = 1'd0 , // 串行输入时钟 + output reg CS_rf = 1'd1 , // 发送使能输入CS + output reg tx_gain = 1'd0 , //发射通道增益 + input rx_gain , + + output reg tx_gain_on = 1'd0 , //发射通道开关 + // output reg rx_gain = 1'd0 , //接收通道增益 + output reg rx_gain_on = 1'd0 , //发射通道开关 + + output reg [11:0] freq_hop_words = 12'd0 , //跳频频率控制字 + output reg hop_words_valid = 1'd0 , //跳频频率控制字有效脉冲 + output reg freq_hop_switch = 1'd0 , //频点切换脉冲 + output reg freq_hop_switch_out = 1'd0 , + + output reg [11:0] freq_hop_words_sweep = 12'd0 + ); + + reg rst_D1_1 = 1'd0; + reg rst_D1_2 = 1'd0; + reg rst_D1_3 = 1'd0; + always @(posedge clk) begin + rst_D1_1 <= rst ; + rst_D1_2 <= rst ; + rst_D1_3 <= rst ; + + end + +//-------------------------------------------------------------------------------------------------- + +//发射通道增益、开关设置 + always @(posedge clk) begin + if(rst_D1_1) + tx_gain_on <= 1'b0 ; + else if(gain_on_vio) + tx_gain_on <= (rf_txrx_vio[1:0] == 2'd1) ? 1'd1 :1'd0 ; + else + tx_gain_on <= (rf_txrx_net[1:0] == 2'd1) ? 1'd1 :1'd0 ; + end + +//-------------------------------------------------------------------------------------------------- +//接收通道增益、开关设置 + reg [5:0] rx_gain_div2 = 5'd0; + always @(posedge clk) begin + if(rst_D1_2) + rx_gain_on <= 1'b0 ; + else if(gain_on_vio) + rx_gain_on <= (rf_txrx_vio[1:0] == 2'd2) ? 1'd1 :1'd0 ; + else + rx_gain_on <= (rf_txrx_net[1:0] == 2'd2) ? 1'd1 :1'd0 ; + end +//-------------------------------------------------------------------------------------------------- +//跳频设置vio控制or网络层设置 + reg [11:0] freq_hop_words_net = 12'd0 ; + reg hop_words_valid_net = 1'd0 ; + reg freq_hop_switch_net = 1'd0 ; + + + always @(posedge clk) begin + if(rst_D1_3)begin + freq_hop_words_net [11:0] <= 12'd0 ; + hop_words_valid_net <= 1'd0 ; + freq_hop_switch_net <= 1'd0 ; + end + else if(rf_txrx_net[1:0] == 2'd1)begin + freq_hop_words_net [11:0] <= tx_freq_hop_words[11:0] ; + hop_words_valid_net <= tx_hop_words_valid ; + freq_hop_switch_net <= tx_freq_hop_switch ; + end + else if(rf_txrx_net[1:0] == 2'd2)begin + freq_hop_words_net [11:0] <= rx_freq_hop_words[11:0] ; + hop_words_valid_net <= rx_hop_words_valid ; + freq_hop_switch_net <= rx_freq_hop_switch ; + end + else begin + freq_hop_words_net [11:0] <= freq_hop_words_net [11:0] ; + hop_words_valid_net <= 1'd0 ; + freq_hop_switch_net <= 1'd0 ; + end + + end + + // reg [11:0] freq_hop_words_sweep = 12'd0; + reg hop_words_valid_sweep = 1'd0; + reg freq_hop_switch_sweep = 1'd0; + + reg hop_words_valid_manual = 1'd0; + reg freq_hop_switch_manual = 1'd0; + + reg [11:0] freq_hop_words_manual = 12'd0 ; + + wire freq_swicth_start; + always @(posedge clk) begin + if(rst_D1_3)begin + freq_hop_words [11:0] <= 12'd0 ; + hop_words_valid <= 1'd0 ; + freq_hop_switch <= 1'd0 ; + freq_hop_switch_out <= 1'd0 ; + end + else if(rf_vio_set)begin // rf_vio_set为1频率控制字控 + freq_hop_words [11:0] <= freq_hop_words_vio[11:0] ; + hop_words_valid <= hop_words_valid_vio ; + freq_hop_switch <= freq_hop_switch_vio ; + freq_hop_switch_out <= freq_hop_switch_vio ; + end + else if(freq_swicth_start)begin + freq_hop_words [11:0] <= freq_hop_words_sweep[11:0] ; + hop_words_valid <= hop_words_valid_sweep ; + freq_hop_switch <= freq_hop_switch_sweep ; + freq_hop_switch_out <= freq_hop_switch_sweep ; + end + else begin + freq_hop_words [11:0] <= freq_hop_words_manual[11:0] ; + hop_words_valid <= hop_words_valid_manual ; + freq_hop_switch <= freq_hop_switch_manual ; + freq_hop_switch_out <= freq_hop_switch_manual ; + end + end + + + + // 12M时钟生成 + // reg clk_12M = 1'd0 ; + reg [2:0] cnt_8 = 3'd0 ; + reg clk_switch = 1'd0 ; + // 8位计数器 + always@(posedge clk) begin + if(rst_D1_1) begin + cnt_8 <= 3'd0 ; + clk_switch <= 1'd0 ; + end + else if(cnt_8 == 3'd7)begin + cnt_8 <= 3'd0 ; + clk_switch <= 1'd1 ; + end + else begin + cnt_8 <= cnt_8 + 3'd1 ; + clk_switch <= 1'd0 ; + end + end + + always@(posedge clk) begin // 产生12M时钟 + if(clk_switch == 1'd1)begin + clk_12M <= ~clk_12M ; + end + else begin + clk_12M <= clk_12M ; + end + end + + // 发送使能输入 + // reg CS_rf = 1'd1; + wire CS_rf_flag; + reg CS_rf_flag_D1 = 1'd0; + wire [31:0] cnt_frechange_top ; + wire [31:0] switch_delay_time ; + wire freq_hop_change ; + + wire [11:0] freq_hop_words_vio1 ; + wire [11:0] freq_hop_words_vio2 ; + wire [31:0] valid_delay_time_max ; + wire [63:0] slot_vio_time ; + wire [4:0] cnt_slot_max ; + wire [7:0] MOSI_tx_atte ; + wire [7:0] MOSI_rx_atte ; + // 发送使能输入vio_rftx_en +vio_rf_test vio_rf_test ( + .clk(clk_12M), // input wire clk + .probe_out0(CS_rf_flag), // output wire [0 : 0] probe_out0 + .probe_out1(MOSI_tx_atte), // output wire [0 : 0] probe_out0 + .probe_out2(MOSI_rx_atte), // output wire [0 : 0] probe_out0 + .probe_out3(cnt_frechange_top), + .probe_out4(freq_hop_change), // 切换频率开始 + .probe_out5(freq_hop_words_vio1[11:0]), + .probe_out6(freq_hop_words_vio2[11:0]), + .probe_out7(switch_delay_time[31:0]), // valid和switch之间的时间 + .probe_out8(valid_delay_time_max[31:0]), // valid和switch的切换时间 + .probe_out9(slot_vio_time[63:0]), // 一个频点的时间 + .probe_out10(cnt_slot_max[4:0]), + .probe_out11(freq_swicth_start) +); + +always@(posedge clk_12M)begin + CS_rf_flag_D1 <= CS_rf_flag; +end + + // 中频-射频数据输出MOSI + reg MOSI = 1'd0 ; + wire [31:0] MOSI_data; + reg [7:0] MOSI_head = 8'h5A; + // wire [7:0] MOSI_tx_atte ; + // wire [7:0] MOSI_rx_atte ; + reg [7:0] MOSI_recv = 8'hA5; + + assign MOSI_data = {MOSI_head,MOSI_tx_atte,MOSI_rx_atte,MOSI_recv}; + +reg [3:0] state_MOSI = 4'd0; +reg [7:0] cnt_64 = 8'd0; + +always@(posedge clk_12M) begin + if(rst_D1_1) begin + state_MOSI <= 4'd0; + cnt_64 <= 8'd0; + end + else begin + case(state_MOSI) + 4'd0:begin // 等待发送指令 + if(CS_rf_flag && !CS_rf_flag_D1)begin + state_MOSI <= 4'd1; + end + else begin + state_MOSI <= 4'd0; + end + end + + 4'd1:begin // 发送数据 + CS_rf <= 1'd0; + if(cnt_64 == 8'd31)begin + cnt_64 <= 8'd0; + tx_gain <= MOSI_data[0]; + state_MOSI <= 4'd2; + end + else begin + cnt_64 <= cnt_64 + 8'd1; + tx_gain <= MOSI_data[31 - cnt_64]; + state_MOSI <= 4'd1; + end + end + + 4'd2:begin + CS_rf <= 1'd1; + state_MOSI <= 4'd0; + tx_gain <= 1'd0; + end + endcase + end +end + + +// 扫频信号 +// 通过vio选择控制频点的方式 + +reg [31:0] cnt_frechange; + +always@(posedge clk) begin + if(rst_D1_1)begin + cnt_frechange <= 32'd0; + end + else begin + if(cnt_frechange == cnt_frechange_top) begin + cnt_frechange <= 32'd0; + end + else begin + cnt_frechange <= cnt_frechange + 32'd1; + end + end +end + + +always@(posedge clk) begin + if(rst_D1_2)begin + freq_hop_words_sweep <= 12'd0; + hop_words_valid_sweep <= 1'd0; + freq_hop_switch_sweep <= 1'd0; + end + else if(cnt_frechange == cnt_frechange_top) begin + if(freq_hop_words_sweep == 12'd3500) begin + freq_hop_words_sweep <= 12'd0; + end + else begin + freq_hop_words_sweep <= freq_hop_words_sweep + 12'd1; + end + hop_words_valid_sweep <= 1'd0; + freq_hop_switch_sweep <= 1'd1; + end + else if(cnt_frechange == cnt_frechange_top - 32'd1920000) begin + freq_hop_words_sweep <= freq_hop_words_sweep; + hop_words_valid_sweep <= 1'd1; + freq_hop_switch_sweep <= 1'd0; + end + else begin + freq_hop_words_sweep <= freq_hop_words_sweep; + hop_words_valid_sweep <= 1'd0; + freq_hop_switch_sweep <= 1'd0; + end +end + +// 控制时隙长短 +reg [31:0] delay_time = 32'd0; +reg hop_words_valid_manual_long = 1'd0; +reg [31:0] valid_delay_time = 32'd0; +reg [31:0] freq_hop_switch_delay_time = 32'd0; +reg [63:0] slot_time_cnt = 64'd0; + + +reg [4:0] state_vio_time = 5'd0; +reg [4:0] cnt_slot = 5'd0; + +reg freq_hop_change_D1 = 1'd0; +reg freq_hop_change_D2 = 1'd0; +reg freq_hop_change_D3 = 1'd0; + +always@(posedge clk) begin + freq_hop_change_D1 <= freq_hop_change; + freq_hop_change_D2 <= freq_hop_change_D1; + freq_hop_change_D3 <= freq_hop_change_D2; +end + +always@(posedge clk) begin + if(rst_D1_1) begin + state_vio_time <= 5'd0; + freq_hop_words_manual <= freq_hop_words_vio1; + end + else begin + case(state_vio_time) + 5'd0:begin // 等待切换频率开始 + if(!freq_hop_change_D1 && freq_hop_change)begin + state_vio_time <= 5'd1; + slot_time_cnt <= 64'd1 + slot_time_cnt; + + if(freq_hop_words_manual == freq_hop_words_vio1) begin + freq_hop_words_manual <= freq_hop_words_vio2; + end + else if(freq_hop_words_manual == freq_hop_words_vio2) begin + freq_hop_words_manual <= freq_hop_words_vio1; + end + else begin + freq_hop_words_manual <= freq_hop_words_vio1; + end + end + else begin + state_vio_time <= 5'd0; + freq_hop_words_manual <= freq_hop_words_manual; + end + end + + 5'd1:begin // 等待valid信号拉高完毕 + if(valid_delay_time == valid_delay_time_max) begin + hop_words_valid_manual <= 1'd0; + valid_delay_time <= 32'd0; + state_vio_time <= 5'd2; + end + else begin + hop_words_valid_manual <= 1'd1; + valid_delay_time <= valid_delay_time + 32'd1; + state_vio_time <= 5'd1; + end + slot_time_cnt <= 64'd1 + slot_time_cnt; + end + + 5'd2:begin // 等待switch信号 + if(delay_time == switch_delay_time) begin + freq_hop_switch_manual <= 1'd1; + delay_time <= 32'd0; + state_vio_time <= 5'd3; + end + else begin + freq_hop_switch_manual <= 1'd0; + delay_time <= 32'd1 + delay_time; + state_vio_time <= 5'd2; + end + slot_time_cnt <= 64'd1 + slot_time_cnt; + end + + 5'd3:begin // 等待switch信号拉高完毕 + if(freq_hop_switch_delay_time == valid_delay_time_max) begin + freq_hop_switch_manual <= 1'd0; + freq_hop_switch_delay_time <= 32'd0; + state_vio_time <= 5'd4; + end + else begin + freq_hop_switch_manual <= 1'd1; + freq_hop_switch_delay_time <= freq_hop_switch_delay_time + 32'd1; + state_vio_time <= 5'd3; + end + slot_time_cnt <= 64'd1 + slot_time_cnt; + end + + 5'd4:begin // 等待时隙结束 + if(slot_time_cnt == slot_vio_time)begin + if(cnt_slot == cnt_slot_max - 5'd1) begin + cnt_slot <= 5'd0; + state_vio_time <= 5'd0; + slot_time_cnt <= 64'd0; + end + else begin + state_vio_time <= 5'd1; + slot_time_cnt <= 64'd0; + cnt_slot <= cnt_slot + 5'd1; + end + end + else begin + state_vio_time <= 5'd4; + slot_time_cnt <= 64'd1 + slot_time_cnt; + cnt_slot <= cnt_slot; + end + end + default:begin + if(!freq_hop_change_D1 && freq_hop_change)begin + state_vio_time <= 5'd1; + end + else begin + state_vio_time <= 5'd0; + end + end + + endcase + end +end + +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v b/projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v new file mode 100644 index 00000000..a670cfd4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/rtl/system_top.v @@ -0,0 +1,505 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/06/07 21:17:23 +// Design Name: +// Module Name: system_top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module system_top +( + // ************************************************************************* + // *************************** Clocks and Resets *************************** + // ************************************************************************* + input sysclk_p , // FPGA_LOGIC_CLK_IN, derived from ad9528, 122.88mhz + input sysclk_n , + input refclk_p , // FPGA_JESD204B_CLK_IN_1, derived from ad9528, 122.88mhz + input refclk_n , + input sysref_p , + input sysref_n , + // ************************************************************************* + // *************************** AD9528 Interface **************************** + // ************************************************************************* + // spi interface + output spi_csn_ad9528 , + output spi_clk_ad9528 , + output spi_mosi_ad9528 , + input spi_miso_ad9528 , + // control signals + output ad9528_reset_b , + output ad9528_sysref_req , + // ************************************************************************* + // *************************** AD9371 Interface **************************** + // ************************************************************************* + // 204b interface, only lane 0 and lane 1 are used + output rx_sync_p , + output rx_sync_n , + input tx_sync_p , + input tx_sync_n , + input [ 1:0] rx_data_p , + input [ 1:0] rx_data_n , + output [ 1:0] tx_data_p , + output [ 1:0] tx_data_n , + // spi interface + output spi_csn_ad9371 , + output spi_clk_ad9371 , + output spi_mosi_ad9371 , + input spi_miso_ad9371 , + // control signals + output ad9371_test , + output ad9371_reset_b , + input ad9371_gpint , + // ************************************************************************* + // ****************************** RF Control ******************************* + // ************************************************************************* + output tx_gain , + input rx_gain , + output clk_12M , + output CS_rf , + + output tx_gain_on , + output rx_gain_on , + + output [11:0] freq_hop_words , + output hop_words_valid , + output freq_hop_switch , + // ************************************************************************* + // ******************* DDR and Fixed-io (Do NOT Modify) ******************** + // ************************************************************************* + // ddr + inout [14:0] ddr_addr , + inout [ 2:0] ddr_ba , + inout ddr_cas_n , + inout ddr_ck_n , + inout ddr_ck_p , + inout ddr_cke , + inout ddr_cs_n , + inout [ 3:0] ddr_dm , + inout [31:0] ddr_dq , + inout [ 3:0] ddr_dqs_n , + inout [ 3:0] ddr_dqs_p , + inout ddr_odt , + inout ddr_ras_n , + inout ddr_reset_n , + inout ddr_we_n , + // fixed-io + inout fixed_io_ddr_vrn , + inout fixed_io_ddr_vrp , + inout [53:0] fixed_io_mio , + inout fixed_io_ps_clk , + inout fixed_io_ps_porb , + inout fixed_io_ps_srstb , + // ************************************************************************* + // ************************* Sync Signal *********************************** + // ************************************************************************* + output sync_signal_out , + output reg sync_gnd = 1'b0 +); + + +//////////////////////////////////////////////////////////////////////////////// +/////////////////////////// System Clock Generation //////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// system main clock, mmcm is included in block design +wire sys_clk ; // 122.88mhz +wire sys_clk_2x ; // 245.76mhz +wire sys_rst ; + +// optional siganl clock, can be changed to whatever frequency you want +wire sig_clk ; // 245.76mhz +wire sig_clk_ld ; +wire sig_rst ; + +assign sig_rst = ~sig_clk_ld; + +sig_clk_gen u_sig_clk_gen +( + // Clock out ports + .clk_out1 (sig_clk ), // output clk_out1 + // Status and control signals + .reset (sys_rst ), // input reset + .locked (sig_clk_ld ), // output locked + // Clock in ports + .clk_in1 (sys_clk ) // input clk_in1 +); + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// Block Design Interface //////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// gpio +wire [15:0] gpio_i ; +wire [15:0] gpio_o ; + +assign gpio_i[15:5] = gpio_o[15:5]; + +assign ad9528_reset_b = gpio_o[4]; // ad9528 reset pin +assign ad9528_sysref_req = gpio_o[3]; // ad9528 sysref requset pin +assign ad9371_test = gpio_o[2]; +assign ad9371_reset_b = gpio_o[1]; +assign gpio_i[0] = ad9371_gpint ; // ad9371 gpio interrupt pin + +// ad9371 jesd204b signals +wire rx_rstn ; +wire [63:0] rx_tdata ; +wire rx_tvalid ; +wire tx_rstn ; +wire [63:0] tx_tdata ; +wire tx_tready ; + +// spi interface +wire spi_clk ; +wire spi_mosi ; +reg spi_miso ; + +assign spi_clk_ad9528 = spi_clk ; +assign spi_clk_ad9371 = spi_clk ; +assign spi_mosi_ad9528 = spi_mosi ; +assign spi_mosi_ad9371 = spi_mosi ; + +always @(*) begin + if (~spi_csn_ad9528) + spi_miso = spi_miso_ad9528; + else if (~spi_csn_ad9371) + spi_miso = spi_miso_ad9371; + else + spi_miso = 1'bz; +end + +system_bd_wrapper u_system_bd +( + // ddr + .ddr_addr (ddr_addr ), // inout [14:0]ddr_addr + .ddr_ba (ddr_ba ), // inout [2:0]ddr_ba + .ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n + .ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n + .ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p + .ddr_cke (ddr_cke ), // inout ddr_cke + .ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n + .ddr_dm (ddr_dm ), // inout [3:0]ddr_dm + .ddr_dq (ddr_dq ), // inout [31:0]ddr_dq + .ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n + .ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p + .ddr_odt (ddr_odt ), // inout ddr_odt + .ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n + .ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n + .ddr_we_n (ddr_we_n ), // inout ddr_we_n + + // fixed io + .fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn + .fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp + .fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio + .fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk + .fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb + .fixed_io_ps_srstb (fixed_io_ps_srstb ), // inout fixed_io_ps_srstb + + // gpio, for control signals + .gpio_i (gpio_i[15:0] ), // input [15:0]gpio_i + .gpio_o (gpio_o[15:0] ), // output [15:0]gpio_o + + // spi interface + .spi_miso (spi_miso ), // input spi_miso + .spi_mosi (spi_mosi ), // output spi_mosi + .spi_sclk (spi_clk ), // output spi_sclk + .spi_ss_0 (spi_csn_ad9528 ), // output spi_ss_0 + .spi_ss_1 (spi_csn_ad9371 ), // output spi_ss_1 + .spi_ss_2 ( ), // output spi_ss_2 + + // system main clock + .sysclk_p (sysclk_p ), // input sysclk_p + .sysclk_n (sysclk_n ), // input sysclk_n + .sys_clk (sys_clk ), // output sys_clk + .sys_rst (sys_rst ), // output sys_rst + + // jesd 204b interface + .refclk_p (refclk_p ), // input refclk_p + .refclk_n (refclk_n ), // input refclk_n + .sysref_p (sysref_p ), // input sysref_p + .sysref_n (sysref_n ), // input sysref_n + + .rxp_in (rx_data_p[1:0] ), // input [1:0]rxp_in + .rxn_in (rx_data_n[1:0] ), // input [1:0]rxn_in + .rx_sync_p (rx_sync_p ), // output rx_sync_p + .rx_sync_n (rx_sync_n ), // output rx_sync_n + .rx_rstn (rx_rstn ), // output rx_rstn + .rx_tdata (rx_tdata[63:0] ), // output [63:0]rx_tdata + .rx_tvalid (rx_tvalid ), // output rx_tvalid + + .txp_out (tx_data_p[1:0] ), // output [1:0]txp_out + .txn_out (tx_data_n[1:0] ), // output [1:0]txn_out + .tx_sync_p (tx_sync_p ), // input tx_sync_p + .tx_sync_n (tx_sync_n ), // input tx_sync_n + .tx_rstn (tx_rstn ), // output tx_rstn + .tx_tdata (tx_tdata[63:0] ), // input [63:0]tx_tdata + .tx_tready (tx_tready ) // output tx_tready +); + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// RF Control Interface ////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +wire gain_on_vio ; +wire [1:0] rf_txrx_vio ; +wire rf_vio_set ; + +wire [5:0] tx_gain_manual ; +wire [5:0] rx_gain_manual ; + +wire [11:0] freq_hop_words_vio ; +wire hop_words_valid_vio ; +wire freq_hop_switch_vio ; + +wire freq_hop_switch_out ; +wire [11:0] freq_hop_words_sweep; + +// rf auto switch frequency function +wire auto_test_enable_vio; +wire rf_auto_start_vio ; +wire rf_ctrl_mode_vio ; +wire switch_next_freq_vio; +wire switch_last_freq_vio; +wire [31:0] cnt_valid_to_switch_vio; +wire [31:0] test_slot_length_vio; + +wire [11:0] freq_hop_words_auto ; +wire hop_words_valid_auto; +wire freq_hop_switch_auto; + +rf_auto_switch_freq u_rf_auto_switch_freq +( + .clk (sys_clk ), + .rst (sys_rst ), + + // vio control + .start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first + .auto_test_enable (auto_test_enable_vio ), // rise-edge active + .rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch + .switch_next_freq (switch_next_freq_vio ), // rise-edge active + .switch_last_freq (switch_last_freq_vio ), // rise-edge active + .cnt_valid_to_switch (cnt_valid_to_switch_vio ), // the clock number from valid to switch + .test_slot_length (test_slot_length_vio[31:0] ), + + // input + .freq_hop_words_vio (freq_hop_words_vio[11:0] ), + .hop_words_valid_vio (hop_words_valid_vio ), + .freq_hop_switch_vio (freq_hop_switch_vio ), + + // output + .freq_hop_words_auto (freq_hop_words_auto[11:0] ), + .hop_words_valid_auto (hop_words_valid_auto ), + .freq_hop_switch_auto (freq_hop_switch_auto ), + .sync_signal (sync_signal_out ) +); + +rf_control u_rf_control +( + .clk (sys_clk ), + .rst (sys_rst ), + + //input + .gain_on_vio (gain_on_vio ), + .rf_txrx_vio (rf_txrx_vio[1:0] ), + .rf_txrx_net (2'd0 ), + .tx_gain_manual (tx_gain_manual[5:0] ), + .rx_gain_manual (rx_gain_manual[5:0] ), + + //0:net->control 1:vio->control + .rf_vio_set (rf_vio_set ), + + //vio hop control + .freq_hop_words_vio (freq_hop_words_auto[10:0] ), + .hop_words_valid_vio (hop_words_valid_auto ), + .freq_hop_switch_vio (freq_hop_switch_auto ), + + //tx hop control + .tx_freq_hop_words (11'b0 ), + .tx_hop_words_valid (1'b0 ), + .tx_freq_hop_switch (1'b0 ), + + //rx hop control + .rx_freq_hop_words (11'b0 ), + .rx_hop_words_valid (1'b0 ), + .rx_freq_hop_switch (1'b0 ), + + //output + .clk_12M (clk_12M ), + .CS_rf (CS_rf ), + .tx_gain (tx_gain ), + .tx_gain_on (tx_gain_on ), + .rx_gain (rx_gain ), + .rx_gain_on (rx_gain_on ), + + .freq_hop_words (freq_hop_words[11:0] ), + .hop_words_valid (hop_words_valid ), + .freq_hop_switch (freq_hop_switch ), + .freq_hop_switch_out (freq_hop_switch_out ), + .freq_hop_words_sweep (freq_hop_words_sweep ) +); + + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////// Tx Baseband Signals ////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// baseband signal +wire [15:0] tx_1_i; +wire [15:0] tx_1_q; +wire [15:0] tx_2_i; +wire [15:0] tx_2_q; + +assign tx_tdata = +{ + tx_2_q[7:0], tx_2_q[15:8], tx_2_i[7:0], tx_2_i[15:8], + tx_1_q[7:0], tx_1_q[15:8], tx_1_i[7:0], tx_1_i[15:8] +}; + +wire [15:0] tx_data_i; +wire [15:0] tx_data_q; + +assign tx_1_i = tx_data_i; +assign tx_1_q = tx_data_q; +assign tx_2_i = tx_data_i; +assign tx_2_q = tx_data_q; + +// <---------------------------------------------------------------------------> +// <--------------------- insert transmitter logic below ----------------------> +// <---------------------------------------------------------------------------> +wire [ 2:0] waveform_sel; +wire sweep_on ; +wire [31:0] freq_set ; +wire [ 1:0] iq_sel ; +wire [ 3:0] bb_rshift ; + +tx_control u_tx_wave +( + .sys_clk (sys_clk ), // input sys_clk + .sys_rst (sys_rst ), // input sys_rst + .sig_clk (sig_clk ), // input sig_clk + .sig_rst (sig_rst ), // input sig_rst + .tx_data_i (tx_data_i ), // output [15:0] tx_data_i + .tx_data_q (tx_data_q ), // output [15:0] tx_data_q + // debug ports + .waveform_sel (waveform_sel ), // input [ 2:0] waveform_sel + .sweep_on (sweep_on ), // input sweep_on + .freq_set (freq_set ), // input [31:0] freq_set + .iq_sel (iq_sel ), // input [ 1:0] iq_sel + .bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift +); + + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////// Rx Baseband Signals ////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// rx signal +wire [15:0] rx_1_i; +wire [15:0] rx_1_q; +wire [15:0] rx_2_i; +wire [15:0] rx_2_q; + +assign rx_1_i = { rx_tdata[ 7: 0] , rx_tdata[15: 8]}; +assign rx_1_q = { rx_tdata[23:16] , rx_tdata[31:24]}; + +assign rx_2_i = { rx_tdata[39:32] , rx_tdata[47:40]}; +assign rx_2_q = { rx_tdata[55:48] , rx_tdata[63:56]}; + +// <---------------------------------------------------------------------------> +// <----------------------- insert receiver logic below -----------------------> +// <---------------------------------------------------------------------------> + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////// ILAs and VIOs ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +ila_2x16x131072 u_ila_tx +( + .clk (sys_clk ), // input wire clk + .probe0 (tx_data_i ), // input wire [15:0] probe0 + .probe1 (tx_data_q ) // input wire [15:0] probe1 +); + +ila_4x16x131072 u_ila_rx +( + .clk (sys_clk ), // input wire clk + .probe0 (rx_1_i ), // input wire [15:0] probe0 + .probe1 (rx_1_q ), // input wire [15:0] probe1 + .probe2 (rx_2_i ), // input wire [15:0] probe2 + .probe3 (rx_2_q ) // input wire [15:0] probe3 +); + +ila_ctrl_signal u_ila_ctrl_signal +( + .clk (sys_clk ), // input wire clk + .probe0 (u_system_bd.system_bd_i.jesd204b.jesd_reset ), // input wire [0:0] probe0 + .probe1 (u_system_bd.system_bd_i.jesd204b.rx_sync ), // input wire [0:0] probe1 + .probe2 (rx_rstn ), // input wire [0:0] probe2 + .probe3 (u_system_bd.system_bd_i.jesd204b.tx_sync ), // input wire [0:0] probe3 + .probe4 (tx_rstn ), // input wire [0:0] probe4 + .probe5 (u_system_bd.system_bd_i.jesd204b.sysref ) // input wire [0:0] probe5 +); + +vio_manual_ctrl u_vio_manual_ctrl +( + .clk (sys_clk ), // input wire clk + .probe_out0 (waveform_sel ), // output wire [2 : 0] probe_out0 + .probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1 + .probe_out2 (freq_set ), // output wire [31 : 0] probe_out2 + .probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3 + .probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4 +); + +vio_rf_control u_vio_rf_control +( + .clk (sys_clk ), // input wire clk + .probe_out0 (gain_on_vio ), // output wire [0 : 0] probe_out0 + .probe_out1 (rf_txrx_vio[1:0] ), // output wire [1 : 0] probe_out1 + .probe_out2 (rf_vio_set ), // output wire [0 : 0] probe_out2 + .probe_out3 (tx_gain_manual[5:0] ), // output wire [5 : 0] probe_out3 + .probe_out4 (rx_gain_manual[5:0] ), // output wire [5 : 0] probe_out4 + .probe_out5 (freq_hop_words_vio[11:0] ), // output wire [10 : 0] probe_out5 + .probe_out6 (hop_words_valid_vio ), // output wire [0 : 0] probe_out6 + .probe_out7 (freq_hop_switch_vio ), // output wire [0 : 0] probe_out7 + .probe_out8 (self_check_dout ), // output wire [0 : 0] probe_out8 + .probe_out9 (rf_auto_start_vio ), // output wire [0 : 0] probe_out9 + .probe_out10 (rf_ctrl_mode_vio ), // output wire [0 : 0] probe_out10 + .probe_out11 (switch_next_freq_vio ), // output wire [0 : 0] probe_out11 + .probe_out12 (switch_last_freq_vio ), // output wire [0 : 0] probe_out12 + .probe_out13 (cnt_valid_to_switch_vio[31:0] ), // output wire [31: 0] probe_out13 + .probe_out14 (auto_test_enable_vio ), // output wire [0 : 0] probe_out14 + .probe_out15 (test_slot_length_vio[31:0] ), // output wire [31: 0] probe_out15 + .probe_in0 (freq_hop_words_auto[10:0] ) // input wire [10: 0] probe_in0 +); + +ila_rf_test ila_rf_test +( + .clk (sys_clk ), // input wire clk + .probe0 (freq_hop_words[11:0] ), // input wire [11:0] probe0 + .probe1 (tx_gain_on ), // input wire [0:0] probe1 + .probe2 (rx_gain ), // input wire [0:0] probe2 + .probe3 (rx_gain_on ), // input wire [0:0] probe3 + .probe4 (tx_gain ), // input wire [0:0] probe4 + .probe5 (hop_words_valid ), // input wire [0:0] probe5 + .probe6 (freq_hop_switch ), // input wire [0:0] probe6 + .probe7 (clk_12M ), // input wire [0:0] probe7 + .probe8 (CS_rf ), // input wire [0:0] probe8 + .probe9 (freq_hop_words_sweep ) // input wire [11:0] probe9 +); + +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/rtl/tx_control.v b/projects/dl814_dj/dl814_dj_new_48m/rtl/tx_control.v new file mode 100644 index 00000000..1757c6d8 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/rtl/tx_control.v @@ -0,0 +1,103 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/03/21 18:35:38 +// Design Name: +// Module Name: tx_control +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tx_control +( + input sys_clk , // 122.88MHz + input sys_rst , + input sig_clk , // 48MHz + input sig_rst , + + output [15:0] tx_data_i , + output [15:0] tx_data_q , + // debug ports + input [ 2:0] waveform_sel , + input sweep_on , + input [31:0] freq_set , + input [ 1:0] iq_sel , + input [ 3:0] bb_rshift +); + +// pn seq +wire [15:0] tx_pn_seq_i; +wire [15:0] tx_pn_seq_q; + +tx_pn_seq_6mcps #( + .DATA_WIDTH (16), + .BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001), + .BIT_DATA_LEN (1024) +) u_tx_pn_seq +( + .sys_clk (sys_clk ), // 122.88MHz + .sys_rst (sys_rst ), + .sig_clk (sig_clk ), // 48MHz + .sig_rst (sig_rst ), + + .tx_data_i (tx_pn_seq_i), + .tx_data_q (tx_pn_seq_q) +); + +// qpsk +wire [15:0] tx_qpsk_i; +wire [15:0] tx_qpsk_q; + +tx_qpsk #( + .DATA_WIDTH (16 ), + .SQUARE_INTERP (32 ), + .CLK_FREQ (122880000 ) +) u_tx_qpsk +( + .clk (sys_clk ), + .rst (sys_rst ), + .tx_data_i (tx_qpsk_i ), + .tx_data_q (tx_qpsk_q ), + // debug ports + .waveform_sel (waveform_sel[1:0] ), + .sweep_on (sweep_on ), + .freq_set (freq_set ), + .iq_sel (iq_sel ), + .bb_rshift (bb_rshift ) +); + +// output +reg [15:0] tx_data_buf_i = 'b0; +reg [15:0] tx_data_buf_q = 'b0; + +assign tx_data_i = tx_data_buf_i; +assign tx_data_q = tx_data_buf_q; + +always @(posedge sys_clk) begin + if (sys_rst) begin + tx_data_buf_i <= 'b0; + tx_data_buf_q <= 'b0; + end + else if (waveform_sel[2]) begin + tx_data_buf_i <= tx_pn_seq_i; + tx_data_buf_q <= tx_pn_seq_q; + end + else begin + tx_data_buf_i <= tx_qpsk_i; + tx_data_buf_q <= tx_qpsk_q; + end +end + +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/rtl/tx_pn_seq_6mcps.v b/projects/dl814_dj/dl814_dj_new_48m/rtl/tx_pn_seq_6mcps.v new file mode 100644 index 00000000..e2e255d5 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/rtl/tx_pn_seq_6mcps.v @@ -0,0 +1,152 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/03/21 16:09:18 +// Design Name: +// Module Name: tx_pn_seq_6mcps +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tx_pn_seq_6mcps +#( + parameter DATA_WIDTH = 12, // need to be <= 16 + parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)] + parameter BIT_DATA_LEN = 128, + parameter SQUARE_INTERP = 8 +) +( + input sys_clk , // 122.88MHz + input sys_rst , + input sig_clk , // 48MHz + input sig_rst , + + output [DATA_WIDTH-1:0] tx_data_i , + output [DATA_WIDTH-1:0] tx_data_q +); + +localparam MAX_DATA_WIDTH = 16; + +integer i; +genvar m; + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////////// Data Counter ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// symbol & interpolation counter +reg [$clog2(SQUARE_INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0; + +always @(posedge sig_clk) begin + if (sig_rst) begin + cnt <= 'b0; + end + else begin + cnt <= (cnt == SQUARE_INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1; + end +end + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// Square Shaping Filter ///////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// address +reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0; + +always @(posedge sig_clk) begin + if (sig_rst) begin + hsq_data_addr <= 'b0; + end + else + hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]}; +end + +// bit data +reg hsq_data = 'b0; + +always @(posedge sig_clk) begin + if (sig_rst) begin + hsq_data <= 'b0; + end + else begin + hsq_data <= BIT_DATA[hsq_data_addr]; + end +end + +// square shaping-filter +reg [MAX_DATA_WIDTH-1 : 0] hsq_wave [0:1]; + +always @(posedge sig_clk) begin + if (sig_rst) begin + for (i = 0; i < 2; i = i + 1) begin + hsq_wave[i] <= 'b0; + end + end + else begin + hsq_wave[0] <= hsq_data ? {1'b0,{(MAX_DATA_WIDTH-2){1'b1}},1'b1} : {1'b1,{(MAX_DATA_WIDTH-2){1'b0}},1'b1}; + hsq_wave[1] <= hsq_data ? {1'b1,{(MAX_DATA_WIDTH-2){1'b0}},1'b1} : {1'b0,{(MAX_DATA_WIDTH-2){1'b1}},1'b1}; + end +end + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////////////// Resampling ////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +wire cdc_fifo_s_axis_valid [0:1]; +wire cdc_fifo_s_axis_ready [0:1]; +wire [15:0] cdc_fifo_s_axis_tdata [0:1]; + +wire lpf_s_axis_valid [0:1]; +wire lpf_s_axis_ready [0:1]; +wire [15:0] lpf_s_axis_tdata [0:1]; + +wire lpf_m_axis_valid [0:1]; +wire [39:0] lpf_m_axis_tdata [0:1]; + +generate +for (m = 0; m < 2; m = m + 1) begin: cdc_resample + +assign cdc_fifo_s_axis_tdata[m] = hsq_wave[m]; +assign cdc_fifo_s_axis_valid[m] = ~sig_rst; + +fifo_48m_to_122p88m u_fifo_cdc +( + .wr_rst_busy ( ), // output wire wr_rst_busy + .rd_rst_busy ( ), // output wire rd_rst_busy + .m_aclk (sys_clk ), // input wire m_aclk + .s_aclk (sig_clk ), // input wire s_aclk + .s_aresetn (~sig_rst ), // input wire s_aresetn + .s_axis_tvalid (cdc_fifo_s_axis_valid[m] ), // input wire s_axis_tvalid + .s_axis_tready (cdc_fifo_s_axis_ready[m] ), // output wire s_axis_tready + .s_axis_tdata (cdc_fifo_s_axis_tdata[m] ), // input wire [15 : 0] s_axis_tdata + .m_axis_tvalid (lpf_s_axis_valid[m] ), // output wire m_axis_tvalid + .m_axis_tready (lpf_s_axis_ready[m] ), // input wire m_axis_tready + .m_axis_tdata (lpf_s_axis_tdata[m] ) // output wire [15 : 0] m_axis_tdata +); + +lpf_125k u_resample_lpf +( + .aclk (sys_clk ), // input wire aclk + .s_axis_data_tvalid (lpf_s_axis_valid[m] ), // input wire s_axis_data_tvalid + .s_axis_data_tready (lpf_s_axis_ready[m] ), // output wire s_axis_data_tready + .s_axis_data_tdata (lpf_s_axis_tdata[m] ), // input wire [15 : 0] s_axis_data_tdata + .m_axis_data_tvalid (lpf_m_axis_valid[m] ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (lpf_m_axis_tdata[m] ) // output wire [39 : 0] m_axis_data_tdata +); + +end +endgenerate + +assign tx_data_i = lpf_m_axis_tdata[0][31 -: DATA_WIDTH]; +assign tx_data_q = lpf_m_axis_tdata[1][31 -: DATA_WIDTH]; + +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/rtl/tx_wave.v b/projects/dl814_dj/dl814_dj_new_48m/rtl/tx_wave.v new file mode 100644 index 00000000..24eac3c4 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/rtl/tx_wave.v @@ -0,0 +1,26 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 03/23/2023 06:52:21 PM +// Design Name: +// Module Name: tx_wave +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tx_wave( + + ); +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/scripts/lpf_125k.m b/projects/dl814_dj/dl814_dj_new_48m/scripts/lpf_125k.m new file mode 100644 index 00000000..ec9e19c9 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/scripts/lpf_125k.m @@ -0,0 +1,30 @@ +clc; clear; close all; + +% parameters +fs1 = 48e6; % sample rate 1 +fs2 = 122.88e6; % sample rate 2 +ratio_up = fs2/gcd(fs1,fs2); % upsample ratio +ratio_dn = fs1/gcd(fs1,fs2); % downsample ratio +interp = 8; % interpolation factor +sumbol_num = 16; + +% standard pn sequence +pn_seq = comm.PNSequence('Polynomial','x^7+x^6+1', ... + 'InitialConditions',[zeros(1,6),1],'SamplesPerFrame',2^7-1); +PRBS7 = pn_seq(); +PRBS7_polar = 1-2*[PRBS7;0]; + +% square shaping +data_fs1 = kron(repmat(PRBS7_polar,sumbol_num,1),ones(interp,1)); + +% upsample +data_fs1_up = upsample(data_fs1,ratio_up); + +% anti-aliasing filter +fir = fir1(1024,6e6/48e6/max(ratio_up,ratio_dn)*2*pi,'low'); + +% filtering & downsample +data_fs2 = downsample(conv(data_fs1_up,fir,'same'),ratio_dn); + +% quantize & export fir coefficients +coe_gen(round(fir/max(abs(fir))*(2^15-1)),'lpf_125k.coe','filter'); diff --git a/projects/dl814_dj/dl814_dj_new_48m/testbenches/tb_tx_pn_seq.v b/projects/dl814_dj/dl814_dj_new_48m/testbenches/tb_tx_pn_seq.v new file mode 100644 index 00000000..98b073a6 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/testbenches/tb_tx_pn_seq.v @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/03/21 16:43:18 +// Design Name: +// Module Name: tb_tx_pn_seq +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_tx_pn_seq; + +reg sys_clk = 1'b1; +reg sys_rst = 1'b1; +reg sig_clk = 1'b1; +reg sig_rst = 1'b1; + +wire [15:0] tx_data_i; +wire [15:0] tx_data_q; + +tx_pn_seq_6mcps #( + .DATA_WIDTH (16) +) +u_tx_pn_seq_6mcps +( + .sys_clk (sys_clk ), // 122.88MHz + .sys_rst (sys_rst ), + .sig_clk (sig_clk ), // 48MHz + .sig_rst (sig_rst ), + + .tx_data_i (tx_data_i ), + .tx_data_q (tx_data_q ) +); + +initial begin + #102 + sys_rst = 1'b0; + sig_rst = 1'b0; +end + +always #10 sys_clk = ~sys_clk; +always #25.6 sig_clk = ~sig_clk; + +endmodule diff --git a/projects/dl814_dj/dl814_dj_new_48m/testbenches/tb_tx_qpsk.v b/projects/dl814_dj/dl814_dj_new_48m/testbenches/tb_tx_qpsk.v new file mode 100644 index 00000000..51a39802 --- /dev/null +++ b/projects/dl814_dj/dl814_dj_new_48m/testbenches/tb_tx_qpsk.v @@ -0,0 +1,125 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2020/12/08 12:43:46 +// Design Name: +// Module Name: tb_tx_qpsk +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_tx_qpsk; + +reg clk = 1'b0 ; +reg rst = 1'b1 ; +reg tx_on = 1'b1 ; +reg [31:0] freq_set ; +reg [ 1:0] waveform_sel = 2'b00; +reg [ 1:0] iq_sel = 2'b11 ; +wire [11:0] tx_data_i ; +wire [11:0] tx_data_q ; +reg [ 3:0] bb_rshift = 5'b0 ; + +tx_qpsk u_tx_qpsk +( + .clk (clk ), + .rst (rst ), + .tx_data_i (tx_data_i ), + .tx_data_q (tx_data_q ), + .waveform_sel (waveform_sel ), + .sweep_on (1'b0 ), + // .freq_set (32'd447392426 ), + .freq_set (32'd0 ), + .iq_sel (iq_sel ), + .bb_rshift (bb_rshift ) +); + +initial begin + #102 + rst = 1'b0; + // freq_set = 32'd873813333; + // waveform_sel = 2'b00; + // bb_rshift = 5'd0; + // #5000 + // bb_rshift = 5'd1; + // #5000 + // bb_rshift = 5'd2; + // #5000 + // bb_rshift = 5'd3; + // #5000 + // bb_rshift = 5'd4; + // #5000 + // bb_rshift = 5'd5; + // #5000 + // bb_rshift = 5'd6; + // #5000 + // bb_rshift = 5'd7; + // #5000 + // bb_rshift = 5'd8; + // #5000 + // bb_rshift = 5'd9; + // #5000 + // bb_rshift = 5'd14; + // #5000 + // bb_rshift = 5'd15; + // #5000 + // bb_rshift = 5'd16; + // freq_set = 32'd0; + // func_sel = 3'b010; + // #7777 + // freq_set = 32'd536870912; + // func_sel = 3'b100; + // #7777 + // freq_set = 32'd0; + // func_sel = 3'b100; + // #7777 + // freq_set = 32'd536870912; + // func_sel = 3'b010; + // #7777 + // freq_set = 32'd0; + // func_sel = 3'b010; + // freq_set = 32'd536870912; + // iq_sel = 2'b00; + // #7777 + // freq_set = 32'd536870912; + // iq_sel = 2'b01; + // #7777 + // freq_set = 32'd536870912; + // iq_sel = 2'b10; + // #7777 + // freq_set = 32'd536870912; + // iq_sel = 2'b11; +end + +always #5 clk = ~clk; + +// integer i; +// integer w_file; + +// initial begin +// w_file = $fopen("D:\\qpsk_josh.txt","w"); +// for (i = 0; i <= 35000; i = i + 1) begin +// wait(clk); +// #10; +// $fdisplay(w_file,"%d %d",$signed(tx_data_i), +// $signed(tx_data_q)); +// if (i == 35000) begin +// $fclose(w_file); +// $stop; +// end +// end +// end + +endmodule