Archived
add sampled data; add new online acq proj
the function of dmf is correct
This commit is contained in:
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:library>ipcache</spirit:library>
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<spirit:name>7a8b36a18eaf3577</spirit:name>
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<spirit:version>0</spirit:version>
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<spirit:componentInstances>
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<spirit:componentInstance>
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<spirit:instanceName>rotate_12b</spirit:instanceName>
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<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="cordic" spirit:version="6.0"/>
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<spirit:configurableElementValues>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_CARTESIAN.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_PHASE.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Architectural_Configuration">Parallel</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coarse_Rotation">true</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.1.3</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
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// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
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// Date : Tue Apr 25 15:12:40 2023
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// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
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// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_12b_stub.v
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// Design : rotate_12b
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7k410tffg900-2
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* x_core_info = "cordic_v6_0_15,Vivado 2019.1.3" *)
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module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_phase_tvalid,
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s_axis_phase_tdata, s_axis_cartesian_tvalid, s_axis_cartesian_tdata,
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m_axis_dout_tvalid, m_axis_dout_tdata)
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/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]" */;
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input aclk;
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input s_axis_phase_tvalid;
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input [15:0]s_axis_phase_tdata;
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input s_axis_cartesian_tvalid;
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input [31:0]s_axis_cartesian_tdata;
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output m_axis_dout_tvalid;
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output [31:0]m_axis_dout_tdata;
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endmodule
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+36
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-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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-- --------------------------------------------------------------------------------
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-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
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-- Date : Tue Apr 25 15:12:40 2023
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-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
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-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
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-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_12b_stub.vhdl
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-- Design : rotate_12b
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-- Purpose : Stub declaration of top-level module interface
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-- Device : xc7k410tffg900-2
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-- --------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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Port (
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aclk : in STD_LOGIC;
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s_axis_phase_tvalid : in STD_LOGIC;
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s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
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s_axis_cartesian_tvalid : in STD_LOGIC;
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s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
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m_axis_dout_tvalid : out STD_LOGIC;
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m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
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);
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end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
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architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
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attribute syn_black_box : boolean;
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attribute black_box_pad_pin : string;
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attribute syn_black_box of stub : architecture is true;
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attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]";
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attribute x_core_info : string;
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attribute x_core_info of stub : architecture is "cordic_v6_0_15,Vivado 2019.1.3";
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begin
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end;
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+10
-10
@@ -1,13 +1,13 @@
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version:1
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|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:36:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3536:00:00
|
||||
eof:514474141
|
||||
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3539:00:00
|
||||
eof:2084225446
|
||||
|
||||
+1
-1
@@ -1,3 +1,3 @@
|
||||
version:1
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:12
|
||||
6d6f64655f636f756e7465727c4755494d6f6465:13
|
||||
eof:
|
||||
|
||||
+5
-5
@@ -1,7 +1,7 @@
|
||||
version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b343130746666673930302d32:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6669666f5f6163636f725f636463:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:726f746174655f313262:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
@@ -33,7 +33,7 @@ version:1
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313573:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323131372e3431384d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3731352e3035314d42:00:00
|
||||
eof:1363044444
|
||||
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313473:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323039322e3930364d42:00:00
|
||||
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3639312e3938384d42:00:00
|
||||
eof:1114033916
|
||||
|
||||
+16
-16
@@ -3,7 +3,7 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pa" timeStamp="Wed Apr 19 21:06:41 2023">
|
||||
<application name="pa" timeStamp="Tue Apr 25 15:15:28 2023">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="cf48733ed6784c129006f962746a20c1" type="ProjectID"/>
|
||||
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
|
||||
@@ -19,26 +19,26 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<item name="Java Command Handlers">
|
||||
<property name="AddExistingIPHandler" value="16" type="JavaHandler"/>
|
||||
<property name="CloseProject" value="10" type="JavaHandler"/>
|
||||
<property name="CopyIPHandler" value="11" type="JavaHandler"/>
|
||||
<property name="CopyIPHandler" value="12" type="JavaHandler"/>
|
||||
<property name="CustomizeCore" value="2" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="7" type="JavaHandler"/>
|
||||
<property name="EditDelete" value="9" type="JavaHandler"/>
|
||||
<property name="ManageCompositeTargets" value="5" type="JavaHandler"/>
|
||||
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="6" type="JavaHandler"/>
|
||||
<property name="OpenIPLocationHandler" value="7" type="JavaHandler"/>
|
||||
<property name="OpenPreviousIPHandler" value="6" type="JavaHandler"/>
|
||||
<property name="OpenProject" value="1" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="56" type="JavaHandler"/>
|
||||
<property name="RecustomizeCore" value="59" type="JavaHandler"/>
|
||||
</item>
|
||||
<item name="Gui Handlers">
|
||||
<property name="BaseDialog_CANCEL" value="25" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="59" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_CANCEL" value="28" type="GuiHandlerData"/>
|
||||
<property name="BaseDialog_OK" value="62" type="GuiHandlerData"/>
|
||||
<property name="CmdMsgDialog_OK" value="3" type="GuiHandlerData"/>
|
||||
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="10" type="GuiHandlerData"/>
|
||||
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="11" type="GuiHandlerData"/>
|
||||
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="15" type="GuiHandlerData"/>
|
||||
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="18" type="GuiHandlerData"/>
|
||||
<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="297" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="7" type="GuiHandlerData"/>
|
||||
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="312" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_MANAGE_IP" value="8" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
|
||||
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="2" type="GuiHandlerData"/>
|
||||
<property name="HJFileChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="2" type="GuiHandlerData"/>
|
||||
@@ -52,15 +52,15 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="NewIPProjectWizard_PART" value="1" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_ADD_EXISTING_IP" value="16" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_CLOSE_PROJECT" value="10" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_COPY_IP" value="11" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_COPY_IP" value="12" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="3" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="6" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_OPEN_IP_LOCATION" value="7" type="GuiHandlerData"/>
|
||||
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
|
||||
<property name="ProgressDialog_BACKGROUND" value="5" type="GuiHandlerData"/>
|
||||
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
|
||||
<property name="RemoveSourcesDialog_ALSO_DELETE" value="7" type="GuiHandlerData"/>
|
||||
<property name="RemoveSourcesDialog_ALSO_DELETE" value="8" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="6" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="17" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="18" type="GuiHandlerData"/>
|
||||
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="15" type="GuiHandlerData"/>
|
||||
<property name="SrcChooserPanel_MAKE_LOCAL_COPY_OF_THESE_FILES_INTO" value="1" type="GuiHandlerData"/>
|
||||
@@ -68,9 +68,9 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="6" type="GuiHandlerData"/>
|
||||
</item>
|
||||
<item name="Other">
|
||||
<property name="GuiMode" value="99" type="GuiMode"/>
|
||||
<property name="GuiMode" value="112" type="GuiMode"/>
|
||||
<property name="BatchMode" value="0" type="BatchMode"/>
|
||||
<property name="TclMode" value="67" type="TclMode"/>
|
||||
<property name="TclMode" value="79" type="TclMode"/>
|
||||
</item>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
+8
@@ -0,0 +1,8 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="rotate_12b_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_12b_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
</Runs>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="add_s24_s32_s32_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
|
||||
<File Type="RDS-UTIL" Name="add_s24_s32_s32_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="add_s24_s32_s32_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="add_s24_s32_s32_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="add_s24_s32_s32.vds"/>
|
||||
<File Type="RDS-DCP" Name="add_s24_s32_s32.dcp"/>
|
||||
<File Type="PA-TCL" Name="add_s24_s32_s32.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ant_clk_gen_stg1_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg1_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg1.vds"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ant_clk_gen_stg2_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg2_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ant_clk_gen_stg2.vds"/>
|
||||
<File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
|
||||
<File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="atan2_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
|
||||
<File Type="RDS-UTIL" Name="atan2_16b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="atan2_16b_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="atan2_16b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="atan2_16b.vds"/>
|
||||
<File Type="RDS-DCP" Name="atan2_16b.dcp"/>
|
||||
<File Type="PA-TCL" Name="atan2_16b.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="cmpy_12x12_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
|
||||
<File Type="RDS-UTIL" Name="cmpy_12x12_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="cmpy_12x12_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="cmpy_12x12_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="cmpy_12x12.vds"/>
|
||||
<File Type="RDS-DCP" Name="cmpy_12x12.dcp"/>
|
||||
<File Type="PA-TCL" Name="cmpy_12x12.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="cmpy_16x12_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="cmpy_16x12_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="cmpy_16x12_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="cmpy_16x12_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="cmpy_16x12.vds"/>
|
||||
<File Type="RDS-DCP" Name="cmpy_16x12.dcp"/>
|
||||
<File Type="PA-TCL" Name="cmpy_16x12.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="fifo_AntCtrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="fifo_AntCtrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="fifo_AntCtrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="fifo_AntCtrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="fifo_AntCtrl.vds"/>
|
||||
<File Type="RDS-DCP" Name="fifo_AntCtrl.dcp"/>
|
||||
<File Type="PA-TCL" Name="fifo_AntCtrl.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_2x12x1024_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681303807">
|
||||
<File Type="RDS-UTIL" Name="ila_2x12x1024_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_2x12x1024_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_2x12x1024_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ila_2x12x1024.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_2x12x1024.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_2x12x1024.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_8x12_2x30_131072_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681303790">
|
||||
<File Type="RDS-UTIL" Name="ila_8x12_2x30_131072_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_8x12_2x30_131072_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_8x12_2x30_131072_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ila_8x12_2x30_131072.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_8x12_2x30_131072.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_8x12_2x30_131072.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ila_8x12_2x30_8192_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681882578">
|
||||
<File Type="RDS-UTIL-PB" Name="ila_8x12_2x30_8192_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ila_8x12_2x30_8192_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ila_8x12_2x30_8192_utilization_synth.pb"/>
|
||||
<File Type="RDS-RDS" Name="ila_8x12_2x30_8192.vds"/>
|
||||
<File Type="RDS-DCP" Name="ila_8x12_2x30_8192.dcp"/>
|
||||
<File Type="PA-TCL" Name="ila_8x12_2x30_8192.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="ram_hop_data_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="ram_hop_data_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="ram_hop_data_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="ram_hop_data_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="ram_hop_data.vds"/>
|
||||
<File Type="RDS-DCP" Name="ram_hop_data.dcp"/>
|
||||
<File Type="PA-TCL" Name="ram_hop_data.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="rotate_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="rotate_16b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="rotate_16b_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="rotate_16b_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="rotate_16b.vds"/>
|
||||
<File Type="RDS-DCP" Name="rotate_16b.dcp"/>
|
||||
<File Type="PA-TCL" Name="rotate_16b.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_ant_rd_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="vio_ant_rd_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_ant_rd_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_ant_rd_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="vio_ant_rd.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_ant_rd.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_ant_rd.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_ant_test_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="vio_ant_test_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_ant_test_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_ant_test_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="vio_ant_test.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_ant_test.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_ant_test.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_rf_rd_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="vio_rf_rd_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_rf_rd_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_rf_rd_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="vio_rf_rd.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_rf_rd.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_rf_rd.tcl"/>
|
||||
|
||||
+1
-1
@@ -1,7 +1,7 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="vio_rfcontrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
|
||||
<File Type="RDS-UTIL" Name="vio_rfcontrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-UTIL-PB" Name="vio_rfcontrl_utilization_synth.pb"/>
|
||||
<File Type="RDS-UTIL" Name="vio_rfcontrl_utilization_synth.rpt"/>
|
||||
<File Type="RDS-RDS" Name="vio_rfcontrl.vds"/>
|
||||
<File Type="RDS-DCP" Name="vio_rfcontrl.dcp"/>
|
||||
<File Type="PA-TCL" Name="vio_rfcontrl.tcl"/>
|
||||
|
||||
@@ -39,13 +39,13 @@
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="72"/>
|
||||
<Option Name="WTModelSimExportSim" Val="72"/>
|
||||
<Option Name="WTQuestaExportSim" Val="72"/>
|
||||
<Option Name="WTIesExportSim" Val="72"/>
|
||||
<Option Name="WTVcsExportSim" Val="72"/>
|
||||
<Option Name="WTRivieraExportSim" Val="72"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="72"/>
|
||||
<Option Name="WTXSimExportSim" Val="73"/>
|
||||
<Option Name="WTModelSimExportSim" Val="73"/>
|
||||
<Option Name="WTQuestaExportSim" Val="73"/>
|
||||
<Option Name="WTIesExportSim" Val="73"/>
|
||||
<Option Name="WTVcsExportSim" Val="73"/>
|
||||
<Option Name="WTRivieraExportSim" Val="73"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="73"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
|
||||
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|
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|
+63
-62
@@ -17,68 +17,69 @@ channelNum = 4;
|
||||
dataLen = 8192;
|
||||
fs = 48e6;
|
||||
dataFile = [...
|
||||
"iladata_25.0G_1-1.csv",...
|
||||
"iladata_25.0G_1-2.csv",...
|
||||
"iladata_25.0G_1-3.csv",...
|
||||
"iladata_25.1G_1-1.csv",...
|
||||
"iladata_25.1G_1-2.csv",...
|
||||
"iladata_25.1G_1-3.csv",...
|
||||
"iladata_25.2G_1-1.csv",...
|
||||
"iladata_25.2G_1-2.csv",...
|
||||
"iladata_25.2G_1-3.csv",...
|
||||
"iladata_25.3G_1-1.csv",...
|
||||
"iladata_25.3G_1-2.csv",...
|
||||
"iladata_25.3G_1-3.csv",...
|
||||
"iladata_25.4G_1-1.csv",...
|
||||
"iladata_25.4G_1-2.csv",...
|
||||
"iladata_25.4G_1-3.csv",...
|
||||
"iladata_25.5G_1-1.csv",...
|
||||
"iladata_25.5G_1-2.csv",...
|
||||
"iladata_25.5G_1-3.csv",...
|
||||
"iladata_25.6G_1-1.csv",...
|
||||
"iladata_25.6G_1-2.csv",...
|
||||
"iladata_25.6G_1-3.csv",...
|
||||
"iladata_25.7G_1-1.csv",...
|
||||
"iladata_25.7G_1-2.csv",...
|
||||
"iladata_25.7G_1-3.csv",...
|
||||
"iladata_25.8G_1-1.csv",...
|
||||
"iladata_25.8G_1-2.csv",...
|
||||
"iladata_25.8G_1-3.csv",...
|
||||
"iladata_25.9G_1-1.csv",...
|
||||
"iladata_25.9G_1-2.csv",...
|
||||
"iladata_25.9G_1-3.csv",...
|
||||
"iladata_26.0G_1-1.csv",...
|
||||
"iladata_26.0G_1-2.csv",...
|
||||
"iladata_26.0G_1-3.csv",...
|
||||
"iladata_26.1G_1-1.csv",...
|
||||
"iladata_26.1G_1-2.csv",...
|
||||
"iladata_26.1G_1-3.csv",...
|
||||
"iladata_26.2G_1-1.csv",...
|
||||
"iladata_26.2G_1-2.csv",...
|
||||
"iladata_26.2G_1-3.csv",...
|
||||
"iladata_26.3G_1-1.csv",...
|
||||
"iladata_26.3G_1-2.csv",...
|
||||
"iladata_26.3G_1-3.csv",...
|
||||
"iladata_26.4G_1-1.csv",...
|
||||
"iladata_26.4G_1-2.csv",...
|
||||
"iladata_26.4G_1-3.csv",...
|
||||
"iladata_26.5G_1-1.csv",...
|
||||
"iladata_26.5G_1-2.csv",...
|
||||
"iladata_26.5G_1-3.csv",...
|
||||
"iladata_26.6G_1-1.csv",...
|
||||
"iladata_26.6G_1-2.csv",...
|
||||
"iladata_26.6G_1-3.csv",...
|
||||
"iladata_26.7G_1-1.csv",...
|
||||
"iladata_26.7G_1-2.csv",...
|
||||
"iladata_26.8G_1-1.csv",...
|
||||
"iladata_26.8G_1-2.csv",...
|
||||
"iladata_26.8G_1-3.csv",...
|
||||
"iladata_26.9G_1-1.csv",...
|
||||
"iladata_26.9G_1-2.csv",...
|
||||
"iladata_26.9G_1-3.csv",...
|
||||
"iladata_27.0G_1-1.csv",...
|
||||
"iladata_27.0G_1-2.csv",...
|
||||
"iladata_27.0G_1-3.csv",...
|
||||
"iladata_26.0G_2-1.csv",...
|
||||
% "iladata_25.0G_2-2.csv",...
|
||||
% "iladata_25.0G_2-3.csv",...
|
||||
% "iladata_25.1G_2-1.csv",...
|
||||
% "iladata_25.1G_2-2.csv",...
|
||||
% "iladata_25.1G_2-3.csv",...
|
||||
% "iladata_25.2G_2-1.csv",...
|
||||
% "iladata_25.2G_2-2.csv",...
|
||||
% "iladata_25.2G_2-3.csv",...
|
||||
% "iladata_25.3G_2-1.csv",...
|
||||
% "iladata_25.3G_2-2.csv",...
|
||||
% "iladata_25.3G_2-3.csv",...
|
||||
% "iladata_25.4G_2-1.csv",...
|
||||
% "iladata_25.4G_2-2.csv",...
|
||||
% "iladata_25.4G_2-3.csv",...
|
||||
% "iladata_25.5G_2-1.csv",...
|
||||
% "iladata_25.5G_2-2.csv",...
|
||||
% "iladata_25.5G_2-3.csv",...
|
||||
% "iladata_25.6G_2-1.csv",...
|
||||
% "iladata_25.6G_2-2.csv",...
|
||||
% "iladata_25.6G_2-3.csv",...
|
||||
% "iladata_25.7G_2-1.csv",...
|
||||
% "iladata_25.7G_2-2.csv",...
|
||||
% "iladata_25.7G_2-3.csv",...
|
||||
% "iladata_25.8G_2-1.csv",...
|
||||
% "iladata_25.8G_2-2.csv",...
|
||||
% "iladata_25.8G_2-3.csv",...
|
||||
% "iladata_25.9G_2-1.csv",...
|
||||
% "iladata_25.9G_2-2.csv",...
|
||||
% "iladata_25.9G_2-3.csv",...
|
||||
% "iladata_26.0G_2-1.csv",...
|
||||
% "iladata_26.0G_2-2.csv",...
|
||||
% "iladata_26.0G_2-3.csv",...
|
||||
% "iladata_26.1G_2-1.csv",...
|
||||
% "iladata_26.1G_2-2.csv",...
|
||||
% "iladata_26.1G_2-3.csv",...
|
||||
% "iladata_26.2G_2-1.csv",...
|
||||
% "iladata_26.2G_2-2.csv",...
|
||||
% "iladata_26.2G_2-3.csv",...
|
||||
% "iladata_26.3G_2-1.csv",...
|
||||
% "iladata_26.3G_2-2.csv",...
|
||||
% "iladata_26.3G_2-3.csv",...
|
||||
% "iladata_26.4G_2-1.csv",...
|
||||
% "iladata_26.4G_2-2.csv",...
|
||||
% "iladata_26.4G_2-3.csv",...
|
||||
% "iladata_26.5G_2-1.csv",...
|
||||
% "iladata_26.5G_2-2.csv",...
|
||||
% "iladata_26.5G_2-3.csv",...
|
||||
% "iladata_26.6G_2-1.csv",...
|
||||
% "iladata_26.6G_2-2.csv",...
|
||||
% "iladata_26.6G_2-3.csv",...
|
||||
% "iladata_26.7G_2-1.csv",...
|
||||
% "iladata_26.7G_2-2.csv",...
|
||||
% "iladata_26.7G_2-3.csv",... % none for 1-3
|
||||
% "iladata_26.8G_2-1.csv",...
|
||||
% "iladata_26.8G_2-2.csv",...
|
||||
% "iladata_26.8G_2-3.csv",...
|
||||
% "iladata_26.9G_2-1.csv",...
|
||||
% "iladata_26.9G_2-2.csv",...
|
||||
% "iladata_26.9G_2-3.csv",...
|
||||
% "iladata_27.0G_2-1.csv",...
|
||||
% "iladata_27.0G_2-2.csv",...
|
||||
% "iladata_27.0G_2-3.csv",...
|
||||
];
|
||||
dataFileNum = length(dataFile);
|
||||
|
||||
|
||||
projects/dl814_k7/dl814_k7_cal_coarse/data/20230424-单音信号调零结果/iladata_rx_singletone_25.5G_withFIR.csv
LFS
BIN
Binary file not shown.
|
projects/dl814_k7/dl814_k7_cal_coarse/data/20230424-单音信号调零结果/iladata_rx_singletone_26.0G_withFIR.csv
LFS
BIN
Binary file not shown.
|
projects/dl814_k7/dl814_k7_cal_coarse/data/20230424-单音信号调零结果/iladata_rx_singletone_26.5G_withFIR.csv
LFS
BIN
Binary file not shown.
|
@@ -0,0 +1,14 @@
|
||||
dataFileName = "iladata_rx_singletone_25.5G_withFIR.csv";
|
||||
rxdata = readmatrix(dataFileName);
|
||||
|
||||
seqRx(:,1) = (rxdata(:, 4) + 1i*rxdata(:, 5)).';
|
||||
seqRx(:,2) = (rxdata(:, 6) + 1i*rxdata(:, 7)).';
|
||||
seqRx(:,3) = (rxdata(:, 8) + 1i*rxdata(:, 9)).';
|
||||
seqRx(:,4) = (rxdata(:,10) + 1i*rxdata(:,11)).';
|
||||
seqRx(:,5) = (rxdata(:,12) + 1i*rxdata(:,13)).';
|
||||
|
||||
figure(1);
|
||||
pwelch(seqRx(:,1),[],[],[],48e6);
|
||||
|
||||
figure(2);
|
||||
pwelch(seqRx(:,5),[],[],[],48e6);
|
||||
@@ -0,0 +1,131 @@
|
||||
################################################################################
|
||||
########################### Single Project Specific ############################
|
||||
################################################################################
|
||||
|
||||
# ------------------------------------------------------------------------------
|
||||
# ------------------------------ Vivado Specific -------------------------------
|
||||
# ------------------------------------------------------------------------------
|
||||
|
||||
# exclude everything in project directory
|
||||
project/**
|
||||
|
||||
# include hardware manager projects and sources
|
||||
# 1. include `.hw` directory
|
||||
# 2. include everything in `.hw` directory
|
||||
!project/*.hw/
|
||||
!project/*.hw/**
|
||||
|
||||
# include design run results
|
||||
# 1. include `*.runs` directory
|
||||
# 2. exclude everything in `.runs` directory
|
||||
# 3. include `.impl_*` directory
|
||||
# 4. include `*.bit` file in `.impl_*` directory
|
||||
# 5. include `*.ltx` file in `.impl_*` directory
|
||||
!/project/*.runs/
|
||||
/project/*.runs/**
|
||||
!/project/*.runs/impl_*/
|
||||
!/project/*.runs/impl_*/*.bit
|
||||
!/project/*.runs/impl_*/*.ltx
|
||||
|
||||
# ------------------------------------------------------------------------------
|
||||
# -------------------------------- SDK Specific --------------------------------
|
||||
# ------------------------------------------------------------------------------
|
||||
|
||||
# include sdk directory and everything in it
|
||||
!/project/*.sdk/
|
||||
!/project/*.sdk/**
|
||||
/project/*.sdk/**.log
|
||||
|
||||
# exclude some obscure hidden SDK folders
|
||||
/project/*.sdk/.metadata/
|
||||
/project/*.sdk/.sdk/
|
||||
/project/*.sdk/RemoteSystemsTempFiles/
|
||||
/project/*.sdk/webtalk/
|
||||
|
||||
# hw_platform: exclude the entire hw_platform folder, as everything can be
|
||||
# generated from the .hdf file. Make sure to include the bitstream in the .hdf
|
||||
# file when exporting from Vivado!
|
||||
/project/*.sdk/*_hw_platform_*/
|
||||
|
||||
# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
|
||||
# Makefile, ps lib files are regenerated automatically
|
||||
/project/*.sdk/*_bsp/*
|
||||
!/project/*.sdk/*_bsp/*.cproject
|
||||
!/project/*.sdk/*_bsp/*.project
|
||||
!/project/*.sdk/*_bsp/*.sdkproject
|
||||
!/project/*.sdk/*_bsp/system.mss
|
||||
!/project/*.sdk/*_bsp/Makefile
|
||||
|
||||
# Application: ignored file patterns, exclude Debug & Release folders
|
||||
/project/*.sdk/**/*.o
|
||||
/project/*.sdk/**/*.d
|
||||
/project/*.sdk/**/*.a
|
||||
/project/*.sdk/*/Debug/
|
||||
/project/*.sdk/*/Release/
|
||||
|
||||
|
||||
################################################################################
|
||||
# ############################ Multi Project Specific ############################
|
||||
# ################################################################################
|
||||
|
||||
# # ------------------------------------------------------------------------------
|
||||
# # ------------------------------ Vivado Specific -------------------------------
|
||||
# # ------------------------------------------------------------------------------
|
||||
|
||||
# # exclude everything in project directory expect for top level directory
|
||||
# project/**
|
||||
# !/project/*/
|
||||
|
||||
# # include hardware manager projects and sources
|
||||
# # 1. include `.hw` directory
|
||||
# # 2. include everything in `.hw` directory
|
||||
# !project/*/*.hw/
|
||||
# !project/*/*.hw/**
|
||||
|
||||
# # include design run results
|
||||
# # 1. include `*.runs` directory
|
||||
# # 2. exclude everything in `.runs` directory
|
||||
# # 3. include `.impl_*` directory
|
||||
# # 4. include `*.bit` file in `.impl_*` directory
|
||||
# # 5. include `*.ltx` file in `.impl_*` directory
|
||||
# !/project/*/*.runs/
|
||||
# /project/*/*.runs/**
|
||||
# !/project/*/*.runs/impl_*/
|
||||
# !/project/*/*.runs/impl_*/*.bit
|
||||
# !/project/*/*.runs/impl_*/*.ltx
|
||||
|
||||
# # ------------------------------------------------------------------------------
|
||||
# # -------------------------------- SDK Specific --------------------------------
|
||||
# # ------------------------------------------------------------------------------
|
||||
|
||||
# # include sdk directory and everything in it
|
||||
# !/project/*/*.sdk/
|
||||
# !/project/*/*.sdk/**
|
||||
# /project/*/*.sdk/**.log
|
||||
|
||||
# # exclude some obscure hidden SDK folders
|
||||
# /project/*/*.sdk/.metadata/
|
||||
# /project/*/*.sdk/.sdk/
|
||||
# /project/*/*.sdk/RemoteSystemsTempFiles/
|
||||
# /project/*/*.sdk/webtalk/
|
||||
|
||||
# # hw_platform: exclude the entire hw_platform folder, as everything can be
|
||||
# # generated from the .hdf file. Make sure to include the bitstream in the .hdf
|
||||
# # file when exporting from Vivado!
|
||||
# /project/*/*.sdk/*_hw_platform_*/
|
||||
|
||||
# # BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
|
||||
# # Makefile, ps lib files are regenerated automatically
|
||||
# /project/*/*.sdk/*_bsp/*
|
||||
# !/project/*/*.sdk/*_bsp/*.cproject
|
||||
# !/project/*/*.sdk/*_bsp/*.project
|
||||
# !/project/*/*.sdk/*_bsp/*.sdkproject
|
||||
# !/project/*/*.sdk/*_bsp/system.mss
|
||||
# !/project/*/*.sdk/*_bsp/Makefile
|
||||
|
||||
# # Application: ignored file patterns, exclude Debug & Release folders
|
||||
# /project/*/*.sdk/**/*.o
|
||||
# /project/*/*.sdk/**/*.d
|
||||
# /project/*/*.sdk/**/*.a
|
||||
# /project/*/*.sdk/*/Debug/
|
||||
# /project/*/*.sdk/*/Release/
|
||||
@@ -0,0 +1,220 @@
|
||||
# smq7k410t_b9361
|
||||
|
||||
## Timing Assertions Section
|
||||
|
||||
## Physical Constraints Section
|
||||
|
||||
# Clocks
|
||||
set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports clk_25m ] ;# CLK_25M
|
||||
set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25 } [get_ports clk_250m_p ] ;# CLK_250M_P
|
||||
set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# B9361_1_CLK_OUT
|
||||
set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# B9361_2_CLK_OUT
|
||||
|
||||
# HMC7044-1 Interface
|
||||
set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_clk ] ;# GM4526C_SPI_SCLK
|
||||
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_csn ] ;# GM4526C_SPI_CSB
|
||||
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_mosi ] ;# GM4526C_SPI_SDIO
|
||||
set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_miso ] ;# GM4526C_SPI_SDO
|
||||
|
||||
set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS33} [get_ports ad9516_refmon ] ;# GM4526C_REFMON
|
||||
set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS33} [get_ports ad9516_ld ] ;# GM4526C_LD
|
||||
set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS33} [get_ports ad9516_status ] ;# GM4526C_STATUS
|
||||
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports ad9516_pd_b ] ;# GM4526C_PDB
|
||||
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports ad9516_reset_b ] ;# GM4526C_RESETB
|
||||
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS33} [get_ports ad9516_sync_b ] ;# GM4526C_SYNCB
|
||||
|
||||
# AD9361-1 Interface
|
||||
set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# B9361_1_DATA_CLK
|
||||
set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# B9361_1_RX_FRAME
|
||||
set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# B9361_1_P0_00_TX0_N
|
||||
set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# B9361_1_P0_01_TX0_P
|
||||
set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# B9361_1_P0_02_TX1_N
|
||||
set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# B9361_1_P0_03_TX1_P
|
||||
set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# B9361_1_P0_04_TX2_N
|
||||
set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# B9361_1_P0_05_TX2_P
|
||||
set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# B9361_1_P0_06_TX3_N
|
||||
set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# B9361_1_P0_07_TX3_P
|
||||
set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# B9361_1_P0_08_TX4_N
|
||||
set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# B9361_1_P0_09_TX4_P
|
||||
set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# B9361_1_P0_10_TX5_N
|
||||
set_property -dict {PACKAGE_PIN G23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# B9361_1_P0_11_TX5_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# B9361_1_FB_CLK
|
||||
set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# B9361_1_TX_FRAME
|
||||
set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# B9361_1_P1_00_RX0_N
|
||||
set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# B9361_1_P1_01_RX0_P
|
||||
set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# B9361_1_P1_02_RX1_N
|
||||
set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# B9361_1_P1_03_RX1_P
|
||||
set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# B9361_1_P1_04_RX2_N
|
||||
set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# B9361_1_P1_05_RX2_P
|
||||
set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# B9361_1_P1_06_RX3_N
|
||||
set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# B9361_1_P1_07_RX3_P
|
||||
set_property -dict {PACKAGE_PIN F28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# B9361_1_P1_08_RX4_N
|
||||
set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# B9361_1_P1_09_RX4_P
|
||||
set_property -dict {PACKAGE_PIN H25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# B9361_1_P1_10_RX5_N
|
||||
set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# B9361_1_P1_11_RX5_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# B9361_1_SPI_CLK
|
||||
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# B9361_1_SPI_ENB
|
||||
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# B9361_1_SPI_DI
|
||||
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# B9361_1_SPI_DO
|
||||
|
||||
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# B9361_1_RESETB
|
||||
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# B9361_1_EN_AGC
|
||||
set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# B9361_1_ENABLE
|
||||
set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# B9361_1_TXNRX
|
||||
|
||||
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# B9361_1_CTRL_IN0
|
||||
set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# B9361_1_CTRL_IN1
|
||||
set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# B9361_1_CTRL_IN2
|
||||
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# B9361_1_CTRL_IN3
|
||||
|
||||
set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# B9361_1_CTRL_OUT0
|
||||
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# B9361_1_CTRL_OUT1
|
||||
set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# B9361_1_CTRL_OUT2
|
||||
set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# B9361_1_CTRL_OUT3
|
||||
set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# B9361_1_CTRL_OUT4
|
||||
set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# B9361_1_CTRL_OUT5
|
||||
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# B9361_1_CTRL_OUT6
|
||||
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# B9361_1_CTRL_OUT7
|
||||
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports ad9361_sync ] ;# B9361_SYNC
|
||||
|
||||
# AD9361-2 Interface
|
||||
set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# B9361_2_DATA_CLK
|
||||
set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# B9361_2_RX_FRAME
|
||||
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# B9361_2_P0_00_TX0_N
|
||||
set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# B9361_2_P0_01_TX0_P
|
||||
set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# B9361_2_P0_02_TX1_N
|
||||
set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# B9361_2_P0_03_TX1_P
|
||||
set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# B9361_2_P0_04_TX2_N
|
||||
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# B9361_2_P0_05_TX2_P
|
||||
set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# B9361_2_P0_06_TX3_N
|
||||
set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# B9361_2_P0_07_TX3_P
|
||||
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# B9361_2_P0_08_TX4_N
|
||||
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# B9361_2_P0_09_TX4_P
|
||||
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# B9361_2_P0_10_TX5_N
|
||||
set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# B9361_2_P0_11_TX5_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# B9361_2_FB_CLK
|
||||
set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# B9361_2_TX_FRAME
|
||||
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# B9361_2_P1_00_RX0_N
|
||||
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# B9361_2_P1_01_RX0_P
|
||||
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# B9361_2_P1_02_RX1_N
|
||||
set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# B9361_2_P1_03_RX1_P
|
||||
set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# B9361_2_P1_04_RX2_N
|
||||
set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# B9361_2_P1_05_RX2_P
|
||||
set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# B9361_2_P1_06_RX3_N
|
||||
set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# B9361_2_P1_07_RX3_P
|
||||
set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# B9361_2_P1_08_RX4_N
|
||||
set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# B9361_2_P1_09_RX4_P
|
||||
set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# B9361_2_P1_10_RX5_N
|
||||
set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# B9361_2_P1_11_RX5_P
|
||||
|
||||
set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# B9361_2_SPI_CLK
|
||||
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# B9361_2_SPI_ENB
|
||||
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# B9361_2_SPI_DI
|
||||
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# B9361_2_SPI_DO
|
||||
|
||||
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B9361_2_RESETB
|
||||
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B9361_2_EN_AGC
|
||||
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B9361_2_ENABLE
|
||||
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B9361_2_TXNRX
|
||||
|
||||
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B9361_2_CTRL_IN0
|
||||
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# B9361_2_CTRL_IN1
|
||||
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# B9361_2_CTRL_IN2
|
||||
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# B9361_2_CTRL_IN3
|
||||
|
||||
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# B9361_2_CTRL_OUT0
|
||||
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# B9361_2_CTRL_OUT1
|
||||
set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# B9361_2_CTRL_OUT2
|
||||
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# B9361_2_CTRL_OUT3
|
||||
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# B9361_2_CTRL_OUT4
|
||||
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# B9361_2_CTRL_OUT5
|
||||
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# B9361_2_CTRL_OUT6
|
||||
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# B9361_2_CTRL_OUT7
|
||||
|
||||
# Phased-Array Control
|
||||
set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVTTL } [get_ports ant_cin ] ;# ANT_CIN0
|
||||
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVTTL } [get_ports ant_din0 ] ;# ANT_DIN0
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVTTL } [get_ports ant_din1 ] ;# ANT_DIN1
|
||||
set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVTTL } [get_ports ant_cout ] ;# ANT_COUT0
|
||||
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVTTL } [get_ports ant_dout0 ] ;# ANT_DOUT0
|
||||
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVTTL } [get_ports ant_dout1 ] ;# ANT_DOUT1
|
||||
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVTTL } [get_ports ant_tr ] ;# ANT_TR_IN
|
||||
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVTTL } [get_ports ant_dary ] ;# ANT_DARY_IN
|
||||
|
||||
# RF Synthesizer Control
|
||||
set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVTTL } [get_ports rf_standby ] ;# RF_STANDBY
|
||||
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVTTL } [get_ports rf_sw_pll ] ;# RF_SW_PLL
|
||||
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVTTL } [get_ports rf_t ] ;# RF_T
|
||||
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVTTL } [get_ports rf_r ] ;# RF_R
|
||||
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVTTL } [get_ports rf_sw_bpf ] ;# RF_SW_BPF
|
||||
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVTTL } [get_ports rf_sclk1 ] ;# RF_SCLK1
|
||||
set_property -dict {PACKAGE_PIN AA26 IOSTANDARD LVTTL } [get_ports rf_sdio1 ] ;# RF_SDIO1
|
||||
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVTTL } [get_ports rf_cs1 ] ;# RF_CS1
|
||||
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVTTL } [get_ports rf_ld1 ] ;# RF_LD1
|
||||
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVTTL } [get_ports rf_sclk2 ] ;# RF_SCLK2
|
||||
set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVTTL } [get_ports rf_sdio2 ] ;# RF_SDIO2
|
||||
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVTTL } [get_ports rf_cs2 ] ;# RF_CS2
|
||||
set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVTTL } [get_ports rf_ld2 ] ;# RF_LD2
|
||||
set_property -dict {PACKAGE_PIN AC30 IOSTANDARD LVTTL } [get_ports rf_sclk3 ] ;# RF_SCLK3
|
||||
set_property -dict {PACKAGE_PIN AE29 IOSTANDARD LVTTL } [get_ports rf_sdio3 ] ;# RF_SDIO3
|
||||
set_property -dict {PACKAGE_PIN AB28 IOSTANDARD LVTTL } [get_ports rf_cs3 ] ;# RF_CS3
|
||||
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVTTL } [get_ports rf_ld3 ] ;# RF_LD3
|
||||
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVTTL } [get_ports rf_tmgc_16 ] ;# RF_TMGC_16
|
||||
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVTTL } [get_ports rf_tmgc_8 ] ;# RF_TMGC_8
|
||||
set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVTTL } [get_ports rf_tmgc_4 ] ;# RF_TMGC_4
|
||||
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVTTL } [get_ports rf_tmgc_2 ] ;# RF_TMGC_2
|
||||
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVTTL } [get_ports rf_tmgc_1 ] ;# RF_TMGC_1
|
||||
set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVTTL } [get_ports rf_rmgc_16 ] ;# RF_RMGC_16
|
||||
set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVTTL } [get_ports rf_rmgc_8 ] ;# RF_RMGC_8
|
||||
set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVTTL } [get_ports rf_rmgc_4 ] ;# RF_RMGC_4
|
||||
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVTTL } [get_ports rf_rmgc_2 ] ;# RF_RMGC_2
|
||||
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVTTL } [get_ports rf_rmgc_1 ] ;# RF_RMGC_1
|
||||
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVTTL } [get_ports rf_enable ] ;# RF_ENABLE
|
||||
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVTTL } [get_ports rf_sc ] ;# RF_SC
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVTTL } [get_ports rf_sd ] ;# RF_SD
|
||||
set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVTTL } [get_ports rf_endsyn ] ;# RF_END_SYN
|
||||
set_property -dict {PACKAGE_PIN W27 IOSTANDARD LVTTL } [get_ports rf_sdout ] ;# RF_SDOUT
|
||||
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVTTL } [get_ports rf_dq_wd ] ;# RF_DQ_WD
|
||||
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVTTL } [get_ports rf_sw_rx ] ;# RF_SW_RX
|
||||
|
||||
# LVDS for Time Synchronization
|
||||
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS33} [get_ports lvds_in_1 ] ;# LVDS_IN1
|
||||
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports lvds_out_1 ] ;# LVDS_OUT1
|
||||
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports lvds_in_2 ] ;# LVDS_IN2
|
||||
set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS33} [get_ports lvds_out_2 ] ;# LVDS_OUT2
|
||||
|
||||
# Debug IO
|
||||
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART_1_TXD
|
||||
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART_1_RXD
|
||||
set_property -dict {PACKAGE_PIN U23 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART_2_TXD
|
||||
set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART_2_RXD
|
||||
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART_3_TXD
|
||||
set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART_3_RXD
|
||||
|
||||
set_property -dict {PACKAGE_PIN V25 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# DEBUG_IO_1
|
||||
set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# DEBUG_IO_2
|
||||
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3
|
||||
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4
|
||||
set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5
|
||||
set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6
|
||||
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# DEBUG_IO_7
|
||||
set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports debug_io_8 ] ;# DEBUG_IO_8
|
||||
|
||||
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25 } [get_ports debug_io_00_p ] ;# DEBUG_IO_00_P
|
||||
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVDS_25 } [get_ports debug_io_01_p ] ;# DEBUG_IO_01_P
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS_25 } [get_ports debug_io_02_p ] ;# DEBUG_IO_02_P
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25 } [get_ports debug_io_03_p ] ;# DEBUG_IO_03_P
|
||||
set_property -dict {PACKAGE_PIN AC20 IOSTANDARD LVDS_25 } [get_ports debug_io_04_p ] ;# DEBUG_IO_04_P
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 } [get_ports debug_io_05_p ] ;# DEBUG_IO_05_P
|
||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVDS_25 } [get_ports debug_io_06_p ] ;# DEBUG_IO_06_P
|
||||
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVDS_25 } [get_ports debug_io_07_p ] ;# DEBUG_IO_07_P
|
||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25 } [get_ports debug_io_08_p ] ;# DEBUG_IO_08_P
|
||||
|
||||
# FLASH
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
@@ -0,0 +1,4 @@
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[7]/C}] -to [get_pins u_tx_pre_process/ad9361_tx_switch_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_recal_d1_reg/D]
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user