add sampled data; add new online acq proj

the function of dmf is correct
This commit is contained in:
2023-05-04 20:27:06 +08:00
parent 78e60b6e2d
commit e07389e326
1132 changed files with 356684 additions and 738 deletions
@@ -0,0 +1,65 @@
<?xml version="1.0" encoding="UTF-8"?>
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@@ -0,0 +1,28 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
// Date : Tue Apr 25 15:12:40 2023
// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_12b_stub.v
// Design : rotate_12b
// Purpose : Stub declaration of top-level module interface
// Device : xc7k410tffg900-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "cordic_v6_0_15,Vivado 2019.1.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_phase_tvalid,
s_axis_phase_tdata, s_axis_cartesian_tvalid, s_axis_cartesian_tdata,
m_axis_dout_tvalid, m_axis_dout_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [15:0]s_axis_phase_tdata;
input s_axis_cartesian_tvalid;
input [31:0]s_axis_cartesian_tdata;
output m_axis_dout_tvalid;
output [31:0]m_axis_dout_tdata;
endmodule
@@ -0,0 +1,36 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
-- Date : Tue Apr 25 15:12:40 2023
-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_12b_stub.vhdl
-- Design : rotate_12b
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k410tffg900-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_cartesian_tvalid : in STD_LOGIC;
s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_dout_tvalid : out STD_LOGIC;
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "cordic_v6_0_15,Vivado 2019.1.3";
begin
end;
@@ -1,13 +1,13 @@
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73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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eof:1363044444
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eof:1114033916
@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Wed Apr 19 21:06:41 2023">
<application name="pa" timeStamp="Tue Apr 25 15:15:28 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="cf48733ed6784c129006f962746a20c1" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
@@ -19,26 +19,26 @@ This means code written to parse this file will need to be revisited each subseq
<item name="Java Command Handlers">
<property name="AddExistingIPHandler" value="16" type="JavaHandler"/>
<property name="CloseProject" value="10" type="JavaHandler"/>
<property name="CopyIPHandler" value="11" type="JavaHandler"/>
<property name="CopyIPHandler" value="12" type="JavaHandler"/>
<property name="CustomizeCore" value="2" type="JavaHandler"/>
<property name="EditDelete" value="7" type="JavaHandler"/>
<property name="EditDelete" value="9" type="JavaHandler"/>
<property name="ManageCompositeTargets" value="5" type="JavaHandler"/>
<property name="NewIPLocationHandler" value="1" type="JavaHandler"/>
<property name="OpenIPLocationHandler" value="6" type="JavaHandler"/>
<property name="OpenIPLocationHandler" value="7" type="JavaHandler"/>
<property name="OpenPreviousIPHandler" value="6" type="JavaHandler"/>
<property name="OpenProject" value="1" type="JavaHandler"/>
<property name="RecustomizeCore" value="56" type="JavaHandler"/>
<property name="RecustomizeCore" value="59" type="JavaHandler"/>
</item>
<item name="Gui Handlers">
<property name="BaseDialog_CANCEL" value="25" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="59" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="28" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="62" type="GuiHandlerData"/>
<property name="CmdMsgDialog_OK" value="3" type="GuiHandlerData"/>
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="10" type="GuiHandlerData"/>
<property name="CopyIPHandler_DESTINATION_IP_NAME" value="11" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="15" type="GuiHandlerData"/>
<property name="ExpRunTreePanel_EXP_RUN_TREE_TABLE" value="18" type="GuiHandlerData"/>
<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="297" type="GuiHandlerData"/>
<property name="GettingStartedView_MANAGE_IP" value="7" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="312" type="GuiHandlerData"/>
<property name="GettingStartedView_MANAGE_IP" value="8" type="GuiHandlerData"/>
<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>
<property name="GettingStartedView_START_USING_VIVADO_WITH_IP_CATALOG" value="2" type="GuiHandlerData"/>
<property name="HJFileChooserHelpers_JUMP_TO_RECENT_PROJECT_DIRECTORY" value="2" type="GuiHandlerData"/>
@@ -52,15 +52,15 @@ This means code written to parse this file will need to be revisited each subseq
<property name="NewIPProjectWizard_PART" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_EXISTING_IP" value="16" type="GuiHandlerData"/>
<property name="PACommandNames_CLOSE_PROJECT" value="10" type="GuiHandlerData"/>
<property name="PACommandNames_COPY_IP" value="11" type="GuiHandlerData"/>
<property name="PACommandNames_COPY_IP" value="12" type="GuiHandlerData"/>
<property name="PACommandNames_GENERATE_COMPOSITE_FILE" value="3" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_IP_LOCATION" value="6" type="GuiHandlerData"/>
<property name="PACommandNames_OPEN_IP_LOCATION" value="7" type="GuiHandlerData"/>
<property name="PACommandNames_RESET_COMPOSITE_FILE" value="2" type="GuiHandlerData"/>
<property name="ProgressDialog_BACKGROUND" value="5" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="RemoveSourcesDialog_ALSO_DELETE" value="7" type="GuiHandlerData"/>
<property name="RemoveSourcesDialog_ALSO_DELETE" value="8" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_CLOSE_DIALOG_UNSAVED_CHANGES_WILL" value="6" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="17" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="18" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_RESET_OUTPUT_PRODUCTS" value="1" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_CONFIGURABLE_IP_FILES" value="15" type="GuiHandlerData"/>
<property name="SrcChooserPanel_MAKE_LOCAL_COPY_OF_THESE_FILES_INTO" value="1" type="GuiHandlerData"/>
@@ -68,9 +68,9 @@ This means code written to parse this file will need to be revisited each subseq
<property name="SyntheticaGettingStartedView_RECENT_IP_LOCATIONS" value="6" type="GuiHandlerData"/>
</item>
<item name="Other">
<property name="GuiMode" value="99" type="GuiMode"/>
<property name="GuiMode" value="112" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="67" type="TclMode"/>
<property name="TclMode" value="79" type="TclMode"/>
</item>
</section>
</application>
@@ -0,0 +1,8 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="rotate_12b_synth_1" LaunchDir="/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_12b_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
</Parameters>
</Runs>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="add_s24_s32_s32_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
<File Type="RDS-UTIL" Name="add_s24_s32_s32_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="add_s24_s32_s32_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="add_s24_s32_s32_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="add_s24_s32_s32.vds"/>
<File Type="RDS-DCP" Name="add_s24_s32_s32.dcp"/>
<File Type="PA-TCL" Name="add_s24_s32_s32.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ant_clk_gen_stg1_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg1_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ant_clk_gen_stg1_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="ant_clk_gen_stg1.vds"/>
<File Type="RDS-DCP" Name="ant_clk_gen_stg1.dcp"/>
<File Type="PA-TCL" Name="ant_clk_gen_stg1.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ant_clk_gen_stg2_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ant_clk_gen_stg2_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ant_clk_gen_stg2_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="ant_clk_gen_stg2.vds"/>
<File Type="RDS-DCP" Name="ant_clk_gen_stg2.dcp"/>
<File Type="PA-TCL" Name="ant_clk_gen_stg2.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="atan2_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
<File Type="RDS-UTIL" Name="atan2_16b_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="atan2_16b_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="atan2_16b_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="atan2_16b.vds"/>
<File Type="RDS-DCP" Name="atan2_16b.dcp"/>
<File Type="PA-TCL" Name="atan2_16b.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="cmpy_12x12_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300767">
<File Type="RDS-UTIL" Name="cmpy_12x12_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="cmpy_12x12_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="cmpy_12x12_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="cmpy_12x12.vds"/>
<File Type="RDS-DCP" Name="cmpy_12x12.dcp"/>
<File Type="PA-TCL" Name="cmpy_12x12.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="cmpy_16x12_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
<File Type="RDS-UTIL" Name="cmpy_16x12_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="cmpy_16x12_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="cmpy_16x12_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="cmpy_16x12.vds"/>
<File Type="RDS-DCP" Name="cmpy_16x12.dcp"/>
<File Type="PA-TCL" Name="cmpy_16x12.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="fifo_AntCtrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
<File Type="RDS-UTIL" Name="fifo_AntCtrl_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="fifo_AntCtrl_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="fifo_AntCtrl_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="fifo_AntCtrl.vds"/>
<File Type="RDS-DCP" Name="fifo_AntCtrl.dcp"/>
<File Type="PA-TCL" Name="fifo_AntCtrl.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_2x12x1024_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681303807">
<File Type="RDS-UTIL" Name="ila_2x12x1024_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ila_2x12x1024_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ila_2x12x1024_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="ila_2x12x1024.vds"/>
<File Type="RDS-DCP" Name="ila_2x12x1024.dcp"/>
<File Type="PA-TCL" Name="ila_2x12x1024.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_8x12_2x30_131072_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681303790">
<File Type="RDS-UTIL" Name="ila_8x12_2x30_131072_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ila_8x12_2x30_131072_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ila_8x12_2x30_131072_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="ila_8x12_2x30_131072.vds"/>
<File Type="RDS-DCP" Name="ila_8x12_2x30_131072.dcp"/>
<File Type="PA-TCL" Name="ila_8x12_2x30_131072.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ila_8x12_2x30_8192_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681882578">
<File Type="RDS-UTIL-PB" Name="ila_8x12_2x30_8192_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ila_8x12_2x30_8192_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ila_8x12_2x30_8192_utilization_synth.pb"/>
<File Type="RDS-RDS" Name="ila_8x12_2x30_8192.vds"/>
<File Type="RDS-DCP" Name="ila_8x12_2x30_8192.dcp"/>
<File Type="PA-TCL" Name="ila_8x12_2x30_8192.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="ram_hop_data_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
<File Type="RDS-UTIL" Name="ram_hop_data_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="ram_hop_data_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="ram_hop_data_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="ram_hop_data.vds"/>
<File Type="RDS-DCP" Name="ram_hop_data.dcp"/>
<File Type="PA-TCL" Name="ram_hop_data.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="rotate_16b_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
<File Type="RDS-UTIL" Name="rotate_16b_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="rotate_16b_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="rotate_16b_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="rotate_16b.vds"/>
<File Type="RDS-DCP" Name="rotate_16b.dcp"/>
<File Type="PA-TCL" Name="rotate_16b.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_ant_rd_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
<File Type="RDS-UTIL" Name="vio_ant_rd_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="vio_ant_rd_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="vio_ant_rd_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="vio_ant_rd.vds"/>
<File Type="RDS-DCP" Name="vio_ant_rd.dcp"/>
<File Type="PA-TCL" Name="vio_ant_rd.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_ant_test_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
<File Type="RDS-UTIL" Name="vio_ant_test_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="vio_ant_test_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="vio_ant_test_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="vio_ant_test.vds"/>
<File Type="RDS-DCP" Name="vio_ant_test.dcp"/>
<File Type="PA-TCL" Name="vio_ant_test.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_rf_rd_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
<File Type="RDS-UTIL" Name="vio_rf_rd_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="vio_rf_rd_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="vio_rf_rd_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="vio_rf_rd.vds"/>
<File Type="RDS-DCP" Name="vio_rf_rd.dcp"/>
<File Type="PA-TCL" Name="vio_rf_rd.tcl"/>
@@ -1,7 +1,7 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="vio_rfcontrl_synth_1" LaunchPart="xc7k410tffg900-2" LaunchTime="1681300768">
<File Type="RDS-UTIL" Name="vio_rfcontrl_utilization_synth.rpt"/>
<File Type="RDS-UTIL-PB" Name="vio_rfcontrl_utilization_synth.pb"/>
<File Type="RDS-UTIL" Name="vio_rfcontrl_utilization_synth.rpt"/>
<File Type="RDS-RDS" Name="vio_rfcontrl.vds"/>
<File Type="RDS-DCP" Name="vio_rfcontrl.dcp"/>
<File Type="PA-TCL" Name="vio_rfcontrl.tcl"/>
@@ -39,13 +39,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="72"/>
<Option Name="WTModelSimExportSim" Val="72"/>
<Option Name="WTQuestaExportSim" Val="72"/>
<Option Name="WTIesExportSim" Val="72"/>
<Option Name="WTVcsExportSim" Val="72"/>
<Option Name="WTRivieraExportSim" Val="72"/>
<Option Name="WTActivehdlExportSim" Val="72"/>
<Option Name="WTXSimExportSim" Val="73"/>
<Option Name="WTModelSimExportSim" Val="73"/>
<Option Name="WTQuestaExportSim" Val="73"/>
<Option Name="WTIesExportSim" Val="73"/>
<Option Name="WTVcsExportSim" Val="73"/>
<Option Name="WTRivieraExportSim" Val="73"/>
<Option Name="WTActivehdlExportSim" Val="73"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>