Archived
add sampled data; add new online acq proj
the function of dmf is correct
This commit is contained in:
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################################################################################
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########################### Single Project Specific ############################
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################################################################################
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# ------------------------------------------------------------------------------
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# ------------------------------ Vivado Specific -------------------------------
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# ------------------------------------------------------------------------------
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# exclude everything in project directory
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project/**
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# include hardware manager projects and sources
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# 1. include `.hw` directory
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# 2. include everything in `.hw` directory
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!project/*.hw/
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!project/*.hw/**
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# include design run results
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# 1. include `*.runs` directory
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# 2. exclude everything in `.runs` directory
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# 3. include `.impl_*` directory
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# 4. include `*.bit` file in `.impl_*` directory
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# 5. include `*.ltx` file in `.impl_*` directory
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!/project/*.runs/
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/project/*.runs/**
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!/project/*.runs/impl_*/
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!/project/*.runs/impl_*/*.bit
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!/project/*.runs/impl_*/*.ltx
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# ------------------------------------------------------------------------------
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# -------------------------------- SDK Specific --------------------------------
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# ------------------------------------------------------------------------------
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# include sdk directory and everything in it
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!/project/*.sdk/
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!/project/*.sdk/**
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/project/*.sdk/**.log
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# exclude some obscure hidden SDK folders
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/project/*.sdk/.metadata/
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/project/*.sdk/.sdk/
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/project/*.sdk/RemoteSystemsTempFiles/
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/project/*.sdk/webtalk/
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# hw_platform: exclude the entire hw_platform folder, as everything can be
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# generated from the .hdf file. Make sure to include the bitstream in the .hdf
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# file when exporting from Vivado!
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/project/*.sdk/*_hw_platform_*/
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# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
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# Makefile, ps lib files are regenerated automatically
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/project/*.sdk/*_bsp/*
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!/project/*.sdk/*_bsp/*.cproject
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!/project/*.sdk/*_bsp/*.project
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!/project/*.sdk/*_bsp/*.sdkproject
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!/project/*.sdk/*_bsp/system.mss
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!/project/*.sdk/*_bsp/Makefile
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# Application: ignored file patterns, exclude Debug & Release folders
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/project/*.sdk/**/*.o
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/project/*.sdk/**/*.d
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/project/*.sdk/**/*.a
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/project/*.sdk/*/Debug/
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/project/*.sdk/*/Release/
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################################################################################
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# ############################ Multi Project Specific ############################
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# ################################################################################
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# # ------------------------------------------------------------------------------
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# # ------------------------------ Vivado Specific -------------------------------
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# # ------------------------------------------------------------------------------
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# # exclude everything in project directory expect for top level directory
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# project/**
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# !/project/*/
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# # include hardware manager projects and sources
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# # 1. include `.hw` directory
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# # 2. include everything in `.hw` directory
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# !project/*/*.hw/
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# !project/*/*.hw/**
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# # include design run results
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# # 1. include `*.runs` directory
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# # 2. exclude everything in `.runs` directory
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# # 3. include `.impl_*` directory
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# # 4. include `*.bit` file in `.impl_*` directory
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# # 5. include `*.ltx` file in `.impl_*` directory
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# !/project/*/*.runs/
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# /project/*/*.runs/**
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# !/project/*/*.runs/impl_*/
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# !/project/*/*.runs/impl_*/*.bit
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# !/project/*/*.runs/impl_*/*.ltx
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# # ------------------------------------------------------------------------------
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# # -------------------------------- SDK Specific --------------------------------
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# # ------------------------------------------------------------------------------
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# # include sdk directory and everything in it
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# !/project/*/*.sdk/
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# !/project/*/*.sdk/**
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# /project/*/*.sdk/**.log
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# # exclude some obscure hidden SDK folders
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# /project/*/*.sdk/.metadata/
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# /project/*/*.sdk/.sdk/
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# /project/*/*.sdk/RemoteSystemsTempFiles/
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# /project/*/*.sdk/webtalk/
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# # hw_platform: exclude the entire hw_platform folder, as everything can be
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# # generated from the .hdf file. Make sure to include the bitstream in the .hdf
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# # file when exporting from Vivado!
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# /project/*/*.sdk/*_hw_platform_*/
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# # BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and
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# # Makefile, ps lib files are regenerated automatically
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# /project/*/*.sdk/*_bsp/*
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# !/project/*/*.sdk/*_bsp/*.cproject
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# !/project/*/*.sdk/*_bsp/*.project
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# !/project/*/*.sdk/*_bsp/*.sdkproject
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# !/project/*/*.sdk/*_bsp/system.mss
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# !/project/*/*.sdk/*_bsp/Makefile
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# # Application: ignored file patterns, exclude Debug & Release folders
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# /project/*/*.sdk/**/*.o
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# /project/*/*.sdk/**/*.d
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# /project/*/*.sdk/**/*.a
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# /project/*/*.sdk/*/Debug/
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# /project/*/*.sdk/*/Release/
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@@ -0,0 +1,220 @@
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# smq7k410t_b9361
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## Timing Assertions Section
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## Physical Constraints Section
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# Clocks
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set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports clk_25m ] ;# CLK_25M
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set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25 } [get_ports clk_250m_p ] ;# CLK_250M_P
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set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# B9361_1_CLK_OUT
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# B9361_2_CLK_OUT
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# HMC7044-1 Interface
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set_property -dict {PACKAGE_PIN J23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_clk ] ;# GM4526C_SPI_SCLK
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set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_csn ] ;# GM4526C_SPI_CSB
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set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_mosi ] ;# GM4526C_SPI_SDIO
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set_property -dict {PACKAGE_PIN K23 IOSTANDARD LVCMOS33} [get_ports ad9516_spi_miso ] ;# GM4526C_SPI_SDO
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set_property -dict {PACKAGE_PIN L23 IOSTANDARD LVCMOS33} [get_ports ad9516_refmon ] ;# GM4526C_REFMON
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set_property -dict {PACKAGE_PIN K24 IOSTANDARD LVCMOS33} [get_ports ad9516_ld ] ;# GM4526C_LD
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set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS33} [get_ports ad9516_status ] ;# GM4526C_STATUS
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set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS33} [get_ports ad9516_pd_b ] ;# GM4526C_PDB
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set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports ad9516_reset_b ] ;# GM4526C_RESETB
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set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS33} [get_ports ad9516_sync_b ] ;# GM4526C_SYNCB
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# AD9361-1 Interface
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set_property -dict {PACKAGE_PIN D27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# B9361_1_DATA_CLK
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set_property -dict {PACKAGE_PIN B27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# B9361_1_RX_FRAME
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set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# B9361_1_P0_00_TX0_N
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set_property -dict {PACKAGE_PIN B23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# B9361_1_P0_01_TX0_P
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set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# B9361_1_P0_02_TX1_N
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set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# B9361_1_P0_03_TX1_P
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set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# B9361_1_P0_04_TX2_N
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set_property -dict {PACKAGE_PIN E24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# B9361_1_P0_05_TX2_P
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set_property -dict {PACKAGE_PIN E25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# B9361_1_P0_06_TX3_N
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set_property -dict {PACKAGE_PIN F25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# B9361_1_P0_07_TX3_P
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set_property -dict {PACKAGE_PIN E26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# B9361_1_P0_08_TX4_N
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set_property -dict {PACKAGE_PIN F26 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# B9361_1_P0_09_TX4_P
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set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# B9361_1_P0_10_TX5_N
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set_property -dict {PACKAGE_PIN G23 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# B9361_1_P0_11_TX5_P
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set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# B9361_1_FB_CLK
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set_property -dict {PACKAGE_PIN G27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# B9361_1_TX_FRAME
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set_property -dict {PACKAGE_PIN E30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# B9361_1_P1_00_RX0_N
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set_property -dict {PACKAGE_PIN E29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# B9361_1_P1_01_RX0_P
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set_property -dict {PACKAGE_PIN C30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# B9361_1_P1_02_RX1_N
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set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# B9361_1_P1_03_RX1_P
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set_property -dict {PACKAGE_PIN A30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# B9361_1_P1_04_RX2_N
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set_property -dict {PACKAGE_PIN B30 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# B9361_1_P1_05_RX2_P
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set_property -dict {PACKAGE_PIN B29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# B9361_1_P1_06_RX3_N
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set_property -dict {PACKAGE_PIN C29 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# B9361_1_P1_07_RX3_P
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set_property -dict {PACKAGE_PIN F28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# B9361_1_P1_08_RX4_N
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set_property -dict {PACKAGE_PIN G28 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# B9361_1_P1_09_RX4_P
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set_property -dict {PACKAGE_PIN H25 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# B9361_1_P1_10_RX5_N
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set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# B9361_1_P1_11_RX5_P
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set_property -dict {PACKAGE_PIN H20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# B9361_1_SPI_CLK
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set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# B9361_1_SPI_ENB
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set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# B9361_1_SPI_DI
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set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# B9361_1_SPI_DO
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set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# B9361_1_RESETB
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set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# B9361_1_EN_AGC
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set_property -dict {PACKAGE_PIN H17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# B9361_1_ENABLE
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set_property -dict {PACKAGE_PIN A27 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# B9361_1_TXNRX
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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# B9361_1_CTRL_IN0
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set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# B9361_1_CTRL_IN1
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set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# B9361_1_CTRL_IN2
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set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# B9361_1_CTRL_IN3
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set_property -dict {PACKAGE_PIN H21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# B9361_1_CTRL_OUT0
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set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# B9361_1_CTRL_OUT1
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set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# B9361_1_CTRL_OUT2
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set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# B9361_1_CTRL_OUT3
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set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# B9361_1_CTRL_OUT4
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set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# B9361_1_CTRL_OUT5
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set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# B9361_1_CTRL_OUT6
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set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# B9361_1_CTRL_OUT7
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set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS18} [get_ports ad9361_sync ] ;# B9361_SYNC
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# AD9361-2 Interface
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set_property -dict {PACKAGE_PIN D12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# B9361_2_DATA_CLK
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set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# B9361_2_RX_FRAME
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set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# B9361_2_P0_00_TX0_N
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set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# B9361_2_P0_01_TX0_P
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set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# B9361_2_P0_02_TX1_N
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set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# B9361_2_P0_03_TX1_P
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set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# B9361_2_P0_04_TX2_N
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set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# B9361_2_P0_05_TX2_P
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set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# B9361_2_P0_06_TX3_N
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set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# B9361_2_P0_07_TX3_P
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set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# B9361_2_P0_08_TX4_N
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set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# B9361_2_P0_09_TX4_P
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set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# B9361_2_P0_10_TX5_N
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set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# B9361_2_P0_11_TX5_P
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set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# B9361_2_FB_CLK
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set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# B9361_2_TX_FRAME
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set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# B9361_2_P1_00_RX0_N
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set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# B9361_2_P1_01_RX0_P
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set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# B9361_2_P1_02_RX1_N
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set_property -dict {PACKAGE_PIN E14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# B9361_2_P1_03_RX1_P
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set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# B9361_2_P1_04_RX2_N
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set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# B9361_2_P1_05_RX2_P
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set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# B9361_2_P1_06_RX3_N
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set_property -dict {PACKAGE_PIN A11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# B9361_2_P1_07_RX3_P
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set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# B9361_2_P1_08_RX4_N
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set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# B9361_2_P1_09_RX4_P
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set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# B9361_2_P1_10_RX5_N
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set_property -dict {PACKAGE_PIN F11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# B9361_2_P1_11_RX5_P
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set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# B9361_2_SPI_CLK
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set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# B9361_2_SPI_ENB
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set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# B9361_2_SPI_DI
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||||
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# B9361_2_SPI_DO
|
||||
|
||||
set_property -dict {PACKAGE_PIN G18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B9361_2_RESETB
|
||||
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B9361_2_EN_AGC
|
||||
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B9361_2_ENABLE
|
||||
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B9361_2_TXNRX
|
||||
|
||||
set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B9361_2_CTRL_IN0
|
||||
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# B9361_2_CTRL_IN1
|
||||
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# B9361_2_CTRL_IN2
|
||||
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# B9361_2_CTRL_IN3
|
||||
|
||||
set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# B9361_2_CTRL_OUT0
|
||||
set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# B9361_2_CTRL_OUT1
|
||||
set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# B9361_2_CTRL_OUT2
|
||||
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# B9361_2_CTRL_OUT3
|
||||
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# B9361_2_CTRL_OUT4
|
||||
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# B9361_2_CTRL_OUT5
|
||||
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# B9361_2_CTRL_OUT6
|
||||
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# B9361_2_CTRL_OUT7
|
||||
|
||||
# Phased-Array Control
|
||||
set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVTTL } [get_ports ant_cin ] ;# ANT_CIN0
|
||||
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVTTL } [get_ports ant_din0 ] ;# ANT_DIN0
|
||||
set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVTTL } [get_ports ant_din1 ] ;# ANT_DIN1
|
||||
set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVTTL } [get_ports ant_cout ] ;# ANT_COUT0
|
||||
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVTTL } [get_ports ant_dout0 ] ;# ANT_DOUT0
|
||||
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVTTL } [get_ports ant_dout1 ] ;# ANT_DOUT1
|
||||
set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVTTL } [get_ports ant_tr ] ;# ANT_TR_IN
|
||||
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVTTL } [get_ports ant_dary ] ;# ANT_DARY_IN
|
||||
|
||||
# RF Synthesizer Control
|
||||
set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVTTL } [get_ports rf_standby ] ;# RF_STANDBY
|
||||
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVTTL } [get_ports rf_sw_pll ] ;# RF_SW_PLL
|
||||
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVTTL } [get_ports rf_t ] ;# RF_T
|
||||
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVTTL } [get_ports rf_r ] ;# RF_R
|
||||
set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVTTL } [get_ports rf_sw_bpf ] ;# RF_SW_BPF
|
||||
set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVTTL } [get_ports rf_sclk1 ] ;# RF_SCLK1
|
||||
set_property -dict {PACKAGE_PIN AA26 IOSTANDARD LVTTL } [get_ports rf_sdio1 ] ;# RF_SDIO1
|
||||
set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVTTL } [get_ports rf_cs1 ] ;# RF_CS1
|
||||
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVTTL } [get_ports rf_ld1 ] ;# RF_LD1
|
||||
set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVTTL } [get_ports rf_sclk2 ] ;# RF_SCLK2
|
||||
set_property -dict {PACKAGE_PIN AD27 IOSTANDARD LVTTL } [get_ports rf_sdio2 ] ;# RF_SDIO2
|
||||
set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVTTL } [get_ports rf_cs2 ] ;# RF_CS2
|
||||
set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVTTL } [get_ports rf_ld2 ] ;# RF_LD2
|
||||
set_property -dict {PACKAGE_PIN AC30 IOSTANDARD LVTTL } [get_ports rf_sclk3 ] ;# RF_SCLK3
|
||||
set_property -dict {PACKAGE_PIN AE29 IOSTANDARD LVTTL } [get_ports rf_sdio3 ] ;# RF_SDIO3
|
||||
set_property -dict {PACKAGE_PIN AB28 IOSTANDARD LVTTL } [get_ports rf_cs3 ] ;# RF_CS3
|
||||
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVTTL } [get_ports rf_ld3 ] ;# RF_LD3
|
||||
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVTTL } [get_ports rf_tmgc_16 ] ;# RF_TMGC_16
|
||||
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVTTL } [get_ports rf_tmgc_8 ] ;# RF_TMGC_8
|
||||
set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVTTL } [get_ports rf_tmgc_4 ] ;# RF_TMGC_4
|
||||
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVTTL } [get_ports rf_tmgc_2 ] ;# RF_TMGC_2
|
||||
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVTTL } [get_ports rf_tmgc_1 ] ;# RF_TMGC_1
|
||||
set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVTTL } [get_ports rf_rmgc_16 ] ;# RF_RMGC_16
|
||||
set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVTTL } [get_ports rf_rmgc_8 ] ;# RF_RMGC_8
|
||||
set_property -dict {PACKAGE_PIN Y29 IOSTANDARD LVTTL } [get_ports rf_rmgc_4 ] ;# RF_RMGC_4
|
||||
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVTTL } [get_ports rf_rmgc_2 ] ;# RF_RMGC_2
|
||||
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVTTL } [get_ports rf_rmgc_1 ] ;# RF_RMGC_1
|
||||
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVTTL } [get_ports rf_enable ] ;# RF_ENABLE
|
||||
set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVTTL } [get_ports rf_sc ] ;# RF_SC
|
||||
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVTTL } [get_ports rf_sd ] ;# RF_SD
|
||||
set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVTTL } [get_ports rf_endsyn ] ;# RF_END_SYN
|
||||
set_property -dict {PACKAGE_PIN W27 IOSTANDARD LVTTL } [get_ports rf_sdout ] ;# RF_SDOUT
|
||||
set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVTTL } [get_ports rf_dq_wd ] ;# RF_DQ_WD
|
||||
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVTTL } [get_ports rf_sw_rx ] ;# RF_SW_RX
|
||||
|
||||
# LVDS for Time Synchronization
|
||||
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS33} [get_ports lvds_in_1 ] ;# LVDS_IN1
|
||||
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports lvds_out_1 ] ;# LVDS_OUT1
|
||||
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports lvds_in_2 ] ;# LVDS_IN2
|
||||
set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS33} [get_ports lvds_out_2 ] ;# LVDS_OUT2
|
||||
|
||||
# Debug IO
|
||||
set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART_1_TXD
|
||||
set_property -dict {PACKAGE_PIN V19 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART_1_RXD
|
||||
set_property -dict {PACKAGE_PIN U23 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART_2_TXD
|
||||
set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART_2_RXD
|
||||
set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART_3_TXD
|
||||
set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART_3_RXD
|
||||
|
||||
set_property -dict {PACKAGE_PIN V25 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# DEBUG_IO_1
|
||||
set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# DEBUG_IO_2
|
||||
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3
|
||||
set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4
|
||||
set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5
|
||||
set_property -dict {PACKAGE_PIN W22 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6
|
||||
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# DEBUG_IO_7
|
||||
set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports debug_io_8 ] ;# DEBUG_IO_8
|
||||
|
||||
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25 } [get_ports debug_io_00_p ] ;# DEBUG_IO_00_P
|
||||
set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVDS_25 } [get_ports debug_io_01_p ] ;# DEBUG_IO_01_P
|
||||
set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVDS_25 } [get_ports debug_io_02_p ] ;# DEBUG_IO_02_P
|
||||
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25 } [get_ports debug_io_03_p ] ;# DEBUG_IO_03_P
|
||||
set_property -dict {PACKAGE_PIN AC20 IOSTANDARD LVDS_25 } [get_ports debug_io_04_p ] ;# DEBUG_IO_04_P
|
||||
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25 } [get_ports debug_io_05_p ] ;# DEBUG_IO_05_P
|
||||
set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVDS_25 } [get_ports debug_io_06_p ] ;# DEBUG_IO_06_P
|
||||
set_property -dict {PACKAGE_PIN AB22 IOSTANDARD LVDS_25 } [get_ports debug_io_07_p ] ;# DEBUG_IO_07_P
|
||||
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25 } [get_ports debug_io_08_p ] ;# DEBUG_IO_08_P
|
||||
|
||||
# FLASH
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
@@ -0,0 +1,4 @@
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[9]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_2_cal_start_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[7]/C}] -to [get_pins u_tx_pre_process/ad9361_tx_switch_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[10]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_1_cal_start_d1_reg/D]
|
||||
set_false_path -from [get_pins {u_system_bd_wrapper/system_bd_i/axi_gpio/U0/gpio_core_1/Dual.gpio_Data_Out_reg[8]/C}] -to [get_pins u_rx_pre_process/u_ad9361_phase_cal/ad9361_recal_d1_reg/D]
|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
+109
@@ -0,0 +1,109 @@
|
||||
%% File Header/文件说明
|
||||
%
|
||||
% Beamforming with phased array derives signal characteristics from phase
|
||||
% differences between sensors. Therefore the amplitude-phase consistence is
|
||||
% vital to phased systems.
|
||||
%
|
||||
% The script analyzes the amp-phase relations of ILA captured data, the format
|
||||
% of which is square-shaped pseudorandorm bit sequence. Each channel is
|
||||
% processed seperately with different frequency shifts and different optimum
|
||||
% sampling points. The estimation of amplitude and phase are based on
|
||||
% acculumated correlation peaks.
|
||||
%
|
||||
clc; clear;
|
||||
%% initial parameters/初始参数
|
||||
interp = 8; % interpolation factor
|
||||
channelNum = 4;
|
||||
dataLen = 131072;
|
||||
fs = 48e6;
|
||||
dataFile = "iladata_ant_3-1.csv";
|
||||
|
||||
% standard pn sequence
|
||||
pnSequence = comm.PNSequence('Polynomial','x^7+x^6+1', ...
|
||||
'InitialConditions',[zeros(1,6),1],'SamplesPerFrame',2^7-1);
|
||||
PRBS7 = pnSequence();
|
||||
PRBS7_polar = 1-2*[PRBS7;0];
|
||||
|
||||
chipLen = length(PRBS7_polar); % pn chip length
|
||||
symNum = dataLen/chipLen/interp; % total symbol number
|
||||
symNumPerAccum = 1; % symbol nbumber of each accumulation
|
||||
accNum = symNum/symNumPerAccum; % total accumulation numbers, i.e. peak numbers
|
||||
|
||||
%% data analysis
|
||||
|
||||
% read data, and swap ch1 and ch2, because loop data locate at ch2 and ch4
|
||||
rxdata = readmatrix(dataFile);
|
||||
seqRx(:,1) = (rxdata(:, 6) + 1i*rxdata(:, 7)).';
|
||||
seqRx(:,2) = (rxdata(:, 4) + 1i*rxdata(:, 5)).';
|
||||
seqRx(:,3) = (rxdata(:, 8) + 1i*rxdata(:, 9)).';
|
||||
seqRx(:,4) = (rxdata(:,10) + 1i*rxdata(:,11)).';
|
||||
|
||||
% compensate frequecny deviation and downsample at optimum sample position based
|
||||
% on the varience of constellation
|
||||
if dataFile.contains("loop")
|
||||
[seqRxDown,fd,samplePos] = suqareShapeFreqEst(seqRx,interp,fs,-50,50,5);
|
||||
else
|
||||
[seqRxDown,fd,samplePos] = suqareShapeFreqEst(seqRx,interp,fs,24900,25100,1);
|
||||
end
|
||||
|
||||
% split [seqRxDown] into multiple groups, each group contains several symbols to
|
||||
% be correlated with PRBS7 and accumulated
|
||||
seqRxDownSplit = reshape(seqRxDown(1:dataLen/interp,:),chipLen*symNumPerAccum, ...
|
||||
accNum,channelNum);
|
||||
|
||||
seqRxAcc = zeros(chipLen,accNum,channelNum);
|
||||
desiredPnt = zeros(accNum,channelNum);
|
||||
ampEstSym = zeros(accNum,channelNum);
|
||||
angleEstSym = zeros(accNum,channelNum);
|
||||
|
||||
for i = 1:accNum
|
||||
for j = 1:channelNum
|
||||
% correlation & multi-symbol accumulation
|
||||
groupCorrAcc = sum(reshape(conv(flip(seqRxDownSplit(:,i,j)), ...
|
||||
PRBS7_polar,'same'),chipLen,symNumPerAccum),2)';
|
||||
seqRxAcc(:,i,j) = groupCorrAcc;
|
||||
% peak position
|
||||
desiredPnt(i,j) = groupCorrAcc(abs(groupCorrAcc)==max(abs(groupCorrAcc)));
|
||||
end
|
||||
end
|
||||
|
||||
for i = 1:channelNum
|
||||
ampEstSym(:,i) = abs(desiredPnt(:,i))./abs(desiredPnt(:,1));
|
||||
angleEstSym(:,i) = mod((angle(desiredPnt(:,i))-angle(desiredPnt(:,1)))/pi*180,360);
|
||||
end
|
||||
|
||||
%% figures
|
||||
figure(1);
|
||||
if dataFile.contains("loop")
|
||||
|
||||
subplot(121);
|
||||
plot(ampEstSym(:,[1,4]));
|
||||
legend({"ch1","ch4"});
|
||||
title("Amplitude Estimation");
|
||||
ylim([min(ampEstSym(:,[1,4]),[],'all')-0.1,max(ampEstSym(:,[1,4]),[],'all')+0.1]);
|
||||
grid on; grid minor;
|
||||
|
||||
subplot(122);
|
||||
plot(angleEstSym(:,[1,4]));
|
||||
legend({"ch1","ch4"});
|
||||
title("Angle Estimation");
|
||||
ylim([min(angleEstSym(:,[1,4]),[],'all')-1,max(angleEstSym(:,[1,4]),[],'all')+1]);
|
||||
grid on; grid minor;
|
||||
|
||||
else
|
||||
|
||||
subplot(121);
|
||||
plot(ampEstSym);
|
||||
legend({"ch1","ch2","ch3","ch4"});
|
||||
title("Amplitude Estimation");
|
||||
ylim([min(ampEstSym,[],'all')-0.2,max(ampEstSym,[],'all')+0.2]);
|
||||
grid on; grid minor;
|
||||
|
||||
subplot(122);
|
||||
plot(angleEstSym);
|
||||
legend({"ch1","ch2","ch3","ch4"});
|
||||
title("Angle Estimation");
|
||||
ylim([min(angleEstSym,[],'all')-10,max(angleEstSym,[],'all')+10]);
|
||||
grid on; grid minor;
|
||||
|
||||
end
|
||||
@@ -0,0 +1,50 @@
|
||||
function [dataOut, fdTarget, samplePosTarget] = suqareShapeFreqEst(dataIn, interp, fs, fmin, fmax, fd)
|
||||
%suqareShapeFreqEst - 利用星座图的集中程度在一定频率范围内使用频率步进估计方波成形信号的频偏
|
||||
%
|
||||
% data - input complex data, row vector
|
||||
% dataLen - data length
|
||||
% interp - interpolation rate
|
||||
% fs - sampling rate, in Herts
|
||||
% fmin - minimum estimation frequency, in Herts
|
||||
% fmax - maximum estimation frequency, in Herts
|
||||
% fd - estimation frequency step, in Herts
|
||||
|
||||
% dimension
|
||||
[dataLen,channelNum] = size(dataIn);
|
||||
|
||||
freqList = fmin:fd:fmax;
|
||||
freqNum = length(freqList);
|
||||
varRecord = zeros(freqNum,interp);
|
||||
|
||||
dataOut = zeros(dataLen/interp,channelNum);
|
||||
fdTarget = zeros(channelNum,1);
|
||||
samplePosTarget = zeros(channelNum,1);
|
||||
|
||||
for channel = 1:channelNum
|
||||
|
||||
for freq = 1:freqNum
|
||||
|
||||
% carrier
|
||||
cxr = exp(-1i*2*pi*freqList(freq)/fs*(0:dataLen-1)');
|
||||
|
||||
% apply frequency shift onto input data
|
||||
seqRx = dataIn(:,channel).*cxr;
|
||||
|
||||
for samplePos = 0:interp-1
|
||||
seqRxDown = downsample(seqRx,interp,samplePos); % 下采样
|
||||
seqRxDownQuaterOne = abs(real(seqRxDown)) + 1i*abs(imag(seqRxDown)); % 集中到第一象限
|
||||
varRecord(freq,samplePos+1) = var(seqRxDownQuaterOne);
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
[fdIndex, samplePosIndex] = find(varRecord==min(min(varRecord)));
|
||||
fdTarget(channel) = freqList(fdIndex);
|
||||
samplePosTarget(channel) = samplePosIndex-1;
|
||||
|
||||
cxrTarget = exp(-1i*2*pi*fdTarget(channel)/fs*(0:dataLen-1)');
|
||||
seqRxTarget = dataIn(:,channel).*cxrTarget;
|
||||
dataOut(:,channel) = downsample(seqRxTarget,interp,samplePosTarget(channel));
|
||||
end
|
||||
|
||||
end
|
||||
LFS
Executable
BIN
Binary file not shown.
|
LFS
Executable
BIN
Binary file not shown.
|
LFS
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@@ -0,0 +1,71 @@
|
||||
close all;
|
||||
|
||||
% 4 ch
|
||||
fileNameList = [...
|
||||
"iladata_814_1t1r_48msps_bw15m_ext_lo_1-1.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_ext_lo_1-2.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_ext_lo_1-3.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_ext_lo_2-1.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_ext_lo_2-2.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_ext_lo_2-3.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_ext_lo_3-1.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_ext_lo_3-2.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_ext_lo_3-3.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_int_lo_1-1.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_int_lo_1-2.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_int_lo_1-3.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_int_lo_2-1.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_int_lo_2-2.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_int_lo_2-3.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_int_lo_3-1.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_int_lo_3-2.csv",...
|
||||
"iladata_814_1t1r_48msps_bw15m_int_lo_3-3.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_ext_lo_1-1.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_ext_lo_1-2.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_ext_lo_1-3.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_ext_lo_2-1.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_ext_lo_2-2.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_ext_lo_2-3.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_ext_lo_3-1.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_ext_lo_3-2.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_ext_lo_3-3.csv",...
|
||||
"iladata_814_1t2r_48msps_bw40m_ext_lo_1-1.csv",...
|
||||
"iladata_814_1t2r_48msps_bw40m_ext_lo_1-2.csv",...
|
||||
"iladata_814_1t2r_48msps_bw40m_ext_lo_1-3.csv",...
|
||||
"iladata_814_1t2r_48msps_bw40m_ext_lo_2-1.csv",...
|
||||
"iladata_814_1t2r_48msps_bw40m_ext_lo_2-2.csv",...
|
||||
"iladata_814_1t2r_48msps_bw40m_ext_lo_2-3.csv",...
|
||||
"iladata_814_1t2r_48msps_bw40m_ext_lo_3-1.csv",...
|
||||
"iladata_814_1t2r_48msps_bw40m_ext_lo_3-2.csv",...
|
||||
"iladata_814_1t2r_48msps_bw40m_ext_lo_3-3.csv"
|
||||
];
|
||||
|
||||
[~,fileNum] = size(fileNameList);
|
||||
|
||||
maxList = strings(fileNum+1,5);
|
||||
stdList = strings(fileNum+1,5);
|
||||
|
||||
maxList(1,:) = ["Max Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
maxList(2:end,1) = fileNameList;
|
||||
stdList(1,:) = ["Std Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
stdList(2:end,1) = fileNameList;
|
||||
|
||||
for i = 1:fileNum
|
||||
rxRaw = readmatrix(fileNameList(:,i));
|
||||
[rowNum,colNum] = size(rxRaw);
|
||||
|
||||
if (colNum == 11)
|
||||
rx = [rxRaw(:, 4)+1i*rxRaw(:, 5),rxRaw(:, 6)+1i*rxRaw(:, 7),...
|
||||
rxRaw(:, 8)+1i*rxRaw(:, 9),rxRaw(:,10)+1i*rxRaw(:,11)];
|
||||
elseif (colNum == 7)
|
||||
rx = [rxRaw(:, 4)+1i*rxRaw(:, 5),rxRaw(:, 6)+1i*rxRaw(:, 7),...
|
||||
zeros(rowNum,1),zeros(rowNum,1)];
|
||||
else
|
||||
disp('Invalid Data Format.')
|
||||
return
|
||||
end
|
||||
|
||||
maxList(i+1,2:end) = string(max(rx));
|
||||
stdList(i+1,2:end) = string(std(rx));
|
||||
|
||||
end
|
||||
@@ -0,0 +1,11 @@
|
||||
# 数据说明
|
||||
|
||||
1. iladata_ad9361_pure_noise.csv: 调零板 AD9361 单板噪声。
|
||||
|
||||
2. iladata_ad9361_ant_noise.csv: 调零板射频接收噪声。
|
||||
|
||||
3. iladata_ad9361_pure_noise_A-B.csv: 调零板 AD9361 单板噪声，第 A 次上电过程中第 B 次采集结果。
|
||||
|
||||
> 1~3 AD9361 配置均为 48Msps，BW 40MHz，外部本振，使用 AD9516-3 的 VCO 分频时钟。
|
||||
|
||||
4. iladata_814_1t2r_48msps_bwxxm_xxx_lo_A-B.csv：调零板 AD9361 单板噪声，48Msps，BW xxMHz，ext_lo 表示外部本振，int_lo 表示内部本振，第 A 次上电过程中第 B 次采集结果。
|
||||
BIN
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|
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|
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|
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|
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|
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|
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|
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|
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|
+44
@@ -0,0 +1,44 @@
|
||||
clear; close all;
|
||||
|
||||
% 4 ch
|
||||
fileNameList = [...
|
||||
"iladata_814_1t2r_48msps_bw15m_buff_clk_noise_1-1.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_buff_clk_noise_1-2.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_buff_clk_noise_1-3.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_buff_clk_noise_2-1.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_buff_clk_noise_2-2.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_buff_clk_noise_2-3.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_buff_clk_noise_3-1.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_buff_clk_noise_3-2.csv",...
|
||||
"iladata_814_1t2r_48msps_bw15m_buff_clk_noise_3-3.csv",...
|
||||
];
|
||||
|
||||
[~,fileNum] = size(fileNameList);
|
||||
|
||||
maxList = strings(fileNum+1,5);
|
||||
stdList = strings(fileNum+1,5);
|
||||
|
||||
maxList(1,:) = ["Max Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
maxList(2:end,1) = fileNameList;
|
||||
stdList(1,:) = ["Std Value", "ch1", "ch2", "ch3", "ch4"];
|
||||
stdList(2:end,1) = fileNameList;
|
||||
|
||||
for i = 1:fileNum
|
||||
rxRaw = readmatrix(fileNameList(:,i));
|
||||
[rowNum,colNum] = size(rxRaw);
|
||||
|
||||
if (colNum == 11)
|
||||
rx = [rxRaw(:, 4)+1i*rxRaw(:, 5),rxRaw(:, 6)+1i*rxRaw(:, 7),...
|
||||
rxRaw(:, 8)+1i*rxRaw(:, 9),rxRaw(:,10)+1i*rxRaw(:,11)];
|
||||
elseif (colNum == 7)
|
||||
rx = [rxRaw(:, 4)+1i*rxRaw(:, 5),rxRaw(:, 6)+1i*rxRaw(:, 7),...
|
||||
zeros(rowNum,1),zeros(rowNum,1)];
|
||||
else
|
||||
disp('Invalid Data Format.')
|
||||
return
|
||||
end
|
||||
|
||||
maxList(i+1,2:end) = string(max(rx));
|
||||
stdList(i+1,2:end) = string(std(rx));
|
||||
|
||||
end
|
||||
BIN
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|
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|
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|
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|
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|
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|
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|
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|
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|
+86
@@ -0,0 +1,86 @@
|
||||
%% File Header/文件说明
|
||||
%
|
||||
% Beamforming with phased array derives signal characteristics from phase
|
||||
% differences between sensors. Therefore the amplitude-phase consistence is
|
||||
% vital to phased systems.
|
||||
%
|
||||
% The script analyzes the amp-phase relations of ILA captured data, the format
|
||||
% of which is square-shaped pseudorandorm bit sequence. Each channel is
|
||||
% processed seperately with different frequency shifts and different optimum
|
||||
% sampling points. The estimation of amplitude and phase are based on
|
||||
% acculumated correlation peaks.
|
||||
%
|
||||
clc; clear;
|
||||
%% initial parameters/初始参数
|
||||
interp = 8; % interpolation factor
|
||||
channelNum = 4;
|
||||
dataLen = 131072;
|
||||
fs = 48e6;
|
||||
dataFile = "iladata_814_1t2r_48msps_bw15m_ext_lo_rxfir_bpsk_1-1.csv";
|
||||
|
||||
% standard pn sequence
|
||||
pnSequence = comm.PNSequence('Polynomial','x^7+x^6+1', ...
|
||||
'InitialConditions',[zeros(1,6),1],'SamplesPerFrame',2^7-1);
|
||||
PRBS7 = pnSequence();
|
||||
PRBS7_polar = 1-2*[PRBS7;0];
|
||||
|
||||
chipLen = length(PRBS7_polar); % pn chip length
|
||||
symNum = dataLen/chipLen/interp; % total symbol number
|
||||
symNumPerAccum = 1; % symbol nbumber of each accumulation
|
||||
accNum = symNum/symNumPerAccum; % total accumulation numbers, i.e. peak numbers
|
||||
|
||||
%% data analysis
|
||||
|
||||
% read data, and swap ch1 and ch2, because loop data locate at ch2 and ch4
|
||||
rxdata = readmatrix(dataFile);
|
||||
seqRx(:,1) = (rxdata(:, 6) + 1i*rxdata(:, 7)).';
|
||||
seqRx(:,2) = (rxdata(:, 4) + 1i*rxdata(:, 5)).';
|
||||
seqRx(:,3) = (rxdata(:, 8) + 1i*rxdata(:, 9)).';
|
||||
seqRx(:,4) = (rxdata(:,10) + 1i*rxdata(:,11)).';
|
||||
|
||||
% compensate frequecny deviation and downsample at optimum sample position based
|
||||
% on the varience of constellation
|
||||
[seqRxDown,fd,samplePos] = suqareShapeFreqEst(seqRx,interp,fs,-50,50,5);
|
||||
|
||||
% split [seqRxDown] into multiple groups, each group contains several symbols to
|
||||
% be correlated with PRBS7 and accumulated
|
||||
seqRxDownSplit = reshape(seqRxDown(1:dataLen/interp,:),chipLen*symNumPerAccum, ...
|
||||
accNum,channelNum);
|
||||
|
||||
seqRxAcc = zeros(chipLen,accNum,channelNum);
|
||||
desiredPnt = zeros(accNum,channelNum);
|
||||
ampEstSym = zeros(accNum,channelNum);
|
||||
angleEstSym = zeros(accNum,channelNum);
|
||||
|
||||
for i = 1:accNum
|
||||
for j = 1:channelNum
|
||||
% correlation & multi-symbol accumulation
|
||||
groupCorrAcc = sum(reshape(conv(flip(seqRxDownSplit(:,i,j)), ...
|
||||
PRBS7_polar,'same'),chipLen,symNumPerAccum),2)';
|
||||
seqRxAcc(:,i,j) = groupCorrAcc;
|
||||
% peak position
|
||||
desiredPnt(i,j) = groupCorrAcc(abs(groupCorrAcc)==max(abs(groupCorrAcc)));
|
||||
end
|
||||
end
|
||||
|
||||
for i = 1:channelNum
|
||||
ampEstSym(:,i) = abs(desiredPnt(:,i))./abs(desiredPnt(:,1));
|
||||
angleEstSym(:,i) = mod((angle(desiredPnt(:,i))-angle(desiredPnt(:,1)))/pi*180,360);
|
||||
end
|
||||
|
||||
%% figures
|
||||
figure(1);
|
||||
|
||||
subplot(121);
|
||||
plot(ampEstSym(:,[1,4]));
|
||||
legend({"ch1","ch4"});
|
||||
title("Amplitude Estimation");
|
||||
ylim([min(ampEstSym(:,[1,4]),[],'all')-0.1,max(ampEstSym(:,[1,4]),[],'all')+0.1]);
|
||||
grid on; grid minor;
|
||||
|
||||
subplot(122);
|
||||
plot(angleEstSym(:,[1,4]));
|
||||
legend({"ch1","ch4"});
|
||||
title("Angle Estimation");
|
||||
ylim([min(angleEstSym(:,[1,4]),[],'all')-1,max(angleEstSym(:,[1,4]),[],'all')+1]);
|
||||
grid on; grid minor;
|
||||
+50
@@ -0,0 +1,50 @@
|
||||
function [dataOut, fdTarget, samplePosTarget] = suqareShapeFreqEst(dataIn, interp, fs, fmin, fmax, fd)
|
||||
%suqareShapeFreqEst - 利用星座图的集中程度在一定频率范围内使用频率步进估计方波成形信号的频偏
|
||||
%
|
||||
% data - input complex data, row vector
|
||||
% dataLen - data length
|
||||
% interp - interpolation rate
|
||||
% fs - sampling rate, in Herts
|
||||
% fmin - minimum estimation frequency, in Herts
|
||||
% fmax - maximum estimation frequency, in Herts
|
||||
% fd - estimation frequency step, in Herts
|
||||
|
||||
% dimension
|
||||
[dataLen,channelNum] = size(dataIn);
|
||||
|
||||
freqList = fmin:fd:fmax;
|
||||
freqNum = length(freqList);
|
||||
varRecord = zeros(freqNum,interp);
|
||||
|
||||
dataOut = zeros(dataLen/interp,channelNum);
|
||||
fdTarget = zeros(channelNum,1);
|
||||
samplePosTarget = zeros(channelNum,1);
|
||||
|
||||
for channel = 1:channelNum
|
||||
|
||||
for freq = 1:freqNum
|
||||
|
||||
% carrier
|
||||
cxr = exp(-1i*2*pi*freqList(freq)/fs*(0:dataLen-1)');
|
||||
|
||||
% apply frequency shift onto input data
|
||||
seqRx = dataIn(:,channel).*cxr;
|
||||
|
||||
for samplePos = 0:interp-1
|
||||
seqRxDown = downsample(seqRx,interp,samplePos); % 下采样
|
||||
seqRxDownQuaterOne = abs(real(seqRxDown)) + 1i*abs(imag(seqRxDown)); % 集中到第一象限
|
||||
varRecord(freq,samplePos+1) = var(seqRxDownQuaterOne);
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
[fdIndex, samplePosIndex] = find(varRecord==min(min(varRecord)));
|
||||
fdTarget(channel) = freqList(fdIndex);
|
||||
samplePosTarget(channel) = samplePosIndex-1;
|
||||
|
||||
cxrTarget = exp(-1i*2*pi*fdTarget(channel)/fs*(0:dataLen-1)');
|
||||
seqRxTarget = dataIn(:,channel).*cxrTarget;
|
||||
dataOut(:,channel) = downsample(seqRxTarget,interp,samplePosTarget(channel));
|
||||
end
|
||||
|
||||
end
|
||||
BIN
Binary file not shown.
|
BIN
Binary file not shown.
|
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user