Archived
add sampled data; add new online acq proj
the function of dmf is correct
This commit is contained in:
@@ -0,0 +1,188 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 11:51:06 06/08/2020
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// Design Name:
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// Module Name: test_784TR_top
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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// ??????9?byte? ?1-8?????????????????8???????????????????3?byte???5?don't care??
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// ?9byte??4bit??spi??4bit??????
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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/*************?????????*******************/
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module adf4351_2(
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input i_sysclk ,
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input i_arstn ,
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output o_cfgover ,
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output o_ADF4351_SCK ,
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output o_ADF4351_DATA ,
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output o_ADF4351_LE ,
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output o_ADF4351_CE ,
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output o_ADF4351_mutel ,
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input i_ADF4351_locked
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);
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localparam DATA_WIDTH = 32;
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localparam DATA_LENTH = 6;
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localparam SYS_CLOCK = 10;
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localparam LOCK_PIRED = SYS_CLOCK * 100000;
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localparam rst_time = 16'h7fff;//16'h7fff
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reg[7:0] cnt_word = 8'd0;
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reg[5:0] cnt_bits = 6'd0;
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reg [DATA_WIDTH-1:0] cfgdata = 0;
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wire [DATA_WIDTH-1:0] regdata;
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reg cfgover = 1'b0 ;
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reg pll_locked = 1'b0 ;
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reg load_en = 1'b0 ;
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reg [31:0] cnt_lock = 32'b0;
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(* KEEP = "TRUE" *)reg[3:0] cfgstate = 4'b0000;
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wire spiIdle;
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reg spi_sdi = 1'b0,spi_csb = 1'b1 ;
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assign o_cfgover = cfgover ;
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assign o_ADF4351_LE = load_en ;
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assign o_ADF4351_mutel= 1'b1 ;
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assign o_ADF4351_SCK = o_ADF4351_CE ? 1'b0 : i_sysclk ;
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assign o_ADF4351_CE = spi_csb ;
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assign o_ADF4351_DATA = spi_sdi ;
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reg [DATA_WIDTH-1:0] CFGREG0 ;
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assign regdata = CFGREG0 ;
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reg cfg_start ;
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reg [15:0] counter0 ;
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always@ (posedge i_sysclk)
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if(~i_arstn)
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CFGREG0 <= 32'b0;
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else begin
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//RFout = Fpfd*(INT + (Frac/Mod)) Fpfd = Refin*[(1+D)/(R*(1+T))]
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case (cnt_word)
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8'h00: CFGREG0 <= {32'h580005}; //reg 5
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8'h01: CFGREG0 <= {32'h85003C}; //reg 4
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8'h02: CFGREG0 <= {32'h4B3}; //reg 3
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8'h03: CFGREG0 <= {32'h28F42}; //reg 2 {5'b0,T,R,D,12'h,reg2} R = 1 D = 1 T = 1
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8'h04: CFGREG0 <= {32'h8008011}; //reg 1 {3'd0,phase adjust,prescaler,phase value,Frac,reg1}mod = 25
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8'h05: CFGREG0 <= {32'hC80000}; //reg 0 {1'b0,int,frac,reg0} int = 52 frac= 8
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default : CFGREG0 <= 32'b0;
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endcase
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end
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always@(negedge i_sysclk)begin
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if(~i_arstn)begin
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cfgdata <= 0;
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cnt_word <= 8'd0;
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cnt_bits <= 6'd0;
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cfgover <= 1'b0;
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cfgstate <= 4'd0;
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spi_csb <= 1'b1;
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load_en <= 1'b1;
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spi_sdi <= 1'b0;
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end
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else begin
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case(cfgstate)
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4'd0:begin
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if(cfg_start)begin
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cfgstate <= 4'd1;
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end
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else begin
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spi_csb <= 1'b1;
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load_en <= 1'b0;
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spi_sdi <= 1'b0;
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cfgover <= 1'b0;
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cfgstate <= 4'd0;
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end
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end
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4'd1:begin
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cfgdata <= regdata;
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cnt_lock <= 32'd0;
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cnt_bits <= 6'd0;
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cfgstate <= cfgstate + 1'b1;
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end
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4'd2:begin
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spi_csb <= 1'b0;
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load_en <= 1'b0;
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spi_sdi <= cfgdata[DATA_WIDTH-1];
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cfgdata <= cfgdata << 1'b1;
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cnt_bits <= cnt_bits + 1'b1;
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if(cnt_bits == DATA_WIDTH-1)begin
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cfgstate <= cfgstate + 1'b1;
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cnt_word <= cnt_word + 1'b1;
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end
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end
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4'd3:begin
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spi_csb <= 1'b1;
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load_en <= 1'b1;
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spi_sdi <= 1'b0;
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if(cnt_word == DATA_LENTH)
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cfgstate <= cfgstate + 1'b1;
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else
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cfgstate <= 4'd0;
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end
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4'd4:begin
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cfgstate <= 4'd5;
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spi_csb <= 1'b1;
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load_en <= 1'b0;
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spi_sdi <= 1'b0;
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end
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4'd5:begin//ftw cfg
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if(cnt_lock > LOCK_PIRED)
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begin
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pll_locked <= i_ADF4351_locked;
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cnt_lock <= cnt_lock;
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if( (pll_locked == 1'b0) && (cnt_lock > LOCK_PIRED))
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begin
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cfgstate <= 4'd1;
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cnt_word <= 8'd0;
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end
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else
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begin
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cfgstate <= 4'd5;
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spi_csb <= 1'b1;
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spi_sdi <= 1'b0;
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cfgover <= 1'b1;
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end
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end
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else
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begin
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cnt_lock <= cnt_lock + 1'b1;
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end
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end
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default:cfgstate <= 4'd0;
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endcase
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end
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end
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always@(negedge i_sysclk)begin
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if(~i_arstn)begin
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counter0 <= 16'd0;
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cfg_start <= 1'b0;
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end
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else begin
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if(counter0 == rst_time)begin//16'h7fff
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counter0 <= counter0;
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cfg_start <= 1'b1;
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end
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else begin
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counter0 <= counter0 + 1'b1;
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cfg_start <= 1'b0;
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end
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end
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end
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endmodule
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@@ -0,0 +1,441 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 14:37:16 01/15/2022
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// Design Name:
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// Module Name: FRAC1
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module FRAC1(
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input clka,
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input [15:0] addra,
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output reg[24:0] douta
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);
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reg[11:0] addr=0;
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always@(posedge clka)begin
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addr<= (addra+375) % 400 ;
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end
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always@(posedge clka)begin
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case(addr)
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0 : douta <= 0 ;
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1 : douta <= 83886 ;
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2 : douta <= 167772 ;
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3 : douta <= 251658 ;
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4 : douta <= 335544 ;
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5 : douta <= 419430 ;
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6 : douta <= 503316 ;
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7 : douta <= 587202 ;
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8 : douta <= 671088 ;
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9 : douta <= 754974 ;
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10 : douta <= 838860 ;
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11 : douta <= 922746 ;
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12 : douta <= 1006632 ;
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13 : douta <= 1090519 ;
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14 : douta <= 1174405 ;
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15 : douta <= 1258291 ;
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16 : douta <= 1342177 ;
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17 : douta <= 1426063 ;
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18 : douta <= 1509949 ;
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19 : douta <= 1593835 ;
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20 : douta <= 1677721 ;
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21 : douta <= 1761607 ;
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22 : douta <= 1845493 ;
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23 : douta <= 1929379 ;
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24 : douta <= 2013265 ;
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25 : douta <= 2097152 ;
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26 : douta <= 2181038 ;
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27 : douta <= 2264924 ;
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28 : douta <= 2348810 ;
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29 : douta <= 2432696 ;
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30 : douta <= 2516582 ;
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31 : douta <= 2600468 ;
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32 : douta <= 2684354 ;
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33 : douta <= 2768240 ;
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34 : douta <= 2852126 ;
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35 : douta <= 2936012 ;
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36 : douta <= 3019898 ;
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37 : douta <= 3103784 ;
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38 : douta <= 3187671 ;
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39 : douta <= 3271557 ;
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40 : douta <= 3355443 ;
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41 : douta <= 3439329 ;
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42 : douta <= 3523215 ;
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43 : douta <= 3607101 ;
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44 : douta <= 3690987 ;
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45 : douta <= 3774873 ;
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46 : douta <= 3858759 ;
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47 : douta <= 3942645 ;
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48 : douta <= 4026531 ;
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49 : douta <= 4110417 ;
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50 : douta <= 4194304 ;
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51 : douta <= 4278190 ;
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52 : douta <= 4362076 ;
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53 : douta <= 4445962 ;
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54 : douta <= 4529848 ;
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55 : douta <= 4613734 ;
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56 : douta <= 4697620 ;
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57 : douta <= 4781506 ;
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58 : douta <= 4865392 ;
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59 : douta <= 4949278 ;
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60 : douta <= 5033164 ;
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61 : douta <= 5117050 ;
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62 : douta <= 5200936 ;
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63 : douta <= 5284823 ;
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64 : douta <= 5368709 ;
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65 : douta <= 5452595 ;
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66 : douta <= 5536481 ;
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67 : douta <= 5620367 ;
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68 : douta <= 5704253 ;
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69 : douta <= 5788139 ;
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70 : douta <= 5872025 ;
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71 : douta <= 5955911 ;
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72 : douta <= 6039797 ;
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73 : douta <= 6123683 ;
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74 : douta <= 6207569 ;
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75 : douta <= 6291456 ;
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76 : douta <= 6375342 ;
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77 : douta <= 6459228 ;
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78 : douta <= 6543114 ;
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79 : douta <= 6627000 ;
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80 : douta <= 6710886 ;
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81 : douta <= 6794772 ;
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82 : douta <= 6878658 ;
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83 : douta <= 6962544 ;
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84 : douta <= 7046430 ;
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85 : douta <= 7130316 ;
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86 : douta <= 7214202 ;
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87 : douta <= 7298088 ;
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88 : douta <= 7381975 ;
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89 : douta <= 7465861 ;
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90 : douta <= 7549747 ;
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91 : douta <= 7633633 ;
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92 : douta <= 7717519 ;
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93 : douta <= 7801405 ;
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94 : douta <= 7885291 ;
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95 : douta <= 7969177 ;
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96 : douta <= 8053063 ;
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97 : douta <= 8136949 ;
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98 : douta <= 8220835 ;
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99 : douta <= 8304721 ;
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100 : douta <= 8388608 ;
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101 : douta <= 8472494 ;
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102 : douta <= 8556380 ;
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103 : douta <= 8640266 ;
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104 : douta <= 8724152 ;
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105 : douta <= 8808038 ;
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106 : douta <= 8891924 ;
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107 : douta <= 8975810 ;
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108 : douta <= 9059696 ;
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109 : douta <= 9143582 ;
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110 : douta <= 9227468 ;
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111 : douta <= 9311354 ;
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112 : douta <= 9395240 ;
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113 : douta <= 9479127 ;
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114 : douta <= 9563013 ;
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115 : douta <= 9646899 ;
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116 : douta <= 9730785 ;
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117 : douta <= 9814671 ;
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118 : douta <= 9898557 ;
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119 : douta <= 9982443 ;
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120 : douta <= 10066329 ;
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121 : douta <= 10150215 ;
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122 : douta <= 10234101 ;
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123 : douta <= 10317987 ;
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124 : douta <= 10401873 ;
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125 : douta <= 10485760 ;
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126 : douta <= 10569646 ;
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127 : douta <= 10653532 ;
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128 : douta <= 10737418 ;
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129 : douta <= 10821304 ;
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130 : douta <= 10905190 ;
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131 : douta <= 10989076 ;
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132 : douta <= 11072962 ;
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133 : douta <= 11156848 ;
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134 : douta <= 11240734 ;
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135 : douta <= 11324620 ;
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136 : douta <= 11408506 ;
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137 : douta <= 11492392 ;
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138 : douta <= 11576279 ;
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139 : douta <= 11660165 ;
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140 : douta <= 11744051 ;
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141 : douta <= 11827937 ;
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142 : douta <= 11911823 ;
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143 : douta <= 11995709 ;
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144 : douta <= 12079595 ;
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145 : douta <= 12163481 ;
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146 : douta <= 12247367 ;
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147 : douta <= 12331253 ;
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148 : douta <= 12415139 ;
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149 : douta <= 12499025 ;
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150 : douta <= 12582912 ;
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151 : douta <= 12666798 ;
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152 : douta <= 12750684 ;
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153 : douta <= 12834570 ;
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154 : douta <= 12918456 ;
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155 : douta <= 13002342 ;
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156 : douta <= 13086228 ;
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157 : douta <= 13170114 ;
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158 : douta <= 13254000 ;
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159 : douta <= 13337886 ;
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160 : douta <= 13421772 ;
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161 : douta <= 13505658 ;
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162 : douta <= 13589544 ;
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163 : douta <= 13673431 ;
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164 : douta <= 13757317 ;
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165 : douta <= 13841203 ;
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166 : douta <= 13925089 ;
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167 : douta <= 14008975 ;
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168 : douta <= 14092861 ;
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169 : douta <= 14176747 ;
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170 : douta <= 14260633 ;
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171 : douta <= 14344519 ;
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172 : douta <= 14428405 ;
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173 : douta <= 14512291 ;
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174 : douta <= 14596177 ;
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175 : douta <= 14680064 ;
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176 : douta <= 14763950 ;
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177 : douta <= 14847836 ;
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178 : douta <= 14931722 ;
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179 : douta <= 15015608 ;
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180 : douta <= 15099494 ;
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181 : douta <= 15183380 ;
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182 : douta <= 15267266 ;
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183 : douta <= 15351152 ;
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184 : douta <= 15435038 ;
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185 : douta <= 15518924 ;
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186 : douta <= 15602810 ;
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187 : douta <= 15686696 ;
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188 : douta <= 15770583 ;
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189 : douta <= 15854469 ;
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190 : douta <= 15938355 ;
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191 : douta <= 16022241 ;
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192 : douta <= 16106127 ;
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193 : douta <= 16190013 ;
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194 : douta <= 16273899 ;
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195 : douta <= 16357785 ;
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196 : douta <= 16441671 ;
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197 : douta <= 16525557 ;
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198 : douta <= 16609443 ;
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199 : douta <= 16693329 ;
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200 : douta <= 16777216 ;
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201 : douta <= 16861102 ;
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202 : douta <= 16944988 ;
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203 : douta <= 17028874 ;
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204 : douta <= 17112760 ;
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205 : douta <= 17196646 ;
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206 : douta <= 17280532 ;
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207 : douta <= 17364418 ;
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208 : douta <= 17448304 ;
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209 : douta <= 17532190 ;
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210 : douta <= 17616076 ;
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211 : douta <= 17699962 ;
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212 : douta <= 17783848 ;
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213 : douta <= 17867735 ;
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214 : douta <= 17951621 ;
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215 : douta <= 18035507 ;
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216 : douta <= 18119393 ;
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217 : douta <= 18203279 ;
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218 : douta <= 18287165 ;
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219 : douta <= 18371051 ;
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220 : douta <= 18454937 ;
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221 : douta <= 18538823 ;
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222 : douta <= 18622709 ;
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223 : douta <= 18706595 ;
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224 : douta <= 18790481 ;
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225 : douta <= 18874368 ;
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226 : douta <= 18958254 ;
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227 : douta <= 19042140 ;
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228 : douta <= 19126026 ;
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229 : douta <= 19209912 ;
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230 : douta <= 19293798 ;
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231 : douta <= 19377684 ;
|
||||
232 : douta <= 19461570 ;
|
||||
233 : douta <= 19545456 ;
|
||||
234 : douta <= 19629342 ;
|
||||
235 : douta <= 19713228 ;
|
||||
236 : douta <= 19797114 ;
|
||||
237 : douta <= 19881000 ;
|
||||
238 : douta <= 19964887 ;
|
||||
239 : douta <= 20048773 ;
|
||||
240 : douta <= 20132659 ;
|
||||
241 : douta <= 20216545 ;
|
||||
242 : douta <= 20300431 ;
|
||||
243 : douta <= 20384317 ;
|
||||
244 : douta <= 20468203 ;
|
||||
245 : douta <= 20552089 ;
|
||||
246 : douta <= 20635975 ;
|
||||
247 : douta <= 20719861 ;
|
||||
248 : douta <= 20803747 ;
|
||||
249 : douta <= 20887633 ;
|
||||
250 : douta <= 20971520 ;
|
||||
251 : douta <= 21055406 ;
|
||||
252 : douta <= 21139292 ;
|
||||
253 : douta <= 21223178 ;
|
||||
254 : douta <= 21307064 ;
|
||||
255 : douta <= 21390950 ;
|
||||
256 : douta <= 21474836 ;
|
||||
257 : douta <= 21558722 ;
|
||||
258 : douta <= 21642608 ;
|
||||
259 : douta <= 21726494 ;
|
||||
260 : douta <= 21810380 ;
|
||||
261 : douta <= 21894266 ;
|
||||
262 : douta <= 21978152 ;
|
||||
263 : douta <= 22062039 ;
|
||||
264 : douta <= 22145925 ;
|
||||
265 : douta <= 22229811 ;
|
||||
266 : douta <= 22313697 ;
|
||||
267 : douta <= 22397583 ;
|
||||
268 : douta <= 22481469 ;
|
||||
269 : douta <= 22565355 ;
|
||||
270 : douta <= 22649241 ;
|
||||
271 : douta <= 22733127 ;
|
||||
272 : douta <= 22817013 ;
|
||||
273 : douta <= 22900899 ;
|
||||
274 : douta <= 22984785 ;
|
||||
275 : douta <= 23068672 ;
|
||||
276 : douta <= 23152558 ;
|
||||
277 : douta <= 23236444 ;
|
||||
278 : douta <= 23320330 ;
|
||||
279 : douta <= 23404216 ;
|
||||
280 : douta <= 23488102 ;
|
||||
281 : douta <= 23571988 ;
|
||||
282 : douta <= 23655874 ;
|
||||
283 : douta <= 23739760 ;
|
||||
284 : douta <= 23823646 ;
|
||||
285 : douta <= 23907532 ;
|
||||
286 : douta <= 23991418 ;
|
||||
287 : douta <= 24075304 ;
|
||||
288 : douta <= 24159191 ;
|
||||
289 : douta <= 24243077 ;
|
||||
290 : douta <= 24326963 ;
|
||||
291 : douta <= 24410849 ;
|
||||
292 : douta <= 24494735 ;
|
||||
293 : douta <= 24578621 ;
|
||||
294 : douta <= 24662507 ;
|
||||
295 : douta <= 24746393 ;
|
||||
296 : douta <= 24830279 ;
|
||||
297 : douta <= 24914165 ;
|
||||
298 : douta <= 24998051 ;
|
||||
299 : douta <= 25081937 ;
|
||||
300 : douta <= 25165824 ;
|
||||
301 : douta <= 25249710 ;
|
||||
302 : douta <= 25333596 ;
|
||||
303 : douta <= 25417482 ;
|
||||
304 : douta <= 25501368 ;
|
||||
305 : douta <= 25585254 ;
|
||||
306 : douta <= 25669140 ;
|
||||
307 : douta <= 25753026 ;
|
||||
308 : douta <= 25836912 ;
|
||||
309 : douta <= 25920798 ;
|
||||
310 : douta <= 26004684 ;
|
||||
311 : douta <= 26088570 ;
|
||||
312 : douta <= 26172456 ;
|
||||
313 : douta <= 26256343 ;
|
||||
314 : douta <= 26340229 ;
|
||||
315 : douta <= 26424115 ;
|
||||
316 : douta <= 26508001 ;
|
||||
317 : douta <= 26591887 ;
|
||||
318 : douta <= 26675773 ;
|
||||
319 : douta <= 26759659 ;
|
||||
320 : douta <= 26843545 ;
|
||||
321 : douta <= 26927431 ;
|
||||
322 : douta <= 27011317 ;
|
||||
323 : douta <= 27095203 ;
|
||||
324 : douta <= 27179089 ;
|
||||
325 : douta <= 27262976 ;
|
||||
326 : douta <= 27346862 ;
|
||||
327 : douta <= 27430748 ;
|
||||
328 : douta <= 27514634 ;
|
||||
329 : douta <= 27598520 ;
|
||||
330 : douta <= 27682406 ;
|
||||
331 : douta <= 27766292 ;
|
||||
332 : douta <= 27850178 ;
|
||||
333 : douta <= 27934064 ;
|
||||
334 : douta <= 28017950 ;
|
||||
335 : douta <= 28101836 ;
|
||||
336 : douta <= 28185722 ;
|
||||
337 : douta <= 28269608 ;
|
||||
338 : douta <= 28353495 ;
|
||||
339 : douta <= 28437381 ;
|
||||
340 : douta <= 28521267 ;
|
||||
341 : douta <= 28605153 ;
|
||||
342 : douta <= 28689039 ;
|
||||
343 : douta <= 28772925 ;
|
||||
344 : douta <= 28856811 ;
|
||||
345 : douta <= 28940697 ;
|
||||
346 : douta <= 29024583 ;
|
||||
347 : douta <= 29108469 ;
|
||||
348 : douta <= 29192355 ;
|
||||
349 : douta <= 29276241 ;
|
||||
350 : douta <= 29360128 ;
|
||||
351 : douta <= 29444014 ;
|
||||
352 : douta <= 29527900 ;
|
||||
353 : douta <= 29611786 ;
|
||||
354 : douta <= 29695672 ;
|
||||
355 : douta <= 29779558 ;
|
||||
356 : douta <= 29863444 ;
|
||||
357 : douta <= 29947330 ;
|
||||
358 : douta <= 30031216 ;
|
||||
359 : douta <= 30115102 ;
|
||||
360 : douta <= 30198988 ;
|
||||
361 : douta <= 30282874 ;
|
||||
362 : douta <= 30366760 ;
|
||||
363 : douta <= 30450647 ;
|
||||
364 : douta <= 30534533 ;
|
||||
365 : douta <= 30618419 ;
|
||||
366 : douta <= 30702305 ;
|
||||
367 : douta <= 30786191 ;
|
||||
368 : douta <= 30870077 ;
|
||||
369 : douta <= 30953963 ;
|
||||
370 : douta <= 31037849 ;
|
||||
371 : douta <= 31121735 ;
|
||||
372 : douta <= 31205621 ;
|
||||
373 : douta <= 31289507 ;
|
||||
374 : douta <= 31373393 ;
|
||||
375 : douta <= 31457280 ;
|
||||
376 : douta <= 31541166 ;
|
||||
377 : douta <= 31625052 ;
|
||||
378 : douta <= 31708938 ;
|
||||
379 : douta <= 31792824 ;
|
||||
380 : douta <= 31876710 ;
|
||||
381 : douta <= 31960596 ;
|
||||
382 : douta <= 32044482 ;
|
||||
383 : douta <= 32128368 ;
|
||||
384 : douta <= 32212254 ;
|
||||
385 : douta <= 32296140 ;
|
||||
386 : douta <= 32380026 ;
|
||||
387 : douta <= 32463912 ;
|
||||
388 : douta <= 32547799 ;
|
||||
389 : douta <= 32631685 ;
|
||||
390 : douta <= 32715571 ;
|
||||
391 : douta <= 32799457 ;
|
||||
392 : douta <= 32883343 ;
|
||||
393 : douta <= 32967229 ;
|
||||
394 : douta <= 33051115 ;
|
||||
395 : douta <= 33135001 ;
|
||||
396 : douta <= 33218887 ;
|
||||
397 : douta <= 33302773 ;
|
||||
398 : douta <= 33386659 ;
|
||||
399 : douta <= 33470545 ;
|
||||
default : douta <= douta ;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,348 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:05:24 04/08/2022
|
||||
// Design Name:
|
||||
// Module Name: R_CAL
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module R_CAL_1(
|
||||
input i_clk ,
|
||||
input i_rstn ,
|
||||
input signed[7:0] i_temp ,
|
||||
input [15:0] fre_mode ,
|
||||
output reg[3:0] R_CAL
|
||||
|
||||
);
|
||||
|
||||
//接收通道1
|
||||
always@(posedge i_clk,negedge i_rstn)begin //1dB 步进
|
||||
if(!i_rstn)
|
||||
R_CAL<='d0;
|
||||
else if(i_temp>=8'sd70)begin//高温校准接收通道1
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 6 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 6 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 6 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 6 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 6 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 5 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 5 ; //20735 ~ 20774
|
||||
10: R_CAL<= 6 ; //20775 ~ 20814
|
||||
11: R_CAL<= 6 ; //20815 ~ 20854
|
||||
12: R_CAL<= 6 ; //20855 ~ 20894
|
||||
13: R_CAL<= 6 ; //20895 ~ 20934
|
||||
14: R_CAL<= 6 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 6 ; //21055 ~ 21094
|
||||
18: R_CAL<= 6 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 7 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 8 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 7 ; //21895 ~ 21934
|
||||
39: R_CAL<= 7 ; //21935 ~ 21974
|
||||
40: R_CAL<= 7 ; //21975 ~ 22014
|
||||
41: R_CAL<= 7 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 8 ; //22695 ~ 22734
|
||||
59: R_CAL<= 8 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 8 ; //23055 ~ 23094
|
||||
68: R_CAL<= 7 ; //23095 ~ 23134
|
||||
69: R_CAL<= 7 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 6 ; //23255 ~ 23294
|
||||
73: R_CAL<= 6 ; //23295 ~ 23334
|
||||
74: R_CAL<= 6 ; //23335 ~ 23374
|
||||
75: R_CAL<= 6 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 6 ; //23495 ~ 23534
|
||||
79: R_CAL<= 5 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 6 ; //23615 ~ 23654
|
||||
82: R_CAL<= 6 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 6 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
|
||||
else if(i_temp>=8'sd0)begin//常温校准接收通道1
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 6 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 6 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 6 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 6 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 6 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 5 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 5 ; //20735 ~ 20774
|
||||
10: R_CAL<= 6 ; //20775 ~ 20814
|
||||
11: R_CAL<= 6 ; //20815 ~ 20854
|
||||
12: R_CAL<= 6 ; //20855 ~ 20894
|
||||
13: R_CAL<= 6 ; //20895 ~ 20934
|
||||
14: R_CAL<= 6 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 6 ; //21055 ~ 21094
|
||||
18: R_CAL<= 6 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 7 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 8 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 7 ; //21895 ~ 21934
|
||||
39: R_CAL<= 7 ; //21935 ~ 21974
|
||||
40: R_CAL<= 7 ; //21975 ~ 22014
|
||||
41: R_CAL<= 7 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 8 ; //22695 ~ 22734
|
||||
59: R_CAL<= 8 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 8 ; //23055 ~ 23094
|
||||
68: R_CAL<= 7 ; //23095 ~ 23134
|
||||
69: R_CAL<= 7 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 6 ; //23255 ~ 23294
|
||||
73: R_CAL<= 6 ; //23295 ~ 23334
|
||||
74: R_CAL<= 6 ; //23335 ~ 23374
|
||||
75: R_CAL<= 6 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 6 ; //23495 ~ 23534
|
||||
79: R_CAL<= 5 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 6 ; //23615 ~ 23654
|
||||
82: R_CAL<= 6 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 6 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
else begin//低温校准接收通道1
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 6 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 6 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 6 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 6 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 6 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 5 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 5 ; //20735 ~ 20774
|
||||
10: R_CAL<= 6 ; //20775 ~ 20814
|
||||
11: R_CAL<= 6 ; //20815 ~ 20854
|
||||
12: R_CAL<= 6 ; //20855 ~ 20894
|
||||
13: R_CAL<= 6 ; //20895 ~ 20934
|
||||
14: R_CAL<= 6 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 6 ; //21055 ~ 21094
|
||||
18: R_CAL<= 6 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 7 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 8 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 7 ; //21895 ~ 21934
|
||||
39: R_CAL<= 7 ; //21935 ~ 21974
|
||||
40: R_CAL<= 7 ; //21975 ~ 22014
|
||||
41: R_CAL<= 7 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 8 ; //22695 ~ 22734
|
||||
59: R_CAL<= 8 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 8 ; //23055 ~ 23094
|
||||
68: R_CAL<= 7 ; //23095 ~ 23134
|
||||
69: R_CAL<= 7 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 6 ; //23255 ~ 23294
|
||||
73: R_CAL<= 6 ; //23295 ~ 23334
|
||||
74: R_CAL<= 6 ; //23335 ~ 23374
|
||||
75: R_CAL<= 6 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 6 ; //23495 ~ 23534
|
||||
79: R_CAL<= 5 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 6 ; //23615 ~ 23654
|
||||
82: R_CAL<= 6 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 6 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,349 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:05:24 04/08/2022
|
||||
// Design Name:
|
||||
// Module Name: R_CAL
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module R_CAL_2(
|
||||
input i_clk ,
|
||||
input i_rstn ,
|
||||
input signed[7:0] i_temp ,
|
||||
input [15:0] fre_mode ,
|
||||
output reg[3:0] R_CAL
|
||||
|
||||
);
|
||||
|
||||
|
||||
//接收通道2
|
||||
always@(posedge i_clk,negedge i_rstn)begin //1dB 步进
|
||||
if(!i_rstn)
|
||||
R_CAL<='d0;
|
||||
else if(i_temp>=8'sd70)begin//高温校准接收通道2
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 6 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 6 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 6 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 5 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 5 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 5 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 5 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 5 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 5 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 5 ; //20735 ~ 20774
|
||||
10: R_CAL<= 5 ; //20775 ~ 20814
|
||||
11: R_CAL<= 5 ; //20815 ~ 20854
|
||||
12: R_CAL<= 5 ; //20855 ~ 20894
|
||||
13: R_CAL<= 5 ; //20895 ~ 20934
|
||||
14: R_CAL<= 5 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 6 ; //21055 ~ 21094
|
||||
18: R_CAL<= 6 ; //21095 ~ 21134
|
||||
19: R_CAL<= 6 ; //21135 ~ 21174
|
||||
20: R_CAL<= 6 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 7 ; //21255 ~ 21294
|
||||
23: R_CAL<= 7 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 7 ; //21895 ~ 21934
|
||||
39: R_CAL<= 7 ; //21935 ~ 21974
|
||||
40: R_CAL<= 7 ; //21975 ~ 22014
|
||||
41: R_CAL<= 7 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 7 ; //22695 ~ 22734
|
||||
59: R_CAL<= 7 ; //22735 ~ 22774
|
||||
60: R_CAL<= 7 ; //22775 ~ 22814
|
||||
61: R_CAL<= 7 ; //22815 ~ 22854
|
||||
62: R_CAL<= 7 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 7 ; //23055 ~ 23094
|
||||
68: R_CAL<= 7 ; //23095 ~ 23134
|
||||
69: R_CAL<= 7 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 7 ; //23255 ~ 23294
|
||||
73: R_CAL<= 6 ; //23295 ~ 23334
|
||||
74: R_CAL<= 6 ; //23335 ~ 23374
|
||||
75: R_CAL<= 6 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 5 ; //23495 ~ 23534
|
||||
79: R_CAL<= 5 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 5 ; //23615 ~ 23654
|
||||
82: R_CAL<= 5 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 5 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
|
||||
else if(i_temp>=8'sd0)begin//常温校准接收通道2
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 6 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 6 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 6 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 5 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 5 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 5 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 5 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 5 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 5 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 5 ; //20735 ~ 20774
|
||||
10: R_CAL<= 5 ; //20775 ~ 20814
|
||||
11: R_CAL<= 5 ; //20815 ~ 20854
|
||||
12: R_CAL<= 5 ; //20855 ~ 20894
|
||||
13: R_CAL<= 5 ; //20895 ~ 20934
|
||||
14: R_CAL<= 5 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 6 ; //21055 ~ 21094
|
||||
18: R_CAL<= 6 ; //21095 ~ 21134
|
||||
19: R_CAL<= 6 ; //21135 ~ 21174
|
||||
20: R_CAL<= 6 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 7 ; //21255 ~ 21294
|
||||
23: R_CAL<= 7 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 7 ; //21895 ~ 21934
|
||||
39: R_CAL<= 7 ; //21935 ~ 21974
|
||||
40: R_CAL<= 7 ; //21975 ~ 22014
|
||||
41: R_CAL<= 7 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 7 ; //22695 ~ 22734
|
||||
59: R_CAL<= 7 ; //22735 ~ 22774
|
||||
60: R_CAL<= 7 ; //22775 ~ 22814
|
||||
61: R_CAL<= 7 ; //22815 ~ 22854
|
||||
62: R_CAL<= 7 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 7 ; //23055 ~ 23094
|
||||
68: R_CAL<= 7 ; //23095 ~ 23134
|
||||
69: R_CAL<= 7 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 7 ; //23255 ~ 23294
|
||||
73: R_CAL<= 6 ; //23295 ~ 23334
|
||||
74: R_CAL<= 6 ; //23335 ~ 23374
|
||||
75: R_CAL<= 6 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 5 ; //23495 ~ 23534
|
||||
79: R_CAL<= 5 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 5 ; //23615 ~ 23654
|
||||
82: R_CAL<= 5 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 5 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
else begin//低温校准接收通道2
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 6 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 6 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 6 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 5 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 5 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 5 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 5 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 5 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 5 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 5 ; //20735 ~ 20774
|
||||
10: R_CAL<= 5 ; //20775 ~ 20814
|
||||
11: R_CAL<= 5 ; //20815 ~ 20854
|
||||
12: R_CAL<= 5 ; //20855 ~ 20894
|
||||
13: R_CAL<= 5 ; //20895 ~ 20934
|
||||
14: R_CAL<= 5 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 6 ; //21055 ~ 21094
|
||||
18: R_CAL<= 6 ; //21095 ~ 21134
|
||||
19: R_CAL<= 6 ; //21135 ~ 21174
|
||||
20: R_CAL<= 6 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 7 ; //21255 ~ 21294
|
||||
23: R_CAL<= 7 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 7 ; //21895 ~ 21934
|
||||
39: R_CAL<= 7 ; //21935 ~ 21974
|
||||
40: R_CAL<= 7 ; //21975 ~ 22014
|
||||
41: R_CAL<= 7 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 7 ; //22695 ~ 22734
|
||||
59: R_CAL<= 7 ; //22735 ~ 22774
|
||||
60: R_CAL<= 7 ; //22775 ~ 22814
|
||||
61: R_CAL<= 7 ; //22815 ~ 22854
|
||||
62: R_CAL<= 7 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 7 ; //23055 ~ 23094
|
||||
68: R_CAL<= 7 ; //23095 ~ 23134
|
||||
69: R_CAL<= 7 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 7 ; //23255 ~ 23294
|
||||
73: R_CAL<= 6 ; //23295 ~ 23334
|
||||
74: R_CAL<= 6 ; //23335 ~ 23374
|
||||
75: R_CAL<= 6 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 5 ; //23495 ~ 23534
|
||||
79: R_CAL<= 5 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 5 ; //23615 ~ 23654
|
||||
82: R_CAL<= 5 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 5 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,348 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:05:24 04/08/2022
|
||||
// Design Name:
|
||||
// Module Name: R_CAL
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module R_CAL_3(
|
||||
input i_clk ,
|
||||
input i_rstn ,
|
||||
input signed[7:0] i_temp ,
|
||||
input [15:0] fre_mode ,
|
||||
output reg[3:0] R_CAL
|
||||
|
||||
);
|
||||
|
||||
//接收通道3
|
||||
always@(posedge i_clk,negedge i_rstn)begin //1dB 步进
|
||||
if(!i_rstn)
|
||||
R_CAL<='d0;
|
||||
else if(i_temp>=8'sd70)begin//高温校准接收通道3
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 7 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 7 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 7 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 6 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 6 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 6 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 6 ; //20735 ~ 20774
|
||||
10: R_CAL<= 6 ; //20775 ~ 20814
|
||||
11: R_CAL<= 6 ; //20815 ~ 20854
|
||||
12: R_CAL<= 6 ; //20855 ~ 20894
|
||||
13: R_CAL<= 6 ; //20895 ~ 20934
|
||||
14: R_CAL<= 6 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 7 ; //21055 ~ 21094
|
||||
18: R_CAL<= 7 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 8 ; //21175 ~ 21214
|
||||
21: R_CAL<= 8 ; //21215 ~ 21254
|
||||
22: R_CAL<= 8 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 9 ; //21415 ~ 21454
|
||||
27: R_CAL<= 9 ; //21455 ~ 21494
|
||||
28: R_CAL<= 9 ; //21495 ~ 21534
|
||||
29: R_CAL<= 9 ; //21535 ~ 21574
|
||||
30: R_CAL<= 9 ; //21575 ~ 21614
|
||||
31: R_CAL<= 9 ; //21615 ~ 21654
|
||||
32: R_CAL<= 9 ; //21655 ~ 21694
|
||||
33: R_CAL<= 9 ; //21695 ~ 21734
|
||||
34: R_CAL<= 9 ; //21735 ~ 21774
|
||||
35: R_CAL<= 9 ; //21775 ~ 21814
|
||||
36: R_CAL<= 9 ; //21815 ~ 21854
|
||||
37: R_CAL<= 9 ; //21855 ~ 21894
|
||||
38: R_CAL<= 9 ; //21895 ~ 21934
|
||||
39: R_CAL<= 9 ; //21935 ~ 21974
|
||||
40: R_CAL<= 8 ; //21975 ~ 22014
|
||||
41: R_CAL<= 8 ; //22015 ~ 22054
|
||||
42: R_CAL<= 8 ; //22055 ~ 22094
|
||||
43: R_CAL<= 8 ; //22095 ~ 22134
|
||||
44: R_CAL<= 8 ; //22135 ~ 22174
|
||||
45: R_CAL<= 8 ; //22175 ~ 22214
|
||||
46: R_CAL<= 8 ; //22215 ~ 22254
|
||||
47: R_CAL<= 8 ; //22255 ~ 22294
|
||||
48: R_CAL<= 8 ; //22295 ~ 22334
|
||||
49: R_CAL<= 8 ; //22335 ~ 22374
|
||||
50: R_CAL<= 8 ; //22375 ~ 22414
|
||||
51: R_CAL<= 8 ; //22415 ~ 22454
|
||||
52: R_CAL<= 8 ; //22455 ~ 22494
|
||||
53: R_CAL<= 8 ; //22495 ~ 22534
|
||||
54: R_CAL<= 8 ; //22535 ~ 22574
|
||||
55: R_CAL<= 8 ; //22575 ~ 22614
|
||||
56: R_CAL<= 8 ; //22615 ~ 22654
|
||||
57: R_CAL<= 8 ; //22655 ~ 22694
|
||||
58: R_CAL<= 8 ; //22695 ~ 22734
|
||||
59: R_CAL<= 8 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 9 ; //22895 ~ 22934
|
||||
64: R_CAL<= 9 ; //22935 ~ 22974
|
||||
65: R_CAL<= 9 ; //22975 ~ 23014
|
||||
66: R_CAL<= 9 ; //23015 ~ 23054
|
||||
67: R_CAL<= 9 ; //23055 ~ 23094
|
||||
68: R_CAL<= 8 ; //23095 ~ 23134
|
||||
69: R_CAL<= 8 ; //23135 ~ 23174
|
||||
70: R_CAL<= 8 ; //23175 ~ 23214
|
||||
71: R_CAL<= 8 ; //23215 ~ 23254
|
||||
72: R_CAL<= 8 ; //23255 ~ 23294
|
||||
73: R_CAL<= 7 ; //23295 ~ 23334
|
||||
74: R_CAL<= 7 ; //23335 ~ 23374
|
||||
75: R_CAL<= 7 ; //23375 ~ 23414
|
||||
76: R_CAL<= 7 ; //23415 ~ 23454
|
||||
77: R_CAL<= 7 ; //23455 ~ 23494
|
||||
78: R_CAL<= 7 ; //23495 ~ 23534
|
||||
79: R_CAL<= 7 ; //23535 ~ 23574
|
||||
80: R_CAL<= 7 ; //23575 ~ 23614
|
||||
81: R_CAL<= 7 ; //23615 ~ 23654
|
||||
82: R_CAL<= 7 ; //23655 ~ 23694
|
||||
83: R_CAL<= 7 ; //23695 ~ 23734
|
||||
84: R_CAL<= 7 ; //23735 ~ 23774
|
||||
85: R_CAL<= 7 ; //23775 ~ 23814
|
||||
86: R_CAL<= 7 ; //23815 ~ 23854
|
||||
87: R_CAL<= 7 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
|
||||
else if(i_temp>=8'sd0)begin//常温校准接收通道3
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 7 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 7 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 7 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 6 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 6 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 6 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 6 ; //20735 ~ 20774
|
||||
10: R_CAL<= 6 ; //20775 ~ 20814
|
||||
11: R_CAL<= 6 ; //20815 ~ 20854
|
||||
12: R_CAL<= 6 ; //20855 ~ 20894
|
||||
13: R_CAL<= 6 ; //20895 ~ 20934
|
||||
14: R_CAL<= 6 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 7 ; //21055 ~ 21094
|
||||
18: R_CAL<= 7 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 8 ; //21175 ~ 21214
|
||||
21: R_CAL<= 8 ; //21215 ~ 21254
|
||||
22: R_CAL<= 8 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 9 ; //21415 ~ 21454
|
||||
27: R_CAL<= 9 ; //21455 ~ 21494
|
||||
28: R_CAL<= 9 ; //21495 ~ 21534
|
||||
29: R_CAL<= 9 ; //21535 ~ 21574
|
||||
30: R_CAL<= 9 ; //21575 ~ 21614
|
||||
31: R_CAL<= 9 ; //21615 ~ 21654
|
||||
32: R_CAL<= 9 ; //21655 ~ 21694
|
||||
33: R_CAL<= 9 ; //21695 ~ 21734
|
||||
34: R_CAL<= 9 ; //21735 ~ 21774
|
||||
35: R_CAL<= 9 ; //21775 ~ 21814
|
||||
36: R_CAL<= 9 ; //21815 ~ 21854
|
||||
37: R_CAL<= 9 ; //21855 ~ 21894
|
||||
38: R_CAL<= 9 ; //21895 ~ 21934
|
||||
39: R_CAL<= 9 ; //21935 ~ 21974
|
||||
40: R_CAL<= 8 ; //21975 ~ 22014
|
||||
41: R_CAL<= 8 ; //22015 ~ 22054
|
||||
42: R_CAL<= 8 ; //22055 ~ 22094
|
||||
43: R_CAL<= 8 ; //22095 ~ 22134
|
||||
44: R_CAL<= 8 ; //22135 ~ 22174
|
||||
45: R_CAL<= 8 ; //22175 ~ 22214
|
||||
46: R_CAL<= 8 ; //22215 ~ 22254
|
||||
47: R_CAL<= 8 ; //22255 ~ 22294
|
||||
48: R_CAL<= 8 ; //22295 ~ 22334
|
||||
49: R_CAL<= 8 ; //22335 ~ 22374
|
||||
50: R_CAL<= 8 ; //22375 ~ 22414
|
||||
51: R_CAL<= 8 ; //22415 ~ 22454
|
||||
52: R_CAL<= 8 ; //22455 ~ 22494
|
||||
53: R_CAL<= 8 ; //22495 ~ 22534
|
||||
54: R_CAL<= 8 ; //22535 ~ 22574
|
||||
55: R_CAL<= 8 ; //22575 ~ 22614
|
||||
56: R_CAL<= 8 ; //22615 ~ 22654
|
||||
57: R_CAL<= 8 ; //22655 ~ 22694
|
||||
58: R_CAL<= 8 ; //22695 ~ 22734
|
||||
59: R_CAL<= 8 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 9 ; //22895 ~ 22934
|
||||
64: R_CAL<= 9 ; //22935 ~ 22974
|
||||
65: R_CAL<= 9 ; //22975 ~ 23014
|
||||
66: R_CAL<= 9 ; //23015 ~ 23054
|
||||
67: R_CAL<= 9 ; //23055 ~ 23094
|
||||
68: R_CAL<= 8 ; //23095 ~ 23134
|
||||
69: R_CAL<= 8 ; //23135 ~ 23174
|
||||
70: R_CAL<= 8 ; //23175 ~ 23214
|
||||
71: R_CAL<= 8 ; //23215 ~ 23254
|
||||
72: R_CAL<= 8 ; //23255 ~ 23294
|
||||
73: R_CAL<= 7 ; //23295 ~ 23334
|
||||
74: R_CAL<= 7 ; //23335 ~ 23374
|
||||
75: R_CAL<= 7 ; //23375 ~ 23414
|
||||
76: R_CAL<= 7 ; //23415 ~ 23454
|
||||
77: R_CAL<= 7 ; //23455 ~ 23494
|
||||
78: R_CAL<= 7 ; //23495 ~ 23534
|
||||
79: R_CAL<= 7 ; //23535 ~ 23574
|
||||
80: R_CAL<= 7 ; //23575 ~ 23614
|
||||
81: R_CAL<= 7 ; //23615 ~ 23654
|
||||
82: R_CAL<= 7 ; //23655 ~ 23694
|
||||
83: R_CAL<= 7 ; //23695 ~ 23734
|
||||
84: R_CAL<= 7 ; //23735 ~ 23774
|
||||
85: R_CAL<= 7 ; //23775 ~ 23814
|
||||
86: R_CAL<= 7 ; //23815 ~ 23854
|
||||
87: R_CAL<= 7 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
else begin//低温校准接收通道3
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 7 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 7 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 7 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 6 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 6 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 6 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 6 ; //20735 ~ 20774
|
||||
10: R_CAL<= 6 ; //20775 ~ 20814
|
||||
11: R_CAL<= 6 ; //20815 ~ 20854
|
||||
12: R_CAL<= 6 ; //20855 ~ 20894
|
||||
13: R_CAL<= 6 ; //20895 ~ 20934
|
||||
14: R_CAL<= 6 ; //20935 ~ 20974
|
||||
15: R_CAL<= 6 ; //20975 ~ 21014
|
||||
16: R_CAL<= 6 ; //21015 ~ 21054
|
||||
17: R_CAL<= 7 ; //21055 ~ 21094
|
||||
18: R_CAL<= 7 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 8 ; //21175 ~ 21214
|
||||
21: R_CAL<= 8 ; //21215 ~ 21254
|
||||
22: R_CAL<= 8 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 9 ; //21415 ~ 21454
|
||||
27: R_CAL<= 9 ; //21455 ~ 21494
|
||||
28: R_CAL<= 9 ; //21495 ~ 21534
|
||||
29: R_CAL<= 9 ; //21535 ~ 21574
|
||||
30: R_CAL<= 9 ; //21575 ~ 21614
|
||||
31: R_CAL<= 9 ; //21615 ~ 21654
|
||||
32: R_CAL<= 9 ; //21655 ~ 21694
|
||||
33: R_CAL<= 9 ; //21695 ~ 21734
|
||||
34: R_CAL<= 9 ; //21735 ~ 21774
|
||||
35: R_CAL<= 9 ; //21775 ~ 21814
|
||||
36: R_CAL<= 9 ; //21815 ~ 21854
|
||||
37: R_CAL<= 9 ; //21855 ~ 21894
|
||||
38: R_CAL<= 9 ; //21895 ~ 21934
|
||||
39: R_CAL<= 9 ; //21935 ~ 21974
|
||||
40: R_CAL<= 8 ; //21975 ~ 22014
|
||||
41: R_CAL<= 8 ; //22015 ~ 22054
|
||||
42: R_CAL<= 8 ; //22055 ~ 22094
|
||||
43: R_CAL<= 8 ; //22095 ~ 22134
|
||||
44: R_CAL<= 8 ; //22135 ~ 22174
|
||||
45: R_CAL<= 8 ; //22175 ~ 22214
|
||||
46: R_CAL<= 8 ; //22215 ~ 22254
|
||||
47: R_CAL<= 8 ; //22255 ~ 22294
|
||||
48: R_CAL<= 8 ; //22295 ~ 22334
|
||||
49: R_CAL<= 8 ; //22335 ~ 22374
|
||||
50: R_CAL<= 8 ; //22375 ~ 22414
|
||||
51: R_CAL<= 8 ; //22415 ~ 22454
|
||||
52: R_CAL<= 8 ; //22455 ~ 22494
|
||||
53: R_CAL<= 8 ; //22495 ~ 22534
|
||||
54: R_CAL<= 8 ; //22535 ~ 22574
|
||||
55: R_CAL<= 8 ; //22575 ~ 22614
|
||||
56: R_CAL<= 8 ; //22615 ~ 22654
|
||||
57: R_CAL<= 8 ; //22655 ~ 22694
|
||||
58: R_CAL<= 8 ; //22695 ~ 22734
|
||||
59: R_CAL<= 8 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 9 ; //22895 ~ 22934
|
||||
64: R_CAL<= 9 ; //22935 ~ 22974
|
||||
65: R_CAL<= 9 ; //22975 ~ 23014
|
||||
66: R_CAL<= 9 ; //23015 ~ 23054
|
||||
67: R_CAL<= 9 ; //23055 ~ 23094
|
||||
68: R_CAL<= 8 ; //23095 ~ 23134
|
||||
69: R_CAL<= 8 ; //23135 ~ 23174
|
||||
70: R_CAL<= 8 ; //23175 ~ 23214
|
||||
71: R_CAL<= 8 ; //23215 ~ 23254
|
||||
72: R_CAL<= 8 ; //23255 ~ 23294
|
||||
73: R_CAL<= 7 ; //23295 ~ 23334
|
||||
74: R_CAL<= 7 ; //23335 ~ 23374
|
||||
75: R_CAL<= 7 ; //23375 ~ 23414
|
||||
76: R_CAL<= 7 ; //23415 ~ 23454
|
||||
77: R_CAL<= 7 ; //23455 ~ 23494
|
||||
78: R_CAL<= 7 ; //23495 ~ 23534
|
||||
79: R_CAL<= 7 ; //23535 ~ 23574
|
||||
80: R_CAL<= 7 ; //23575 ~ 23614
|
||||
81: R_CAL<= 7 ; //23615 ~ 23654
|
||||
82: R_CAL<= 7 ; //23655 ~ 23694
|
||||
83: R_CAL<= 7 ; //23695 ~ 23734
|
||||
84: R_CAL<= 7 ; //23735 ~ 23774
|
||||
85: R_CAL<= 7 ; //23775 ~ 23814
|
||||
86: R_CAL<= 7 ; //23815 ~ 23854
|
||||
87: R_CAL<= 7 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,349 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:05:24 04/08/2022
|
||||
// Design Name:
|
||||
// Module Name: R_CAL
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module R_CAL_4(
|
||||
input i_clk ,
|
||||
input i_rstn ,
|
||||
input signed[7:0] i_temp ,
|
||||
input [15:0] fre_mode ,
|
||||
output reg[3:0] R_CAL
|
||||
|
||||
);
|
||||
|
||||
|
||||
//接收通道4
|
||||
always@(posedge i_clk,negedge i_rstn)begin //1dB 步进
|
||||
if(!i_rstn)
|
||||
R_CAL<='d0;
|
||||
else if(i_temp>=8'sd70)begin//高温校准接收通道4
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 7 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 7 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 7 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 7 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 7 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 7 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 7 ; //20735 ~ 20774
|
||||
10: R_CAL<= 7 ; //20775 ~ 20814
|
||||
11: R_CAL<= 7 ; //20815 ~ 20854
|
||||
12: R_CAL<= 7 ; //20855 ~ 20894
|
||||
13: R_CAL<= 7 ; //20895 ~ 20934
|
||||
14: R_CAL<= 7 ; //20935 ~ 20974
|
||||
15: R_CAL<= 7 ; //20975 ~ 21014
|
||||
16: R_CAL<= 7 ; //21015 ~ 21054
|
||||
17: R_CAL<= 7 ; //21055 ~ 21094
|
||||
18: R_CAL<= 7 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 7 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 7 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 8 ; //21895 ~ 21934
|
||||
39: R_CAL<= 8 ; //21935 ~ 21974
|
||||
40: R_CAL<= 8 ; //21975 ~ 22014
|
||||
41: R_CAL<= 8 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 7 ; //22695 ~ 22734
|
||||
59: R_CAL<= 7 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 8 ; //23055 ~ 23094
|
||||
68: R_CAL<= 8 ; //23095 ~ 23134
|
||||
69: R_CAL<= 8 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 7 ; //23255 ~ 23294
|
||||
73: R_CAL<= 7 ; //23295 ~ 23334
|
||||
74: R_CAL<= 7 ; //23335 ~ 23374
|
||||
75: R_CAL<= 7 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 6 ; //23495 ~ 23534
|
||||
79: R_CAL<= 6 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 6 ; //23615 ~ 23654
|
||||
82: R_CAL<= 6 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 6 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
|
||||
else if(i_temp>=8'sd0)begin//常温校准接收通道4
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 7 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 7 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 7 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 7 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 7 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 7 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 7 ; //20735 ~ 20774
|
||||
10: R_CAL<= 7 ; //20775 ~ 20814
|
||||
11: R_CAL<= 7 ; //20815 ~ 20854
|
||||
12: R_CAL<= 7 ; //20855 ~ 20894
|
||||
13: R_CAL<= 7 ; //20895 ~ 20934
|
||||
14: R_CAL<= 7 ; //20935 ~ 20974
|
||||
15: R_CAL<= 7 ; //20975 ~ 21014
|
||||
16: R_CAL<= 7 ; //21015 ~ 21054
|
||||
17: R_CAL<= 7 ; //21055 ~ 21094
|
||||
18: R_CAL<= 7 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 7 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 7 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 8 ; //21895 ~ 21934
|
||||
39: R_CAL<= 8 ; //21935 ~ 21974
|
||||
40: R_CAL<= 8 ; //21975 ~ 22014
|
||||
41: R_CAL<= 8 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 7 ; //22695 ~ 22734
|
||||
59: R_CAL<= 7 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 8 ; //23055 ~ 23094
|
||||
68: R_CAL<= 8 ; //23095 ~ 23134
|
||||
69: R_CAL<= 8 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 7 ; //23255 ~ 23294
|
||||
73: R_CAL<= 7 ; //23295 ~ 23334
|
||||
74: R_CAL<= 7 ; //23335 ~ 23374
|
||||
75: R_CAL<= 7 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 6 ; //23495 ~ 23534
|
||||
79: R_CAL<= 6 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 6 ; //23615 ~ 23654
|
||||
82: R_CAL<= 6 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 6 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
else begin//低温校准接收通道4
|
||||
case(fre_mode)
|
||||
0 : R_CAL<= 7 ; //20375 ~ 20414
|
||||
1 : R_CAL<= 7 ; //20415 ~ 20454
|
||||
2 : R_CAL<= 7 ; //20455 ~ 20494
|
||||
3 : R_CAL<= 7 ; //20495 ~ 20534
|
||||
4 : R_CAL<= 7 ; //20535 ~ 20574
|
||||
5 : R_CAL<= 7 ; //20575 ~ 20614
|
||||
6 : R_CAL<= 7 ; //20615 ~ 20654
|
||||
7 : R_CAL<= 7 ; //20655 ~ 20694
|
||||
8 : R_CAL<= 7 ; //20695 ~ 20734
|
||||
9 : R_CAL<= 7 ; //20735 ~ 20774
|
||||
10: R_CAL<= 7 ; //20775 ~ 20814
|
||||
11: R_CAL<= 7 ; //20815 ~ 20854
|
||||
12: R_CAL<= 7 ; //20855 ~ 20894
|
||||
13: R_CAL<= 7 ; //20895 ~ 20934
|
||||
14: R_CAL<= 7 ; //20935 ~ 20974
|
||||
15: R_CAL<= 7 ; //20975 ~ 21014
|
||||
16: R_CAL<= 7 ; //21015 ~ 21054
|
||||
17: R_CAL<= 7 ; //21055 ~ 21094
|
||||
18: R_CAL<= 7 ; //21095 ~ 21134
|
||||
19: R_CAL<= 7 ; //21135 ~ 21174
|
||||
20: R_CAL<= 7 ; //21175 ~ 21214
|
||||
21: R_CAL<= 7 ; //21215 ~ 21254
|
||||
22: R_CAL<= 7 ; //21255 ~ 21294
|
||||
23: R_CAL<= 8 ; //21295 ~ 21334
|
||||
24: R_CAL<= 8 ; //21335 ~ 21374
|
||||
25: R_CAL<= 8 ; //21375 ~ 21414
|
||||
26: R_CAL<= 8 ; //21415 ~ 21454
|
||||
27: R_CAL<= 8 ; //21455 ~ 21494
|
||||
28: R_CAL<= 8 ; //21495 ~ 21534
|
||||
29: R_CAL<= 8 ; //21535 ~ 21574
|
||||
30: R_CAL<= 8 ; //21575 ~ 21614
|
||||
31: R_CAL<= 8 ; //21615 ~ 21654
|
||||
32: R_CAL<= 8 ; //21655 ~ 21694
|
||||
33: R_CAL<= 8 ; //21695 ~ 21734
|
||||
34: R_CAL<= 8 ; //21735 ~ 21774
|
||||
35: R_CAL<= 8 ; //21775 ~ 21814
|
||||
36: R_CAL<= 8 ; //21815 ~ 21854
|
||||
37: R_CAL<= 8 ; //21855 ~ 21894
|
||||
38: R_CAL<= 8 ; //21895 ~ 21934
|
||||
39: R_CAL<= 8 ; //21935 ~ 21974
|
||||
40: R_CAL<= 8 ; //21975 ~ 22014
|
||||
41: R_CAL<= 8 ; //22015 ~ 22054
|
||||
42: R_CAL<= 7 ; //22055 ~ 22094
|
||||
43: R_CAL<= 7 ; //22095 ~ 22134
|
||||
44: R_CAL<= 7 ; //22135 ~ 22174
|
||||
45: R_CAL<= 7 ; //22175 ~ 22214
|
||||
46: R_CAL<= 7 ; //22215 ~ 22254
|
||||
47: R_CAL<= 7 ; //22255 ~ 22294
|
||||
48: R_CAL<= 7 ; //22295 ~ 22334
|
||||
49: R_CAL<= 7 ; //22335 ~ 22374
|
||||
50: R_CAL<= 7 ; //22375 ~ 22414
|
||||
51: R_CAL<= 7 ; //22415 ~ 22454
|
||||
52: R_CAL<= 7 ; //22455 ~ 22494
|
||||
53: R_CAL<= 7 ; //22495 ~ 22534
|
||||
54: R_CAL<= 7 ; //22535 ~ 22574
|
||||
55: R_CAL<= 7 ; //22575 ~ 22614
|
||||
56: R_CAL<= 7 ; //22615 ~ 22654
|
||||
57: R_CAL<= 7 ; //22655 ~ 22694
|
||||
58: R_CAL<= 7 ; //22695 ~ 22734
|
||||
59: R_CAL<= 7 ; //22735 ~ 22774
|
||||
60: R_CAL<= 8 ; //22775 ~ 22814
|
||||
61: R_CAL<= 8 ; //22815 ~ 22854
|
||||
62: R_CAL<= 8 ; //22855 ~ 22894
|
||||
63: R_CAL<= 8 ; //22895 ~ 22934
|
||||
64: R_CAL<= 8 ; //22935 ~ 22974
|
||||
65: R_CAL<= 8 ; //22975 ~ 23014
|
||||
66: R_CAL<= 8 ; //23015 ~ 23054
|
||||
67: R_CAL<= 8 ; //23055 ~ 23094
|
||||
68: R_CAL<= 8 ; //23095 ~ 23134
|
||||
69: R_CAL<= 8 ; //23135 ~ 23174
|
||||
70: R_CAL<= 7 ; //23175 ~ 23214
|
||||
71: R_CAL<= 7 ; //23215 ~ 23254
|
||||
72: R_CAL<= 7 ; //23255 ~ 23294
|
||||
73: R_CAL<= 7 ; //23295 ~ 23334
|
||||
74: R_CAL<= 7 ; //23335 ~ 23374
|
||||
75: R_CAL<= 7 ; //23375 ~ 23414
|
||||
76: R_CAL<= 6 ; //23415 ~ 23454
|
||||
77: R_CAL<= 6 ; //23455 ~ 23494
|
||||
78: R_CAL<= 6 ; //23495 ~ 23534
|
||||
79: R_CAL<= 6 ; //23535 ~ 23574
|
||||
80: R_CAL<= 6 ; //23575 ~ 23614
|
||||
81: R_CAL<= 6 ; //23615 ~ 23654
|
||||
82: R_CAL<= 6 ; //23655 ~ 23694
|
||||
83: R_CAL<= 6 ; //23695 ~ 23734
|
||||
84: R_CAL<= 6 ; //23735 ~ 23774
|
||||
85: R_CAL<= 6 ; //23775 ~ 23814
|
||||
86: R_CAL<= 6 ; //23815 ~ 23854
|
||||
87: R_CAL<= 6 ; //23855 ~ 23875
|
||||
default:R_CAL<=R_CAL;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,301 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company: Chengdu Tiger
|
||||
// Engineer: Tangxy
|
||||
//
|
||||
// Create Date: 14:14:49 09/06/2021
|
||||
// Design Name:
|
||||
// Module Name: top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module Sisyif(
|
||||
input clk_40m ,
|
||||
input clk_20m ,
|
||||
input rst_n ,
|
||||
//调零至信处接口
|
||||
input SPI_CLK_F ,//SPI控制，时钟暂定50MHz，用来发送跳频频点、发射MGC值、接收MGC值
|
||||
input SPI_SYN_F ,//片选
|
||||
input SPI_MOSI_F ,
|
||||
output SPI_MISO_F ,
|
||||
input TP_EN_F ,//跳频使能控制(上升沿更新)
|
||||
input TR_MGC_F ,//接收发射MGC使能控制(上升沿更新)
|
||||
input CAL_F ,//校准MGC使能(上升沿更新)
|
||||
input PRF ,//高发低收，默认接收
|
||||
|
||||
//信处至射频接口
|
||||
output standby ,//高开低待机，默认待机
|
||||
output SW_PLL ,//乒乓频率源选择0：频率源A —— 1：频率源B
|
||||
output T ,//发射电源控制
|
||||
output R ,//接收电源控制
|
||||
output SW_BPF ,//开关滤波器选择
|
||||
output SCLK1 ,//锁相环A控制
|
||||
output SDIO1 ,//
|
||||
output CS1 ,//
|
||||
input LD1 ,//
|
||||
output SCLK2 ,//锁相环B控制
|
||||
output SDIO2 ,//
|
||||
output CS2 ,//
|
||||
input LD2 ,//
|
||||
output SCLK3 ,//点频源控制
|
||||
output SDIO3 ,//
|
||||
output CS3 ,//
|
||||
input LD3 ,//
|
||||
output TMGC_16db ,//发射通道MGC控制,高电平衰减
|
||||
output TMGC_8db ,//
|
||||
output TMGC_4db ,//
|
||||
output TMGC_2db ,//
|
||||
output TMGC_1db ,//
|
||||
output RMGC_16db ,//四个接收通道MGC控制，同时控制，高电平衰减
|
||||
output RMGC_8db ,//
|
||||
output RMGC_4db ,//
|
||||
output RMGC_2db ,//
|
||||
output RMGC_1db ,//
|
||||
output ENABLE ,//SPI控制四个接收通道增益校准
|
||||
output SC ,//
|
||||
output SD ,//
|
||||
output END_SYN ,//
|
||||
input SDOUT ,//
|
||||
inout DQ_WD ,//温度传感器
|
||||
output SW_RX //接收监测控制
|
||||
|
||||
);
|
||||
|
||||
wire vio_rstn ;
|
||||
wire [9:0] SYNC_OUT ;
|
||||
wire [35:0] CONTROL0 ;
|
||||
wire [35:0] CONTROL1 ;
|
||||
wire [150:0] TRIG0 ;
|
||||
|
||||
wire[15:0] temp_data ;//LSB =0.625 C
|
||||
wire[7:0] temp ;//LSB =1°C
|
||||
wire[11:0] hop_fre_code;
|
||||
wire adf4371_hop1 ;
|
||||
wire adf4371_hop2 ;
|
||||
wire [15:0] fre_code ;
|
||||
wire [7:0] tx_mgc ;
|
||||
wire [7:0] rx1_mgc ;
|
||||
wire [7:0] rx2_mgc ;
|
||||
wire [7:0] rx3_mgc ;
|
||||
wire [7:0] rx4_mgc ;
|
||||
wire [3:0] cal1_mgc ;
|
||||
wire [3:0] cal2_mgc ;
|
||||
wire [3:0] cal3_mgc ;
|
||||
wire [3:0] cal4_mgc ;
|
||||
wire [7:0] tx_cal_mgc ;
|
||||
wire [3:0] model ;
|
||||
wire [3:0] rf_en ;
|
||||
wire [31:0] frame_count;
|
||||
wire [3:0] ceshi_model;
|
||||
wire [15:0] current_fre_code ;
|
||||
wire [15:0] cal_fre_code ;
|
||||
wire [7:0] R_MGC_1 ;
|
||||
|
||||
wire SW_C1;
|
||||
wire SW;
|
||||
wire SW2;
|
||||
wire SW3;
|
||||
|
||||
wire [3:0] R_CAL1;
|
||||
wire [3:0] R_CAL2;
|
||||
wire [3:0] R_CAL3;
|
||||
wire [3:0] R_CAL4;
|
||||
wire [4:0] T_CAL ;
|
||||
|
||||
assign temp = temp_data[11:4] ;
|
||||
assign RMGC_16db = R_MGC_1[4] ;
|
||||
assign RMGC_8db = R_MGC_1[3] ;
|
||||
assign RMGC_4db = R_MGC_1[2] ;
|
||||
assign RMGC_2db = R_MGC_1[1] ;
|
||||
assign RMGC_1db = R_MGC_1[0] ;
|
||||
assign standby = rf_en == 4'b0 ;
|
||||
assign T = PRF ;
|
||||
assign R = ~PRF ;
|
||||
assign SW_BPF = SW_C1 ;
|
||||
assign SW_PLL = SW ;
|
||||
assign SW_RX = rx2_mgc == 8'b0 ? 1'b0 :1'b1 ;
|
||||
|
||||
|
||||
spi_slave u_spi_slave (
|
||||
.i_sys_clk(clk_40m),
|
||||
.i_sys_rst_n(rst_n),
|
||||
.i_spi_sck(SPI_CLK_F),
|
||||
.i_spi_cs(SPI_SYN_F),
|
||||
.i_spi_sdi(SPI_MOSI_F),
|
||||
.o_frame_count(frame_count),
|
||||
.o_fre_code(fre_code),
|
||||
.o_tx_mgc(tx_mgc),
|
||||
.o_model(model),
|
||||
.o_rf_en(rf_en),
|
||||
.o_cal1_mgc(cal1_mgc),
|
||||
.o_cal2_mgc(cal2_mgc),
|
||||
.o_cal3_mgc(cal3_mgc),
|
||||
.o_cal4_mgc(cal4_mgc),
|
||||
.o_tx_cal_mgc(tx_cal_mgc),
|
||||
.o_rx1_mgc(rx1_mgc),
|
||||
.o_rx2_mgc(rx2_mgc),
|
||||
.o_rx3_mgc(rx3_mgc),
|
||||
.o_rx4_mgc(rx4_mgc),
|
||||
.o_ceshi_model(ceshi_model)
|
||||
);
|
||||
|
||||
spi_master u_spi_master (
|
||||
.i_sys_rst_n (rst_n) ,
|
||||
.i_clk (clk_40m) ,
|
||||
//.debug_clk (clk_80m) ,
|
||||
.i_spi_sck (SPI_CLK_F) ,
|
||||
.i_spi_cs (SPI_SYN_F) ,
|
||||
.o_spi_sdo (SPI_MISO_F) ,
|
||||
.i_spi_sdi (SPI_MOSI_F) ,
|
||||
.i_LD_LO3 (LD3) ,
|
||||
.i_LD1 (LD1) ,
|
||||
.i_LD2 (LD2) ,
|
||||
.i_cal1_mgc (R_CAL4) ,
|
||||
.i_cal2_mgc (R_CAL3) ,
|
||||
.i_cal3_mgc (R_CAL2) ,
|
||||
.i_cal4_mgc (R_CAL1) ,
|
||||
.i_temp (temp ) ,
|
||||
.i_frame_count (frame_count)
|
||||
);
|
||||
|
||||
mgc_ctrl u_mgc_ctrl(
|
||||
.i_sys_clk (clk_40m ),
|
||||
.i_rst_n (rst_n ),
|
||||
.i_TR_SW_F (PRF ),
|
||||
.i_TP_EN_F (TP_EN_F ),
|
||||
.i_T_MGC_EN_F (TR_MGC_F ),
|
||||
.i_R_MGC_EN_F (TR_MGC_F ),
|
||||
.i_CAL_F (CAL_F ),
|
||||
.i_fre_code (fre_code ),
|
||||
.i_tx_mgc (tx_mgc ),
|
||||
.i_rx1_mgc (rx1_mgc ),
|
||||
.i_rx2_mgc (rx2_mgc ),
|
||||
.i_rx3_mgc (rx3_mgc ),
|
||||
.i_rx4_mgc (rx4_mgc ),
|
||||
.i_ceshi_module (ceshi_model ),
|
||||
.o_current_fre_code (current_fre_code ),
|
||||
.o_cal_fre_code (cal_fre_code ),
|
||||
.o_hop_fre_code (hop_fre_code ), //0(20.375GHz)~3500(23.875GHz)
|
||||
.o_adf4371_hop1 (adf4371_hop1 ), //high active
|
||||
.o_adf4371_hop2 (adf4371_hop2 ),
|
||||
.o_SW (SW ),
|
||||
.o_SW2 (SW2 ),
|
||||
.o_SW3 (SW3 ),
|
||||
.o_SW_C1 (SW_C1 ),
|
||||
.o_T_MGC_1dB (TMGC_1db ),
|
||||
.o_T_MGC_2dB (TMGC_2db ),
|
||||
.o_T_MGC_4dB (TMGC_4db ),
|
||||
.o_T_MGC_8dB (TMGC_8db ),
|
||||
.o_T_MGC_16dB (TMGC_16db ),
|
||||
.o_R_MGC_1 (R_MGC_1 )
|
||||
//.o_R_MGC_2 (R_MGC_2 ),
|
||||
//.o_R_MGC_3 (R_MGC_3 ),
|
||||
//.o_R_MGC_4 (R_MGC_4 )
|
||||
);
|
||||
|
||||
wire cfgover;
|
||||
adf4371_a u_adf4371_a (
|
||||
.sysclk (clk_40m ),
|
||||
.arstn (rst_n&vio_rstn ),
|
||||
.cs (CS1 ),
|
||||
.mux_out (LD1 ),
|
||||
.sclk (SCLK1 ),
|
||||
.sdio (SDIO1 ),
|
||||
.rf_en (rf_en ),
|
||||
.SW_PLL (SW_PLL ),
|
||||
.CAL_F (CAL_F ),
|
||||
.o_cfgover (cfgover ),
|
||||
.ceshi_model(ceshi_model ),
|
||||
.adf4371_hop(adf4371_hop1),
|
||||
.fre_code (hop_fre_code)
|
||||
);
|
||||
|
||||
adf4371_b u_adf4371_b (
|
||||
.sysclk (clk_40m ),
|
||||
.arstn (rst_n&vio_rstn),
|
||||
.cs (CS2 ),
|
||||
.mux_out (LD2 ),
|
||||
.sclk (SCLK2 ),
|
||||
.sdio (SDIO2 ),
|
||||
.rf_en (rf_en ),
|
||||
.SW_PLL (SW_PLL ),
|
||||
.CAL_F (CAL_F ),
|
||||
.i_cfgover (cfgover ),
|
||||
.ceshi_model(ceshi_model ),
|
||||
.adf4371_hop(adf4371_hop2),
|
||||
.fre_code (hop_fre_code)
|
||||
);
|
||||
|
||||
fre_caliatt u_fre_caliatt (
|
||||
.i_clk (clk_40m ),
|
||||
.i_rstn (rst_n ),
|
||||
.ENABLE (ENABLE ),
|
||||
.SC (SC ),
|
||||
.SD (SD ),
|
||||
.END_SYN (END_SYN ),
|
||||
.SDOUT (SDOUT ),
|
||||
.CAL_F (CAL_F ),
|
||||
.i_temp (temp ),
|
||||
.i_fre_mode (current_fre_code ),
|
||||
.i_cal_fre_code (cal_fre_code ),
|
||||
// .SYNC_OUT (SYNC_OUT ),
|
||||
.SW (SW ),
|
||||
.cal1_mgc (cal1_mgc ),
|
||||
.cal2_mgc (cal2_mgc ),
|
||||
.cal3_mgc (cal3_mgc ),
|
||||
.cal4_mgc (cal4_mgc ),
|
||||
.tx_cal_mgc (tx_cal_mgc ),
|
||||
.tx_mgc (tx_mgc ),
|
||||
.i_ceshi_module (ceshi_model ),
|
||||
.R_CAL1 (R_CAL1 ),
|
||||
.R_CAL2 (R_CAL2 ),
|
||||
.R_CAL3 (R_CAL3 ),
|
||||
.R_CAL4 (R_CAL4 ),
|
||||
.T_CAL (T_CAL )
|
||||
);
|
||||
|
||||
|
||||
adf4351_2 u_adf4351 (
|
||||
.i_sysclk(clk_20m),
|
||||
.i_arstn(rst_n),
|
||||
.o_ADF4351_SCK(SCLK3),
|
||||
.o_ADF4351_DATA(SDIO3),
|
||||
.o_ADF4351_LE(CS3),
|
||||
.i_ADF4351_locked(LD3)
|
||||
);
|
||||
|
||||
|
||||
ds18b20_temp u_temp (
|
||||
.clk(clk_40m),
|
||||
.rstn(rst_n),
|
||||
.dq(DQ_WD),
|
||||
.temp_data(temp_data)
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
assign vio_rstn = 1'b1;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,631 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 17:05:24 04/08/2022
|
||||
// Design Name:
|
||||
// Module Name: T_CAL_
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module T_CAL(
|
||||
input i_clk ,
|
||||
input i_rstn ,
|
||||
input SW ,
|
||||
input signed[7:0] i_temp ,
|
||||
input [31:0] hop_fre_mode ,
|
||||
output reg[4:0] T_CAL_
|
||||
|
||||
);
|
||||
|
||||
|
||||
|
||||
//发射通道
|
||||
always@(posedge i_clk,negedge i_rstn)begin//1dB 步进
|
||||
if(!i_rstn)
|
||||
T_CAL_<='d0;
|
||||
else if(SW==1'b1)//B环校准值
|
||||
begin
|
||||
if(i_temp>=8'sd70)//B环高温校准值
|
||||
begin
|
||||
if(hop_fre_mode<=20414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20454) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20494) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20534) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20734) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20774) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20814) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20854) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20894) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20934) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20974) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21014) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21054) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21094) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21134) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21174) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21214) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21254) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21294) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21334) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21374) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21454) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21494) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21534) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21734) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21774) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21814) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21854) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21875) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894
|
||||
else if(hop_fre_mode<=21934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=21974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22054) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22094) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22134) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22174) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22214) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22254) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22294) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22334) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22374) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22414) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22454) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22494) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22534) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22574) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22614) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22654) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22694) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22734) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22774) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22814) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22854) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22894) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23054) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23094) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23134) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23174) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23214) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23254) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23294) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23334) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23374) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23414) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23454) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23494) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23534) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23574) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23614) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23654) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23694) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23734) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23774) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23814) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23854) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23875) T_CAL_<= 9 ;
|
||||
end
|
||||
|
||||
else if(i_temp>=8'sd0)//B环常温校准值
|
||||
begin
|
||||
if(hop_fre_mode<=20414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20454) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20494) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20534) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20734) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20774) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20814) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20854) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20894) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20934) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20974) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21014) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21054) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21094) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21134) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21174) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21214) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21254) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21294) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21334) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21374) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21454) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21494) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21534) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21734) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21774) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21814) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21854) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21875) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894
|
||||
else if(hop_fre_mode<=21934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=21974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22054) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22094) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22134) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22174) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22214) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22254) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22294) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22334) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22374) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22414) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22454) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22494) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22534) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22574) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22614) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22654) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22694) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22734) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22774) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22814) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22854) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22894) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23054) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23094) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23134) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23174) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23214) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23254) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23294) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23334) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23374) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23414) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23454) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23494) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23534) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23574) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23614) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23654) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23694) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23734) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23774) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23814) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23854) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23875) T_CAL_<= 9 ;
|
||||
end
|
||||
|
||||
else //B环低温校准值
|
||||
begin
|
||||
if(hop_fre_mode<=20414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20454) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20494) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20534) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20734) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20774) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20814) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20854) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20894) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20934) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20974) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21014) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21054) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21094) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21134) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21174) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21214) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21254) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21294) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21334) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21374) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21454) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21494) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21534) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21734) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21774) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21814) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21854) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21875) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894
|
||||
else if(hop_fre_mode<=21934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=21974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22054) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22094) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22134) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22174) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22214) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22254) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22294) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22334) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22374) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22414) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22454) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22494) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22534) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22574) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22614) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22654) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22694) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22734) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22774) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22814) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22854) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22894) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23054) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23094) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23134) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23174) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23214) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23254) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23294) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23334) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23374) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23414) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23454) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23494) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23534) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23574) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23614) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23654) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23694) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23734) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23774) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23814) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23854) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23875) T_CAL_<= 9 ;
|
||||
end
|
||||
end
|
||||
else //A环校准值
|
||||
begin
|
||||
if(i_temp>=8'sd70)//A环高温校准值
|
||||
begin
|
||||
if(hop_fre_mode<=20414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20454) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20494) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20534) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20734) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20774) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20814) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20854) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20894) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20934) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20974) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21014) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21054) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21094) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21134) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21174) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21214) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21254) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21294) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21334) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21374) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21454) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21494) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21534) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21734) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21774) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21814) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21854) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21875) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894
|
||||
else if(hop_fre_mode<=21934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=21974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22054) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22094) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22134) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22174) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22214) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22254) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22294) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22334) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22374) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22414) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22454) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22494) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22534) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22574) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22614) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22654) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22694) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22734) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22774) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22814) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22854) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22894) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23054) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23094) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23134) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23174) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23214) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23254) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23294) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23334) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23374) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23414) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23454) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23494) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23534) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23574) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23614) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23654) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23694) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23734) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23774) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23814) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23854) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23875) T_CAL_<= 9 ;
|
||||
end
|
||||
|
||||
else if(i_temp>=8'sd0)//A环常温校准值
|
||||
begin
|
||||
if(hop_fre_mode<=20414) T_CAL_<= 14 ; //20375 ~ 20414
|
||||
else if(hop_fre_mode<=20454) T_CAL_<= 14 ; //20415 ~ 20454
|
||||
else if(hop_fre_mode<=20494) T_CAL_<= 14 ; //20455 ~ 20494
|
||||
else if(hop_fre_mode<=20534) T_CAL_<= 14 ; //20495 ~ 20534
|
||||
else if(hop_fre_mode<=20574) T_CAL_<= 15 ; //20535 ~ 20574
|
||||
else if(hop_fre_mode<=20614) T_CAL_<= 15 ; //20575 ~ 20614
|
||||
else if(hop_fre_mode<=20654) T_CAL_<= 15 ; //20615 ~ 20654
|
||||
else if(hop_fre_mode<=20694) T_CAL_<= 15 ; //20655 ~ 20694
|
||||
else if(hop_fre_mode<=20734) T_CAL_<= 15 ; //20695 ~ 20734
|
||||
else if(hop_fre_mode<=20774) T_CAL_<= 16 ; //20735 ~ 20774
|
||||
else if(hop_fre_mode<=20814) T_CAL_<= 16 ; //20775 ~ 20814
|
||||
else if(hop_fre_mode<=20854) T_CAL_<= 16 ; //20815 ~ 20854
|
||||
else if(hop_fre_mode<=20894) T_CAL_<= 16 ; //20855 ~ 20894
|
||||
else if(hop_fre_mode<=20934) T_CAL_<= 16 ; //20895 ~ 20934
|
||||
else if(hop_fre_mode<=20974) T_CAL_<= 16 ; //20935 ~ 20974
|
||||
else if(hop_fre_mode<=21014) T_CAL_<= 16 ; //20975 ~ 21014
|
||||
else if(hop_fre_mode<=21054) T_CAL_<= 16 ; //21015 ~ 21054
|
||||
else if(hop_fre_mode<=21094) T_CAL_<= 15 ; //21055 ~ 21094
|
||||
else if(hop_fre_mode<=21134) T_CAL_<= 14 ; //21095 ~ 21134
|
||||
else if(hop_fre_mode<=21174) T_CAL_<= 14 ; //21135 ~ 21174
|
||||
else if(hop_fre_mode<=21214) T_CAL_<= 13 ; //21175 ~ 21214
|
||||
else if(hop_fre_mode<=21254) T_CAL_<= 13 ; //21215 ~ 21254
|
||||
else if(hop_fre_mode<=21294) T_CAL_<= 13 ; //21255 ~ 21294
|
||||
else if(hop_fre_mode<=21334) T_CAL_<= 13 ; //21295 ~ 21334
|
||||
else if(hop_fre_mode<=21374) T_CAL_<= 14 ; //21335 ~ 21374
|
||||
else if(hop_fre_mode<=21414) T_CAL_<= 14 ; //21375 ~ 21414
|
||||
else if(hop_fre_mode<=21454) T_CAL_<= 15 ; //21415 ~ 21454
|
||||
else if(hop_fre_mode<=21494) T_CAL_<= 15 ; //21455 ~ 21494
|
||||
else if(hop_fre_mode<=21534) T_CAL_<= 15 ; //21495 ~ 21534
|
||||
else if(hop_fre_mode<=21574) T_CAL_<= 15 ; //21535 ~ 21574
|
||||
else if(hop_fre_mode<=21614) T_CAL_<= 15 ; //21575 ~ 21614
|
||||
else if(hop_fre_mode<=21654) T_CAL_<= 15 ; //21615 ~ 21654
|
||||
else if(hop_fre_mode<=21694) T_CAL_<= 15 ; //21655 ~ 21694
|
||||
else if(hop_fre_mode<=21734) T_CAL_<= 14 ; //21695 ~ 21734
|
||||
else if(hop_fre_mode<=21774) T_CAL_<= 14 ; //21735 ~ 21774
|
||||
else if(hop_fre_mode<=21814) T_CAL_<= 13 ; //21775 ~ 21814
|
||||
else if(hop_fre_mode<=21854) T_CAL_<= 13 ; //21815 ~ 21854
|
||||
else if(hop_fre_mode<=21875) T_CAL_<= 13 ; //21855 ~ 21875
|
||||
else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21874 ~ 21894
|
||||
else if(hop_fre_mode<=21934) T_CAL_<= 11 ; //21895 ~ 21934
|
||||
else if(hop_fre_mode<=21974) T_CAL_<= 11 ; //21935 ~ 21974
|
||||
else if(hop_fre_mode<=22014) T_CAL_<= 11 ; //21975 ~ 22014
|
||||
else if(hop_fre_mode<=22054) T_CAL_<= 11 ; //22015 ~ 22054
|
||||
else if(hop_fre_mode<=22094) T_CAL_<= 11 ; //22055 ~ 22094
|
||||
else if(hop_fre_mode<=22134) T_CAL_<= 11 ; //22095 ~ 22134
|
||||
else if(hop_fre_mode<=22174) T_CAL_<= 11 ; //22135 ~ 22174
|
||||
else if(hop_fre_mode<=22214) T_CAL_<= 11 ; //22175 ~ 22214
|
||||
else if(hop_fre_mode<=22254) T_CAL_<= 11 ; //22215 ~ 22254
|
||||
else if(hop_fre_mode<=22294) T_CAL_<= 11 ; //22255 ~ 22294
|
||||
else if(hop_fre_mode<=22334) T_CAL_<= 11 ; //22295 ~ 22334
|
||||
else if(hop_fre_mode<=22374) T_CAL_<= 11 ; //22335 ~ 22374
|
||||
else if(hop_fre_mode<=22414) T_CAL_<= 11 ; //22375 ~ 22414
|
||||
else if(hop_fre_mode<=22454) T_CAL_<= 11 ; //22415 ~ 22454
|
||||
else if(hop_fre_mode<=22494) T_CAL_<= 11 ; //22455 ~ 22494
|
||||
else if(hop_fre_mode<=22534) T_CAL_<= 11 ; //22495 ~ 22534
|
||||
else if(hop_fre_mode<=22574) T_CAL_<= 11 ; //22535 ~ 22574
|
||||
else if(hop_fre_mode<=22614) T_CAL_<= 11 ; //22575 ~ 22614
|
||||
else if(hop_fre_mode<=22654) T_CAL_<= 11 ; //22615 ~ 22654
|
||||
else if(hop_fre_mode<=22694) T_CAL_<= 11 ; //22655 ~ 22694
|
||||
else if(hop_fre_mode<=22734) T_CAL_<= 11 ; //22695 ~ 22734
|
||||
else if(hop_fre_mode<=22774) T_CAL_<= 11 ; //22735 ~ 22774
|
||||
else if(hop_fre_mode<=22814) T_CAL_<= 11 ; //22775 ~ 22814
|
||||
else if(hop_fre_mode<=22854) T_CAL_<= 11 ; //22815 ~ 22854
|
||||
else if(hop_fre_mode<=22894) T_CAL_<= 11 ; //22855 ~ 22894
|
||||
else if(hop_fre_mode<=22934) T_CAL_<= 11 ; //22895 ~ 22934
|
||||
else if(hop_fre_mode<=22974) T_CAL_<= 11 ; //22935 ~ 22974
|
||||
else if(hop_fre_mode<=23014) T_CAL_<= 11 ; //22975 ~ 23014
|
||||
else if(hop_fre_mode<=23054) T_CAL_<= 10 ; //23015 ~ 23054
|
||||
else if(hop_fre_mode<=23094) T_CAL_<= 10 ; //23055 ~ 23094
|
||||
else if(hop_fre_mode<=23134) T_CAL_<= 10 ; //23095 ~ 23134
|
||||
else if(hop_fre_mode<=23174) T_CAL_<= 10 ; //23135 ~ 23174
|
||||
else if(hop_fre_mode<=23214) T_CAL_<= 10 ; //23175 ~ 23214
|
||||
else if(hop_fre_mode<=23254) T_CAL_<= 10 ; //23215 ~ 23254
|
||||
else if(hop_fre_mode<=23294) T_CAL_<= 10 ; //23255 ~ 23294
|
||||
else if(hop_fre_mode<=23334) T_CAL_<= 10 ; //23295 ~ 23334
|
||||
else if(hop_fre_mode<=23374) T_CAL_<= 10 ; //23335 ~ 23374
|
||||
else if(hop_fre_mode<=23414) T_CAL_<= 10 ; //23375 ~ 23414
|
||||
else if(hop_fre_mode<=23454) T_CAL_<= 10 ; //23415 ~ 23454
|
||||
else if(hop_fre_mode<=23494) T_CAL_<= 10 ; //23455 ~ 23494
|
||||
else if(hop_fre_mode<=23534) T_CAL_<= 10 ; //23495 ~ 23534
|
||||
else if(hop_fre_mode<=23574) T_CAL_<= 10 ; //23535 ~ 23574
|
||||
else if(hop_fre_mode<=23614) T_CAL_<= 9 ; //23575 ~ 23614
|
||||
else if(hop_fre_mode<=23654) T_CAL_<= 9 ; //23615 ~ 23654
|
||||
else if(hop_fre_mode<=23694) T_CAL_<= 9 ; //23655 ~ 23694
|
||||
else if(hop_fre_mode<=23734) T_CAL_<= 9 ; //23695 ~ 23734
|
||||
else if(hop_fre_mode<=23774) T_CAL_<= 9 ; //23735 ~ 23774
|
||||
else if(hop_fre_mode<=23814) T_CAL_<= 9 ; //23775 ~ 23814
|
||||
else if(hop_fre_mode<=23854) T_CAL_<= 9 ; //23815 ~ 23854
|
||||
else if(hop_fre_mode<=23875) T_CAL_<= 9 ; //23855 ~ 23875
|
||||
end
|
||||
else //A环低温校准值
|
||||
begin
|
||||
if(hop_fre_mode<=20414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20454) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20494) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20534) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=20574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20734) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=20774) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20814) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20854) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20894) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20934) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=20974) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21014) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21054) T_CAL_<= 16 ;
|
||||
else if(hop_fre_mode<=21094) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21134) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21174) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21214) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21254) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21294) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21334) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21374) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21414) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21454) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21494) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21534) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21574) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21614) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21654) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21694) T_CAL_<= 15 ;
|
||||
else if(hop_fre_mode<=21734) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21774) T_CAL_<= 14 ;
|
||||
else if(hop_fre_mode<=21814) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21854) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21875) T_CAL_<= 13 ;
|
||||
else if(hop_fre_mode<=21894) T_CAL_<= 11 ; //21894
|
||||
else if(hop_fre_mode<=21934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=21974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22054) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22094) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22134) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22174) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22214) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22254) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22294) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22334) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22374) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22414) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22454) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22494) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22534) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22574) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22614) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22654) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22694) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22734) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22774) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22814) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22854) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22894) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22934) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=22974) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23014) T_CAL_<= 11 ;
|
||||
else if(hop_fre_mode<=23054) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23094) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23134) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23174) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23214) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23254) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23294) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23334) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23374) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23414) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23454) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23494) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23534) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23574) T_CAL_<= 10 ;
|
||||
else if(hop_fre_mode<=23614) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23654) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23694) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23734) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23774) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23814) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23854) T_CAL_<= 9 ;
|
||||
else if(hop_fre_mode<=23875) T_CAL_<= 9 ;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,633 @@
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2021/8/13 00:24:20
|
||||
// Design Name:
|
||||
// Module Name: LMX2595
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
|
||||
// fRFOUT= (INT+ (FRAC1+FRAC2/MOD2)/MOD1)× (fPFD/R)
|
||||
// fPFD = fPFD = REFIN × ((1 + D)/(R × (1 + T)))
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module adf4371_a(//20.375Ghz ~ 23.875Ghz
|
||||
input sysclk ,//40MHZ
|
||||
input arstn ,
|
||||
output cs ,
|
||||
input mux_out ,
|
||||
output sclk ,
|
||||
output sdio ,
|
||||
input [3:0] rf_en ,
|
||||
input SW_PLL ,
|
||||
input CAL_F ,
|
||||
input [3:0] ceshi_model ,
|
||||
input adf4371_hop ,
|
||||
output o_cfgover ,
|
||||
input[11:0] fre_code
|
||||
);
|
||||
|
||||
localparam DATA_WIDTH = 24 ;
|
||||
localparam DATA_LENTH = 72 ;
|
||||
localparam WAIT_ld = 40000 ;
|
||||
//*****************************************************************************
|
||||
reg[7:0] cnt_word = 8'd0 ;
|
||||
reg csb_reg = 1'b1 ;
|
||||
reg[5:0] cnt_bits = 6'd0 ;
|
||||
reg[DATA_WIDTH-1:0] cfgdata = 0, regdata = 0 ;
|
||||
reg[3:0] state = 4'b000 ;
|
||||
reg spi_sdo = 1'b0, spi_csb = 1'b1;
|
||||
wire pll_locked ;
|
||||
reg cfgover ;
|
||||
reg[31:0] cnt_lock = 32'd0 ;
|
||||
reg[31:0] cnt_locked = 32'd0 ;
|
||||
wire[15:0] band ;
|
||||
assign o_cfgover =cfgover ;
|
||||
//-----------------------------------
|
||||
assign pll_locked = mux_out ;
|
||||
assign sclk = spi_csb ? 1'b0 : ~sysclk ;
|
||||
assign cs = spi_csb & csb_reg ;
|
||||
assign sdio = spi_sdo ;
|
||||
//-----------------------------------
|
||||
|
||||
wire [7:0] SI_BAND_SEL ; //VCO频段
|
||||
wire [7:0] SI_VCO_SEL_BIAS_CODE ; //[7:4]=VCO内核, [3:0]=VCO偏置
|
||||
reg[13:0] MOD2 ;
|
||||
reg[13:0] FRAC2 ;
|
||||
reg[24:0] FRAC1 ;
|
||||
reg[15:0] INT ;
|
||||
|
||||
assign SI_BAND_SEL = band[15:8] ;
|
||||
assign SI_VCO_SEL_BIAS_CODE = band[7:0] ;
|
||||
|
||||
reg[2:0] hop_en ;
|
||||
reg[15:0] code ;
|
||||
reg[11:0] pre_fre_code ;
|
||||
reg[3:0] rf_en_r ;
|
||||
reg[2:0] CAL_F_R ;
|
||||
|
||||
reg [3:0] R_DIV ;
|
||||
reg [3:0] D ;
|
||||
wire[13:0] douta3 ;
|
||||
wire[13:0] douta4 ;
|
||||
wire[24:0] douta2 ;
|
||||
wire[15:0] douta1 ;
|
||||
//-----------------------------------
|
||||
|
||||
INT_ROMb int_rom (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta1)
|
||||
);
|
||||
|
||||
// Instantiate the module
|
||||
FRAC1 frac1_rom (
|
||||
.clka(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta2)
|
||||
);
|
||||
|
||||
|
||||
// FRAC1_ROM FRAC1_ROM (
|
||||
// .clka(sysclk), // input clka
|
||||
// .addra(code), // input [11 : 0] addra
|
||||
// .douta(douta2) // output [24 : 0] douta
|
||||
//);
|
||||
|
||||
frac2_rom frac2_rom (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta4)
|
||||
);
|
||||
|
||||
mod2_rom mod2_rom (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta3)
|
||||
);
|
||||
|
||||
|
||||
band_rom_a band_rom_a (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(band) // output [15 : 0] douta
|
||||
);
|
||||
|
||||
|
||||
//-------------------整数边界杂散用66.666666Mhz鉴相----------------------------------
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
INT<=douta1;
|
||||
else if(code==24 || code==26 )
|
||||
INT<=76;
|
||||
else if(code==424 )
|
||||
INT<=77;
|
||||
else if(code==426 )
|
||||
INT<=78;
|
||||
else if(code==824 || code==826 )
|
||||
INT<=79;
|
||||
else if(code==1224)
|
||||
INT<=80;
|
||||
else if(code==1226 )
|
||||
INT<=81;
|
||||
else if(code==1624 || code==1626 )
|
||||
INT<=82;
|
||||
else if(code==2024 )
|
||||
INT<=83;
|
||||
else if(code==2026 )
|
||||
INT<=84;
|
||||
else if(code==2424 || code==2426 )
|
||||
INT<=85;
|
||||
else if(code==2824 )
|
||||
INT<=86;
|
||||
else if( code==2826 )
|
||||
INT<=87;
|
||||
else
|
||||
INT<=douta1;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
FRAC1<=douta2;
|
||||
else if(code==24 )
|
||||
FRAC1<=16651386;
|
||||
else if(code==26 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==424 )
|
||||
FRAC1<=33428602;
|
||||
else if(code==426 )
|
||||
FRAC1<=125829;
|
||||
else if(code==824 )
|
||||
FRAC1<=16651386;
|
||||
else if(code==826 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==1224)
|
||||
FRAC1<=33428602;
|
||||
else if(code==1226 )
|
||||
FRAC1<=125829;
|
||||
else if(code==1624)
|
||||
FRAC1<=16651386;
|
||||
else if(code==1626 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==2024 )
|
||||
FRAC1<=33428602;
|
||||
else if(code==2026 )
|
||||
FRAC1<=125829;
|
||||
else if(code==2424 )
|
||||
FRAC1<=16651386;
|
||||
else if(code==2426 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==2824 )
|
||||
FRAC1<=33428602;
|
||||
else if( code==2826 )
|
||||
FRAC1<=125829;
|
||||
else
|
||||
FRAC1<=douta2;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
MOD2<=douta3;
|
||||
else if(code==24 )
|
||||
MOD2<=25;
|
||||
else if(code==26 )
|
||||
MOD2<=25;
|
||||
else if(code==424 )
|
||||
MOD2<=25;
|
||||
else if(code==426 )
|
||||
MOD2<=25;
|
||||
else if(code==824 )
|
||||
MOD2<=25;
|
||||
else if(code==826 )
|
||||
MOD2<=25;
|
||||
else if(code==1224)
|
||||
MOD2<=25;
|
||||
else if(code==1226 )
|
||||
MOD2<=25;
|
||||
else if(code==1624)
|
||||
MOD2<=25;
|
||||
else if(code==1626 )
|
||||
MOD2<=25;
|
||||
else if(code==2024 )
|
||||
MOD2<=25;
|
||||
else if(code==2026 )
|
||||
MOD2<=25;
|
||||
else if(code==2424 )
|
||||
MOD2<=25;
|
||||
else if(code==2426 )
|
||||
MOD2<=25;
|
||||
else if(code==2824 )
|
||||
MOD2<=25;
|
||||
else if( code==2826 )
|
||||
MOD2<=25;
|
||||
else
|
||||
MOD2<=douta3;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
FRAC2<=douta4;
|
||||
else if(code==24 )
|
||||
FRAC2<=22;
|
||||
else if(code==26 )
|
||||
FRAC2<=3;
|
||||
else if(code==424 )
|
||||
FRAC2<=22;
|
||||
else if(code==426 )
|
||||
FRAC2<=3;
|
||||
else if(code==824 )
|
||||
FRAC2<=22;
|
||||
else if(code==826 )
|
||||
FRAC2<=3;
|
||||
else if(code==1224)
|
||||
FRAC2<=22;
|
||||
else if(code==1226 )
|
||||
FRAC2<=3;
|
||||
else if(code==1624)
|
||||
FRAC2<=22;
|
||||
else if(code==1626 )
|
||||
FRAC2<=3;
|
||||
else if(code==2024 )
|
||||
FRAC2<=22;
|
||||
else if(code==2026 )
|
||||
FRAC2<=3;
|
||||
else if(code==2424 )
|
||||
FRAC2<=22;
|
||||
else if(code==2426 )
|
||||
FRAC2<=3;
|
||||
else if(code==2824 )
|
||||
FRAC2<=22;
|
||||
else if( code==2826 )
|
||||
FRAC2<=3;
|
||||
else
|
||||
FRAC2<=douta4;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)begin
|
||||
R_DIV<=4'b1;
|
||||
D<=4'b0;
|
||||
end
|
||||
else if(code==24 || code==26 || code==424 || code==426 || code==824 || code==826|| code==1224 || code==1226 || code==1624 || code==1626 ||code==2024 || code==2026 ||code==2424 || code==2426 ||code==2824 || code==2826 )
|
||||
begin
|
||||
R_DIV<= 4'd3;
|
||||
D<=4'd2;
|
||||
end
|
||||
else
|
||||
begin
|
||||
R_DIV<=4'b1;
|
||||
D<=4'b0;
|
||||
end
|
||||
end
|
||||
|
||||
//----------------------------------------------------------------
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
pre_fre_code<=11'h6d6;
|
||||
else if(CAL_F_R==3'b011)
|
||||
pre_fre_code<=fre_code;
|
||||
else
|
||||
pre_fre_code<=pre_fre_code;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
code<=16'h0;
|
||||
else if(hop_en==2'b01)
|
||||
code<=fre_code;
|
||||
else
|
||||
code<=code;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)begin
|
||||
hop_en <= 3'b0;
|
||||
rf_en_r <= 4'b0;
|
||||
CAL_F_R <= 3'b0;
|
||||
end
|
||||
else begin
|
||||
hop_en <= {hop_en[1:0],adf4371_hop};
|
||||
CAL_F_R <= {CAL_F_R[1:0],CAL_F};
|
||||
rf_en_r <= rf_en ;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
csb_reg <= 1'b1;
|
||||
else
|
||||
csb_reg <= spi_csb;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
cnt_locked<=32'b0;
|
||||
else if(cnt_locked==WAIT_ld)
|
||||
cnt_locked<=32'b0;
|
||||
else if(!pll_locked)
|
||||
cnt_locked<=cnt_locked+1'b1;
|
||||
else
|
||||
cnt_locked<=32'b0;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)begin
|
||||
cfgdata <= 0;
|
||||
cnt_word <= 7'd0;
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'b0;
|
||||
cnt_lock <= 32'd0;
|
||||
spi_csb <= 1'b1;
|
||||
cfgover <= 1'b0;
|
||||
spi_sdo <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
case(state)
|
||||
4'd0:begin
|
||||
cnt_word <= 7'd0;
|
||||
if(rf_en==1'b1)
|
||||
state <= 4'd0;
|
||||
else if(cnt_lock >= 32'd4000)
|
||||
state <= 4'd1;
|
||||
else
|
||||
state <= state;
|
||||
|
||||
if(rf_en==1'b0)
|
||||
cnt_lock <= cnt_lock + 1'b1;
|
||||
else
|
||||
cnt_lock<=32'd0;
|
||||
|
||||
end
|
||||
4'd1:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
if(rf_en==1'b1)
|
||||
state <= 4'd0;
|
||||
else
|
||||
state <= 4'd2;
|
||||
end
|
||||
4'd2:begin
|
||||
cfgdata <= regdata;
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'd3;
|
||||
end
|
||||
4'd3:begin
|
||||
spi_csb <= 1'b0;
|
||||
spi_sdo <= cfgdata[DATA_WIDTH-1];
|
||||
cfgdata <= cfgdata << 1'b1;
|
||||
cnt_bits <= cnt_bits + 1'b1;
|
||||
if(cnt_bits == DATA_WIDTH-1)begin
|
||||
state <= 4'd4;
|
||||
cnt_word <= cnt_word + 1'b1;
|
||||
end
|
||||
cnt_lock <= 32'd0;
|
||||
end
|
||||
4'd4:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
cnt_lock <= 32'd0;
|
||||
cnt_bits <= 32'd0;
|
||||
if(cnt_word == DATA_LENTH)begin
|
||||
state <= 4'd5;
|
||||
end
|
||||
else
|
||||
state <= 4'd1;
|
||||
end
|
||||
4'd5:begin
|
||||
if(cnt_lock>=40000 || pll_locked)begin
|
||||
cnt_lock <= 32'd0 ;
|
||||
state <= 4'd6 ;
|
||||
end
|
||||
else begin
|
||||
cnt_lock <=cnt_lock+1'b1;
|
||||
state <= state ;
|
||||
end
|
||||
end
|
||||
4'd6:begin
|
||||
cnt_word <= 7'd0;
|
||||
if(pll_locked)
|
||||
state <= 4'd7 ;
|
||||
else
|
||||
state <= 4'b1 ;
|
||||
end
|
||||
//----------------------------------------------------------------
|
||||
4'd7:begin//IDLE
|
||||
cnt_word <= DATA_LENTH;
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
cnt_bits <= 6'd0;
|
||||
cfgover <= 1'b0;
|
||||
if(rf_en==4'b1)
|
||||
state <= state;
|
||||
else if(rf_en==4'b0 && rf_en_r==4'b1 )
|
||||
state <= 4'd0;
|
||||
else if(hop_en==2'b10 || cnt_locked==WAIT_ld )
|
||||
state <= 4'd8;
|
||||
else if(CAL_F_R==3'b011 && (pre_fre_code!=fre_code))//打开RF_OUT
|
||||
state <= 4'd12;
|
||||
else
|
||||
state <= state;
|
||||
end
|
||||
4'd8:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
state <= 4'd9;
|
||||
end
|
||||
4'd9:begin
|
||||
cfgdata <= regdata;
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'd10;
|
||||
end
|
||||
4'd10:begin
|
||||
spi_csb <= 1'b0;
|
||||
spi_sdo <= cfgdata[DATA_WIDTH-1];
|
||||
cfgdata <= cfgdata << 1'b1;
|
||||
cnt_bits <= cnt_bits + 1'b1;
|
||||
if(cnt_bits == DATA_WIDTH-1)begin
|
||||
state <= 4'd11;
|
||||
cnt_word <= cnt_word + 1'b1;
|
||||
end
|
||||
end
|
||||
4'd11:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
cnt_lock <= 32'd0;
|
||||
cnt_bits <= 32'd0;
|
||||
if(cnt_word == 8'd85)begin
|
||||
state <= 4'd7;
|
||||
end
|
||||
else
|
||||
state <= 4'd8;
|
||||
end
|
||||
4'd12:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
state <= 4'd13;
|
||||
end
|
||||
4'd13:begin
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'd14;
|
||||
if(ceshi_model==4'ha)
|
||||
cfgdata<={16'h0025,8'h13};
|
||||
else if(ceshi_model==4'hb)
|
||||
cfgdata<={16'h0025,8'h00};
|
||||
else if(SW_PLL)
|
||||
cfgdata<={16'h0025,8'h13};
|
||||
else
|
||||
cfgdata<={16'h0025,8'h00};
|
||||
end
|
||||
4'd14:begin
|
||||
spi_csb <= 1'b0;
|
||||
spi_sdo <= cfgdata[DATA_WIDTH-1];
|
||||
cfgdata <= cfgdata << 1'b1;
|
||||
cnt_bits <= cnt_bits + 1'b1;
|
||||
if(cnt_bits == DATA_WIDTH-1)begin
|
||||
state <= 4'd7;
|
||||
cfgover <= 1'b1;
|
||||
cnt_word <= cnt_word ;
|
||||
end
|
||||
end
|
||||
|
||||
//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#//
|
||||
default: begin
|
||||
spi_csb <= 1'b1;
|
||||
state <= 4'd0;
|
||||
cnt_lock <= 32'd0;
|
||||
cnt_word <= 8'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
regdata <= {16'h0000,8'h18 };
|
||||
else case(cnt_word)
|
||||
8'd0 : regdata <= {16'h0000,8'h18 };
|
||||
8'd1 : regdata <= {16'h0001,8'h00 };
|
||||
8'd2 : regdata <= {16'h0003,8'h00 };
|
||||
8'd3 : regdata <= {16'h0004,8'h00 };
|
||||
8'd4 : regdata <= {16'h0005,8'h00 };
|
||||
8'd5 : regdata <= {16'h0006,8'hFF };
|
||||
8'd6 : regdata <= {16'h000C,8'h00 };
|
||||
8'd7 : regdata <= {16'h000D,8'h00 };
|
||||
8'd8 : regdata <= {16'h0010 ,INT[7:0] } ;
|
||||
8'd9 : regdata <= {16'h0011 ,INT[15:8] } ;
|
||||
8'd10 : regdata <= {16'h0012,8'h00 };//[6]No Autocalibration
|
||||
//8'd10 : regdata <= {16'h0012,8'h40 };//[6]Autocalibration
|
||||
8'd11 : regdata <= {16'h0014 ,FRAC1[7:0]} ;
|
||||
8'd12 : regdata <= {16'h0015 ,FRAC1[15:8]} ;
|
||||
8'd13 : regdata <= {16'h0016 ,FRAC1[23:16]} ;
|
||||
8'd14 : regdata <= {16'h0017 ,FRAC2[6:0],FRAC1[24]} ;
|
||||
8'd15 : regdata <= {16'h0018 ,1'b0,FRAC2[13:7] } ;
|
||||
8'd16 : regdata <= {16'h0019 ,MOD2[7:0]} ;
|
||||
8'd17 : regdata <= {16'h001A ,2'b0,MOD2[13:8]} ;
|
||||
8'd18 : regdata <= {16'h001B,8'h00 };
|
||||
8'd19 : regdata <= {16'h001C,8'h00 };
|
||||
8'd20 : regdata <= {16'h001D,8'h00 };
|
||||
8'd21 : regdata <= {16'h001E,8'h18 };//CP_CURRENT 电荷泵
|
||||
// 8'd21 : regdata <= { 16'h001E,cp,4'h8 };//CP_CURRENT 电荷泵
|
||||
8'd22 : regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器
|
||||
8'd23 : regdata <= {16'h0020,8'h1c };//digital lock detect 数字锁定ld
|
||||
8'd24 : regdata <= {16'h0021,8'h00 };
|
||||
8'd25 : regdata <= {16'h0022,D,4'd0 };//[4]2分频 [5]double 2倍频器
|
||||
8'd26 : regdata <= {16'h0023,8'h00 };
|
||||
8'd27 : regdata <= {16'h0024,8'h80 };//Fout_clk DIV_SEL
|
||||
8'd28 : regdata <= {16'h0025,8'h13 };//X4_EN
|
||||
8'd29 : regdata <= {16'h0026,8'h1F };
|
||||
8'd30 : regdata <= {16'h0027,8'hCD };
|
||||
//8'd30 : regdata <= {16'h0027,8'hCD };
|
||||
8'd31 : regdata <= {16'h0028,8'h83 };
|
||||
8'd32 : regdata <= {16'h002A,8'h00 };
|
||||
8'd33 : regdata <= {16'h002B,8'h00 };
|
||||
8'd34 : regdata <= {16'h002C,8'h44 };
|
||||
8'd35 : regdata <= {16'h002D,8'h11 };
|
||||
8'd36 : regdata <= {16'h002E,8'h12 };
|
||||
8'd37 : regdata <= {16'h002F,8'h94 };
|
||||
8'd38 : regdata <= {16'h0030,8'h2A };
|
||||
8'd39 : regdata <= {16'h0031,8'h02 };
|
||||
8'd40 : regdata <= {16'h0032,8'h04 };
|
||||
8'd41 : regdata <= {16'h0033,8'h22 };
|
||||
8'd42 : regdata <= {16'h0034,8'h25 };
|
||||
8'd43 : regdata <= {16'h0035,8'hFA };
|
||||
8'd44 : regdata <= {16'h0036,8'h30 };
|
||||
8'd45 : regdata <= {16'h0037,SI_BAND_SEL} ;//VCO频段
|
||||
8'd46 : regdata <= {16'h0038,SI_VCO_SEL_BIAS_CODE };//[7:4]=VCO内核,[3:0]VCO偏置
|
||||
8'd47 : regdata <= {16'h0039,8'h07 };
|
||||
8'd48 : regdata <= {16'h003A,8'h55 };
|
||||
8'd49 : regdata <= {16'h003D,8'h00 };
|
||||
8'd50 : regdata <= {16'h003E,8'h0C };
|
||||
8'd51 : regdata <= {16'h003F,8'h80 };
|
||||
8'd52 : regdata <= {16'h0040,8'h50 };
|
||||
8'd53 : regdata <= {16'h0041,8'h28 };
|
||||
8'd54 : regdata <= {16'h0042,8'h00 };
|
||||
8'd55 : regdata <= {16'h0043,8'h00 };
|
||||
8'd56 : regdata <= {16'h0044,8'h00 };
|
||||
8'd57 : regdata <= {16'h0045,8'h00 };
|
||||
8'd58 : regdata <= {16'h0046,8'h00 };
|
||||
8'd59 : regdata <= {16'h0047,8'hC0 };
|
||||
8'd60 : regdata <= {16'h0052,8'hF4 };
|
||||
8'd61 : regdata <= {16'h006C,8'h00 };
|
||||
8'd62 : regdata <= {16'h006E,8'h00 };
|
||||
8'd63 : regdata <= {16'h006F,8'h00 };
|
||||
8'd64 : regdata <= {16'h0070,8'hE3 };
|
||||
8'd65 : regdata <= {16'h0071,8'h60 };
|
||||
8'd66 : regdata <= {16'h0072,8'h32 };
|
||||
8'd67 : regdata <= {16'h0073,8'h00 };
|
||||
8'd68 : regdata <= {16'h0079,8'h00 };
|
||||
8'd69 : regdata <= {16'h007A,8'h00 };
|
||||
8'd70 : regdata <= {16'h007B,8'h00 };
|
||||
8'd71 : regdata <= {16'h007C,8'h00 };
|
||||
|
||||
//跳频
|
||||
8'd72:regdata <= { 16'h0022,D,4'd0 };//double D倍频器
|
||||
8'd73:regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器
|
||||
8'd74:regdata <= { 16'h001A ,2'b0,MOD2[13:8] } ;
|
||||
8'd75:regdata <= { 16'h0019 ,MOD2[7:0] } ;
|
||||
8'd76:regdata <= { 16'h0018 ,1'b0,FRAC2[13:7] } ;
|
||||
8'd77:regdata <= { 16'h0017 ,FRAC2[6:0],FRAC1[24] } ;
|
||||
8'd78:regdata <= { 16'h0016 ,FRAC1[23:16] } ;
|
||||
8'd79:regdata <= { 16'h0015 ,FRAC1[15:8] } ;
|
||||
8'd80:regdata <= { 16'h0014 ,FRAC1[7:0] } ;
|
||||
8'd81:regdata <= { 16'h0037 ,SI_BAND_SEL } ;
|
||||
8'd82:regdata <= { 16'h0038 ,SI_VCO_SEL_BIAS_CODE } ;
|
||||
8'd83:regdata <= { 16'h0011 ,INT[15:8] } ;
|
||||
8'd84:regdata <= { 16'h0010 ,INT[7:0] } ;
|
||||
|
||||
default: regdata <= regdata;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,622 @@
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2021/8/13 00:24:20
|
||||
// Design Name:
|
||||
// Module Name: LMX2595
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
|
||||
// fRFOUT= (INT+ (FRAC1+FRAC2/MOD2)/MOD1)× (fPFD/R)
|
||||
// fPFD = fPFD = REFIN × ((1 + D)/(R × (1 + T)))
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module adf4371_b(//20.375Ghz ~ 23.875Ghz
|
||||
input sysclk ,//40MHZ
|
||||
input arstn ,
|
||||
output cs ,
|
||||
input mux_out ,
|
||||
output sclk ,
|
||||
output sdio ,
|
||||
input [3:0] rf_en ,
|
||||
input CAL_F ,
|
||||
input SW_PLL ,
|
||||
input i_cfgover ,
|
||||
input [3:0] ceshi_model ,
|
||||
input adf4371_hop ,
|
||||
input[11:0] fre_code
|
||||
);
|
||||
|
||||
localparam DATA_WIDTH = 24 ;
|
||||
localparam DATA_LENTH = 72 ;
|
||||
localparam WAIT_ld = 40000 ;
|
||||
//***********************************************************************************************************//
|
||||
reg[7:0] cnt_word = 8'd0 ;
|
||||
reg csb_reg = 1'b1 ;
|
||||
reg[5:0] cnt_bits = 6'd0 ;
|
||||
reg[DATA_WIDTH-1:0] cfgdata = 0, regdata = 0 ;
|
||||
reg[3:0] state = 4'b000 ;
|
||||
reg spi_sdo = 1'b0, spi_csb = 1'b1;
|
||||
wire pll_locked ;
|
||||
reg[31:0] cnt_lock = 32'd0 ;
|
||||
reg[31:0] cnt_locked = 32'd0 ;
|
||||
wire[15:0] band ;
|
||||
|
||||
//-----------------------------------
|
||||
assign pll_locked = mux_out ;
|
||||
assign sclk = spi_csb ? 1'b0 : ~sysclk ;
|
||||
assign cs = spi_csb & csb_reg ;
|
||||
assign sdio = spi_sdo ;
|
||||
//-----------------------------------
|
||||
|
||||
wire [7:0] SI_BAND_SEL ; //VCO频段
|
||||
wire [7:0] SI_VCO_SEL_BIAS_CODE ; //[7:4]=VCO内核, [3:0]=VCO偏置
|
||||
reg[13:0] MOD2 ;
|
||||
reg[13:0] FRAC2 ;
|
||||
reg[24:0] FRAC1 ;
|
||||
reg[15:0] INT ;
|
||||
|
||||
assign SI_BAND_SEL = band[15:8] ;
|
||||
assign SI_VCO_SEL_BIAS_CODE = band[7:0] ;
|
||||
|
||||
reg[2:0] hop_en;
|
||||
reg[15:0] code;
|
||||
reg[11:0] pre_fre_code;
|
||||
reg[3:0] cp_r;
|
||||
reg[3:0] rf_en_r;
|
||||
reg[2:0] CAL_F_R;
|
||||
|
||||
reg [3:0] R_DIV ;
|
||||
reg [3:0] D ;
|
||||
wire[13:0] douta3 ;
|
||||
wire[13:0] douta4 ;
|
||||
wire[24:0] douta2 ;
|
||||
wire[15:0] douta1 ;
|
||||
|
||||
//-----------------------------------
|
||||
INT_ROMb int_rom (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta1)
|
||||
);
|
||||
|
||||
FRAC1 frac1_rom (
|
||||
.clka(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta2)
|
||||
);
|
||||
|
||||
// FRAC1_ROM FRAC1_ROM (
|
||||
// .clka(sysclk), // input clka
|
||||
// .addra(code), // input [11 : 0] addra
|
||||
// .douta(douta2) // output [24 : 0] douta
|
||||
//);
|
||||
|
||||
frac2_rom frac2_rom (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta4)
|
||||
);
|
||||
|
||||
mod2_rom mod2_rom (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(douta3)
|
||||
);
|
||||
|
||||
|
||||
band_rom_b band_rom_b (
|
||||
.sysclk(sysclk),
|
||||
.addra(code),
|
||||
.douta(band) // output [15 : 0] douta
|
||||
);
|
||||
|
||||
//-------------------整数边界杂散用66.666666Mhz鉴相----------------------------------
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
INT<=douta1;
|
||||
else if(code==24 || code==26 )
|
||||
INT<=76;
|
||||
else if(code==424 )
|
||||
INT<=77;
|
||||
else if(code==426 )
|
||||
INT<=78;
|
||||
else if(code==824 || code==826 )
|
||||
INT<=79;
|
||||
else if(code==1224)
|
||||
INT<=80;
|
||||
else if(code==1226 )
|
||||
INT<=81;
|
||||
else if(code==1624 || code==1626 )
|
||||
INT<=82;
|
||||
else if(code==2024 )
|
||||
INT<=83;
|
||||
else if(code==2026 )
|
||||
INT<=84;
|
||||
else if(code==2424 || code==2426 )
|
||||
INT<=85;
|
||||
else if(code==2824 )
|
||||
INT<=86;
|
||||
else if( code==2826 )
|
||||
INT<=87;
|
||||
else
|
||||
INT<=douta1;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
FRAC1<=douta2;
|
||||
else if(code==24 )
|
||||
FRAC1<=16651386;
|
||||
else if(code==26 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==424 )
|
||||
FRAC1<=33428602;
|
||||
else if(code==426 )
|
||||
FRAC1<=125829;
|
||||
else if(code==824 )
|
||||
FRAC1<=16651386;
|
||||
else if(code==826 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==1224)
|
||||
FRAC1<=33428602;
|
||||
else if(code==1226 )
|
||||
FRAC1<=125829;
|
||||
else if(code==1624)
|
||||
FRAC1<=16651386;
|
||||
else if(code==1626 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==2024 )
|
||||
FRAC1<=33428602;
|
||||
else if(code==2026 )
|
||||
FRAC1<=125829;
|
||||
else if(code==2424 )
|
||||
FRAC1<=16651386;
|
||||
else if(code==2426 )
|
||||
FRAC1<=16903045;
|
||||
else if(code==2824 )
|
||||
FRAC1<=33428602;
|
||||
else if( code==2826 )
|
||||
FRAC1<=125829;
|
||||
else
|
||||
FRAC1<=douta2;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
MOD2<=douta3;
|
||||
else if(code==24 )
|
||||
MOD2<=25;
|
||||
else if(code==26 )
|
||||
MOD2<=25;
|
||||
else if(code==424 )
|
||||
MOD2<=25;
|
||||
else if(code==426 )
|
||||
MOD2<=25;
|
||||
else if(code==824 )
|
||||
MOD2<=25;
|
||||
else if(code==826 )
|
||||
MOD2<=25;
|
||||
else if(code==1224)
|
||||
MOD2<=25;
|
||||
else if(code==1226 )
|
||||
MOD2<=25;
|
||||
else if(code==1624)
|
||||
MOD2<=25;
|
||||
else if(code==1626 )
|
||||
MOD2<=25;
|
||||
else if(code==2024 )
|
||||
MOD2<=25;
|
||||
else if(code==2026 )
|
||||
MOD2<=25;
|
||||
else if(code==2424 )
|
||||
MOD2<=25;
|
||||
else if(code==2426 )
|
||||
MOD2<=25;
|
||||
else if(code==2824 )
|
||||
MOD2<=25;
|
||||
else if( code==2826 )
|
||||
MOD2<=25;
|
||||
else
|
||||
MOD2<=douta3;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
FRAC2<=douta4;
|
||||
else if(code==24 )
|
||||
FRAC2<=22;
|
||||
else if(code==26 )
|
||||
FRAC2<=3;
|
||||
else if(code==424 )
|
||||
FRAC2<=22;
|
||||
else if(code==426 )
|
||||
FRAC2<=3;
|
||||
else if(code==824 )
|
||||
FRAC2<=22;
|
||||
else if(code==826 )
|
||||
FRAC2<=3;
|
||||
else if(code==1224)
|
||||
FRAC2<=22;
|
||||
else if(code==1226 )
|
||||
FRAC2<=3;
|
||||
else if(code==1624)
|
||||
FRAC2<=22;
|
||||
else if(code==1626 )
|
||||
FRAC2<=3;
|
||||
else if(code==2024 )
|
||||
FRAC2<=22;
|
||||
else if(code==2026 )
|
||||
FRAC2<=3;
|
||||
else if(code==2424 )
|
||||
FRAC2<=22;
|
||||
else if(code==2426 )
|
||||
FRAC2<=3;
|
||||
else if(code==2824 )
|
||||
FRAC2<=22;
|
||||
else if( code==2826 )
|
||||
FRAC2<=3;
|
||||
else
|
||||
FRAC2<=douta4;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)begin
|
||||
R_DIV<=4'b1;
|
||||
D<=4'b0;
|
||||
end
|
||||
else if(code==24 || code==26 || code==424 || code==426 || code==824 || code==826|| code==1224 || code==1226 || code==1624 || code==1626 ||code==2024 || code==2026 ||code==2424 || code==2426 ||code==2824 || code==2826 )
|
||||
begin
|
||||
R_DIV<= 4'd3;
|
||||
D<=4'd2;
|
||||
end
|
||||
else
|
||||
begin
|
||||
R_DIV<=4'b1;
|
||||
D<=4'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
pre_fre_code<=11'h6d6;
|
||||
else if(CAL_F_R==3'b011)
|
||||
pre_fre_code<=fre_code;
|
||||
else
|
||||
pre_fre_code<=pre_fre_code;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
code<=16'h6d6;
|
||||
else if(hop_en==2'b01)
|
||||
code<=fre_code;
|
||||
else
|
||||
code<=code;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)begin
|
||||
hop_en <= 3'b0;
|
||||
CAL_F_R <= 3'b0;
|
||||
rf_en_r <= 4'b0;
|
||||
end
|
||||
else begin
|
||||
hop_en <= {hop_en[1:0],adf4371_hop};
|
||||
CAL_F_R <= {CAL_F_R[1:0],CAL_F};
|
||||
rf_en_r <= rf_en ;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
csb_reg <= 1'b1;
|
||||
else
|
||||
csb_reg <= spi_csb;
|
||||
end
|
||||
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)
|
||||
cnt_locked<=32'b0;
|
||||
else if(cnt_locked==WAIT_ld)
|
||||
cnt_locked<=32'b0;
|
||||
else if(!pll_locked)
|
||||
cnt_locked<=cnt_locked+1'b1;
|
||||
else
|
||||
cnt_locked<=32'b0;
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)begin
|
||||
if(~arstn)begin
|
||||
cfgdata <= 0;
|
||||
cnt_word <= 7'd0;
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'b0;
|
||||
cnt_lock <= 32'd0;
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
case(state)
|
||||
4'd0:begin
|
||||
cnt_word <= 7'd0;
|
||||
if(rf_en==1'b1)
|
||||
state <= 4'd0;
|
||||
else if(cnt_lock >= 32'd6000)
|
||||
state <= 4'd1;
|
||||
else
|
||||
state <= state;
|
||||
|
||||
if(rf_en==1'b0)
|
||||
cnt_lock <= cnt_lock + 1'b1;
|
||||
else
|
||||
cnt_lock<=32'd0;
|
||||
|
||||
end
|
||||
4'd1:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
state <= 4'd2;
|
||||
end
|
||||
4'd2:begin
|
||||
cfgdata <= regdata;
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'd3;
|
||||
end
|
||||
4'd3:begin
|
||||
spi_csb <= 1'b0;
|
||||
spi_sdo <= cfgdata[DATA_WIDTH-1];
|
||||
cfgdata <= cfgdata << 1'b1;
|
||||
cnt_bits <= cnt_bits + 1'b1;
|
||||
if(cnt_bits == DATA_WIDTH-1)begin
|
||||
state <= 4'd4;
|
||||
cnt_word <= cnt_word + 1'b1;
|
||||
end
|
||||
cnt_lock <= 32'd0;
|
||||
end
|
||||
4'd4:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
cnt_lock <= 32'd0;
|
||||
cnt_bits <= 32'd0;
|
||||
if(cnt_word == DATA_LENTH)begin
|
||||
state <= 4'd5;
|
||||
end
|
||||
else
|
||||
state <= 4'd1;
|
||||
end
|
||||
4'd5:begin
|
||||
if(cnt_lock>=40000 || pll_locked)begin
|
||||
cnt_lock <= 32'd0 ;
|
||||
state <= 4'd6 ;
|
||||
end
|
||||
else begin
|
||||
cnt_lock <=cnt_lock+1'b1;
|
||||
state <= state ;
|
||||
end
|
||||
end
|
||||
4'd6:begin
|
||||
cnt_word <= 7'd0;
|
||||
if(pll_locked)
|
||||
state <= 4'd7 ;
|
||||
else
|
||||
state <= 4'b1 ;
|
||||
end
|
||||
//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#//
|
||||
4'd7:begin//IDLE
|
||||
cnt_word <= DATA_LENTH;
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
cnt_bits <= 6'd0;
|
||||
if(rf_en==4'b1)
|
||||
state <= state;
|
||||
else if(rf_en==4'b0 && rf_en_r==4'b1 )
|
||||
state <= 4'd0;
|
||||
else if(hop_en==2'b10 || cnt_locked==WAIT_ld )
|
||||
state <= 4'd8;
|
||||
//else if(CAL_F_R==3'b011 && (pre_fre_code!=fre_code))//打开RF_OUT
|
||||
else if(i_cfgover)
|
||||
state <= 4'd12;
|
||||
else
|
||||
state <= state;
|
||||
end
|
||||
4'd8:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
state <= 4'd9;
|
||||
end
|
||||
4'd9:begin
|
||||
cfgdata <= regdata;
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'd10;
|
||||
end
|
||||
4'd10:begin
|
||||
spi_csb <= 1'b0;
|
||||
spi_sdo <= cfgdata[DATA_WIDTH-1];
|
||||
cfgdata <= cfgdata << 1'b1;
|
||||
cnt_bits <= cnt_bits + 1'b1;
|
||||
if(cnt_bits == DATA_WIDTH-1)begin
|
||||
state <= 4'd11;
|
||||
cnt_word <= cnt_word + 1'b1;
|
||||
end
|
||||
end
|
||||
4'd11:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
cnt_lock <= 32'd0;
|
||||
cnt_bits <= 32'd0;
|
||||
if(cnt_word == 8'd85)begin
|
||||
state <= 4'd7;
|
||||
end
|
||||
else
|
||||
state <= 4'd8;
|
||||
end
|
||||
4'd12:begin
|
||||
spi_csb <= 1'b1;
|
||||
spi_sdo <= 1'b0;
|
||||
state <= 4'd13;
|
||||
end
|
||||
4'd13:begin
|
||||
cnt_bits <= 6'd0;
|
||||
state <= 4'd14;
|
||||
if(ceshi_model==4'hb)
|
||||
cfgdata <= {16'h0025,8'h13};
|
||||
else if(ceshi_model==4'ha)
|
||||
cfgdata <= {16'h0025,8'h00};
|
||||
else if (SW_PLL)
|
||||
cfgdata <= {16'h0025,8'h00};
|
||||
else
|
||||
cfgdata <= {16'h0025,8'h13};
|
||||
end
|
||||
4'd14:begin
|
||||
spi_csb <= 1'b0;
|
||||
spi_sdo <= cfgdata[DATA_WIDTH-1];
|
||||
cfgdata <= cfgdata << 1'b1;
|
||||
cnt_bits <= cnt_bits + 1'b1;
|
||||
if(cnt_bits == DATA_WIDTH-1)begin
|
||||
state <= 4'd7;
|
||||
cnt_word <= cnt_word ;
|
||||
end
|
||||
end
|
||||
//&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#&*&#//
|
||||
default: begin
|
||||
spi_csb <= 1'b1;
|
||||
state <= 4'd0;
|
||||
cnt_lock <= 32'd0;
|
||||
cnt_word <= 8'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge sysclk,negedge arstn)
|
||||
begin
|
||||
if(!arstn)
|
||||
regdata <= {16'h0000,8'h18 };
|
||||
else case(cnt_word)
|
||||
8'd0 : regdata <= {16'h0000,8'h18 };
|
||||
8'd1 : regdata <= {16'h0001,8'h00 };
|
||||
8'd2 : regdata <= {16'h0003,8'h00 };
|
||||
8'd3 : regdata <= {16'h0004,8'h00 };
|
||||
8'd4 : regdata <= {16'h0005,8'h00 };
|
||||
8'd5 : regdata <= {16'h0006,8'hFF };
|
||||
8'd6 : regdata <= {16'h000C,8'h00 };
|
||||
8'd7 : regdata <= {16'h000D,8'h00 };
|
||||
8'd8 : regdata <= {16'h0010 ,INT[7:0] } ;
|
||||
8'd9 : regdata <= {16'h0011 ,INT[15:8] } ;
|
||||
8'd10 : regdata <= {16'h0012,8'h00 };//[6]Autocalibration
|
||||
//8'd10 : regdata <= {16'h0012,8'h40 };//[6]Autocalibration
|
||||
8'd11 : regdata <= {16'h0014 ,FRAC1[7:0]} ;
|
||||
8'd12 : regdata <= {16'h0015 ,FRAC1[15:8]} ;
|
||||
8'd13 : regdata <= {16'h0016 ,FRAC1[23:16]} ;
|
||||
8'd14 : regdata <= {16'h0017 ,FRAC2[6:0],FRAC1[24]} ;
|
||||
8'd15 : regdata <= {16'h0018 ,1'b0,FRAC2[13:7] } ;
|
||||
8'd16 : regdata <= {16'h0019 ,MOD2[7:0]} ;
|
||||
8'd17 : regdata <= {16'h001A ,2'b0,MOD2[13:8]} ;
|
||||
8'd18 : regdata <= {16'h001B,8'h00 };
|
||||
8'd19 : regdata <= {16'h001C,8'h00 };
|
||||
8'd20 : regdata <= {16'h001D,8'h00 };
|
||||
8'd21 : regdata <= {16'h001E,8'h18 };//CP_CURRENT 电荷泵
|
||||
//8'd21 : regdata <= {16'h001E,cp,4'h8 };//CP_CURRENT 电荷泵
|
||||
8'd22 : regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器
|
||||
8'd23 : regdata <= {16'h0020,8'h1c };//digital lock detect 数字锁定ld
|
||||
8'd24 : regdata <= {16'h0021,8'h00 };
|
||||
8'd25 : regdata <= { 16'h0022,D,4'd0 };//double D倍频器
|
||||
8'd26 : regdata <= {16'h0023,8'h00 };
|
||||
8'd27 : regdata <= {16'h0024,8'h80 };//DIV_SEL
|
||||
8'd28 : regdata <= {16'h0025,8'h13 };//X4_EN
|
||||
8'd29 : regdata <= {16'h0026,8'h1F };
|
||||
8'd30 : regdata <= {16'h0027,8'hCD };
|
||||
//8'd30 : regdata <= {16'h0027,8'hCD };
|
||||
8'd31 : regdata <= {16'h0028,8'h83 };
|
||||
8'd32 : regdata <= {16'h002A,8'h00 };
|
||||
8'd33 : regdata <= {16'h002B,8'h00 };
|
||||
8'd34 : regdata <= {16'h002C,8'h44 };
|
||||
8'd35 : regdata <= {16'h002D,8'h11 };
|
||||
8'd36 : regdata <= {16'h002E,8'h12 };
|
||||
8'd37 : regdata <= {16'h002F,8'h94 };
|
||||
8'd38 : regdata <= {16'h0030,8'h2A };
|
||||
8'd39 : regdata <= {16'h0031,8'h02 };
|
||||
8'd40 : regdata <= {16'h0032,8'h04 };
|
||||
8'd41 : regdata <= {16'h0033,8'h22 };
|
||||
8'd42 : regdata <= {16'h0034,8'h25 };
|
||||
8'd43 : regdata <= {16'h0035,8'hFA };
|
||||
8'd44 : regdata <= {16'h0036,8'h30 };
|
||||
8'd45 : regdata <= {16'h0037,SI_BAND_SEL} ;//VCO频段
|
||||
8'd46 : regdata <= {16'h0038,SI_VCO_SEL_BIAS_CODE };//[7:4]=VCO内核,[3:0]VCO偏置
|
||||
8'd47 : regdata <= {16'h0039,8'h07 };
|
||||
8'd48 : regdata <= {16'h003A,8'h55 };
|
||||
8'd49 : regdata <= {16'h003D,8'h00 };
|
||||
8'd50 : regdata <= {16'h003E,8'h0C };
|
||||
8'd51 : regdata <= {16'h003F,8'h80 };
|
||||
8'd52 : regdata <= {16'h0040,8'h50 };
|
||||
8'd53 : regdata <= {16'h0041,8'h28 };
|
||||
8'd54 : regdata <= {16'h0042,8'h00 };
|
||||
8'd55 : regdata <= {16'h0043,8'h00 };
|
||||
8'd56 : regdata <= {16'h0044,8'h00 };
|
||||
8'd57 : regdata <= {16'h0045,8'h00 };
|
||||
8'd58 : regdata <= {16'h0046,8'h00 };
|
||||
8'd59 : regdata <= {16'h0047,8'hC0 };
|
||||
8'd60 : regdata <= {16'h0052,8'hF4 };
|
||||
8'd61 : regdata <= {16'h006C,8'h00 };
|
||||
8'd62 : regdata <= {16'h006E,8'h00 };
|
||||
8'd63 : regdata <= {16'h006F,8'h00 };
|
||||
8'd64 : regdata <= {16'h0070,8'hE3 };
|
||||
8'd65 : regdata <= {16'h0071,8'h60 };
|
||||
8'd66 : regdata <= {16'h0072,8'h32 };
|
||||
8'd67 : regdata <= {16'h0073,8'h00 };
|
||||
8'd68 : regdata <= {16'h0079,8'h00 };
|
||||
8'd69 : regdata <= {16'h007A,8'h00 };
|
||||
8'd70 : regdata <= {16'h007B,8'h00 };
|
||||
8'd71 : regdata <= {16'h007C,8'h00 };
|
||||
|
||||
//跳频
|
||||
8'd72:regdata <= { 16'h0022,D,4'd0 };//double D倍频器
|
||||
8'd73:regdata <= { 16'h001F,4'h0,R_DIV };//R DIV R分频器
|
||||
8'd74:regdata <= { 16'h001A ,2'b0,MOD2[13:8] } ;
|
||||
8'd75:regdata <= { 16'h0019 ,MOD2[7:0] } ;
|
||||
8'd76:regdata <= { 16'h0018 ,1'b0,FRAC2[13:7] } ;
|
||||
8'd77:regdata <= { 16'h0017 ,FRAC2[6:0],FRAC1[24] } ;
|
||||
8'd78:regdata <= { 16'h0016 ,FRAC1[23:16] } ;
|
||||
8'd79:regdata <= { 16'h0015 ,FRAC1[15:8] } ;
|
||||
8'd80:regdata <= { 16'h0014 ,FRAC1[7:0] } ;
|
||||
8'd81:regdata <= { 16'h0037 ,SI_BAND_SEL } ;
|
||||
8'd82:regdata <= { 16'h0038 ,SI_VCO_SEL_BIAS_CODE } ;
|
||||
8'd83:regdata <= { 16'h0011 ,INT[15:8] } ;
|
||||
8'd84:regdata <= { 16'h0010 ,INT[7:0] } ;
|
||||
|
||||
default: regdata <= regdata;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,368 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 13:59:21 10/19/2020
|
||||
// Design Name:
|
||||
// Module Name: DS18B20
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
|
||||
//+125 0000 0111 1101 0000 07D0h
|
||||
//+85* 0000 0101 0101 0000 0550h
|
||||
//+25.0625 0000 0001 1001 0001 0191h
|
||||
//+10.125 0000 0000 1010 0010 00A2h
|
||||
//+0.5 0000 0000 0000 1000 0008h
|
||||
//0 0000 0000 0000 0000 0000h
|
||||
//-0.5 1111 1111 1111 1000 FFF8h
|
||||
//-10.125 1111 1111 0101 1110 FF5Eh
|
||||
//-25.0625 1111 1110 0110 1111 FE6Fh
|
||||
//-55 1111 1100 1001 0000 FC90h
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module ds18b20_temp(
|
||||
input clk , //40_000_000
|
||||
input rstn ,
|
||||
inout dq ,
|
||||
output reg signed[15:0] temp_data //LSB =0.625 C
|
||||
);
|
||||
|
||||
parameter FRE = 40 ;// //clk为40M时钟，若clk为50M，则 FRE=50；
|
||||
|
||||
parameter INIT = 3'b000 , //Gray code
|
||||
WR_CMD = 3'b001 ,
|
||||
WAIT = 3'b011 ,
|
||||
INIT_AGAIN = 3'b010 ,
|
||||
RD_CMD = 3'b110 ,
|
||||
RD_TEMP = 3'b111 ;
|
||||
|
||||
localparam WR_CC_44 = 16'h44cc ;
|
||||
localparam WR_CC_BE = 16'hbecc ;
|
||||
localparam cnt_max = FRE[31:1]-1 ;
|
||||
localparam WAIT_TEMP_CNT = 20'd750_000 ;//750ms
|
||||
|
||||
reg flag ;
|
||||
reg [15:0] data_reg ;
|
||||
reg [2:0] state ;
|
||||
reg clk_1us ;
|
||||
reg [31:0] cnt_1us ;
|
||||
reg dq_en ;
|
||||
reg dq_reg ;
|
||||
reg [19:0] cnt ;
|
||||
reg [3:0] bit_cnt ;
|
||||
|
||||
assign dq = dq_en ? dq_reg : 1'bz;
|
||||
|
||||
always@(posedge clk,negedge rstn)
|
||||
if(!rstn)
|
||||
cnt_1us<=32'b0;
|
||||
else if(cnt_1us==cnt_max)
|
||||
cnt_1us<=32'b0;
|
||||
else
|
||||
cnt_1us<=cnt_1us+1'b1;
|
||||
|
||||
always@(posedge clk,negedge rstn)
|
||||
if(!rstn)
|
||||
clk_1us<=1'b0;
|
||||
else if(cnt_1us==cnt_max)
|
||||
clk_1us<=~clk_1us;
|
||||
else
|
||||
clk_1us<=clk_1us;
|
||||
|
||||
always@(posedge clk_1us,negedge rstn)
|
||||
if(!rstn)
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg <=1'b0;
|
||||
state <=INIT;
|
||||
cnt <=20'd0;
|
||||
flag <=1'b0;
|
||||
bit_cnt <=4'b0;
|
||||
data_reg <=16'd0;
|
||||
temp_data<=12'b0;
|
||||
end
|
||||
else case(state)
|
||||
INIT :begin
|
||||
//if(cnt==16'd999)begin //for sim
|
||||
if(cnt==16'd9999)
|
||||
cnt <=20'd0;
|
||||
else if(cnt==16'd999&&flag)begin
|
||||
cnt <=20'd0;
|
||||
state<=WR_CMD;
|
||||
end
|
||||
else begin
|
||||
cnt <=cnt+1'd1;
|
||||
state<=INIT;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==16'd9999)begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
//else if(cnt==16'd499)begin
|
||||
else if(cnt==16'd599)begin
|
||||
dq_en <=1'b0;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else begin
|
||||
dq_en <=dq_en;
|
||||
dq_reg<=dq_reg;
|
||||
end
|
||||
//------------------
|
||||
// if(cnt==20'd570)//&&dq==1'b0)
|
||||
if(cnt==20'd670)//&&dq==1'b0)
|
||||
flag<= ~dq;
|
||||
else if(cnt==20'd999)
|
||||
flag<=1'b0;
|
||||
else
|
||||
flag<=flag;
|
||||
end
|
||||
/* INIT :begin
|
||||
//if(cnt==16'd999)begin //for sim
|
||||
if(cnt==16'd999&&flag)begin
|
||||
cnt <=20'd0;
|
||||
state<=WR_CMD;
|
||||
end
|
||||
else begin
|
||||
cnt <=cnt+1'd1;
|
||||
state<=INIT;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==16'd499)begin
|
||||
dq_en <=1'b0;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else begin
|
||||
dq_en <=dq_en;
|
||||
dq_reg<=dq_reg;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==20'd570)//&&dq==1'b0)
|
||||
flag<= ~dq;
|
||||
else if(cnt==20'd999)
|
||||
flag<=1'b0;
|
||||
else
|
||||
flag<=flag;
|
||||
end */
|
||||
WR_CMD :begin
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
begin
|
||||
bit_cnt<=4'd0;
|
||||
state<=WAIT;
|
||||
end
|
||||
else if(cnt==20'd64)
|
||||
begin
|
||||
bit_cnt<=bit_cnt+1'd1;
|
||||
state<=WR_CMD;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bit_cnt<=bit_cnt;
|
||||
state<=WR_CMD;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
cnt<=20'd0;
|
||||
else if(cnt==20'd64)
|
||||
cnt<=20'd0;
|
||||
else
|
||||
cnt<=cnt+1'd1;
|
||||
//------------------
|
||||
if(WR_CC_44[bit_cnt]==1'b0 && cnt<=20'd62)
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else if(WR_CC_44[bit_cnt]==1'b1 && cnt<=20'd1)
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dq_en <=1'b0;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
end
|
||||
WAIT : if(cnt==WAIT_TEMP_CNT)
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
cnt<=20'd0;
|
||||
state<=INIT_AGAIN;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b1;
|
||||
cnt<=cnt+1'd1;
|
||||
state<=WAIT;
|
||||
end
|
||||
INIT_AGAIN :begin
|
||||
if(cnt==16'd999&&flag)
|
||||
//if(cnt==16'd999) //for sim
|
||||
begin
|
||||
cnt <=20'd0;
|
||||
state<=RD_CMD;
|
||||
end
|
||||
else
|
||||
begin
|
||||
cnt <=cnt+1'd1;
|
||||
state<=INIT_AGAIN;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==16'd499)
|
||||
begin
|
||||
dq_en <=1'b0;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dq_en <=dq_en;
|
||||
dq_reg<=dq_reg;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==20'd570)//&&dq==1'b0)
|
||||
flag<=~dq;
|
||||
else if(cnt==20'd999)
|
||||
flag<=1'b0;
|
||||
else
|
||||
flag<=flag;
|
||||
end
|
||||
RD_CMD :begin
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
begin
|
||||
bit_cnt<=4'd0;
|
||||
state<=RD_TEMP;
|
||||
end
|
||||
else if(cnt==20'd64)
|
||||
begin
|
||||
bit_cnt<=bit_cnt+1'd1;
|
||||
state<=RD_CMD;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bit_cnt<=bit_cnt;
|
||||
state<=RD_CMD;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
cnt<=20'd0;
|
||||
else if(cnt==20'd64)
|
||||
cnt<=20'd0;
|
||||
else
|
||||
cnt<=cnt+1'd1;
|
||||
//------------------
|
||||
if(WR_CC_BE[bit_cnt]==1'b0 && cnt<=20'd62)
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else if(WR_CC_BE[bit_cnt]==1'b1 && cnt<=20'd1)
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dq_en <=1'b0;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
end
|
||||
RD_TEMP :begin
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
cnt <=20'd0;
|
||||
else if(cnt==20'd64)
|
||||
cnt<=20'd0;
|
||||
else
|
||||
cnt<=cnt+1'd1;
|
||||
//------------------
|
||||
if(cnt<=20'd1|| (cnt==20'd64 && bit_cnt==4'd15))
|
||||
begin
|
||||
dq_en <=1'b1;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
dq_en <=1'b0;
|
||||
dq_reg<=1'b0;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
begin
|
||||
bit_cnt<=4'd0;
|
||||
state<=INIT;
|
||||
end
|
||||
else if(cnt==20'd64)
|
||||
begin
|
||||
bit_cnt<=bit_cnt+1'd1;
|
||||
state<=RD_TEMP;
|
||||
end
|
||||
else
|
||||
begin
|
||||
bit_cnt<=bit_cnt;
|
||||
state<=RD_TEMP;
|
||||
end
|
||||
//------------------
|
||||
if(cnt==20'd8)
|
||||
data_reg<={dq,data_reg[15:1]};
|
||||
else
|
||||
data_reg<=data_reg;
|
||||
//------------------
|
||||
if(cnt==20'd64 && bit_cnt==4'd15)
|
||||
temp_data<=data_reg;
|
||||
else
|
||||
temp_data<=temp_data;
|
||||
end
|
||||
default: state<=INIT;
|
||||
endcase
|
||||
|
||||
|
||||
/* wire[33:0]SYNC_OUT;
|
||||
wire[35:0]CONTROL0;
|
||||
wire[35:0]CONTROL1;
|
||||
wire[149:0]TRIG0;
|
||||
|
||||
vio u_vio (
|
||||
.CONTROL (CONTROL0), // INOUT BUS [35:0]
|
||||
.CLK (clk), // IN
|
||||
.SYNC_OUT (SYNC_OUT) // OUT BUS [33:0]
|
||||
);
|
||||
|
||||
|
||||
icon u_icon (
|
||||
.CONTROL0 (CONTROL0), // INOUT BUS [35:0]
|
||||
.CONTROL1 (CONTROL1) // INOUT BUS [35:0]
|
||||
);
|
||||
|
||||
|
||||
ila u_ila (
|
||||
.CONTROL (CONTROL1), // INOUT BUS [35:0]
|
||||
.CLK (clk), // IN
|
||||
.TRIG0 (TRIG0) // IN BUS [39:0]
|
||||
);
|
||||
|
||||
|
||||
assign TRIG0[2:0] = state ;
|
||||
assign TRIG0[21:3] = cnt ;
|
||||
assign TRIG0[22] = dq ;
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,72 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 15:35:03 01/27/2022
|
||||
// Design Name:
|
||||
// Module Name: mod2_rom
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module frac2_rom(
|
||||
input sysclk,
|
||||
input [11 : 0] addra,
|
||||
output reg[13:0] douta
|
||||
);
|
||||
|
||||
|
||||
reg[11:0] addr=0;
|
||||
|
||||
always@(posedge sysclk)begin
|
||||
addr<=addra%25;
|
||||
end
|
||||
|
||||
always@(posedge sysclk)begin
|
||||
case(addr)
|
||||
0 : douta <= 0;
|
||||
1 : douta <= 2;
|
||||
2 : douta <= 4;
|
||||
3 : douta <= 6;
|
||||
4 : douta <= 8;
|
||||
5 : douta <= 2;
|
||||
6 : douta <= 12;
|
||||
7 : douta <= 14;
|
||||
8 : douta <= 16;
|
||||
9 : douta <= 18;
|
||||
10 : douta <= 4;
|
||||
11 : douta <= 22;
|
||||
12 : douta <= 24;
|
||||
13 : douta <= 1;
|
||||
14 : douta <= 3;
|
||||
15 : douta <= 1;
|
||||
16 : douta <= 7;
|
||||
17 : douta <= 9;
|
||||
18 : douta <= 11;
|
||||
19 : douta <= 13;
|
||||
20 : douta <= 3;
|
||||
21 : douta <= 17;
|
||||
22 : douta <= 19;
|
||||
23 : douta <= 21;
|
||||
24 : douta <= 23;
|
||||
default:douta <= douta ;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,210 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 10:03:33 09/24/2021
|
||||
// Design Name:
|
||||
// Module Name: fre_caliatt
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module fre_caliatt(
|
||||
input i_clk ,
|
||||
input i_rstn ,
|
||||
output ENABLE ,
|
||||
output SC ,
|
||||
output SD ,
|
||||
output END_SYN ,
|
||||
input SDOUT ,
|
||||
input CAL_F ,
|
||||
input signed[7:0] i_temp ,
|
||||
input[15:0] i_fre_mode ,
|
||||
input[15:0] i_cal_fre_code ,
|
||||
input [3:0] cal1_mgc ,
|
||||
input [3:0] cal2_mgc ,
|
||||
input [3:0] cal3_mgc ,
|
||||
input [3:0] cal4_mgc ,
|
||||
input [3:0] i_ceshi_module ,
|
||||
input [40:0] SYNC_OUT ,
|
||||
input SW ,
|
||||
output [3:0] R_CAL1 ,
|
||||
output [3:0] R_CAL2 ,
|
||||
output [3:0] R_CAL3 ,
|
||||
output [3:0] R_CAL4 ,
|
||||
input [4:0] tx_mgc ,
|
||||
input [4:0] tx_cal_mgc ,
|
||||
output [4:0] T_CAL
|
||||
);
|
||||
|
||||
|
||||
wire[15:0] fre_mode ;
|
||||
wire[31:0] hop_fre_mode ;
|
||||
assign fre_mode = i_cal_fre_code/40 ;//20.375Ghz~23.875Ghz
|
||||
assign hop_fre_mode = i_cal_fre_code+20375 ;//20.375Ghz~23.875Ghz
|
||||
|
||||
|
||||
wire [3:0] R_CAL4_r ;
|
||||
wire [3:0] R_CAL3_r ;
|
||||
wire [3:0] R_CAL2_r ;
|
||||
wire [3:0] R_CAL1_r ;
|
||||
wire [4:0] T_CAL_r ;
|
||||
wire [31:0] data_in ;
|
||||
reg [31:0] data_in_r ;
|
||||
reg R_CAL_F ;
|
||||
wire[15:0] cal_mgc_r ;
|
||||
reg [15:0] cal_mgc_rr ;
|
||||
reg tx_en ;
|
||||
reg vio_en ;
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge i_clk)
|
||||
begin
|
||||
cal_mgc_rr <= cal_mgc_r;
|
||||
end
|
||||
//------------------vio_debug------------------------//
|
||||
/* always@(posedge i_clk)
|
||||
begin
|
||||
vio_R_CAL_4 <= SYNC_OUT[4:0];
|
||||
vio_R_CAL_3 <= SYNC_OUT[9:5];
|
||||
vio_R_CAL_2 <= SYNC_OUT[14:10];
|
||||
vio_R_CAL_1 <= SYNC_OUT[19:15];
|
||||
vio_T_CAL <= SYNC_OUT[24:20];
|
||||
vio_en <= SYNC_OUT[25];
|
||||
end */
|
||||
|
||||
//------------------vio_debug------------------------//
|
||||
assign R_CAL1 = R_CAL1_r + cal1_mgc ;//通道1
|
||||
assign R_CAL2 = R_CAL2_r + cal2_mgc ;//通道2
|
||||
assign R_CAL3 = R_CAL3_r + cal3_mgc ;//通道3
|
||||
assign R_CAL4 = R_CAL4_r + cal4_mgc ;//通道4
|
||||
assign T_CAL = ( i_ceshi_module==4'ha || i_ceshi_module==4'hb) ? (tx_mgc[4:0] + tx_cal_mgc) : (T_CAL_r + tx_cal_mgc) ;//发射通道，低衰减
|
||||
|
||||
assign cal_mgc_r = {cal1_mgc,cal2_mgc,cal3_mgc,cal4_mgc};
|
||||
assign data_in = { 4'h0,3'b0,
|
||||
T_CAL , //发射通道
|
||||
R_CAL1[0], //接收通道1_1dB
|
||||
R_CAL1[1], //接收通道1_2dB
|
||||
R_CAL1[2], //接收通道1_4dB
|
||||
R_CAL1[3], //接收通道1_8dB
|
||||
R_CAL2[0], //接收通道2_1dB
|
||||
R_CAL2[1], //接收通道2_2dB
|
||||
R_CAL2[2], //接收通道2_4dB
|
||||
R_CAL2[3], //接收通道2_8dB
|
||||
R_CAL3[0], //接收通道3_1dB
|
||||
R_CAL3[1], //接收通道3_2dB
|
||||
R_CAL3[2], //接收通道3_4dB
|
||||
R_CAL3[3], //接收通道3_8dB
|
||||
R_CAL4 , //
|
||||
4'b0 };
|
||||
reg [31:0] cnt5us=0;
|
||||
|
||||
always@(posedge i_clk)begin
|
||||
if(cnt5us==2000)
|
||||
cnt5us<=2000;
|
||||
else
|
||||
cnt5us<=cnt5us+1'b1;
|
||||
end
|
||||
|
||||
always@(posedge i_clk or negedge i_rstn)begin
|
||||
if(!i_rstn)
|
||||
R_CAL_F <= 1'b0;
|
||||
else
|
||||
R_CAL_F <= CAL_F;
|
||||
end
|
||||
|
||||
always@(posedge i_clk or negedge i_rstn)begin
|
||||
if(!i_rstn)
|
||||
tx_en<=1'b0;
|
||||
else if(cnt5us==1999)
|
||||
tx_en<=1'b1;
|
||||
else if({R_CAL_F,CAL_F}==2'b01 || cal_mgc_rr!=cal_mgc_r)
|
||||
tx_en<=1'b1;
|
||||
else
|
||||
tx_en<=1'b0;
|
||||
end
|
||||
|
||||
|
||||
|
||||
R_CAL_1 R_CAL_1 (
|
||||
.i_clk(i_clk),
|
||||
.i_rstn(i_rstn),
|
||||
.i_temp(i_temp),
|
||||
.fre_mode(fre_mode),
|
||||
.R_CAL(R_CAL1_r)
|
||||
);
|
||||
|
||||
R_CAL_2 R_CAL_2 (
|
||||
.i_clk(i_clk),
|
||||
.i_rstn(i_rstn),
|
||||
.i_temp(i_temp),
|
||||
.fre_mode(fre_mode),
|
||||
.R_CAL(R_CAL2_r)
|
||||
);
|
||||
|
||||
R_CAL_3 R_CAL_3 (
|
||||
.i_clk(i_clk),
|
||||
.i_rstn(i_rstn),
|
||||
.i_temp(i_temp),
|
||||
.fre_mode(fre_mode),
|
||||
.R_CAL(R_CAL3_r)
|
||||
);
|
||||
|
||||
R_CAL_4 R_CAL_4 (
|
||||
.i_clk(i_clk),
|
||||
.i_rstn(i_rstn),
|
||||
.i_temp(i_temp),
|
||||
.fre_mode(fre_mode),
|
||||
.R_CAL(R_CAL4_r)
|
||||
);
|
||||
|
||||
|
||||
T_CAL T_CAL__ (
|
||||
.i_clk(i_clk),
|
||||
.i_rstn(i_rstn),
|
||||
.SW(SW),
|
||||
.i_temp(i_temp),
|
||||
.hop_fre_mode(hop_fre_mode),
|
||||
.T_CAL_(T_CAL_r)
|
||||
);
|
||||
|
||||
|
||||
spi_tx SPI_TX (
|
||||
.clk (i_clk ) ,
|
||||
.rstn (i_rstn ) ,
|
||||
.tx_en (tx_en ) ,
|
||||
.data_in (data_in ) ,
|
||||
.spi_cs (ENABLE ) ,
|
||||
.spi_sclk (SC ) ,
|
||||
.spi_sdo (SD ) ,
|
||||
.DARY (END_SYN )
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,434 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 19:54:29 09/06/2021
|
||||
// Design Name:
|
||||
// Module Name: mgc_ctrl
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module mgc_ctrl(
|
||||
input i_sys_clk ,
|
||||
input i_rst_n ,
|
||||
input i_TR_SW_F ,
|
||||
input i_TP_EN_F ,
|
||||
input i_CAL_F ,
|
||||
input i_T_MGC_EN_F ,
|
||||
input i_R_MGC_EN_F ,
|
||||
|
||||
input [15:0] i_fre_code ,
|
||||
input [7:0] i_tx_mgc ,
|
||||
input [7:0] i_rx1_mgc ,
|
||||
input [7:0] i_rx2_mgc ,
|
||||
input [7:0] i_rx3_mgc ,
|
||||
input [7:0] i_rx4_mgc ,
|
||||
input [3:0] i_ceshi_module,
|
||||
output [15:0] o_current_fre_code,
|
||||
output [15:0] o_cal_fre_code,
|
||||
output [15:0] o_hop_fre_code,
|
||||
output o_adf4371_hop1,
|
||||
output o_adf4371_hop2,
|
||||
|
||||
output o_SW,
|
||||
output o_SW2,
|
||||
output o_SW3,
|
||||
output o_SW_C1,
|
||||
|
||||
//发射通道MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
||||
output o_T_MGC_1dB,
|
||||
output o_T_MGC_2dB,
|
||||
output o_T_MGC_4dB,
|
||||
output o_T_MGC_8dB,
|
||||
output o_T_MGC_16dB,
|
||||
//接收通道1MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
||||
output reg[7:0] o_R_MGC_1,
|
||||
|
||||
//接收通道2MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
||||
output reg[7:0] o_R_MGC_2,
|
||||
|
||||
//接收通道3MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
||||
output reg[7:0] o_R_MGC_3,
|
||||
//接收通道4MGC控制，高衰。31dB，步进1dB。初始态直通（全置1）
|
||||
output reg[7:0] o_R_MGC_4
|
||||
|
||||
);
|
||||
|
||||
|
||||
reg TR_SW_F;
|
||||
reg [2:0] TP_EN_r;
|
||||
reg [2:0] T_MGC_EN_r;
|
||||
reg [2:0] R_MGC_EN_r;
|
||||
reg [2:0] R_CAL_F;
|
||||
reg [15:0] hop_fre_code;
|
||||
reg [15:0] current_fre_code;
|
||||
wire [15:0] cal_fre_code;
|
||||
reg [47:0] fre_code_a_b;
|
||||
reg hop_en;
|
||||
reg hop_en_r;
|
||||
reg hop_en_rr;
|
||||
reg cfg_en;
|
||||
reg cfg_en_r;
|
||||
reg cfg_en_rr;
|
||||
reg hmc704_1_hop;
|
||||
reg hmc704_2_hop;
|
||||
reg [1:0] cnt_cfg;
|
||||
reg [1:0] cnt_hop;
|
||||
|
||||
|
||||
reg sw1;
|
||||
reg sw2;
|
||||
reg sw3;
|
||||
reg SW_C1;
|
||||
|
||||
reg T_MGC_1dB_r ;
|
||||
reg T_MGC_2dB_r ;
|
||||
reg T_MGC_4dB_r ;
|
||||
reg T_MGC_8dB_r ;
|
||||
reg T_MGC_16dB_r;
|
||||
|
||||
assign o_SW = sw1;
|
||||
assign o_SW2 = sw2;
|
||||
assign o_SW3 = sw3;
|
||||
assign o_SW_C1 = SW_C1;
|
||||
|
||||
assign o_current_fre_code= current_fre_code;
|
||||
assign o_cal_fre_code = cal_fre_code;
|
||||
assign o_hop_fre_code = hop_fre_code;
|
||||
assign o_adf4371_hop1 = hmc704_1_hop;
|
||||
assign o_adf4371_hop2 = hmc704_2_hop;
|
||||
|
||||
assign o_T_MGC_1dB = T_MGC_1dB_r ;
|
||||
assign o_T_MGC_2dB = T_MGC_2dB_r ;
|
||||
assign o_T_MGC_4dB = T_MGC_4dB_r ;
|
||||
assign o_T_MGC_8dB = T_MGC_8dB_r ;
|
||||
assign o_T_MGC_16dB = T_MGC_16dB_r ;
|
||||
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
TR_SW_F <= 1'b0;
|
||||
TP_EN_r <= 3'b0;
|
||||
T_MGC_EN_r <= 3'b0;
|
||||
R_MGC_EN_r <= 3'b0;
|
||||
R_CAL_F <= 3'b0;
|
||||
end
|
||||
else begin
|
||||
TR_SW_F <= i_TR_SW_F;
|
||||
TP_EN_r <= {TP_EN_r[1:0] ,i_TP_EN_F};
|
||||
T_MGC_EN_r <= {T_MGC_EN_r[1:0] ,i_T_MGC_EN_F};
|
||||
R_MGC_EN_r <= {R_MGC_EN_r[1:0] ,i_R_MGC_EN_F};
|
||||
R_CAL_F <= {R_CAL_F[1:0] ,i_CAL_F};
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
SW_C1 <= 1'b0;
|
||||
current_fre_code <= 16'h6d6 ;
|
||||
end
|
||||
else begin
|
||||
current_fre_code <= hop_en ? hop_fre_code : current_fre_code ;
|
||||
if(TR_SW_F==1'b1)begin
|
||||
if(current_fre_code<=1500)//20.375Ghz~21.875Ghz
|
||||
SW_C1 <= 1'b1;
|
||||
else //21.875Ghz~23.875Ghz
|
||||
SW_C1 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
SW_C1 <= SW_C1;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign cal_fre_code = R_CAL_F==3'b001 ? hop_fre_code : cal_fre_code ;
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
fre_code_a_b <= 48'h0000000006d6;
|
||||
end
|
||||
else if(cfg_en)begin
|
||||
fre_code_a_b <= {fre_code_a_b[31:0],i_fre_code};
|
||||
end
|
||||
else begin
|
||||
fre_code_a_b <= fre_code_a_b;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
hop_en <= 1'b0;
|
||||
end
|
||||
else if(TP_EN_r==3'b011)begin
|
||||
hop_en <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
hop_en <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
hop_fre_code <= 16'h6d6;
|
||||
end
|
||||
else begin
|
||||
hop_fre_code <= i_fre_code;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
cfg_en <= 1'b0;
|
||||
end
|
||||
else if(hop_fre_code != i_fre_code)begin
|
||||
cfg_en <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
cfg_en <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
hop_en_r <= 1'b0;
|
||||
hop_en_rr <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
hop_en_r <= hop_en;
|
||||
hop_en_rr <= hop_en_r;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
cfg_en_r <= 1'b0;
|
||||
cfg_en_rr <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
cfg_en_r <= cfg_en;
|
||||
cfg_en_rr <= cfg_en_r;
|
||||
end
|
||||
end
|
||||
|
||||
reg [15:0] pre_hop_fre_code;
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
cnt_hop <= 2'b00;
|
||||
end
|
||||
else if(cnt_hop == 2'b10)begin
|
||||
cnt_hop <= 2'b00;
|
||||
end
|
||||
else if(~hop_en_r & hop_en && (pre_hop_fre_code!=hop_fre_code ))begin
|
||||
cnt_hop <= cnt_hop + 1'b1;
|
||||
end
|
||||
else begin
|
||||
cnt_hop <= cnt_hop;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
cnt_cfg <= 2'b00;
|
||||
end
|
||||
else if(cnt_cfg == 2'b10)begin
|
||||
cnt_cfg <= 2'b00;
|
||||
end
|
||||
else if(~cfg_en_r&cfg_en)begin
|
||||
cnt_cfg <= cnt_cfg + 1'b1;
|
||||
end
|
||||
else begin
|
||||
cnt_cfg <= cnt_cfg;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)
|
||||
pre_hop_fre_code<=16'h6d6;
|
||||
else if(hop_en_rr)
|
||||
pre_hop_fre_code<=hop_fre_code;
|
||||
else
|
||||
pre_hop_fre_code<=pre_hop_fre_code;
|
||||
end
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
sw1 <= 1'b1;
|
||||
sw2 <= 1'b1;
|
||||
sw3 <= 1'b0;
|
||||
end
|
||||
else if(i_ceshi_module==4'ha)//自动校准开关到a
|
||||
begin
|
||||
sw1 <= 1'b0;
|
||||
sw2 <= 1'b0;
|
||||
sw3 <= 1'b1;
|
||||
end
|
||||
else if(i_ceshi_module==4'hb)//自动校准开关到b
|
||||
begin
|
||||
sw1 <= 1'b1;
|
||||
sw2 <= 1'b1;
|
||||
sw3 <= 1'b0;
|
||||
end
|
||||
else if(hop_en_rr && pre_hop_fre_code != hop_fre_code)begin
|
||||
if(cnt_hop == 2'b01)begin
|
||||
sw1 <= 1'b0;
|
||||
sw2 <= 1'b0;
|
||||
sw3 <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
sw1 <= 1'b1;
|
||||
sw2 <= 1'b1;
|
||||
sw3 <= 1'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
sw1 <= sw1;
|
||||
sw2 <= sw2;
|
||||
sw3 <= sw3;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
else if(i_ceshi_module==4'ha&&cfg_en_rr)begin
|
||||
hmc704_1_hop <= 1'b1;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
else if(i_ceshi_module==4'hb&&cfg_en_rr)begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b1;
|
||||
end
|
||||
else if(cfg_en_rr)begin
|
||||
if(fre_code_a_b[47:32]==fre_code_a_b[15:0])begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
else if(cnt_cfg == 2'b01)begin
|
||||
hmc704_1_hop <= 1'b1;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
/* always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
sw1 <= 1'b1;
|
||||
sw2 <= 1'b1;
|
||||
sw3 <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @ (posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
else if(cfg_en_rr)begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
hmc704_1_hop <= 1'b0;
|
||||
hmc704_2_hop <= 1'b0;
|
||||
end
|
||||
end */
|
||||
|
||||
|
||||
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
T_MGC_1dB_r <= 1'b0;
|
||||
T_MGC_2dB_r <= 1'b0;
|
||||
T_MGC_4dB_r <= 1'b0;
|
||||
T_MGC_8dB_r <= 1'b0;
|
||||
T_MGC_16dB_r <= 1'b0;
|
||||
end
|
||||
else if(i_ceshi_module==4'ha || i_ceshi_module==4'hb )begin
|
||||
T_MGC_1dB_r <= 1'b0;
|
||||
T_MGC_2dB_r <= 1'b0;
|
||||
T_MGC_4dB_r <= 1'b0;
|
||||
T_MGC_8dB_r <= 1'b0;
|
||||
T_MGC_16dB_r <= 1'b0;
|
||||
end
|
||||
else if(T_MGC_EN_r==3'b011)begin
|
||||
T_MGC_1dB_r <= i_tx_mgc[0];
|
||||
T_MGC_2dB_r <= i_tx_mgc[1];
|
||||
T_MGC_4dB_r <= i_tx_mgc[2];
|
||||
T_MGC_8dB_r <= i_tx_mgc[3];
|
||||
T_MGC_16dB_r <= i_tx_mgc[4];
|
||||
end
|
||||
else begin
|
||||
T_MGC_1dB_r <= T_MGC_1dB_r ;
|
||||
T_MGC_2dB_r <= T_MGC_2dB_r ;
|
||||
T_MGC_4dB_r <= T_MGC_4dB_r ;
|
||||
T_MGC_8dB_r <= T_MGC_8dB_r ;
|
||||
T_MGC_16dB_r <= T_MGC_16dB_r ;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
o_R_MGC_1 <= 1'b0;
|
||||
end
|
||||
else if(R_MGC_EN_r==3'b011)begin
|
||||
o_R_MGC_1 <= i_rx1_mgc;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
o_R_MGC_2 <= 1'b0;
|
||||
end
|
||||
else if(R_MGC_EN_r==3'b011)begin
|
||||
o_R_MGC_2 <= i_rx2_mgc;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
o_R_MGC_3 <= 1'b0;
|
||||
end
|
||||
else if(R_MGC_EN_r==3'b011)begin
|
||||
o_R_MGC_3 <= i_rx3_mgc;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge i_sys_clk or negedge i_rst_n)begin
|
||||
if(!i_rst_n)begin
|
||||
o_R_MGC_4 <= 1'b0;
|
||||
end
|
||||
else if(R_MGC_EN_r==3'b011)begin
|
||||
o_R_MGC_4 <= i_rx4_mgc;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,71 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 15:35:03 01/27/2022
|
||||
// Design Name:
|
||||
// Module Name: mod2_rom
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module mod2_rom(
|
||||
input sysclk,
|
||||
input [11 : 0] addra,
|
||||
|
||||
output reg[13:0] douta
|
||||
);
|
||||
|
||||
reg[11:0] addr=0;
|
||||
always@(posedge sysclk)begin
|
||||
addr<=addra%25;
|
||||
end
|
||||
|
||||
always@(posedge sysclk)begin
|
||||
case(addr)
|
||||
0 : douta <= 1 ;
|
||||
1 : douta <= 25 ;
|
||||
2 : douta <= 25 ;
|
||||
3 : douta <= 25 ;
|
||||
4 : douta <= 25 ;
|
||||
5 : douta <= 5 ;
|
||||
6 : douta <= 25 ;
|
||||
7 : douta <= 25 ;
|
||||
8 : douta <= 25 ;
|
||||
9 : douta <= 25 ;
|
||||
10 : douta <= 5 ;
|
||||
11 : douta <= 25 ;
|
||||
12 : douta <= 25 ;
|
||||
13 : douta <= 25 ;
|
||||
14 : douta <= 25 ;
|
||||
15 : douta <= 5 ;
|
||||
16 : douta <= 25 ;
|
||||
17 : douta <= 25 ;
|
||||
18 : douta <= 25 ;
|
||||
19 : douta <= 25 ;
|
||||
20 : douta <= 5 ;
|
||||
21 : douta <= 25 ;
|
||||
22 : douta <= 25 ;
|
||||
23 : douta <= 25 ;
|
||||
24 : douta <= 25 ;
|
||||
default:douta <= douta ;
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,150 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 20:42:39 09/29/2021
|
||||
// Design Name:
|
||||
// Module Name: spi_master
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module spi_master #(parameter BIT_NUM = 95 )(
|
||||
input i_clk ,
|
||||
input debug_clk ,
|
||||
input i_sys_rst_n ,
|
||||
input i_spi_sck ,
|
||||
input i_spi_cs ,
|
||||
output o_spi_sdo ,
|
||||
input i_spi_sdi ,
|
||||
input i_LD_LO3 ,
|
||||
input i_LD1 ,
|
||||
input i_LD2 ,
|
||||
input[3:0] i_cal1_mgc ,
|
||||
input[3:0] i_cal2_mgc ,
|
||||
input[3:0] i_cal3_mgc ,
|
||||
input[3:0] i_cal4_mgc ,
|
||||
input[7:0] i_temp ,
|
||||
input[31:0] i_frame_count
|
||||
|
||||
);
|
||||
|
||||
wire [BIT_NUM:0] data ;
|
||||
reg [BIT_NUM:0] data_r ;
|
||||
reg [BIT_NUM:0] data_reg ;
|
||||
assign data={ 8'hAA ,
|
||||
i_temp ,
|
||||
7'b0,i_LD_LO3 ,
|
||||
7'b0,i_LD1 ,
|
||||
7'b0,i_LD2 ,
|
||||
i_cal1_mgc,i_cal2_mgc ,
|
||||
i_cal3_mgc,i_cal4_mgc ,
|
||||
i_frame_count ,
|
||||
8'hCC } ;
|
||||
|
||||
wire spi_sck ;
|
||||
wire spi_cs ;
|
||||
reg spi_sdo ;
|
||||
reg [2:0] reg_cs ;
|
||||
reg [31:0] cnt ;
|
||||
|
||||
assign spi_sck = i_spi_sck;
|
||||
assign spi_cs = i_spi_cs;
|
||||
assign o_spi_sdo = spi_sdo;
|
||||
|
||||
always@(negedge spi_sck,negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)
|
||||
reg_cs<=3'b111;
|
||||
else
|
||||
reg_cs<={reg_cs[1:0],i_spi_cs};
|
||||
end
|
||||
|
||||
always@(negedge spi_sck,negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)
|
||||
data_r<={8'hAA,80'b0,8'hCC};
|
||||
else if(reg_cs[2:1]==2'b10)
|
||||
data_r<={8'hAA,data[87:8],8'hCC};
|
||||
end
|
||||
|
||||
always@(negedge spi_sck,negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)
|
||||
spi_sdo <= 1'b0 ;
|
||||
else if(!spi_cs)
|
||||
spi_sdo <= data_r[cnt];
|
||||
else
|
||||
spi_sdo <= 1'b0 ;
|
||||
end
|
||||
|
||||
always@(posedge spi_sck,negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)
|
||||
cnt<=BIT_NUM;
|
||||
else if(spi_cs==1 | cnt==0)
|
||||
cnt<=BIT_NUM;
|
||||
else
|
||||
cnt<=cnt-1;
|
||||
end
|
||||
|
||||
//------------debug------------
|
||||
always@(posedge spi_sck,negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)
|
||||
data_reg <= 0 ;
|
||||
else if(!spi_cs)
|
||||
data_reg <= {data_reg,spi_sdo} ;
|
||||
else
|
||||
data_reg <= data_reg ;
|
||||
end
|
||||
//------------debug------------
|
||||
|
||||
/*
|
||||
wire [40:0] SYNC_OUT ;
|
||||
wire [35:0] CONTROL0 ;
|
||||
wire [35:0] CONTROL1 ;
|
||||
wire [150:0] TRIG0 ;
|
||||
|
||||
vio u_vio (
|
||||
.CONTROL (CONTROL0), // INOUT BUS [35:0]
|
||||
.CLK (i_clk), // IN
|
||||
.SYNC_OUT (SYNC_OUT) // OUT BUS [33:0]
|
||||
);
|
||||
|
||||
|
||||
icon u_icon (
|
||||
.CONTROL0 (CONTROL0), // INOUT BUS [35:0]
|
||||
.CONTROL1 (CONTROL1) // INOUT BUS [35:0]
|
||||
);
|
||||
|
||||
|
||||
ila u_ila (
|
||||
.CONTROL (CONTROL1), // INOUT BUS [35:0]
|
||||
.CLK (debug_clk), // IN
|
||||
.TRIG0 (TRIG0) // IN BUS [39:0]
|
||||
);
|
||||
|
||||
|
||||
assign TRIG0[0] = i_LD_LO3;
|
||||
assign TRIG0[1] = i_LD1 ;
|
||||
assign TRIG0[2] = i_LD2 ;
|
||||
assign TRIG0[98:3] = data_r ;
|
||||
assign TRIG0[101:99] = reg_cs ;
|
||||
assign TRIG0[132:102] = cnt ;
|
||||
assign TRIG0[133] = i_spi_sck ;
|
||||
assign TRIG0[134] = i_spi_cs ;
|
||||
assign TRIG0[135] = o_spi_sdo ;
|
||||
assign TRIG0[136] = i_spi_sdi ;
|
||||
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,171 @@
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2020/09/02 10:48:55
|
||||
// Design Name:
|
||||
// Module Name: d
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
// SPI时钟频率50MHz。每一帧数据12个字节，共96bit数据。
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module spi_slave#(
|
||||
parameter BIT_NUM = 96
|
||||
)
|
||||
(
|
||||
input i_sys_clk,
|
||||
input i_sys_rst_n,
|
||||
|
||||
input i_spi_sck, //从机在时钟下降沿采样数据
|
||||
input i_spi_cs, //低电平时从机接收数据指令
|
||||
input i_spi_sdi,
|
||||
output [31:0] o_frame_count, //帧计数
|
||||
output [15:0] o_fre_code , //天线频率
|
||||
output [7:0] o_tx_mgc, //发射MGC
|
||||
output [3:0] o_model, //模式字
|
||||
output [3:0] o_rf_en, //射频使能
|
||||
output [3:0] o_cal1_mgc, //接收校准1mgc
|
||||
output [3:0] o_cal2_mgc, //接收校准2mgc
|
||||
output [3:0] o_cal3_mgc, //接收校准3mgc
|
||||
output [3:0] o_cal4_mgc, //接收校准4mgc
|
||||
output [7:0] o_tx_cal_mgc, //发射校准mgc
|
||||
output [7:0] o_rx1_mgc, //接收1mgc
|
||||
output [7:0] o_rx2_mgc, //接收2mgc
|
||||
output [7:0] o_rx3_mgc, //接收3mgc
|
||||
output [7:0] o_rx4_mgc , //接收4mgc
|
||||
|
||||
output [3:0] o_ceshi_model
|
||||
);
|
||||
|
||||
reg [BIT_NUM -1:0] receive_data;
|
||||
reg [3:0] rf_en ;
|
||||
reg [3:0] model;
|
||||
reg [31:0] frame_count;
|
||||
reg [11:0] fre_code;
|
||||
reg [7:0] tx_mgc;
|
||||
reg [7:0] rx1_mgc;
|
||||
reg [7:0] rx2_mgc;
|
||||
reg [7:0] rx3_mgc;
|
||||
reg [7:0] rx4_mgc;
|
||||
reg [3:0] cal1_mgc;
|
||||
reg [3:0] cal2_mgc;
|
||||
reg [3:0] cal3_mgc;
|
||||
reg [3:0] cal4_mgc;
|
||||
reg [7:0] tx_cal_mgc;
|
||||
reg [3:0] ceshi_module;
|
||||
|
||||
|
||||
assign o_frame_count= frame_count;
|
||||
assign o_fre_code = {4'b0,fre_code};
|
||||
assign o_rf_en = rf_en;
|
||||
assign o_model = model;
|
||||
assign o_tx_mgc = tx_mgc;
|
||||
assign o_cal1_mgc = cal1_mgc;
|
||||
assign o_cal2_mgc = cal2_mgc;
|
||||
assign o_cal3_mgc = cal3_mgc;
|
||||
assign o_cal4_mgc = cal4_mgc;
|
||||
assign o_tx_cal_mgc = tx_cal_mgc;
|
||||
assign o_rx1_mgc = rx1_mgc;
|
||||
assign o_rx2_mgc = rx2_mgc;
|
||||
assign o_rx3_mgc = rx3_mgc;
|
||||
assign o_rx4_mgc = rx4_mgc;
|
||||
assign o_ceshi_model = ceshi_module;
|
||||
|
||||
always @ ( negedge i_spi_sck or negedge i_sys_rst_n)begin
|
||||
if( !i_sys_rst_n )
|
||||
receive_data <= 'b0;
|
||||
else if(i_spi_cs == 1'b0)
|
||||
receive_data <= {receive_data,i_spi_sdi};
|
||||
else
|
||||
receive_data <= receive_data;
|
||||
end
|
||||
|
||||
|
||||
reg [2:0] cs_reg;
|
||||
|
||||
always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin
|
||||
if( !i_sys_rst_n )
|
||||
cs_reg <= 3'b111;
|
||||
else
|
||||
cs_reg <= {cs_reg[1:0],i_spi_cs};
|
||||
end
|
||||
|
||||
|
||||
|
||||
always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)begin
|
||||
tx_cal_mgc<=8'h0;
|
||||
end
|
||||
else if(cs_reg[2:1]==2'b01 && (receive_data[95:88] == 8'hbb) && (receive_data[7:0] == 8'hdd))begin
|
||||
tx_cal_mgc<=receive_data[15:8];
|
||||
end
|
||||
else begin
|
||||
tx_cal_mgc<=tx_cal_mgc;
|
||||
end
|
||||
end
|
||||
|
||||
always @ ( posedge i_sys_clk or negedge i_sys_rst_n)begin
|
||||
if(!i_sys_rst_n)begin
|
||||
fre_code <= 12'h6d6;
|
||||
tx_mgc <= 8'h00;
|
||||
rf_en <= 4'b1;
|
||||
model <= 4'b0;
|
||||
frame_count <= 32'd1;
|
||||
rx1_mgc <= 4'h0;
|
||||
rx2_mgc <= 4'h0;
|
||||
rx3_mgc <= 4'h0;
|
||||
rx4_mgc <= 4'h0;
|
||||
cal1_mgc <= 4'h0;
|
||||
cal2_mgc <= 4'h0;
|
||||
cal3_mgc <= 4'h0;
|
||||
cal4_mgc <= 4'h0;
|
||||
ceshi_module <= 4'h0;
|
||||
end
|
||||
else if(cs_reg[2:1]==2'b01 && (receive_data[95:88] == 8'haa) && (receive_data[7:0] == 8'hcc))begin
|
||||
frame_count <= frame_count+1'b1;
|
||||
rf_en <= receive_data[87:84];
|
||||
model <= receive_data[83:80];
|
||||
ceshi_module<= receive_data[79:76];
|
||||
fre_code <= receive_data[75:64];
|
||||
tx_mgc <= receive_data[63:56];
|
||||
cal1_mgc <= receive_data[55:52];
|
||||
cal2_mgc <= receive_data[51:48];
|
||||
cal3_mgc <= receive_data[47:44];
|
||||
cal4_mgc <= receive_data[43:40];
|
||||
rx1_mgc <= receive_data[39:32];
|
||||
rx2_mgc <= receive_data[31:24];
|
||||
rx3_mgc <= receive_data[23:16];
|
||||
rx4_mgc <= receive_data[15:8];
|
||||
end
|
||||
else begin
|
||||
frame_count <= frame_count ;
|
||||
rf_en <= rf_en ;
|
||||
model <= model ;
|
||||
fre_code <= fre_code ;
|
||||
tx_mgc <= tx_mgc ;
|
||||
cal1_mgc <= cal1_mgc ;
|
||||
cal2_mgc <= cal2_mgc ;
|
||||
cal3_mgc <= cal3_mgc ;
|
||||
cal4_mgc <= cal4_mgc ;
|
||||
rx1_mgc <= rx1_mgc ;
|
||||
rx2_mgc <= rx2_mgc ;
|
||||
rx3_mgc <= rx3_mgc ;
|
||||
rx4_mgc <= rx4_mgc ;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,118 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 15:23:58 10/12/2020
|
||||
// Design Name: spi发送模块
|
||||
// Module Name: spi
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
module spi_tx #(parameter WHITH=32)(
|
||||
input clk,//系统时钟
|
||||
input rstn,//异步复位
|
||||
input tx_en,//发送使能
|
||||
input [WHITH-1:0] data_in,//待发送数据
|
||||
output reg spi_cs, //片选
|
||||
output reg spi_sclk, //同步时钟，等于clk/2
|
||||
output reg spi_sdo, //发送数据的线
|
||||
output reg DARY
|
||||
);
|
||||
|
||||
//localparam [1:0] polaeity = 2'b10;//negedge 数据下降沿保持
|
||||
localparam [1:0] polaeity = 2'b01;//posedge 数据上降沿保持
|
||||
reg [2:0] state ; //状态机
|
||||
reg [WHITH-1:0] reg_data;//移位寄存器
|
||||
reg [5:0] cnt;//计数器，必须大于数据位宽
|
||||
|
||||
wire CPOL ; //时钟空闲时电平
|
||||
wire CPHA ; //极性
|
||||
assign CPOL = polaeity[0] ;
|
||||
assign CPHA = polaeity[1] ;
|
||||
|
||||
always @(posedge clk,negedge rstn)begin
|
||||
if(!rstn)begin
|
||||
state <= 3'd0;
|
||||
spi_cs <= 1'b1;
|
||||
spi_sclk <= CPOL;
|
||||
reg_data <= 1'd0;
|
||||
cnt <= 5'b0;
|
||||
spi_sdo <= 1'b0;
|
||||
DARY <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
case(state)
|
||||
3'd0:begin//空闲态
|
||||
spi_sclk <= CPOL ;
|
||||
spi_cs <= 1'b1 ;
|
||||
spi_sdo <= 1'b0 ;
|
||||
DARY <= 1'b1 ;
|
||||
cnt <= 5'b0 ;
|
||||
reg_data <= data_in ;
|
||||
if(tx_en)//发送使能跳下一个状态
|
||||
state <= 3'd1 ;
|
||||
else
|
||||
state <= state ;
|
||||
end
|
||||
3'd1:begin
|
||||
spi_cs <= 1'b0 ;
|
||||
state <= 3'd2 ;
|
||||
reg_data <= data_in ;
|
||||
end
|
||||
3'd2:begin//数据移位态
|
||||
spi_cs <= 1'b0 ;
|
||||
reg_data <= reg_data<<1'b1 ;
|
||||
spi_sdo <= reg_data[WHITH-1] ;
|
||||
spi_sclk <= CPHA ;
|
||||
state <= (cnt >= WHITH-1) ? 3'd4:3'd3;
|
||||
end
|
||||
3'd3:begin//时钟翻转
|
||||
cnt <= cnt+1'b1 ;
|
||||
spi_sclk <= ~CPHA ;
|
||||
state <= 3'd2 ;
|
||||
end
|
||||
3'd4:begin//结束态
|
||||
state <= 3'd5;
|
||||
spi_sclk <= ~CPHA;
|
||||
end
|
||||
3'd5:begin//结束态
|
||||
state <= 3'd6;
|
||||
DARY <= 0;
|
||||
spi_sdo <= 1'b0 ;
|
||||
spi_cs <= 1'b1 ;
|
||||
end
|
||||
3'd6:begin//结束态
|
||||
state <= 3'd7;
|
||||
DARY <= 1;
|
||||
spi_cs <= 1'b1 ;
|
||||
end
|
||||
3'd7:begin//结束态
|
||||
state <= 3'd8;
|
||||
DARY <= 0;
|
||||
end
|
||||
3'd8:begin//结束态
|
||||
state <= 3'd0;
|
||||
DARY <= 1;
|
||||
end
|
||||
default :state<=3'd0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,515 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2022/07/13 14:20:24
|
||||
// Design Name:
|
||||
// Module Name: ant_rf_ctrl
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ant_rf_ctrl
|
||||
(
|
||||
input clk_48m ,
|
||||
input clk_96m ,
|
||||
input clk_32m ,
|
||||
input clk_19p2m ,
|
||||
input sys_rst ,
|
||||
|
||||
output ant_clk ,
|
||||
output ant_en ,
|
||||
output ant_data ,
|
||||
output ant_tr ,
|
||||
output ant_dary ,
|
||||
input ant_dout ,
|
||||
|
||||
output rf_standby ,
|
||||
output rf_sw_pll ,
|
||||
output rf_t ,
|
||||
output rf_r ,
|
||||
output rf_sw_bpf ,
|
||||
output rf_sclk1 ,
|
||||
output rf_sdio1 ,
|
||||
output rf_cs1 ,
|
||||
input rf_ld1 ,
|
||||
output rf_sclk2 ,
|
||||
output rf_sdio2 ,
|
||||
output rf_cs2 ,
|
||||
input rf_ld2 ,
|
||||
output rf_sclk3 ,
|
||||
output rf_sdio3 ,
|
||||
output rf_cs3 ,
|
||||
input rf_ld3 ,
|
||||
output rf_tmgc_16 ,
|
||||
output rf_tmgc_8 ,
|
||||
output rf_tmgc_4 ,
|
||||
output rf_tmgc_2 ,
|
||||
output rf_tmgc_1 ,
|
||||
output rf_rmgc_16 ,
|
||||
output rf_rmgc_8 ,
|
||||
output rf_rmgc_4 ,
|
||||
output rf_rmgc_2 ,
|
||||
output rf_rmgc_1 ,
|
||||
output rf_enable ,
|
||||
output rf_sc ,
|
||||
output rf_sd ,
|
||||
output rf_endsyn ,
|
||||
input rf_sdout ,
|
||||
inout rf_dq_wd ,
|
||||
output rf_sw_rx
|
||||
);
|
||||
|
||||
|
||||
(*dont_touch = "true"*) wire vio_switch ; // 键控开关，沿有效
|
||||
(*dont_touch = "true"*) wire vio_trdirection ; // 收发方向
|
||||
(*dont_touch = "true"*) wire [15:0] vio_frequency ; // 收发频率
|
||||
(*dont_touch = "true"*) wire [ 7:0] vio_emitMGC ; // 发送MGC
|
||||
(*dont_touch = "true"*) wire [ 3:0] vio_ch01MGC ; // 1通道校准MGC
|
||||
(*dont_touch = "true"*) wire [ 3:0] vio_ch02MGC ; // 2通道校准MGC
|
||||
(*dont_touch = "true"*) wire [ 3:0] vio_ch03MGC ; // 3通道校准MGC
|
||||
(*dont_touch = "true"*) wire [ 3:0] vio_ch04MGC ; // 4通道校准MGC
|
||||
(*dont_touch = "true"*) wire [ 7:0] vio_recvMGC ; // 接收MGC
|
||||
(*dont_touch = "true"*) wire [ 7:0] vio_AntMod ; // 天线工作模式
|
||||
(*dont_touch = "true"*) wire [15:0] vio_AntOffAxis ; // 天线离轴角
|
||||
(*dont_touch = "true"*) wire [15:0] vio_AntYaw ; // 天线偏航角
|
||||
(*dont_touch = "true"*) wire [15:0] vio_PrecessTime ; // 处理时间，从EN拉低到DARY拉低
|
||||
|
||||
(*dont_touch = "true"*)wire vio_mode_ant ; // 0定频手动，1扫频模式
|
||||
(*dont_touch = "true"*)wire vio_hop_start ; // 0跳频终止，1重新跳频
|
||||
(*dont_touch = "true"*)wire vio_standby ; // 1待机模式，0工作模式
|
||||
(*dont_touch = "true"*)wire [15:0] vio_hoptime ; // 单跳时间计数器
|
||||
|
||||
reg Ant_switch_D1 = 0;
|
||||
reg data_valid = 0;
|
||||
reg switch_valid = 0;
|
||||
reg [95:0] RF_CtrlWord = 0;
|
||||
reg [127:0] Ant_CtrlWord = 0;
|
||||
reg [15:0] data_valid_countdown = 0;
|
||||
reg [15:0] rst_countdown = 100;
|
||||
reg [95:0] RF_CtrlWord_running = 0;
|
||||
reg [127:0] Ant_CtrlWord_running = 0;
|
||||
reg rst_n = 0;
|
||||
reg SPI_SYN_F = 1;
|
||||
reg SPI_MOSI_F = 1;
|
||||
reg TP_EN_F = 0;
|
||||
reg TR_MGC_F = 0;
|
||||
reg CAL_F = 0;
|
||||
reg PRF = 0;
|
||||
wire SPI_MISO_F;
|
||||
reg Ant_DATA = 0;
|
||||
reg Ant_EN = 0;
|
||||
reg Ant_DARY = 0;
|
||||
reg Ant_TR = 0;
|
||||
|
||||
|
||||
|
||||
//相控阵测试程序
|
||||
reg [15:0] cnt_freq_change = 16'd0;
|
||||
|
||||
reg Ant_switch ; // 键控开关，沿有效
|
||||
reg [15:0] Ant_frequency; // 收发频率
|
||||
reg [ 7:0] Ant_mode ; // 相控阵模式
|
||||
reg [ 7:0] RF_mode ; // 射频模式
|
||||
|
||||
always @ (posedge clk_48m) begin
|
||||
if(sys_rst) begin
|
||||
Ant_switch <= 1'b0;
|
||||
cnt_freq_change[15:0] <= 16'd0;
|
||||
Ant_frequency[15:0] <= 16'd0;
|
||||
RF_mode[7:0] <= 8'h10;
|
||||
Ant_mode[7:0] <= 8'h0f;
|
||||
end
|
||||
else begin
|
||||
if(vio_mode_ant) begin
|
||||
if(vio_hop_start) begin
|
||||
if(cnt_freq_change[15:0] == (vio_hoptime[15:0] - 16'd1)) begin
|
||||
Ant_switch <= ~Ant_switch;
|
||||
if(Ant_frequency[15:0] == 16'd3500) begin
|
||||
Ant_frequency[15:0] <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
Ant_frequency[15:0] <= Ant_frequency[15:0] + 16'd1;
|
||||
end
|
||||
cnt_freq_change[15:0] <= 16'd0;
|
||||
end
|
||||
else begin
|
||||
Ant_switch <= Ant_switch;
|
||||
Ant_frequency[15:0] <= Ant_frequency[15:0];
|
||||
cnt_freq_change[15:0] <= cnt_freq_change[15:0] + 16'd1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
Ant_switch <= Ant_switch;
|
||||
Ant_frequency[15:0] <= 16'd0;
|
||||
cnt_freq_change[15:0] <= 16'd0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
Ant_switch <= vio_switch;
|
||||
Ant_frequency[15:0] <= vio_frequency[15:0];
|
||||
cnt_freq_change[15:0] <= 16'd0;
|
||||
end
|
||||
|
||||
if(vio_standby) begin
|
||||
RF_mode[7:0] <= 8'h10;
|
||||
Ant_mode[7:0] <= 8'h0f;
|
||||
end
|
||||
else begin
|
||||
RF_mode[7:0] <= 8'h00;
|
||||
Ant_mode[7:0] <= vio_AntMod[7:0];
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
always @(posedge clk_48m)
|
||||
begin
|
||||
Ant_switch_D1 <= Ant_switch;
|
||||
if(Ant_switch_D1 != Ant_switch)
|
||||
switch_valid <= 1'b1;
|
||||
else
|
||||
switch_valid <= 1'b0;
|
||||
|
||||
if(switch_valid)
|
||||
begin
|
||||
RF_CtrlWord[95:88] <= 8'hAA;
|
||||
RF_CtrlWord[87:80] <= RF_mode[7:0];
|
||||
RF_CtrlWord[79:64] <= Ant_frequency[15:0];
|
||||
RF_CtrlWord[63:56] <= vio_emitMGC[7:0];
|
||||
RF_CtrlWord[55:52] <= vio_ch01MGC[3:0];
|
||||
RF_CtrlWord[51:48] <= vio_ch02MGC[3:0];
|
||||
RF_CtrlWord[47:44] <= vio_ch03MGC[3:0];
|
||||
RF_CtrlWord[43:40] <= vio_ch04MGC[3:0];
|
||||
RF_CtrlWord[39:32] <= vio_recvMGC[7:0];
|
||||
RF_CtrlWord[31:8] <= 24'h00_0000;
|
||||
RF_CtrlWord[7:0] <= 8'hCC;
|
||||
|
||||
Ant_CtrlWord[127:120] <= 8'hAA;
|
||||
Ant_CtrlWord[119:112] <= 8'h00;
|
||||
Ant_CtrlWord[111:104] <= Ant_mode[7:0];
|
||||
Ant_CtrlWord[103: 88] <= vio_AntOffAxis[15:0];
|
||||
Ant_CtrlWord[ 87: 72] <= vio_AntYaw[15:0];
|
||||
Ant_CtrlWord[ 71: 56] <= Ant_frequency[15:0];
|
||||
Ant_CtrlWord[ 55: 8] <= 48'h00_00_00_00_00_00;
|
||||
Ant_CtrlWord[ 7: 0] <= 8'hCC;
|
||||
end
|
||||
else
|
||||
begin
|
||||
RF_CtrlWord[95:0] <= RF_CtrlWord[95:0];
|
||||
// Ant_CtrlWord[127:0] <= Ant_CtrlWord[127:0];
|
||||
end
|
||||
|
||||
if(switch_valid)
|
||||
data_valid_countdown[15:0] <= vio_PrecessTime[15:0];
|
||||
else if(data_valid_countdown[15:0] != 16'd0)
|
||||
data_valid_countdown[15:0] <= data_valid_countdown[15:0] - 16'd1;
|
||||
|
||||
|
||||
// RF控制
|
||||
if(data_valid_countdown[15:0] == vio_PrecessTime[15:0])
|
||||
RF_CtrlWord_running[95:0] <= RF_CtrlWord[95:0];
|
||||
else
|
||||
RF_CtrlWord_running[95:0] <= {RF_CtrlWord_running[94:0],1'b0};
|
||||
|
||||
if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd96 && data_valid_countdown[15:0] < vio_PrecessTime[15:0])
|
||||
begin
|
||||
SPI_SYN_F <= 1'b0;
|
||||
SPI_MOSI_F <= RF_CtrlWord_running[95];
|
||||
end
|
||||
else
|
||||
begin
|
||||
SPI_SYN_F <= 1'b1;
|
||||
SPI_MOSI_F <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
if(data_valid_countdown[15:0] <= 16'd128 && data_valid_countdown[15:0] > 16'd80)
|
||||
CAL_F <= 1'b1;
|
||||
else
|
||||
CAL_F <= 1'b0;
|
||||
|
||||
if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0)
|
||||
begin
|
||||
TP_EN_F <= 1'b1;
|
||||
TR_MGC_F <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
TP_EN_F <= 1'b0;
|
||||
TR_MGC_F <= 1'b0;
|
||||
end
|
||||
|
||||
if(data_valid_countdown[15:0] == 16'd48)
|
||||
PRF <= vio_trdirection;
|
||||
else
|
||||
PRF <= PRF;
|
||||
|
||||
if(sys_rst)
|
||||
rst_countdown[15:0] <= 16'd100;
|
||||
else if(rst_countdown[15:0] != 0)
|
||||
begin
|
||||
rst_countdown[15:0] <= rst_countdown[15:0] - 16'd1;
|
||||
rst_n <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
rst_countdown[15:0] <= rst_countdown[15:0];
|
||||
rst_n <= 1'b1;
|
||||
end
|
||||
|
||||
// 天线控制
|
||||
if(data_valid_countdown[15:0] == vio_PrecessTime[15:0])
|
||||
Ant_CtrlWord_running[127:0] <= Ant_CtrlWord[127:0];
|
||||
else
|
||||
Ant_CtrlWord_running[127:0] <= {Ant_CtrlWord_running[126:0],1'b0};
|
||||
|
||||
if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd128 && data_valid_countdown[15:0] < vio_PrecessTime[15:0])
|
||||
begin
|
||||
Ant_EN <= 1'b0;
|
||||
Ant_DATA <= Ant_CtrlWord_running[127];
|
||||
end
|
||||
else
|
||||
begin
|
||||
Ant_EN <= 1'b1;
|
||||
Ant_DATA <= 1'b0;
|
||||
end
|
||||
|
||||
if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0)
|
||||
Ant_DARY <= 1'b0;
|
||||
else
|
||||
Ant_DARY <= 1'b1;
|
||||
|
||||
if(data_valid_countdown[15:0] == 16'd48)
|
||||
Ant_TR <= vio_trdirection;
|
||||
else
|
||||
Ant_TR <= Ant_TR;
|
||||
end
|
||||
|
||||
|
||||
//RF recv_data
|
||||
reg [1:0] state_rfdata;
|
||||
reg SPI_SYN_F_d1 = 1'b0;
|
||||
reg [15:0] cnt_rfdata = 16'd0;
|
||||
reg [95:0] RF_RecvWord = 96'd0;
|
||||
reg [95:0] RF_RecvWord_last = 96'd0;
|
||||
|
||||
reg [7:0] RF_temperature = 8'd0 ;
|
||||
reg [7:0] RF_IFlocked = 8'd0 ;
|
||||
reg [7:0] RF_RFAlocked = 8'd0 ;
|
||||
reg [7:0] RF_RFBlocked = 8'd0 ;
|
||||
reg [3:0] RF_ch1mgc = 4'd0 ;
|
||||
reg [3:0] RF_ch2mgc = 4'd0 ;
|
||||
reg [3:0] RF_ch3mgc = 4'd0 ;
|
||||
reg [3:0] RF_ch4mgc = 4'd0 ;
|
||||
reg [31:0] RF_Framecount = 32'd0 ;
|
||||
|
||||
always @ (posedge clk_48m) begin
|
||||
if(sys_rst) begin
|
||||
state_rfdata[1:0] <= 2'd0;
|
||||
SPI_SYN_F_d1 <= 1'b0;
|
||||
RF_RecvWord[95:0] <= 96'd0;
|
||||
cnt_rfdata[15:0] <= 16'd0;
|
||||
RF_temperature[7:0] <= 8'd0 ;
|
||||
RF_IFlocked[7:0] <= 8'd0 ;
|
||||
RF_RFAlocked[7:0] <= 8'd0 ;
|
||||
RF_RFBlocked[7:0] <= 8'd0 ;
|
||||
RF_ch1mgc[3:0] <= 4'd0 ;
|
||||
RF_ch2mgc[3:0] <= 4'd0 ;
|
||||
RF_ch3mgc[3:0] <= 4'd0 ;
|
||||
RF_ch4mgc[3:0] <= 4'd0 ;
|
||||
RF_Framecount[31:0] <= 32'd0;
|
||||
end
|
||||
else begin
|
||||
RF_RecvWord[95:0] <= {RF_RecvWord[94:0],SPI_MISO_F};
|
||||
|
||||
if (RF_RecvWord[95:88] == 8'hAA && RF_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾
|
||||
RF_temperature[7:0] <= RF_RecvWord[87:80];
|
||||
RF_IFlocked[7:0] <= RF_RecvWord[79:72];
|
||||
RF_RFAlocked[7:0] <= RF_RecvWord[71:64];
|
||||
RF_RFBlocked[7:0] <= RF_RecvWord[63:56];
|
||||
RF_ch1mgc[3:0] <= RF_RecvWord[55:52];
|
||||
RF_ch2mgc[3:0] <= RF_RecvWord[51:48];
|
||||
RF_ch3mgc[3:0] <= RF_RecvWord[47:44];
|
||||
RF_ch4mgc[3:0] <= RF_RecvWord[43:40];
|
||||
RF_Framecount[31:0] <= RF_RecvWord[39:8];
|
||||
RF_RecvWord_last <= RF_RecvWord;
|
||||
end
|
||||
else begin // hold otherwise
|
||||
RF_temperature[7:0] <= RF_temperature[7:0];
|
||||
RF_IFlocked[7:0] <= RF_IFlocked[7:0] ;
|
||||
RF_RFAlocked[7:0] <= RF_RFAlocked[7:0] ;
|
||||
RF_RFBlocked[7:0] <= RF_RFBlocked[7:0] ;
|
||||
RF_ch1mgc[3:0] <= RF_ch1mgc[3:0] ;
|
||||
RF_ch2mgc[3:0] <= RF_ch2mgc[3:0] ;
|
||||
RF_ch3mgc[3:0] <= RF_ch3mgc[3:0] ;
|
||||
RF_ch4mgc[3:0] <= RF_ch4mgc[3:0] ;
|
||||
RF_Framecount[31:0] <= RF_Framecount[31:0];
|
||||
RF_RecvWord_last <= RF_RecvWord_last;
|
||||
end
|
||||
end
|
||||
end
|
||||
// 天线的输出时钟转换
|
||||
reg Ant_dclk_96m = 1;
|
||||
wire [3:0] fifo_wr_din, fifo_rd_dout;
|
||||
wire fifo_full, fifo_empty;
|
||||
reg Ant_EN_96m = 0;
|
||||
reg Ant_DATA_96m = 0;
|
||||
reg Ant_DARY_96m = 1;
|
||||
reg Ant_TR_96m = 0;
|
||||
assign fifo_wr_din[3] = Ant_EN;
|
||||
assign fifo_wr_din[2] = Ant_DATA;
|
||||
assign fifo_wr_din[1] = Ant_DARY;
|
||||
assign fifo_wr_din[0] = Ant_TR;
|
||||
reg fifo_rd_en = 0;
|
||||
reg fifo_rst = 0;
|
||||
reg [8:0] Ant_clk_countdown = 0;
|
||||
always @(posedge clk_96m)
|
||||
begin
|
||||
fifo_rst <= sys_rst;
|
||||
|
||||
fifo_rd_en <= (fifo_rst == 1'b1)? 1'b0:!fifo_rd_en;
|
||||
|
||||
if(fifo_rd_en)
|
||||
{Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= fifo_rd_dout[3:0];
|
||||
else
|
||||
{Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= {Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m};
|
||||
|
||||
if(fifo_rd_en && Ant_EN_96m && !fifo_rd_dout[3])
|
||||
Ant_clk_countdown[8:0] <= 9'd276;
|
||||
else if(Ant_clk_countdown[8:0] != 9'd0)
|
||||
Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0] - 9'd1;
|
||||
else
|
||||
Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0];
|
||||
end
|
||||
assign ant_clk = !Ant_clk_countdown[0];
|
||||
assign ant_en = Ant_EN_96m;
|
||||
assign ant_data = Ant_DATA_96m;
|
||||
assign ant_tr = Ant_TR_96m;
|
||||
assign ant_dary = Ant_DARY_96m;
|
||||
|
||||
fifo_AntCtrl fifo_AntCtrl
|
||||
(
|
||||
.rst (fifo_rst ), // input wire rst
|
||||
.wr_clk (clk_48m ), // input wire wr_clk
|
||||
.rd_clk (clk_96m ), // input wire rd_clk
|
||||
.din (fifo_wr_din[3:0] ), // input wire [3 : 0] din
|
||||
.wr_en (!fifo_rst ), // input wire wr_en
|
||||
.rd_en (fifo_rd_en ), // input wire rd_en
|
||||
.dout (fifo_rd_dout[3:0] ), // output wire [3 : 0] dout
|
||||
.full (fifo_full ), // output wire full
|
||||
.empty (fifo_empty ) // output wire empty
|
||||
);
|
||||
//Ant recv_data
|
||||
reg [1:0] state_antdata;
|
||||
reg Ant_EN_96m_d1 = 1'b0;
|
||||
reg [15:0] cnt_antdata = 16'd0;
|
||||
reg [127:0] Ant_RecvWord = 128'b0;
|
||||
reg [127:0] Ant_RecvWord_last = 128'b0;
|
||||
|
||||
reg [7:0] Ant_Ant_Volt = 8'd0 ;
|
||||
reg [7:0] Ant_RF_Volt = 8'd0 ;
|
||||
reg [7:0] Ant_IF_Volt = 8'd0 ;
|
||||
reg [7:0] Ant_state = 8'd0 ;
|
||||
reg [31:0] Ant_Framecount = 32'd0 ;
|
||||
|
||||
always @ (posedge clk_96m) begin
|
||||
if(sys_rst) begin
|
||||
state_antdata[1:0] <= 2'd0;
|
||||
Ant_EN_96m_d1 <= 1'b0;
|
||||
Ant_RecvWord[127:0] <= 128'd0;
|
||||
cnt_antdata[15:0] <= 16'd0;
|
||||
Ant_Ant_Volt[7:0] <= 8'd0 ;
|
||||
Ant_RF_Volt[7:0] <= 8'd0 ;
|
||||
Ant_IF_Volt[7:0] <= 8'd0 ;
|
||||
Ant_state[7:0] <= 8'd0 ;
|
||||
Ant_Framecount[31:0] <= 32'd0;
|
||||
Ant_RecvWord_last[127:0] <= 128'd0;
|
||||
end
|
||||
else begin
|
||||
if(!ant_clk) begin
|
||||
Ant_RecvWord[127:0] <= {Ant_RecvWord[126:0],ant_dout};
|
||||
end
|
||||
else begin
|
||||
Ant_RecvWord[127:0] <= Ant_RecvWord[127:0];
|
||||
end
|
||||
|
||||
if(Ant_RecvWord[127:120] == 8'hAA && Ant_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾
|
||||
Ant_Ant_Volt[7:0] <= Ant_RecvWord[119:112];
|
||||
Ant_RF_Volt[7:0] <= Ant_RecvWord[111:104];
|
||||
Ant_IF_Volt[7:0] <= Ant_RecvWord[103:96];
|
||||
Ant_state[7:0] <= Ant_RecvWord[47:40];
|
||||
Ant_Framecount[31:0] <= Ant_RecvWord[39:8] ;
|
||||
Ant_RecvWord_last[127:0] <= Ant_RecvWord[127:0];
|
||||
end
|
||||
else begin // hold otherwise
|
||||
Ant_Ant_Volt[7:0] <= Ant_Ant_Volt[7:0] ;
|
||||
Ant_RF_Volt[7:0] <= Ant_RF_Volt[7:0] ;
|
||||
Ant_IF_Volt[7:0] <= Ant_IF_Volt[7:0] ;
|
||||
Ant_state[7:0] <= Ant_state[7:0] ;
|
||||
Ant_Framecount[31:0] <= Ant_Framecount[31:0] ;
|
||||
Ant_RecvWord_last[127:0] <= Ant_RecvWord_last[127:0];
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
Sisyif uut(
|
||||
.clk_40m(clk_32m),
|
||||
.clk_20m(clk_19p2m),
|
||||
.SPI_CLK_F(clk_48m),
|
||||
.rst_n(rst_n),
|
||||
.SPI_SYN_F(SPI_SYN_F),
|
||||
.SPI_MOSI_F(SPI_MOSI_F),
|
||||
.SPI_MISO_F(SPI_MISO_F),
|
||||
.TP_EN_F(TP_EN_F),
|
||||
.TR_MGC_F(TR_MGC_F),
|
||||
.CAL_F(CAL_F),
|
||||
.PRF(PRF),
|
||||
.standby(rf_standby),
|
||||
.SW_PLL(rf_sw_pll),
|
||||
.T(rf_t),
|
||||
.R(rf_r),
|
||||
.SW_BPF(rf_sw_bpf),
|
||||
.SCLK1(rf_sclk1),
|
||||
.SDIO1(rf_sdio1),
|
||||
.CS1(rf_cs1),
|
||||
.LD1(rf_ld1),
|
||||
.SCLK2(rf_sclk2),
|
||||
.SDIO2(rf_sdio2),
|
||||
.CS2(rf_cs2),
|
||||
.LD2(rf_ld2),
|
||||
.SCLK3(rf_sclk3),
|
||||
.SDIO3(rf_sdio3),
|
||||
.CS3(rf_cs3),
|
||||
.LD3(rf_ld3),
|
||||
.TMGC_16db(rf_tmgc_16),
|
||||
.TMGC_8db(rf_tmgc_8),
|
||||
.TMGC_4db(rf_tmgc_4),
|
||||
.TMGC_2db(rf_tmgc_2),
|
||||
.TMGC_1db(rf_tmgc_1),
|
||||
.RMGC_16db(rf_rmgc_16),
|
||||
.RMGC_8db(rf_rmgc_8),
|
||||
.RMGC_4db(rf_rmgc_4),
|
||||
.RMGC_2db(rf_rmgc_2),
|
||||
.RMGC_1db(rf_rmgc_1),
|
||||
.ENABLE(rf_enable),
|
||||
.SC(rf_sc),
|
||||
.SD(rf_sd),
|
||||
.END_SYN(rf_endsyn),
|
||||
.SDOUT(rf_sdout),
|
||||
.DQ_WD(rf_dq_wd),
|
||||
.SW_RX(rf_sw_rx)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,133 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/11/01 11:15:25
|
||||
// Design Name:
|
||||
// Module Name: clk_dist
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: Clock distribution module
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module clk_dist
|
||||
(
|
||||
// input clocks
|
||||
input clk_250m_p , // generated by ad9516, 250mhz
|
||||
input clk_250m_n ,
|
||||
input ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
|
||||
input ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
|
||||
|
||||
// output clocks & reset
|
||||
// global reset
|
||||
output sys_rst , // global reset signal, active high
|
||||
output ant_rst , // phased-array & rf control reset signal, active high
|
||||
|
||||
// pl signal processing clock
|
||||
output sys_clk , // 41.6667mhz
|
||||
output sys_clk_2x , // 83.3333mhz
|
||||
output sys_clk_3x , // 125mhz
|
||||
output sys_clk_4x , // 166.6667mhz
|
||||
output sys_clk_ld , // system main clock locked indicator
|
||||
|
||||
// ad9361-1 clocks
|
||||
output ad9361_1_clk , // 41.6667mhz
|
||||
output ad9361_1_clk_2x , // 83.3333mhz
|
||||
output ad9361_1_clk_3x , // 125mhz
|
||||
output ad9361_1_clk_4x , // 166.6667mhz
|
||||
output ad9361_1_clk_ld , // ad9361-1 clock group locked indicator
|
||||
|
||||
// ad9361-2 clocks
|
||||
output ad9361_2_clk , // 41.6667mhz
|
||||
output ad9361_2_clk_2x , // 83.3333mhz
|
||||
output ad9361_2_clk_3x , // 125mhz
|
||||
output ad9361_2_clk_4x , // 166.6667mhz
|
||||
output ad9361_2_clk_ld , // ad9361-2 clock group locked indicator
|
||||
|
||||
// phased-array & rf control clocks
|
||||
output clk_96m ,
|
||||
output clk_48m ,
|
||||
output clk_32m ,
|
||||
output clk_19p2m
|
||||
);
|
||||
|
||||
assign sys_clk = ad9361_1_clk ;
|
||||
assign sys_clk_2x = ad9361_1_clk_2x;
|
||||
assign sys_clk_3x = ad9361_1_clk_3x;
|
||||
assign sys_clk_4x = ad9361_1_clk_4x;
|
||||
assign sys_clk_ld = ad9361_1_clk_ld;
|
||||
|
||||
assign sys_rst = ~sys_clk_ld;
|
||||
|
||||
ad9361_clk_gen_cmos_2t2r u_ad9361_1_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ad9361_1_clk ), // output clk_out1
|
||||
.clk_out2 (ad9361_1_clk_2x ), // output clk_out2
|
||||
.clk_out3 (ad9361_1_clk_3x ), // output clk_out3
|
||||
.clk_out4 (ad9361_1_clk_4x ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ad9361_1_clk_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ad9361_1_rx_data_clk ) // input clk_in1
|
||||
);
|
||||
|
||||
ad9361_clk_gen_cmos_2t2r u_ad9361_2_clk_gen
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ad9361_2_clk ), // output clk_out1
|
||||
.clk_out2 (ad9361_2_clk_2x ), // output clk_out2
|
||||
.clk_out3 (ad9361_2_clk_3x ), // output clk_out3
|
||||
.clk_out4 (ad9361_2_clk_4x ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ad9361_2_clk_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ad9361_2_rx_data_clk ) // input clk_in1
|
||||
);
|
||||
|
||||
wire ant_clk_stg1_96m;
|
||||
wire ant_clk_stg1_ld;
|
||||
wire ant_clk_stg2_ld;
|
||||
|
||||
assign ant_rst = ~ant_clk_stg2_ld;
|
||||
|
||||
ant_clk_gen_stg1 u_ant_clk_gen_stg1
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (ant_clk_stg1_96m ), // output clk_out1
|
||||
// Status and control signals
|
||||
.locked (ant_clk_stg1_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1_p (clk_250m_p ), // input clk_in1_p
|
||||
.clk_in1_n (clk_250m_n ) // input clk_in1_n
|
||||
);
|
||||
|
||||
ant_clk_gen_stg2 u_ant_clk_gen_stg2
|
||||
(
|
||||
// Clock out ports
|
||||
.clk_out1 (clk_96m ), // output clk_out1
|
||||
.clk_out2 (clk_48m ), // output clk_out2
|
||||
.clk_out3 (clk_32m ), // output clk_out3
|
||||
.clk_out4 (clk_19p2m ), // output clk_out4
|
||||
// Status and control signals
|
||||
.locked (ant_clk_stg2_ld ), // output locked
|
||||
// Clock in ports
|
||||
.clk_in1 (ant_clk_stg1_96m ) // input clk_in1
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,161 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 04/25/2023 05:53:44 PM
|
||||
// Design Name:
|
||||
// Module Name: rx_dmf
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module rx_dmf
|
||||
#(
|
||||
DATA_I_WIDTH = 12,
|
||||
DATA_O_WIDTH = 19,
|
||||
CHANNEL_NUM = 4,
|
||||
PEAK_WIDTH = DATA_O_WIDTH,
|
||||
PRBS_LEN = 128
|
||||
)
|
||||
(
|
||||
input clk ,
|
||||
input rst ,
|
||||
|
||||
input din_valid ,
|
||||
input [DATA_I_WIDTH*CHANNEL_NUM-1 : 0] din_real ,
|
||||
input [DATA_I_WIDTH*CHANNEL_NUM-1 : 0] din_imag ,
|
||||
|
||||
output dout_valid ,
|
||||
input [DATA_O_WIDTH*CHANNEL_NUM-1 : 0] dout_real,
|
||||
input [DATA_O_WIDTH*CHANNEL_NUM-1 : 0] dout_imag,
|
||||
|
||||
output [$clog2(PRBS_LEN)-1 : 0] peak_index ,
|
||||
output [PEAK_WIDTH-1 : 0] peak_value_i ,
|
||||
output [PEAK_WIDTH-1 : 0] peak_value_q ,
|
||||
output peak_valid
|
||||
);
|
||||
|
||||
localparam FIR_I_WIDTH = 12;
|
||||
localparam FIR_O_WIDTH = 19;
|
||||
|
||||
localparam AXIS_FIR_I_WIDTH = 8*((FIR_I_WIDTH-1)/8+1);
|
||||
localparam AXIS_FIR_O_WIDTH = 8*((FIR_O_WIDTH-1)/8+1);
|
||||
|
||||
genvar m;
|
||||
|
||||
//
|
||||
wire [AXIS_FIR_I_WIDTH-1 : 0] din_real_array [0 : CHANNEL_NUM-1];
|
||||
wire [AXIS_FIR_I_WIDTH-1 : 0] din_imag_array [0 : CHANNEL_NUM-1];
|
||||
|
||||
generate
|
||||
for(m = 0; m < CHANNEL_NUM; m = m + 1) begin: array_convert_in
|
||||
|
||||
if (AXIS_FIR_I_WIDTH > DATA_I_WIDTH) begin
|
||||
// sign extension to fit 8-bit axis data format
|
||||
assign din_real_array[m] = {{(AXIS_FIR_I_WIDTH-DATA_I_WIDTH){din_real[(m+1)*DATA_I_WIDTH-1]}},din_real[m*DATA_I_WIDTH +: DATA_I_WIDTH]};
|
||||
assign din_imag_array[m] = {{(AXIS_FIR_I_WIDTH-DATA_I_WIDTH){din_imag[(m+1)*DATA_I_WIDTH-1]}},din_imag[m*DATA_I_WIDTH +: DATA_I_WIDTH]};
|
||||
end
|
||||
else begin
|
||||
// truncate msb
|
||||
assign din_real_array[m] = din_real[(m+1)*DATA_I_WIDTH-1 -: AXIS_FIR_I_WIDTH];
|
||||
assign din_imag_array[m] = din_imag[(m+1)*DATA_I_WIDTH-1 -: AXIS_FIR_I_WIDTH];
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// fir
|
||||
wire [AXIS_FIR_O_WIDTH-1 : 0] dmf_real_array [0 : CHANNEL_NUM-1];
|
||||
wire [AXIS_FIR_O_WIDTH-1 : 0] dmf_imag_array [0 : CHANNEL_NUM-1];
|
||||
|
||||
generate
|
||||
for(m = 0; m < CHANNEL_NUM; m = m + 1) begin: dmf
|
||||
|
||||
// port definition
|
||||
wire s_axis_data_tvalid_i;
|
||||
wire s_axis_data_tready_i;
|
||||
wire [AXIS_FIR_I_WIDTH-1 : 0] s_axis_data_tdata_i ;
|
||||
wire m_axis_data_tvalid_i;
|
||||
wire [AXIS_FIR_O_WIDTH-1 : 0] m_axis_data_tdata_i ;
|
||||
|
||||
wire s_axis_data_tvalid_q;
|
||||
wire s_axis_data_tready_q;
|
||||
wire [AXIS_FIR_I_WIDTH-1 : 0] s_axis_data_tdata_q ;
|
||||
wire m_axis_data_tvalid_q;
|
||||
wire [AXIS_FIR_O_WIDTH-1 : 0] m_axis_data_tdata_q ;
|
||||
|
||||
// port connection
|
||||
assign s_axis_data_tvalid_i = din_valid;
|
||||
assign s_axis_data_tdata_i = din_real_array[m];
|
||||
assign dmf_real_array[m] = m_axis_data_tdata_i;
|
||||
|
||||
assign s_axis_data_tvalid_q = din_valid;
|
||||
assign s_axis_data_tdata_q = din_imag_array[m];
|
||||
assign dmf_imag_array[m] = m_axis_data_tdata_q;
|
||||
|
||||
// ip core instantiation
|
||||
fir_dmf_invert_prbs7_deci8 u_dmf_i
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (s_axis_data_tvalid_i ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready (s_axis_data_tready_i ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (s_axis_data_tdata_i ), // input wire [15 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid (m_axis_data_tvalid_i ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (m_axis_data_tdata_i ) // output wire [23 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
fir_dmf_invert_prbs7_deci8 u_dmf_q
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_data_tvalid (s_axis_data_tvalid_q ), // input wire s_axis_data_tvalid
|
||||
.s_axis_data_tready (s_axis_data_tready_q ), // output wire s_axis_data_tready
|
||||
.s_axis_data_tdata (s_axis_data_tdata_q ), // input wire [15 : 0] s_axis_data_tdata
|
||||
.m_axis_data_tvalid (m_axis_data_tvalid_q ), // output wire m_axis_data_tvalid
|
||||
.m_axis_data_tdata (m_axis_data_tdata_q ) // output wire [23 : 0] m_axis_data_tdata
|
||||
);
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// output data
|
||||
wire [DATA_O_WIDTH-1 : 0] dout_real_array [0 : CHANNEL_NUM-1];
|
||||
wire [DATA_O_WIDTH-1 : 0] dout_imag_array [0 : CHANNEL_NUM-1];
|
||||
|
||||
generate
|
||||
for(m = 0; m < CHANNEL_NUM; m = m + 1) begin: array_convert_out
|
||||
|
||||
if (DATA_O_WIDTH > FIR_O_WIDTH) begin
|
||||
// append zeros
|
||||
assign dout_real_array[m] = {dmf_real_array[m],{(FIR_O_WIDTH-DATA_O_WIDTH){1'b0}}};
|
||||
assign dout_imag_array[m] = {dmf_imag_array[m],{(FIR_O_WIDTH-DATA_O_WIDTH){1'b0}}};
|
||||
end
|
||||
else begin
|
||||
// truncate msb
|
||||
assign dout_real_array[m] = dmf_real_array[m][(m+1)*FIR_O_WIDTH-1 -: DATA_O_WIDTH];
|
||||
assign dout_imag_array[m] = dmf_imag_array[m][(m+1)*FIR_O_WIDTH-1 -: DATA_O_WIDTH];
|
||||
end
|
||||
|
||||
assign dout_real[m*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_real_array[m];
|
||||
assign dout_imag[m*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_imag_array[m];
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign dout_valid = dmf[0].m_axis_data_tvalid_i;
|
||||
|
||||
// peak record
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,426 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/11/06 15:24:48
|
||||
// Design Name:
|
||||
// Module Name: accor_mat_formatting
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: Formmat the input complex matrix to 1-bit stream.
|
||||
// Parameter:
|
||||
// ROW_NUM: Row number of input matrix.
|
||||
// COL_NUM: Column number of input matrix.
|
||||
// DATA_I_WIDTH: Bit width of input matrix element.
|
||||
// FRAME_HEAD: Frame head indicate autocorrelation matrix frame.
|
||||
// Data format:
|
||||
// din_valid: Indicate [din_real/imag] data are valid.
|
||||
// din_real/imag: Suppose the input matrix x = [x11 x12; x21 x22], then
|
||||
// din_real = {Re{x22}, Re{x21}, Re{x12}, Re{x11}}
|
||||
// din_imag = {Im{x22}, Im{x21}, Im{x12}, Im{x11}}
|
||||
// dout_valid: Indicate [dout_data] is valid. The latency is set to 2 clock
|
||||
// cycles by default.
|
||||
// dout_data:
|
||||
// dout_data = {FRAME_HEAD[msb], ..., FRAME_HEAD[lsb], FRAME_LEN[msb],
|
||||
// ..., FRAME_LEN[lsb], Re{x11}[msb], ..., Re{x11}[lsb], Im{x11}[msb], ...,
|
||||
// Im{x11}[lsb], ..., Re{x12}[msb], ......, Im{x22}[lsb]}
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module accor_mat_formatting
|
||||
#(
|
||||
parameter ROW_NUM = 4,
|
||||
parameter COL_NUM = 4,
|
||||
parameter DATA_I_WIDTH = 32,
|
||||
parameter FRAME_HEAD = 32'h7E7E7E7E
|
||||
)
|
||||
(
|
||||
// clock & reset
|
||||
input sys_clk,
|
||||
input sys_rst,
|
||||
input clk_96m,
|
||||
input ant_rst,
|
||||
|
||||
// input data
|
||||
input din_valid,
|
||||
input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1 : 0] din_real,
|
||||
input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1 : 0] din_imag,
|
||||
input fifo_cdc_rst,
|
||||
|
||||
// output data
|
||||
output dout_valid,
|
||||
output dout_data
|
||||
);
|
||||
|
||||
localparam CMPLX_DIM = 2;
|
||||
localparam FRAME_LEN = ROW_NUM*COL_NUM*CMPLX_DIM; // 32-bit data number per frame
|
||||
localparam BYTE_LEN = 4 * (ROW_NUM*COL_NUM*CMPLX_DIM + 2); // byte number per frame, plus frame head and frame length
|
||||
|
||||
// available state
|
||||
localparam STATE_NUM = 4;
|
||||
localparam STATE_IDLE = 0;
|
||||
localparam STATE_HEAD = 1;
|
||||
localparam STATE_LEN = 2;
|
||||
localparam STATE_DATA = 3;
|
||||
|
||||
genvar i;
|
||||
integer m;
|
||||
|
||||
// format input data to array
|
||||
wire [DATA_I_WIDTH-1 : 0] din_array [0 : ROW_NUM*COL_NUM*CMPLX_DIM-1];
|
||||
reg [DATA_I_WIDTH-1 : 0] din_array_cdc [0 : ROW_NUM*COL_NUM*CMPLX_DIM-1];
|
||||
|
||||
generate
|
||||
for (i = 0; i < ROW_NUM*COL_NUM; i = i + 1) begin: input_mat_reshape
|
||||
assign din_array[i*2] = din_real[i*DATA_I_WIDTH +: DATA_I_WIDTH];
|
||||
assign din_array[i*2+1] = din_imag[i*DATA_I_WIDTH +: DATA_I_WIDTH];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// clock domain crossing fifo, write channel
|
||||
reg fifo_wr_start = 'b0;
|
||||
reg fifo_wr_en = 'b0;
|
||||
reg [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM)-1 : 0] fifo_wr_cnt = 'b0;
|
||||
reg [DATA_I_WIDTH-1 : 0] fifo_din = 'b0;
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
fifo_wr_start <= 'b0;
|
||||
end
|
||||
else if (din_valid) begin
|
||||
fifo_wr_start <= 1'b1;
|
||||
end
|
||||
else if (fifo_wr_cnt == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
|
||||
fifo_wr_start <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
fifo_wr_start <= fifo_wr_start;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
fifo_wr_en <= 'b0;
|
||||
fifo_wr_cnt <= 'b0;
|
||||
fifo_din <= 'b0;
|
||||
end
|
||||
else if (fifo_wr_start) begin
|
||||
fifo_wr_en <= 1'b1;
|
||||
fifo_wr_cnt <= fifo_wr_cnt + 1'b1;
|
||||
fifo_din <= din_array[fifo_wr_cnt];
|
||||
end
|
||||
else begin
|
||||
fifo_wr_en <= 'b0;
|
||||
fifo_wr_cnt <= 'b0;
|
||||
fifo_din <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// clock domain crossing fifo, read channel
|
||||
reg fifo_rd_en = 'b0;
|
||||
reg fifo_rd_en_d1 = 'b0;
|
||||
reg [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt = 'b0;
|
||||
reg [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt_d1 = 'b0; // read data latency
|
||||
reg fifo_rd_valid = 'b0;
|
||||
wire [DATA_I_WIDTH-1 : 0] fifo_dout;
|
||||
wire [$clog2(ROW_NUM*COL_NUM*CMPLX_DIM*2)-1 : 0] fifo_rd_num;
|
||||
wire fifo_full;
|
||||
wire fifo_empty;
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
fifo_rd_en <= 'b0;
|
||||
end
|
||||
else if (fifo_rd_num == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
|
||||
fifo_rd_en <= 1'b1;
|
||||
end
|
||||
else if (fifo_rd_cnt == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
|
||||
fifo_rd_en <= 'b0;
|
||||
end
|
||||
else begin
|
||||
fifo_rd_en <= fifo_rd_en;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
fifo_rd_en_d1 <= 'b0;
|
||||
end
|
||||
else begin
|
||||
fifo_rd_en_d1 <= fifo_rd_en;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
fifo_rd_cnt <= 'b0;
|
||||
end
|
||||
else if (fifo_rd_en) begin
|
||||
fifo_rd_cnt <= fifo_rd_cnt + 1'b1;
|
||||
end
|
||||
else begin
|
||||
fifo_rd_cnt <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
fifo_rd_cnt_d1 <= 'b0;
|
||||
end
|
||||
else begin
|
||||
fifo_rd_cnt_d1 <= fifo_rd_cnt;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
fifo_rd_valid <= 'b0;
|
||||
end
|
||||
else if (fifo_rd_cnt_d1 == ROW_NUM*COL_NUM*CMPLX_DIM-1) begin
|
||||
fifo_rd_valid <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
fifo_rd_valid <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
for (m = 0; m < ROW_NUM*COL_NUM*CMPLX_DIM; m = m + 1) begin
|
||||
din_array_cdc[m] <= 'b0;
|
||||
end
|
||||
end
|
||||
else if (fifo_rd_en_d1) begin
|
||||
din_array_cdc[fifo_rd_cnt_d1] <= fifo_dout;
|
||||
end
|
||||
else begin
|
||||
for (m = 0; m < ROW_NUM*COL_NUM*CMPLX_DIM; m = m + 1) begin
|
||||
din_array_cdc[m] <= din_array_cdc[m];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// clock domain crossing fifo, interface
|
||||
fifo_accor_cdc u_fifo_accor_cdc
|
||||
(
|
||||
.rst (fifo_cdc_rst ), // input wire wr_rst
|
||||
.wr_clk (sys_clk ), // input wire wr_clk
|
||||
.rd_clk (clk_96m ), // input wire rd_clk
|
||||
.din (fifo_din ), // input wire [31 : 0] din
|
||||
.wr_en (fifo_wr_en ), // input wire wr_en
|
||||
.rd_en (fifo_rd_en ), // input wire rd_en
|
||||
.dout (fifo_dout ), // output wire [31 : 0] dout
|
||||
.full (fifo_full ), // output wire full
|
||||
.empty (fifo_empty ), // output wire empty
|
||||
.rd_data_count (fifo_rd_num ) // output wire [5 : 0] rd_data_count
|
||||
);
|
||||
|
||||
// center state machine & counter
|
||||
reg [$clog2(STATE_NUM)-1 : 0] state = STATE_IDLE;
|
||||
reg [$clog2(DATA_I_WIDTH)-1 : 0] bit_cnt = 'b0; // bit counter within one frame
|
||||
reg [$clog2(FRAME_LEN)-1 : 0] frame_cnt = 'b0; // frame counter
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
state <= STATE_IDLE;
|
||||
end
|
||||
else begin
|
||||
case (state)
|
||||
STATE_IDLE: state <= fifo_rd_valid ? STATE_HEAD : STATE_IDLE;
|
||||
STATE_HEAD: state <= (bit_cnt == DATA_I_WIDTH-1) ? STATE_LEN : STATE_HEAD;
|
||||
STATE_LEN : state <= (bit_cnt == DATA_I_WIDTH-1) ? STATE_DATA : STATE_LEN;
|
||||
STATE_DATA: state <= (frame_cnt == FRAME_LEN-1 && bit_cnt == DATA_I_WIDTH-1) ? STATE_IDLE : STATE_DATA;
|
||||
default: state <= STATE_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
bit_cnt <= 'b0;
|
||||
end
|
||||
else if (state == STATE_IDLE) begin
|
||||
bit_cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
bit_cnt <= (bit_cnt == DATA_I_WIDTH-1) ? 'b0 : bit_cnt + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
frame_cnt <= 'b0;
|
||||
end
|
||||
else if (state == STATE_IDLE) begin
|
||||
frame_cnt <= 'b0;
|
||||
end
|
||||
else if (state == STATE_DATA && bit_cnt == DATA_I_WIDTH-1) begin
|
||||
frame_cnt <= frame_cnt + 1'b1;
|
||||
end
|
||||
else begin
|
||||
frame_cnt <= frame_cnt;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// output data
|
||||
reg dout_valid_buf = 'b0;
|
||||
reg dout_data_buf = 'b0;
|
||||
|
||||
assign dout_valid = dout_valid_buf;
|
||||
assign dout_data = dout_data_buf;
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
dout_valid_buf <= 'b0;
|
||||
dout_data_buf <= 'b0;
|
||||
end
|
||||
else case (state)
|
||||
STATE_IDLE: begin dout_valid_buf <= 'b0 ; dout_data_buf <= 'b0; end
|
||||
STATE_HEAD: begin dout_valid_buf <= 1'b1; dout_data_buf <= FRAME_HEAD[DATA_I_WIDTH-1 - bit_cnt]; end
|
||||
STATE_LEN : begin dout_valid_buf <= 1'b1; dout_data_buf <= BYTE_LEN[DATA_I_WIDTH-1 - bit_cnt]; end
|
||||
STATE_DATA: begin dout_valid_buf <= 1'b1; dout_data_buf <= din_array_cdc[frame_cnt][DATA_I_WIDTH-1 - bit_cnt]; end
|
||||
default: begin dout_valid_buf <= 'b0 ; dout_data_buf <= 'b0; end
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/10/30 20:46:26
|
||||
// Design Name:
|
||||
// Module Name: tb_accum
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: Testbench for [accor_mat_formatting]
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// -------------------------------
|
||||
// MATLAB Code for data generation
|
||||
// -------------------------------
|
||||
// COLUMN_NUM = 4;
|
||||
// DATA_I_WIDTH = 12;
|
||||
// ACC_NUM = 10;
|
||||
|
||||
// rng(0);
|
||||
// data = rand(4,2)*2-1;
|
||||
// d_12b = round(data.*(2^(DATA_I_WIDTH-1)-1));
|
||||
// d_12b_cmplx = d_12b(:,1) + 1i*d_12b(:,2);
|
||||
// d_12b_cmplx = d_12b_cmplx(end:-1:1,:);
|
||||
// d_12b_acorr = d_12b_cmplx*d_12b_cmplx';
|
||||
// d_12b_acorr_real_sim = reshape(flip(reshape(real(d_12b_acorr)',1,16)),4,4);
|
||||
// d_12b_acorr_imag_sim = reshape(flip(reshape(imag(d_12b_acorr)',1,16)),4,4);
|
||||
// d_12b_acorr_real_sim_sum = ACC_NUM*d_12b_acorr_real_sim;
|
||||
// d_12b_acorr_imag_sim_sum = ACC_NUM*d_12b_acorr_imag_sim;
|
||||
|
||||
|
||||
// module tb_accor_format;
|
||||
|
||||
// localparam DATA_I_WIDTH = 32;
|
||||
// localparam ROW_NUM = 4;
|
||||
// localparam COL_NUM = 4;
|
||||
|
||||
// reg sys_clk = 1'b1;
|
||||
// reg sys_rst = 1'b1;
|
||||
// reg clk_96m = 1'b1;
|
||||
// reg ant_rst = 1'b1;
|
||||
// reg din_valid = 'b0;
|
||||
// reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = 'b0, din_imag = 'b0;
|
||||
|
||||
// wire dout_valid;
|
||||
// wire dout_data;
|
||||
|
||||
// accor_mat_formatting #(
|
||||
// .ROW_NUM (ROW_NUM),
|
||||
// .COL_NUM (COL_NUM),
|
||||
// .DATA_I_WIDTH (DATA_I_WIDTH)
|
||||
// ) u_accor_mat_formatting
|
||||
// (
|
||||
// // clock & reset
|
||||
// .sys_clk (sys_clk ), // input sys_clk
|
||||
// .sys_rst (sys_rst ), // input sys_rst
|
||||
// .clk_96m (clk_96m ), // input clk_96m
|
||||
// .ant_rst (ant_rst ), // input ant_rst
|
||||
|
||||
// // input data
|
||||
// .din_valid (din_valid ),
|
||||
// .din_real (din_real ),
|
||||
// .din_imag (din_imag ),
|
||||
|
||||
// // output data
|
||||
// .dout_valid (dout_valid ),
|
||||
// .dout_data (dout_data )
|
||||
// );
|
||||
|
||||
|
||||
// initial begin
|
||||
// #102
|
||||
// sys_rst = 1'b0;
|
||||
// ant_rst = 1'b0;
|
||||
|
||||
// #222;
|
||||
// @(posedge sys_clk)
|
||||
// din_valid = 1'b1;
|
||||
// din_real = {
|
||||
// 32'd1952708, 32'd1246152, -32'd2458370, 32'd2283360,
|
||||
// 32'd1246152, 32'd5474825, -32'd1041611, 32'd2493996,
|
||||
// -32'd2458370, -32'd1041611, 32'd3154378, -32'd2757828,
|
||||
// 32'd2283360, 32'd2493996, -32'd2757828, 32'd2899728
|
||||
// };
|
||||
|
||||
// din_imag = {
|
||||
// 32'd1, -32'd3022886, -32'd340582, -32'd669768,
|
||||
// 32'd3022886, 32'd2, -32'd4023023, 32'd3107328,
|
||||
// 32'd340582, 32'd4023023, 32'd3, 32'd1241460,
|
||||
// 32'd669768, -32'd3107328, -32'd1241460, 32'd4
|
||||
// };
|
||||
|
||||
// @(posedge sys_clk)
|
||||
// din_valid = 1'b0;
|
||||
|
||||
// end
|
||||
|
||||
// always begin
|
||||
// #20 sys_clk = ~sys_clk;
|
||||
// end
|
||||
|
||||
// always begin
|
||||
// #7;
|
||||
// clk_96m = ~clk_96m;
|
||||
// #3;
|
||||
// end
|
||||
|
||||
|
||||
// endmodule
|
||||
@@ -0,0 +1,332 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/11/02 11:06:43
|
||||
// Design Name:
|
||||
// Module Name: accum_cmplx_mat
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions: 2019.1.3
|
||||
// Description: Compute the accumulation of complex matrices. The row number
|
||||
// [ROW_NUM] and column number [ROW_NUM] are flexible parameters. The
|
||||
// accumulation number [ACC_NUM], input data width [DATA_I_WIDTH] and output
|
||||
// data width [DATA_ACC_WIDTH] are related to each other and should match the
|
||||
// Adder/Subtracter LogiCORE IP configuration.
|
||||
// Parameter:
|
||||
// ROW_NUM: Row number of input matrix.
|
||||
// COL_NUM: Column number of input matrix.
|
||||
// ACC_NUM: Accumulation number of input matrix.
|
||||
// DATA_I_WIDTH: Bit width of input matrix element.
|
||||
// DATA_ACC_WIDTH: !!!Caution!!! Accumulation adder output data width. It is
|
||||
// determined by [DATA_I_WIDTH] and [ACC_NUM], and is calculated as
|
||||
// log2(ACC_NUM*(2^DATA_I_WIDTH-1)), and should match the Adder/Subtracter
|
||||
// LogiCORE IP configuration.
|
||||
// DATA_O_WIDTH: Bit width of output matrix element. If [DATA_O_WIDTH] <
|
||||
// [DATA_ACC_WIDTH], MSB of accumulation result will be truncated. If
|
||||
// [DATA_O_WIDTH] > [DATA_ACC_WIDTH], the sign bit of accumulation result
|
||||
// will be extended.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module accum_cmplx_mat
|
||||
#(
|
||||
parameter ROW_NUM = 4,
|
||||
parameter COL_NUM = 4,
|
||||
parameter ACC_NUM = 256,
|
||||
parameter DATA_I_WIDTH = 24,
|
||||
parameter DATA_ACC_WIDTH = $clog2(ACC_NUM*(2^DATA_I_WIDTH-1)),
|
||||
parameter DATA_O_WIDTH = 32
|
||||
)
|
||||
(
|
||||
// clock & reset
|
||||
input clk,
|
||||
input rst,
|
||||
input acc_rst, // [acc_rst] should assert before accumulation starts
|
||||
|
||||
// input data
|
||||
input din_valid,
|
||||
input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real,
|
||||
input [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_imag,
|
||||
|
||||
// output data
|
||||
output dout_valid,
|
||||
output [ROW_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real,
|
||||
output [ROW_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_imag
|
||||
);
|
||||
|
||||
genvar i;
|
||||
|
||||
// prepare adder input & output data
|
||||
wire [DATA_I_WIDTH-1:0] add_real_a_array [0:ROW_NUM*COL_NUM-1];
|
||||
wire [DATA_I_WIDTH-1:0] add_imag_a_array [0:ROW_NUM*COL_NUM-1];
|
||||
wire [DATA_ACC_WIDTH-1:0] add_real_b_array [0:ROW_NUM*COL_NUM-1];
|
||||
wire [DATA_ACC_WIDTH-1:0] add_imag_b_array [0:ROW_NUM*COL_NUM-1];
|
||||
wire [DATA_ACC_WIDTH-1:0] add_real_s_array [0:ROW_NUM*COL_NUM-1];
|
||||
wire [DATA_ACC_WIDTH-1:0] add_imag_s_array [0:ROW_NUM*COL_NUM-1];
|
||||
|
||||
generate
|
||||
for (i = 0; i < ROW_NUM*COL_NUM; i = i + 1) begin: cmplx_mat_accum
|
||||
assign add_real_a_array[i] = din_real[i*DATA_I_WIDTH +: DATA_I_WIDTH];
|
||||
assign add_imag_a_array[i] = din_imag[i*DATA_I_WIDTH +: DATA_I_WIDTH];
|
||||
|
||||
assign add_real_b_array[i] = add_real_s_array[i];
|
||||
assign add_imag_b_array[i] = add_imag_s_array[i];
|
||||
|
||||
if (ACC_NUM > 1) begin
|
||||
add_s24_s32_s32 u_accum_real
|
||||
(
|
||||
.A (add_real_a_array[i]), // input wire [23 : 0] A
|
||||
.B (add_real_b_array[i]), // input wire [31 : 0] B
|
||||
.CLK (clk ), // input wire CLK
|
||||
.CE (din_valid ), // input wire CE
|
||||
.SCLR (rst || acc_rst ), // input wire SCLR
|
||||
.S (add_real_s_array[i]) // output wire [31 : 0] S
|
||||
);
|
||||
|
||||
add_s24_s32_s32 u_accum_imag
|
||||
(
|
||||
.A (add_imag_a_array[i]), // input wire [23 : 0] A
|
||||
.B (add_imag_b_array[i]), // input wire [31 : 0] B
|
||||
.CLK (clk ), // input wire CLK
|
||||
.CE (din_valid ), // input wire CE
|
||||
.SCLR (rst || acc_rst ), // input wire SCLR
|
||||
.S (add_imag_s_array[i]) // output wire [31 : 0] S
|
||||
);
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// input data counter & full flag
|
||||
reg [$clog2(ACC_NUM)-1:0] accum_cnt = 'b0;
|
||||
reg accum_full_flag = 'b0;
|
||||
reg accum_full_flag_d = 'b0; // delay of [accum_full_flag]
|
||||
|
||||
if (ACC_NUM > 1) begin
|
||||
always @(posedge clk) begin
|
||||
if (rst || acc_rst) begin
|
||||
accum_cnt <= 'b0;
|
||||
end
|
||||
else if (din_valid) begin
|
||||
accum_cnt <= accum_cnt + 1'b1;
|
||||
end
|
||||
else begin
|
||||
accum_cnt <= accum_cnt;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst || acc_rst) begin
|
||||
accum_full_flag <= 'b0;
|
||||
end
|
||||
else begin
|
||||
accum_full_flag <= (accum_cnt == ACC_NUM - 1) ? 1'b1 : accum_full_flag;
|
||||
end
|
||||
|
||||
accum_full_flag_d <= accum_full_flag;
|
||||
end
|
||||
end
|
||||
|
||||
// output control
|
||||
reg dout_valid_buf;
|
||||
reg [DATA_O_WIDTH-1:0] dout_real_array [0:ROW_NUM*COL_NUM-1];
|
||||
reg [DATA_O_WIDTH-1:0] dout_imag_array [0:ROW_NUM*COL_NUM-1];
|
||||
|
||||
assign dout_valid = dout_valid_buf;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst || acc_rst) begin
|
||||
dout_valid_buf <= 'b0;
|
||||
end
|
||||
else begin
|
||||
if (ACC_NUM > 1) begin
|
||||
dout_valid_buf <= ~accum_full_flag_d & accum_full_flag;
|
||||
end
|
||||
else begin
|
||||
dout_valid_buf <= din_valid;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
generate
|
||||
for (i = 0; i < ROW_NUM*COL_NUM; i = i + 1) begin: output_buf
|
||||
assign dout_real[i*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_real_array[i];
|
||||
assign dout_imag[i*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_imag_array[i];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst || acc_rst) begin
|
||||
dout_real_array[i] <= 'b0;
|
||||
dout_imag_array[i] <= 'b0;
|
||||
end
|
||||
else begin
|
||||
if (ACC_NUM > 1) begin
|
||||
if (~accum_full_flag_d & accum_full_flag) begin
|
||||
if (DATA_O_WIDTH <= DATA_ACC_WIDTH) begin
|
||||
// truncate msb
|
||||
dout_real_array[i] <= add_real_s_array[i][DATA_ACC_WIDTH-1 -: DATA_O_WIDTH];
|
||||
dout_imag_array[i] <= add_imag_s_array[i][DATA_ACC_WIDTH-1 -: DATA_O_WIDTH];
|
||||
end
|
||||
else begin // if (ACC_NUM <= 1)
|
||||
// Sign extension to fit output data width
|
||||
dout_real_array[i] <= {{(DATA_O_WIDTH-DATA_ACC_WIDTH){add_real_s_array[i][DATA_ACC_WIDTH-1]}},add_real_s_array[i]};
|
||||
dout_imag_array[i] <= {{(DATA_O_WIDTH-DATA_ACC_WIDTH){add_imag_s_array[i][DATA_ACC_WIDTH-1]}},add_real_s_array[i]};
|
||||
end
|
||||
end
|
||||
else begin
|
||||
dout_real_array[i] <= dout_real_array[i];
|
||||
dout_imag_array[i] <= dout_imag_array[i];
|
||||
end
|
||||
end // if (ACC_NUM > 1)
|
||||
else begin // if (ACC_NUM <= 1)
|
||||
if (DATA_O_WIDTH <= DATA_I_WIDTH) begin
|
||||
// truncate msb
|
||||
dout_real_array[i] <= add_real_a_array[i][DATA_I_WIDTH-1 -: DATA_O_WIDTH];
|
||||
dout_imag_array[i] <= add_imag_a_array[i][DATA_I_WIDTH-1 -: DATA_O_WIDTH];
|
||||
end
|
||||
else begin // if (DATA_O_WIDTH > DATA_I_WIDTH)
|
||||
// Sign extension to fit output data width
|
||||
dout_real_array[i] <= {{(DATA_O_WIDTH-DATA_I_WIDTH){add_real_a_array[i][DATA_I_WIDTH-1]}},add_real_a_array[i]};
|
||||
dout_imag_array[i] <= {{(DATA_O_WIDTH-DATA_I_WIDTH){add_imag_a_array[i][DATA_I_WIDTH-1]}},add_imag_a_array[i]};
|
||||
end
|
||||
end // if (ACC_NUM <= 1)
|
||||
end
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/10/30 20:46:26
|
||||
// Design Name:
|
||||
// Module Name: tb_accum
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: Testbench for [accum_cmplx_mat]
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// -------------------------------
|
||||
// MATLAB Code for data generation
|
||||
// -------------------------------
|
||||
// COLUMN_NUM = 4;
|
||||
// DATA_I_WIDTH = 12;
|
||||
// ACC_NUM = 10;
|
||||
|
||||
// rng(0);
|
||||
// data = rand(4,2)*2-1;
|
||||
// d_12b = round(data.*(2^(DATA_I_WIDTH-1)-1));
|
||||
// d_12b_cmplx = d_12b(:,1) + 1i*d_12b(:,2);
|
||||
// d_12b_cmplx = d_12b_cmplx(end:-1:1,:);
|
||||
// d_12b_acorr = d_12b_cmplx*d_12b_cmplx';
|
||||
// d_12b_acorr_real_sim = reshape(flip(reshape(real(d_12b_acorr)',1,16)),4,4);
|
||||
// d_12b_acorr_imag_sim = reshape(flip(reshape(imag(d_12b_acorr)',1,16)),4,4);
|
||||
// d_12b_acorr_real_sim_sum = ACC_NUM*d_12b_acorr_real_sim;
|
||||
// d_12b_acorr_imag_sim_sum = ACC_NUM*d_12b_acorr_imag_sim;
|
||||
|
||||
|
||||
// module tb_accum;
|
||||
|
||||
// localparam DATA_I_WIDTH = 24;
|
||||
// localparam DATA_ACC_WIDTH = 32;
|
||||
// localparam DATA_O_WIDTH = 35;
|
||||
// localparam ROW_NUM = 4;
|
||||
// localparam COL_NUM = 4;
|
||||
|
||||
// reg acc_rst = 1'b0;
|
||||
|
||||
// reg clk = 1'b1;
|
||||
// reg rst = 1'b1;
|
||||
// reg din_valid = 'b0;
|
||||
// reg [ROW_NUM*COL_NUM*DATA_I_WIDTH-1:0] din_real = 'b0, din_imag = 'b0;
|
||||
|
||||
// wire dout_valid;
|
||||
// wire [ROW_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag;
|
||||
|
||||
// accum_cmplx_mat #(
|
||||
// .ROW_NUM (ROW_NUM),
|
||||
// .COL_NUM (COL_NUM),
|
||||
// .DATA_I_WIDTH (DATA_I_WIDTH),
|
||||
// .DATA_ACC_WIDTH (DATA_ACC_WIDTH),
|
||||
// .DATA_O_WIDTH (DATA_O_WIDTH),
|
||||
// .ACC_NUM (1)
|
||||
// ) u_accum_cmplx_mat
|
||||
// (
|
||||
// // clock & reset
|
||||
// .clk (clk ),
|
||||
// .rst (rst ),
|
||||
// .acc_rst (acc_rst ), // [acc_rst] should assert before accumulation starts
|
||||
|
||||
// // input data
|
||||
// .din_valid (din_valid ),
|
||||
// .din_real (din_real ),
|
||||
// .din_imag (din_imag ),
|
||||
|
||||
// // output data
|
||||
// .dout_valid (dout_valid ),
|
||||
// .dout_real (dout_real ),
|
||||
// .dout_imag (dout_imag )
|
||||
// );
|
||||
|
||||
|
||||
// initial begin
|
||||
// #102 rst = 1'b0;
|
||||
// #222;
|
||||
// @(posedge clk)
|
||||
// din_valid = 1'b1;
|
||||
// din_real = {
|
||||
// 24'd1952708, 24'd1246152, -24'd2458370, 24'd2283360,
|
||||
// 24'd1246152, 24'd5474825, -24'd1041611, 24'd2493996,
|
||||
// -24'd2458370, -24'd1041611, 24'd3154378, -24'd2757828,
|
||||
// 24'd2283360, 24'd2493996, -24'd2757828, 24'd2899728
|
||||
// };
|
||||
|
||||
// din_imag = {
|
||||
// 24'd0, -24'd3022886, -24'd340582, -24'd669768,
|
||||
// 24'd3022886, 24'd0, -24'd4023023, 24'd3107328,
|
||||
// 24'd340582, 24'd4023023, 24'd0, 24'd1241460,
|
||||
// 24'd669768, -24'd3107328, -24'd1241460, 24'd0
|
||||
// };
|
||||
|
||||
// #1002
|
||||
// acc_rst = 1'b1;
|
||||
// #20
|
||||
// acc_rst = 1'b0;
|
||||
|
||||
// end
|
||||
|
||||
// always #10 clk = ~clk;
|
||||
|
||||
|
||||
// endmodule
|
||||
@@ -0,0 +1,266 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/10/30 19:27:01
|
||||
// Design Name:
|
||||
// Module Name: acorr_cmplx_col_vec
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: Compute the autocorrelation of a complex column vector. The
|
||||
// computation is conducted in fully parallel style.
|
||||
// Parameter:
|
||||
// DATA_I_WIDTH: Bit width of input vector element, the same as of complex
|
||||
// multiplication input data.
|
||||
// DATA_MULT_FULL_WIDTH (local): Bit width of unsigned complex multiplication
|
||||
// output data (The cmpy LogiCore IP does not care whether the input data
|
||||
// are signed or unsigned). It equals to (2*[DATA_MULT_WIDTH]+1).
|
||||
// DATA_MULT_VALID_WIDTH (local): Bit width of signed complex multiplication.acc_rst
|
||||
// It equals to 2*[DATA_MULT_WIDTH].
|
||||
// DATA_O_WIDTH: Bit width of output matrix element. If [DATA_O_WIDTH] <
|
||||
// [DATA_MULT_WIDTH], MSB of valid complex mutiplication output will be
|
||||
// truncated. If [DATA_O_WIDTH] > [DATA_MULT_WIDTH], the sign bit of valid
|
||||
// complex mutiplication output will be extended.
|
||||
// Data format:
|
||||
// din_valid: Indicate [din_real/imag] data are valid.
|
||||
// din_real/imag: Suppose the input column vector x = [x1 x2 x3 x4]^T, then
|
||||
// din_real = {Re{x4}, Re{x3}, Re{x2}, Re{x1}}
|
||||
// din_imag = {Im{x4}, Im{x3}, Im{x2}, Im{x1}}
|
||||
// dout_valid: Indicate [dout_real/imag] data are valid. The latency is
|
||||
// determined by the configuration of the cmpy ip core, which is set to 6
|
||||
// clock cycles by default.
|
||||
// dout_real/imag:
|
||||
// dout_real = {Re{x4*x4^H}, Re{x4*x3^H}, ..., Re{x1*x2^H}, Re{x1*x1^H}}
|
||||
// dout_imag = {Im{x4*x4^H}, Im{x4*x3^H}, ..., Im{x1*x2^H}, Im{x1*x1^H}}
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module acorr_cmplx_col_vec
|
||||
#(
|
||||
parameter DATA_I_WIDTH = 12,
|
||||
parameter DATA_O_WIDTH = 24,
|
||||
parameter COL_NUM = 4
|
||||
)
|
||||
(
|
||||
// clock & reset
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
// input data
|
||||
input din_valid,
|
||||
input [COL_NUM*DATA_I_WIDTH-1:0] din_real,
|
||||
input [COL_NUM*DATA_I_WIDTH-1:0] din_imag,
|
||||
|
||||
// output data
|
||||
output dout_valid,
|
||||
output [COL_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real,
|
||||
output [COL_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_imag
|
||||
);
|
||||
|
||||
localparam DATA_MULT_FULL_WIDTH = 2*DATA_I_WIDTH+1;
|
||||
localparam DATA_MULT_VALID_WIDTH = 2*DATA_I_WIDTH;
|
||||
localparam AXIS_DATA_I_WIDTH = 8*((DATA_I_WIDTH-1)/8+1) ; // axis data width of input real/image data
|
||||
localparam AXIS_DATA_P_WIDTH = 8*((DATA_MULT_FULL_WIDTH-1)/8+1) ; // axis data width of cmpy output real/image data
|
||||
|
||||
genvar i,j;
|
||||
|
||||
|
||||
// prepare cmpy input data
|
||||
wire [AXIS_DATA_I_WIDTH-1:0] din_real_array [0:COL_NUM-1];
|
||||
wire [AXIS_DATA_I_WIDTH-1:0] din_imag_array [0:COL_NUM-1];
|
||||
|
||||
generate
|
||||
for(i = 0; i < COL_NUM; i = i + 1) begin: array_convert
|
||||
// Sign extension to fit 8-bit axis data format
|
||||
assign din_real_array[i] = {{(AXIS_DATA_I_WIDTH-DATA_I_WIDTH){din_real[(i+1)*DATA_I_WIDTH-1]}},din_real[i*DATA_I_WIDTH +: DATA_I_WIDTH]};
|
||||
assign din_imag_array[i] = {{(AXIS_DATA_I_WIDTH-DATA_I_WIDTH){din_imag[(i+1)*DATA_I_WIDTH-1]}},din_imag[i*DATA_I_WIDTH +: DATA_I_WIDTH]};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
// complex multiplication
|
||||
wire [AXIS_DATA_P_WIDTH-1:0] cmpy_real_array [0:COL_NUM*COL_NUM-1];
|
||||
wire [AXIS_DATA_P_WIDTH-1:0] cmpy_imag_array [0:COL_NUM*COL_NUM-1];
|
||||
|
||||
wire [DATA_O_WIDTH-1:0] dout_real_array [0:COL_NUM*COL_NUM-1];
|
||||
wire [DATA_O_WIDTH-1:0] dout_imag_array [0:COL_NUM*COL_NUM-1];
|
||||
|
||||
generate
|
||||
for(i = 0; i < COL_NUM; i = i + 1) begin: acorr_cmpy_col
|
||||
for(j = 0; j < COL_NUM; j = j + 1) begin: acorr_cmpy_row
|
||||
wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_a;
|
||||
wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_b;
|
||||
wire [2*AXIS_DATA_P_WIDTH-1:0] cmpy_p;
|
||||
wire cmpy_p_vld;
|
||||
|
||||
assign cmpy_a = {din_imag_array[i],din_real_array[i]};
|
||||
assign cmpy_b = {-din_imag_array[j],din_real_array[j]};
|
||||
assign {cmpy_imag_array[i*COL_NUM+j],cmpy_real_array[i*COL_NUM+j]} = cmpy_p;
|
||||
|
||||
if (DATA_O_WIDTH <= DATA_MULT_VALID_WIDTH) begin
|
||||
// truncate msb of the valid part
|
||||
assign dout_real_array[i*COL_NUM+j] = cmpy_real_array[i*COL_NUM+j][DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH];
|
||||
assign dout_imag_array[i*COL_NUM+j] = cmpy_imag_array[i*COL_NUM+j][DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH];
|
||||
end
|
||||
else begin
|
||||
// sign extension to fit output data width
|
||||
assign dout_real_array[i*COL_NUM+j] = {{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){cmpy_real_array[i*COL_NUM+j][DATA_MULT_VALID_WIDTH-1]}},cmpy_real_array[i*COL_NUM+j][0 +: DATA_MULT_VALID_WIDTH]};
|
||||
assign dout_imag_array[i*COL_NUM+j] = {{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){cmpy_imag_array[i*COL_NUM+j][DATA_MULT_VALID_WIDTH-1]}},cmpy_imag_array[i*COL_NUM+j][0 +: DATA_MULT_VALID_WIDTH]};
|
||||
end
|
||||
|
||||
assign dout_real[(i*COL_NUM+j)*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_real_array[i*COL_NUM+j];
|
||||
assign dout_imag[(i*COL_NUM+j)*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_imag_array[i*COL_NUM+j];
|
||||
|
||||
cmpy_12x12 u_cmpy_12x12
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_a_tvalid (din_valid ), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid (din_valid ), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata (cmpy_b ), // input wire [31 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata
|
||||
);
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// output mapping
|
||||
assign dout_valid = acorr_cmpy_col[0].acorr_cmpy_row[0].cmpy_p_vld;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/10/30 20:46:26
|
||||
// Design Name:
|
||||
// Module Name: acorr_tb
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: Testbench for [acorr_cmplx_col_vec]
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// -------------------------------
|
||||
// MATLAB Code for data generation
|
||||
// -------------------------------
|
||||
// COLUMN_NUM = 4;
|
||||
// DATA_I_WIDTH = 12;
|
||||
|
||||
// rng(0);
|
||||
// data = (rand(4,2)*2-1) + 1i*(rand(4,2)*2-1);
|
||||
// d_12b = round(data/max(max(abs(data)))*(2^11-1));
|
||||
// d_12b_real = real(d_12b(end:-1:1,:));
|
||||
// d_12b_imag = imag(d_12b(end:-1:1,:));
|
||||
// d_12b_acorr(:,:,1) = d_12b(:,1)*d_12b(:,1)';
|
||||
// d_12b_acorr(:,:,2) = d_12b(:,2)*d_12b(:,2)';
|
||||
|
||||
|
||||
// module tb_acorr;
|
||||
|
||||
// localparam ROW_NUM = 1;
|
||||
// localparam COL_NUM = 4;
|
||||
// localparam DATA_I_WIDTH = 12;
|
||||
// localparam DATA_O_WIDTH = 23;
|
||||
|
||||
// reg acc_rst = 1'b0;
|
||||
|
||||
// reg clk = 1'b1;
|
||||
// reg rst = 1'b1;
|
||||
// reg din_valid = 'b0;
|
||||
// reg [COL_NUM*DATA_I_WIDTH-1:0] din_real = 'b0, din_imag = 'b0;
|
||||
|
||||
// wire dout_valid;
|
||||
// wire [COL_NUM*COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag;
|
||||
|
||||
// acorr_cmplx_col_vec #(
|
||||
// .COL_NUM (COL_NUM),
|
||||
// .DATA_I_WIDTH (DATA_I_WIDTH),
|
||||
// .DATA_O_WIDTH (DATA_O_WIDTH)
|
||||
// ) u_acorr_cmplx_col_vec
|
||||
// (
|
||||
// // clock & reset
|
||||
// .clk (clk ),
|
||||
// .rst (rst ),
|
||||
|
||||
// // input data
|
||||
// .din_valid (din_valid ),
|
||||
// .din_real (din_real ),
|
||||
// .din_imag (din_imag ),
|
||||
|
||||
// // output data
|
||||
// .dout_valid (dout_valid ),
|
||||
// .dout_real (dout_real ),
|
||||
// .dout_imag (dout_imag )
|
||||
// );
|
||||
|
||||
|
||||
// initial begin
|
||||
// #102 rst = 1'b0;
|
||||
// #222;
|
||||
// @(posedge clk)
|
||||
// din_valid = 1'b1;
|
||||
// din_real = {
|
||||
// 12'd1351,
|
||||
// -12'd1219,
|
||||
// 12'd1326,
|
||||
// 12'd1029};
|
||||
|
||||
// din_imag = {
|
||||
// 12'd1538,
|
||||
// -12'd1119,
|
||||
// 12'd1519,
|
||||
// 12'd1495};
|
||||
|
||||
// @(posedge clk)
|
||||
// din_valid = 1'b0;
|
||||
|
||||
// @(posedge clk)
|
||||
// din_valid = 1'b1;
|
||||
// din_real = {
|
||||
// 12'd153 ,
|
||||
// -12'd724 ,
|
||||
// -12'd1315,
|
||||
// 12'd433 };
|
||||
|
||||
// din_imag = {
|
||||
// -12'd1170,
|
||||
// 12'd981 ,
|
||||
// -12'd48 ,
|
||||
// 12'd1494};
|
||||
// end
|
||||
|
||||
// always #10 clk = ~clk;
|
||||
|
||||
|
||||
// endmodule
|
||||
@@ -0,0 +1,443 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/09/14 16:45:10
|
||||
// Last Modified Data: 2023/02/12 17:10
|
||||
// Design Name:
|
||||
// Module Name: ad9361_phase_cal_coarse
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// 2022/09/14 16:45:10 - File Created
|
||||
// 2023/02/12 17:10 - 修改：校准未完成时，将输入信号寄存输出。
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module ad9361_phase_cal_coarse
|
||||
#(
|
||||
parameter COUNTER_MOD = 48,
|
||||
parameter PEAK_POS = 12,
|
||||
parameter ADC_DATA_WIDTH = 12
|
||||
)
|
||||
(
|
||||
// clock & reset
|
||||
input clk ,
|
||||
input rst ,
|
||||
// control interface
|
||||
input ad9361_1_cal_start ,
|
||||
output ad9361_1_cal_done ,
|
||||
input ad9361_2_cal_start ,
|
||||
output ad9361_2_cal_done ,
|
||||
output ad9361_cal_result ,
|
||||
output ad9361_cal_valid ,
|
||||
input ad9361_recal ,
|
||||
// input data interface
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch1_i ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch1_q ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch2_i ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch2_q ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch3_i ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch3_q ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch4_i ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch4_q ,
|
||||
// output data interface
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q
|
||||
);
|
||||
|
||||
localparam STATE_IDLE = 2'd0;
|
||||
localparam STATE_CAL_1 = 2'd1;
|
||||
localparam STATE_CAL_2 = 2'd2;
|
||||
localparam STATE_DONE = 2'd3;
|
||||
|
||||
// buffer input control signals
|
||||
reg ad9361_1_cal_start_d1 = 'b0;
|
||||
reg ad9361_1_cal_start_d2 = 'b0;
|
||||
reg ad9361_2_cal_start_d1 = 'b0;
|
||||
reg ad9361_2_cal_start_d2 = 'b0;
|
||||
reg ad9361_recal_d1 = 'b0;
|
||||
reg ad9361_recal_d2 = 'b0;
|
||||
|
||||
always @(posedge clk) begin
|
||||
ad9361_1_cal_start_d1 <= ad9361_1_cal_start;
|
||||
ad9361_1_cal_start_d2 <= ad9361_1_cal_start_d1;
|
||||
|
||||
ad9361_2_cal_start_d1 <= ad9361_2_cal_start;
|
||||
ad9361_2_cal_start_d2 <= ad9361_2_cal_start_d1;
|
||||
|
||||
ad9361_recal_d1 <= ad9361_recal;
|
||||
ad9361_recal_d2 <= ad9361_recal_d1;
|
||||
end
|
||||
|
||||
// center state machine
|
||||
reg [ 1:0] curr_state = STATE_IDLE;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
curr_state <= STATE_IDLE;
|
||||
end
|
||||
else begin
|
||||
case (curr_state)
|
||||
STATE_IDLE: begin
|
||||
// move to next state when [ad9361_1_cal_start] asserts
|
||||
curr_state <= ad9361_1_cal_start_d2 ? STATE_CAL_1 : STATE_IDLE;
|
||||
end
|
||||
STATE_CAL_1: begin
|
||||
// move to next state when 1st cal finishes [ad9361_2_cal_start] asserts
|
||||
curr_state <= (ad9361_1_cal_done && ad9361_2_cal_start_d2) ? STATE_CAL_2 : STATE_CAL_1;
|
||||
end
|
||||
STATE_CAL_2: begin
|
||||
// move to next state when 2nd cal finishes
|
||||
curr_state <= ad9361_2_cal_done ? STATE_DONE : STATE_CAL_2;
|
||||
end
|
||||
STATE_DONE: begin
|
||||
// move to ILDA state when it needs to recal
|
||||
curr_state <= (ad9361_recal_d2) ? STATE_IDLE : STATE_DONE;
|
||||
end
|
||||
default: begin
|
||||
curr_state <= STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
//
|
||||
reg rx_ch2_i_msb_d1 = 'b0;
|
||||
reg cnt_start = 'b0;
|
||||
reg cnt_start_flag = 'b0;
|
||||
reg [$clog2(COUNTER_MOD)-1:0] cnt = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_ch2_i_rec = 'b0;
|
||||
reg rx_ch2_i_rec_flag = 'b0;
|
||||
|
||||
assign ad9361_1_cal_done = rx_ch2_i_rec_flag;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
rx_ch2_i_msb_d1 <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_IDLE) begin
|
||||
// reset at IDLE state
|
||||
rx_ch2_i_msb_d1 <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_CAL_1) begin
|
||||
rx_ch2_i_msb_d1 <= rx_ch2_i[ADC_DATA_WIDTH-1];
|
||||
end
|
||||
else begin
|
||||
rx_ch2_i_msb_d1 <= rx_ch2_i_msb_d1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_start <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_IDLE) begin
|
||||
// reset at IDLE state
|
||||
cnt_start <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_CAL_1 && ~cnt_start) begin
|
||||
// assert when the 1st falling edge of msb of rx_ch2_i is detected
|
||||
cnt_start <= (rx_ch2_i_msb_d1 & ~rx_ch2_i[ADC_DATA_WIDTH-1]) ? 1'b1 : 1'b0;
|
||||
end
|
||||
else begin
|
||||
cnt_start <= cnt_start;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_IDLE) begin
|
||||
// reset at IDLE state
|
||||
cnt <= 'b0;
|
||||
end
|
||||
else if (cnt_start) begin
|
||||
cnt <= (cnt == COUNTER_MOD - 1) ? 'b0 : cnt + 1'b1;
|
||||
end
|
||||
else begin
|
||||
cnt <= cnt;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
rx_ch2_i_rec <= 'b0;
|
||||
rx_ch2_i_rec_flag <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_IDLE) begin
|
||||
// reset at IDLE state
|
||||
rx_ch2_i_rec <= 'b0;
|
||||
rx_ch2_i_rec_flag <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_CAL_1 && cnt == PEAK_POS && ~rx_ch2_i_rec_flag) begin
|
||||
rx_ch2_i_rec <= rx_ch2_i;
|
||||
rx_ch2_i_rec_flag <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
rx_ch2_i_rec <= rx_ch2_i_rec;
|
||||
rx_ch2_i_rec_flag <= rx_ch2_i_rec_flag;
|
||||
end
|
||||
end
|
||||
|
||||
//
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_ch4_i_rec = 'b0;
|
||||
reg rx_ch4_i_rec_flag = 'b0;
|
||||
|
||||
assign ad9361_2_cal_done = rx_ch4_i_rec_flag;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
rx_ch4_i_rec <= 'b0;
|
||||
rx_ch4_i_rec_flag <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_IDLE) begin
|
||||
// reset at IDLE state
|
||||
rx_ch4_i_rec <= 'b0;
|
||||
rx_ch4_i_rec_flag <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_CAL_2 && cnt == COUNTER_MOD/4 && ~rx_ch4_i_rec_flag) begin
|
||||
rx_ch4_i_rec <= rx_ch4_i;
|
||||
rx_ch4_i_rec_flag <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
rx_ch4_i_rec <= rx_ch4_i_rec;
|
||||
rx_ch4_i_rec_flag <= rx_ch4_i_rec_flag;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg ad9361_cal_valid_buf = 'b0;
|
||||
reg ad9361_cal_result_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q_buf = 'b0;
|
||||
|
||||
assign ad9361_cal_valid = ad9361_cal_valid_buf;
|
||||
assign ad9361_cal_result = ad9361_cal_result_buf;
|
||||
assign rx_cal_ch1_i = rx_cal_ch1_i_buf;
|
||||
assign rx_cal_ch2_i = rx_cal_ch2_i_buf;
|
||||
assign rx_cal_ch3_i = rx_cal_ch3_i_buf;
|
||||
assign rx_cal_ch4_i = rx_cal_ch4_i_buf;
|
||||
assign rx_cal_ch1_q = rx_cal_ch1_q_buf;
|
||||
assign rx_cal_ch2_q = rx_cal_ch2_q_buf;
|
||||
assign rx_cal_ch3_q = rx_cal_ch3_q_buf;
|
||||
assign rx_cal_ch4_q = rx_cal_ch4_q_buf;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
ad9361_cal_valid_buf <= 'b0;
|
||||
ad9361_cal_result_buf <= 'b0;
|
||||
rx_cal_ch1_i_buf <= 'b0;
|
||||
rx_cal_ch2_i_buf <= 'b0;
|
||||
rx_cal_ch3_i_buf <= 'b0;
|
||||
rx_cal_ch4_i_buf <= 'b0;
|
||||
rx_cal_ch1_q_buf <= 'b0;
|
||||
rx_cal_ch2_q_buf <= 'b0;
|
||||
rx_cal_ch3_q_buf <= 'b0;
|
||||
rx_cal_ch4_q_buf <= 'b0;
|
||||
end
|
||||
else if (curr_state == STATE_DONE) begin
|
||||
ad9361_cal_valid_buf <= 1'b1;
|
||||
|
||||
if (rx_ch2_i_rec[ADC_DATA_WIDTH-1] == rx_ch4_i_rec[ADC_DATA_WIDTH-1]) begin
|
||||
ad9361_cal_result_buf <= 'b0;
|
||||
rx_cal_ch1_i_buf <= rx_ch1_i;
|
||||
rx_cal_ch1_q_buf <= rx_ch1_q;
|
||||
rx_cal_ch2_i_buf <= -rx_ch2_i;
|
||||
rx_cal_ch2_q_buf <= -rx_ch2_q;
|
||||
rx_cal_ch3_i_buf <= rx_ch3_i;
|
||||
rx_cal_ch3_q_buf <= rx_ch3_q;
|
||||
rx_cal_ch4_i_buf <= -rx_ch4_i;
|
||||
rx_cal_ch4_q_buf <= -rx_ch4_q;
|
||||
end
|
||||
else begin
|
||||
ad9361_cal_result_buf <= 'b1;
|
||||
rx_cal_ch1_i_buf <= rx_ch1_i;
|
||||
rx_cal_ch1_q_buf <= rx_ch1_q;
|
||||
rx_cal_ch2_i_buf <= -rx_ch2_i;
|
||||
rx_cal_ch2_q_buf <= -rx_ch2_q;
|
||||
rx_cal_ch3_i_buf <= -rx_ch3_i;
|
||||
rx_cal_ch3_q_buf <= -rx_ch3_q;
|
||||
rx_cal_ch4_i_buf <= rx_ch4_i;
|
||||
rx_cal_ch4_q_buf <= rx_ch4_q;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
ad9361_cal_valid_buf <= 1'b0;
|
||||
ad9361_cal_result_buf <= ad9361_cal_result_buf;
|
||||
rx_cal_ch1_i_buf <= rx_ch1_i;
|
||||
rx_cal_ch2_i_buf <= rx_ch2_i;
|
||||
rx_cal_ch3_i_buf <= rx_ch3_i;
|
||||
rx_cal_ch4_i_buf <= rx_ch4_i;
|
||||
rx_cal_ch1_q_buf <= rx_ch1_q;
|
||||
rx_cal_ch2_q_buf <= rx_ch2_q;
|
||||
rx_cal_ch3_q_buf <= rx_ch3_q;
|
||||
rx_cal_ch4_q_buf <= rx_ch4_q;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/09/15 11:12:45
|
||||
// Last Modified Data: 2022/11/02
|
||||
// Design Name:
|
||||
// Module Name: tb_ad9361_cal_coarse
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: testbench for [ad9361_phase_cal_coarse]
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// module tb_ad9361_cal_coarse;
|
||||
|
||||
// reg clk = 'b0;
|
||||
// reg rst = 1'b1;
|
||||
|
||||
// reg ad9361_1_cal_start = 'b0;
|
||||
// wire ad9361_1_cal_done ;
|
||||
// reg ad9361_2_cal_start = 'b0;
|
||||
// wire ad9361_2_cal_done ;
|
||||
// wire ad9361_cal_result ;
|
||||
// wire ad9361_cal_valid;
|
||||
// reg ad9361_recal = 'b0;
|
||||
|
||||
// // phase difference of 180 degree
|
||||
// reg [11:0] rx_ch1_i = 12'd2047;
|
||||
// reg [11:0] rx_ch1_q = 12'd2047;
|
||||
// reg [11:0] rx_ch2_i = -12'd2047;
|
||||
// reg [11:0] rx_ch2_q = -12'd2047;
|
||||
// reg [11:0] rx_ch3_q = -12'd2047;
|
||||
// reg [11:0] rx_ch3_i = -12'd2047;
|
||||
// reg [11:0] rx_ch4_i = 12'd2047;
|
||||
// reg [11:0] rx_ch4_q = 12'd2047;
|
||||
|
||||
// wire [11:0] rx_cal_ch1_i;
|
||||
// wire [11:0] rx_cal_ch2_i;
|
||||
// wire [11:0] rx_cal_ch3_i;
|
||||
// wire [11:0] rx_cal_ch4_i;
|
||||
// wire [11:0] rx_cal_ch1_q;
|
||||
// wire [11:0] rx_cal_ch2_q;
|
||||
// wire [11:0] rx_cal_ch3_q;
|
||||
// wire [11:0] rx_cal_ch4_q;
|
||||
|
||||
// ad9361_phase_cal #(
|
||||
// .COUNTER_MOD (48),
|
||||
// .PEAK_POS (12)
|
||||
// ) u_ad9361_phase_cal
|
||||
// (
|
||||
// // clock & reset
|
||||
// .clk (clk ), // input clk
|
||||
// .rst (rst ), // input rst
|
||||
// // control interface
|
||||
// .ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start
|
||||
// .ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done
|
||||
// .ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start
|
||||
// .ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done
|
||||
// .ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result
|
||||
// .ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid
|
||||
// .ad9361_recal (ad9361_recal ), // input ad9361_recal
|
||||
// // input data interface
|
||||
// .rx_ch1_i (rx_ch1_i ), // input [11:0] rx_ch1_i
|
||||
// .rx_ch2_i (rx_ch2_i ), // input [11:0] rx_ch2_i
|
||||
// .rx_ch3_i (rx_ch3_i ), // input [11:0] rx_ch3_i
|
||||
// .rx_ch4_i (rx_ch4_i ), // input [11:0] rx_ch4_i
|
||||
// .rx_ch1_q (rx_ch1_q ), // input [11:0] rx_ch1_q
|
||||
// .rx_ch2_q (rx_ch2_q ), // input [11:0] rx_ch2_q
|
||||
// .rx_ch3_q (rx_ch3_q ), // input [11:0] rx_ch3_q
|
||||
// .rx_ch4_q (rx_ch4_q ), // input [11:0] rx_ch4_q
|
||||
// // output data interface
|
||||
// .rx_cal_ch1_i (rx_cal_ch1_i ), // output [11:0] rx_cal_ch1_i
|
||||
// .rx_cal_ch2_i (rx_cal_ch2_i ), // output [11:0] rx_cal_ch2_i
|
||||
// .rx_cal_ch3_i (rx_cal_ch3_i ), // output [11:0] rx_cal_ch3_i
|
||||
// .rx_cal_ch4_i (rx_cal_ch4_i ), // output [11:0] rx_cal_ch4_i
|
||||
// .rx_cal_ch1_q (rx_cal_ch1_q ), // output [11:0] rx_cal_ch1_q
|
||||
// .rx_cal_ch2_q (rx_cal_ch2_q ), // output [11:0] rx_cal_ch2_q
|
||||
// .rx_cal_ch3_q (rx_cal_ch3_q ), // output [11:0] rx_cal_ch3_q
|
||||
// .rx_cal_ch4_q (rx_cal_ch4_q ) // output [11:0] rx_cal_ch4_q
|
||||
// );
|
||||
|
||||
// initial begin
|
||||
// #102
|
||||
// rst = 1'b0;
|
||||
// #100
|
||||
// ad9361_1_cal_start = 1'b1;
|
||||
// end
|
||||
|
||||
// initial begin
|
||||
// #10000
|
||||
// ad9361_recal = 1'b1;
|
||||
// #20
|
||||
// ad9361_recal = 1'b0;
|
||||
// end
|
||||
|
||||
// always begin
|
||||
// #2 clk = ~clk;
|
||||
// end
|
||||
|
||||
// always begin
|
||||
// #72
|
||||
// rx_ch1_i = ~rx_ch1_i;
|
||||
// rx_ch2_i = ~rx_ch2_i;
|
||||
// rx_ch3_i = ~rx_ch3_i;
|
||||
// rx_ch4_i = ~rx_ch4_i;
|
||||
// #24
|
||||
// rx_ch1_q = ~rx_ch1_q;
|
||||
// rx_ch2_q = ~rx_ch2_q;
|
||||
// rx_ch3_q = ~rx_ch3_q;
|
||||
// rx_ch4_q = ~rx_ch4_q;
|
||||
// end
|
||||
|
||||
// always @(posedge clk) begin
|
||||
// if (ad9361_1_cal_done) begin
|
||||
// ad9361_2_cal_start <= 1'b1;
|
||||
// end
|
||||
// else begin
|
||||
// ad9361_2_cal_start <= 1'b0;
|
||||
// end
|
||||
// end
|
||||
|
||||
// endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,162 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 04/25/2023 03:22:25 PM
|
||||
// Design Name:
|
||||
// Module Name: phase_compensation
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: Rotate input data using Cordic LogiCORE IP.
|
||||
// Parameter:
|
||||
// DATA_WIDTH: Bit width of input and output data.
|
||||
// PHASE_WIDTH: Bit width of input phase.
|
||||
// CHANNEL_NUM: Channel number of input data.
|
||||
// ROTATE_WIDTH (local): Cordic LogiCORE IP input and output actual data width.
|
||||
// AXIS_ROTATE_WIDTH (local): Cordic LogiCORE IP input and output axis data
|
||||
// width.
|
||||
// Data format:
|
||||
// din_valid: Indicate [din_data_real/imag] and [din_phase] are valid.
|
||||
// din_data_real/imag: Suppose the channel number is 4, then
|
||||
// din_data_real = {Re{ch4}, Re{ch3}, Re{ch2}, Re{ch1}}
|
||||
// din_data_imag = {Im{ch4}, Im{ch3}, Im{ch2}, Im{ch1}}
|
||||
// din_phase = {phase_ch4, phase_ch3, phase_ch2, phase_ch1}
|
||||
// dout_valid: Indicate [dout_real/imag] data are valid. The latency is
|
||||
// determined by the cordic ip core, which is 20 clock cycles.
|
||||
// dout_real/imag:
|
||||
// dout_data_real = {Re{rotate_ch4}, Re{rotate_ch3}, ..., Re{rotate_ch1}}
|
||||
// dout_data_imag = {Im{rotate_ch4}, Im{rotate_ch3}, ..., Im{rotate_ch1}}
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module phase_compensation
|
||||
#(
|
||||
parameter DATA_WIDTH = 12,
|
||||
parameter PHASE_WIDTH = 16,
|
||||
parameter CHANNEL_NUM = 4
|
||||
)
|
||||
(
|
||||
// clock & reset
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
// input data
|
||||
input din_valid,
|
||||
input [CHANNEL_NUM*DATA_WIDTH-1 : 0] din_data_real,
|
||||
input [CHANNEL_NUM*DATA_WIDTH-1 : 0] din_data_imag,
|
||||
input [CHANNEL_NUM*PHASE_WIDTH-1 : 0] din_phase,
|
||||
|
||||
// output data
|
||||
output dout_valid,
|
||||
output [CHANNEL_NUM*DATA_WIDTH-1:0] dout_data_real,
|
||||
output [CHANNEL_NUM*DATA_WIDTH-1:0] dout_data_imag
|
||||
);
|
||||
|
||||
// local parameter & variables
|
||||
localparam ROTATE_WIDTH = 16;
|
||||
localparam AXIS_ROTATE_WIDTH = 8*((ROTATE_WIDTH-1)/8+1); // axis data width of input real/image data
|
||||
|
||||
genvar i,j;
|
||||
|
||||
// prepare rotate input data
|
||||
wire [AXIS_ROTATE_WIDTH-1 : 0] din_data_real_array [0 : CHANNEL_NUM-1];
|
||||
wire [AXIS_ROTATE_WIDTH-1 : 0] din_data_imag_array [0 : CHANNEL_NUM-1];
|
||||
wire [AXIS_ROTATE_WIDTH-1 : 0] din_phase_array [0 : CHANNEL_NUM-1];
|
||||
|
||||
generate
|
||||
for(i = 0; i < CHANNEL_NUM; i = i + 1) begin: array_convert_in
|
||||
|
||||
if (AXIS_ROTATE_WIDTH > DATA_WIDTH) begin
|
||||
// append zeros
|
||||
assign din_data_real_array[i] = {din_data_real[i*DATA_WIDTH +: DATA_WIDTH],{(AXIS_ROTATE_WIDTH-DATA_WIDTH){1'b0}}};
|
||||
assign din_data_imag_array[i] = {din_data_imag[i*DATA_WIDTH +: DATA_WIDTH],{(AXIS_ROTATE_WIDTH-DATA_WIDTH){1'b0}}};
|
||||
end
|
||||
else begin
|
||||
// truncate msb
|
||||
assign din_data_real_array[i] = din_data_real[(i+1)*DATA_WIDTH-1 -: AXIS_ROTATE_WIDTH];
|
||||
assign din_data_imag_array[i] = din_data_imag[(i+1)*DATA_WIDTH-1 -: AXIS_ROTATE_WIDTH];
|
||||
end
|
||||
|
||||
if (AXIS_ROTATE_WIDTH > PHASE_WIDTH) begin
|
||||
// append zeros
|
||||
assign din_phase_array[i] = {din_phase[i*PHASE_WIDTH +: PHASE_WIDTH],{(AXIS_ROTATE_WIDTH-PHASE_WIDTH){1'b0}}};
|
||||
end
|
||||
else begin
|
||||
// truncate msb
|
||||
assign din_phase_array[i] = din_phase[(i+1)*PHASE_WIDTH-1 -: PHASE_WIDTH];
|
||||
end
|
||||
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// rotate
|
||||
wire [AXIS_ROTATE_WIDTH-1 : 0] rotate_out_real_array [0 : CHANNEL_NUM-1];
|
||||
wire [AXIS_ROTATE_WIDTH-1 : 0] rotate_out_imag_array [0 : CHANNEL_NUM-1];
|
||||
|
||||
generate
|
||||
for (i = 0; i < CHANNEL_NUM; i = i + 1) begin: input_data_rotate
|
||||
wire rotate_phase_valid;
|
||||
wire [AXIS_ROTATE_WIDTH-1 : 0] rotate_phase_data;
|
||||
wire rotate_cart_valid;
|
||||
wire [2*AXIS_ROTATE_WIDTH-1 : 0] rotate_cart_data;
|
||||
wire rotate_dout_valid;
|
||||
wire [2*AXIS_ROTATE_WIDTH-1 : 0] rotate_dout_data;
|
||||
|
||||
assign rotate_phase_valid = din_valid;
|
||||
assign rotate_phase_data = din_phase_array[i];
|
||||
assign rotate_cart_valid = din_valid;
|
||||
assign rotate_cart_data = {din_data_imag_array[i],din_data_real_array[i]};
|
||||
assign {rotate_out_imag_array[i],rotate_out_real_array[i]} = rotate_dout_data;
|
||||
|
||||
rotate_16b u_rotate_16b
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_phase_tvalid (rotate_phase_valid ), // input wire s_axis_phase_tvalid
|
||||
.s_axis_phase_tdata (rotate_phase_data ), // input wire [15 : 0] s_axis_phase_tdata
|
||||
.s_axis_cartesian_tvalid(rotate_cart_valid ), // input wire s_axis_cartesian_tvalid
|
||||
.s_axis_cartesian_tdata (rotate_cart_data ), // input wire [31 : 0] s_axis_cartesian_tdata
|
||||
.m_axis_dout_tvalid (rotate_dout_valid ), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata (rotate_dout_data ) // output wire [31 : 0] m_axis_dout_tdata
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// output data
|
||||
wire [DATA_WIDTH-1 : 0] dout_data_real_array [0 : CHANNEL_NUM-1];
|
||||
wire [DATA_WIDTH-1 : 0] dout_data_imag_array [0 : CHANNEL_NUM-1];
|
||||
|
||||
generate
|
||||
for(i = 0; i < CHANNEL_NUM; i = i + 1) begin: array_convert_out
|
||||
|
||||
if (DATA_WIDTH > AXIS_ROTATE_WIDTH) begin
|
||||
// append zeros
|
||||
assign dout_data_real_array[i] = {rotate_out_real_array[i],{(DATA_WIDTH-AXIS_ROTATE_WIDTH){1'b0}}};
|
||||
assign dout_data_imag_array[i] = {rotate_out_imag_array[i],{(DATA_WIDTH-AXIS_ROTATE_WIDTH){1'b0}}};
|
||||
end
|
||||
else begin
|
||||
// truncate msb
|
||||
assign dout_data_real_array[i] = rotate_out_real_array[i][AXIS_ROTATE_WIDTH-1 -: DATA_WIDTH];
|
||||
assign dout_data_imag_array[i] = rotate_out_imag_array[i][AXIS_ROTATE_WIDTH-1 -: DATA_WIDTH];
|
||||
end
|
||||
|
||||
assign dout_data_real[i*DATA_WIDTH +: DATA_WIDTH] = dout_data_real_array[i];
|
||||
assign dout_data_imag[i*DATA_WIDTH +: DATA_WIDTH] = dout_data_imag_array[i];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign dout_valid = input_data_rotate[0].rotate_dout_valid;
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,531 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/10/30 18:09:20
|
||||
// Design Name:
|
||||
// Module Name: rx_pre_process
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: Pre-process rx data, including ad9361 mcs & implementing nulling
|
||||
// algorithm on rx data. The latency of autocorrelation is consisted of 2
|
||||
// parts: 1. [STABLE_CNT_MOD] + [SNAPSHOT_NUM] + several intermediate delay
|
||||
// of [sys_clk] clock cycles; 2. ([CHANNEL_NUM]*[CHANNEL_NUM]*[CMPLX_DIM] +
|
||||
// 1 frame head + 1 frame length)*[ACCUM_WIDTH] of [clk_96m] clock cycles.
|
||||
// The simulation result shows delay of about 30us when [sys_clk] is 48m.
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
/*******************************************************************************
|
||||
* Contents
|
||||
* 01. AD9361 Rx Multi-Channel Calibration
|
||||
* 02. Autocorrelation of Snapshot Vector
|
||||
* 03. Accumulation of Snapshot Autocorrelation Matrices
|
||||
* 04. 32-bit Matrix Element to 1-bit Stream Conversion
|
||||
* 05. 1-bit Stream to 32-bit Vector Element Conversion
|
||||
* 06. RF Synthesizer Control
|
||||
* 07. Debug IO
|
||||
* 08. DDR and Fixed-io (Do NOT Modify)
|
||||
*******************************************************************************/
|
||||
|
||||
module rx_pre_process
|
||||
#(
|
||||
parameter CAL_CNT_MOD = 48 ,
|
||||
parameter CAL_PEAK_POS = 12 ,
|
||||
parameter PHASE_WIDTH = 16 ,
|
||||
parameter STABLE_CNT_MOD = 48 ,
|
||||
parameter ADC_DATA_WIDTH = 12 ,
|
||||
parameter CHANNEL_NUM = 4 ,
|
||||
parameter SNAPSHOT_NUM = 256,
|
||||
parameter PS_PL_WIDTH = 32 ,
|
||||
parameter WEIGHT_TRUNC_WIDTH = 16 ,
|
||||
parameter CMPLX_DIM = 2 ,
|
||||
parameter OUTPUT_DATA_WIDTH = ADC_DATA_WIDTH,
|
||||
parameter ACCOR_FRAME_HEAD = 32'h7E7E7E7E,
|
||||
parameter WEIGHT_FRAME_HEAD = ACCOR_FRAME_HEAD // Same head is required by [c2c_bridge] module
|
||||
)
|
||||
(
|
||||
// clock & reset
|
||||
input sys_clk , // sync to adc data
|
||||
input sys_clk_4x , // sync to adc data
|
||||
input sys_rst , // sync to [sys_clk]
|
||||
input clk_96m , // sync to c2c data
|
||||
input ant_rst , // sync to [clk_96m]
|
||||
|
||||
// input un-calibrated data
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch1_i ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch1_q ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch2_i ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch2_q ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch3_i ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch3_q ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch4_i ,
|
||||
input [ADC_DATA_WIDTH-1:0] rx_ch4_q ,
|
||||
|
||||
// input phase
|
||||
input [PHASE_WIDTH-1:0] phase_ch1 ,
|
||||
input [PHASE_WIDTH-1:0] phase_ch2 ,
|
||||
input [PHASE_WIDTH-1:0] phase_ch3 ,
|
||||
input [PHASE_WIDTH-1:0] phase_ch4 ,
|
||||
|
||||
// ad9361 calibration interface
|
||||
input ad9361_1_cal_start ,
|
||||
output ad9361_1_cal_done ,
|
||||
input ad9361_2_cal_start ,
|
||||
output ad9361_2_cal_done ,
|
||||
output ad9361_cal_result ,
|
||||
output ad9361_cal_valid ,
|
||||
input ad9361_recal ,
|
||||
|
||||
// nulling algotithm interface
|
||||
input hop_start_flag , // sync to [sys_clk_4x]
|
||||
output accor_stream_valid , // sync to [clk_96m]
|
||||
output accor_stream_data , // sync to [clk_96m]
|
||||
input weight_stream_data , // sync to [clk_96m]
|
||||
output rx_data_valid , // sync to [sys_clk]
|
||||
output [OUTPUT_DATA_WIDTH-1:0] rx_data_i, // sync to [sys_clk]
|
||||
output [OUTPUT_DATA_WIDTH-1:0] rx_data_q // sync to [sys_clk]
|
||||
);
|
||||
|
||||
localparam ACORR_WIDTH = 2*ADC_DATA_WIDTH;
|
||||
localparam ACCUM_WIDTH = $clog2(SNAPSHOT_NUM)+ACORR_WIDTH; // = 32
|
||||
// autocorrelation state machine
|
||||
localparam ACORR_STATE_NUM = 3;
|
||||
localparam ACORR_STATE_IDLE = 0;
|
||||
localparam ACORR_STATE_STABLE = 1; // wait until rf is stable
|
||||
localparam ACORR_STATE_CALC = 2; // autocorrelation calculation and formatting
|
||||
|
||||
genvar i;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////// AD9361 Rx Multi-Channel Calibration //////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
wire [11:0] rx_cal_ch1_i, rx_cal_ch1_q;
|
||||
wire [11:0] rx_cal_ch2_i, rx_cal_ch2_q;
|
||||
wire [11:0] rx_cal_ch3_i, rx_cal_ch3_q;
|
||||
wire [11:0] rx_cal_ch4_i, rx_cal_ch4_q;
|
||||
|
||||
ad9361_phase_cal_coarse u_ad9361_phase_cal
|
||||
(
|
||||
// clock & reset
|
||||
.clk (sys_clk ), // input clk
|
||||
.rst (sys_rst ), // input rst
|
||||
// control interface
|
||||
.ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start
|
||||
.ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done
|
||||
.ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start
|
||||
.ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done
|
||||
.ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result
|
||||
.ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid
|
||||
.ad9361_recal (ad9361_recal ), // input ad9361_recal
|
||||
// input data interface
|
||||
.rx_ch1_i (rx_ch1_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch1_i
|
||||
.rx_ch1_q (rx_ch1_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch1_q
|
||||
.rx_ch2_i (rx_ch2_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch2_i
|
||||
.rx_ch2_q (rx_ch2_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch2_q
|
||||
.rx_ch3_i (rx_ch3_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch3_i
|
||||
.rx_ch3_q (rx_ch3_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch3_q
|
||||
.rx_ch4_i (rx_ch4_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch4_i
|
||||
.rx_ch4_q (rx_ch4_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch4_q
|
||||
// output data interface
|
||||
.rx_cal_ch1_i (rx_cal_ch1_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i
|
||||
.rx_cal_ch1_q (rx_cal_ch1_q ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q
|
||||
.rx_cal_ch2_i (rx_cal_ch2_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i
|
||||
.rx_cal_ch2_q (rx_cal_ch2_q ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q
|
||||
.rx_cal_ch3_i (rx_cal_ch3_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i
|
||||
.rx_cal_ch3_q (rx_cal_ch3_q ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q
|
||||
.rx_cal_ch4_i (rx_cal_ch4_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i
|
||||
.rx_cal_ch4_q (rx_cal_ch4_q ) // output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////// Channel Phase Diff Compensation ////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// input
|
||||
wire phase_comp_din_valid;
|
||||
wire [CHANNEL_NUM*ADC_DATA_WIDTH - 1 : 0] phase_comp_din_data_real;
|
||||
wire [CHANNEL_NUM*ADC_DATA_WIDTH - 1 : 0] phase_comp_din_data_imag;
|
||||
wire [CHANNEL_NUM*PHASE_WIDTH-1 : 0] phase_comp_din_phase;
|
||||
|
||||
assign phase_comp_din_valid = ad9361_cal_valid;
|
||||
assign phase_comp_din_data_real = {rx_cal_ch4_i, rx_cal_ch3_i, rx_cal_ch2_i, rx_cal_ch1_i};
|
||||
assign phase_comp_din_data_imag = {rx_cal_ch4_q, rx_cal_ch3_q, rx_cal_ch2_q, rx_cal_ch1_q};
|
||||
assign phase_comp_din_phase = {phase_ch4, phase_ch3, phase_ch2, phase_ch1};
|
||||
|
||||
// output
|
||||
wire phase_comp_dout_valid;
|
||||
wire [CHANNEL_NUM*ADC_DATA_WIDTH - 1 : 0] phase_comp_dout_data_real;
|
||||
wire [CHANNEL_NUM*ADC_DATA_WIDTH - 1 : 0] phase_comp_dout_data_imag;
|
||||
|
||||
phase_compensation #(
|
||||
.DATA_WIDTH (ADC_DATA_WIDTH ),
|
||||
.PHASE_WIDTH (PHASE_WIDTH ),
|
||||
.CHANNEL_NUM (CHANNEL_NUM )
|
||||
) u_phase_compensation
|
||||
(
|
||||
// clock & reset
|
||||
.clk (sys_clk ),
|
||||
.rst (sys_rst ),
|
||||
|
||||
// input data
|
||||
.din_valid (phase_comp_din_valid ),
|
||||
.din_data_real (phase_comp_din_data_real ),
|
||||
.din_data_imag (phase_comp_din_data_imag ),
|
||||
.din_phase (phase_comp_din_phase ),
|
||||
|
||||
// output data
|
||||
.dout_valid (phase_comp_dout_valid ),
|
||||
.dout_data_real (phase_comp_dout_data_real ),
|
||||
.dout_data_imag (phase_comp_dout_data_imag )
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////// Autocorrelation State Machine /////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
reg [$clog2(ACORR_STATE_NUM)-1 : 0] acorr_state = ACORR_STATE_IDLE;
|
||||
reg [$clog2(STABLE_CNT_MOD)-1 : 0] stable_cnt = 'b0;
|
||||
reg [$clog2(SNAPSHOT_NUM)-1 : 0] snapshot_cnt = 'b0;
|
||||
reg snapshot_valid = 'b0;
|
||||
|
||||
reg fifo_cdc_rst = 1'b0; // reset [fifo_accor_cdc] & [fifo_weight_cdc] at each hop
|
||||
|
||||
wire hop_start_flag_cdc;
|
||||
|
||||
xpm_cdc_pulse #(
|
||||
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (1), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.REG_OUTPUT (1), // DECIMAL; 0=disable registered output, 1=enable registered output
|
||||
.RST_USED (0), // DECIMAL; 0=no reset, 1=implement reset
|
||||
.SIM_ASSERT_CHK (1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
) u_hop_start_flag_cdc
|
||||
(
|
||||
.dest_pulse (hop_start_flag_cdc ), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
|
||||
// transfer is correctly initiated on src_pulse input. This output is
|
||||
// combinatorial unless REG_OUTPUT is set to 1.
|
||||
.dest_clk (sys_clk ), // 1-bit input: Destination clock.
|
||||
.dest_rst (1'b1 ), // 1-bit input: optional; required when RST_USED = 1
|
||||
.src_clk (sys_clk_4x ), // 1-bit input: Source clock.
|
||||
.src_pulse (hop_start_flag ), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
|
||||
// destination clock domain. The minimum gap between each pulse transfer must be
|
||||
// at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
|
||||
// between the falling edge of a src_pulse to the rising edge of the next
|
||||
// src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
|
||||
// will generate a pulse the size of one dest_clk period in the destination
|
||||
// clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
|
||||
// src_rst and/or dest_rst are asserted.
|
||||
.src_rst (1'b1 ) // 1-bit input: optional; required when RST_USED = 1
|
||||
);
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
acorr_state <= ACORR_STATE_IDLE;
|
||||
end
|
||||
else begin
|
||||
case (acorr_state)
|
||||
ACORR_STATE_IDLE : acorr_state <= (hop_start_flag_cdc & phase_comp_dout_valid) ? ACORR_STATE_STABLE : ACORR_STATE_IDLE;
|
||||
ACORR_STATE_STABLE: acorr_state <= (stable_cnt == STABLE_CNT_MOD-1) ? ACORR_STATE_CALC : ACORR_STATE_STABLE;
|
||||
ACORR_STATE_CALC : acorr_state <= (snapshot_cnt == SNAPSHOT_NUM-1) ? ACORR_STATE_IDLE : ACORR_STATE_CALC;
|
||||
default: acorr_state <= ACORR_STATE_IDLE;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
stable_cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (acorr_state)
|
||||
ACORR_STATE_IDLE : stable_cnt <= 'b0;
|
||||
ACORR_STATE_STABLE: stable_cnt <= (stable_cnt == STABLE_CNT_MOD-1) ? 'b0 : stable_cnt + 1'b1;
|
||||
ACORR_STATE_CALC : stable_cnt <= 'b0;
|
||||
default: stable_cnt <= 'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
snapshot_cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (acorr_state)
|
||||
ACORR_STATE_IDLE : snapshot_cnt <= 'b0;
|
||||
ACORR_STATE_STABLE: snapshot_cnt <= 'b0;
|
||||
ACORR_STATE_CALC : snapshot_cnt <= (snapshot_cnt == SNAPSHOT_NUM-1) ? 'b0 : snapshot_cnt + 1'b1;
|
||||
default: snapshot_cnt <= 'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
snapshot_valid <= 'b0;
|
||||
end
|
||||
else begin
|
||||
case (acorr_state)
|
||||
ACORR_STATE_IDLE : snapshot_valid <= 'b0;
|
||||
ACORR_STATE_STABLE: snapshot_valid <= 'b0;
|
||||
ACORR_STATE_CALC : snapshot_valid <= 1'b1;
|
||||
default: snapshot_valid <= 'b0;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
fifo_cdc_rst <= 'b0;
|
||||
end
|
||||
else if (acorr_state == ACORR_STATE_STABLE) begin
|
||||
fifo_cdc_rst <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
fifo_cdc_rst <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////// Autocorrelation of Snapshot Vector //////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// input data
|
||||
wire acorr_din_valid;
|
||||
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] acorr_din_real;
|
||||
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] acorr_din_imag;
|
||||
|
||||
assign acorr_din_valid = snapshot_valid;
|
||||
assign acorr_din_real = phase_comp_dout_data_real;
|
||||
assign acorr_din_imag = phase_comp_dout_data_imag;
|
||||
|
||||
// output data
|
||||
wire acorr_dout_valid;
|
||||
wire [CHANNEL_NUM*CHANNEL_NUM*ACORR_WIDTH-1:0] acorr_dout_real;
|
||||
wire [CHANNEL_NUM*CHANNEL_NUM*ACORR_WIDTH-1:0] acorr_dout_imag;
|
||||
|
||||
acorr_cmplx_col_vec #(
|
||||
.DATA_I_WIDTH (ADC_DATA_WIDTH ),
|
||||
.DATA_O_WIDTH (ACORR_WIDTH ),
|
||||
.COL_NUM (CHANNEL_NUM )
|
||||
) u_acorr (
|
||||
// clock & reset
|
||||
.clk (sys_clk ),
|
||||
.rst (sys_rst ),
|
||||
|
||||
// input data
|
||||
.din_valid (acorr_din_valid ),
|
||||
.din_real (acorr_din_real ),
|
||||
.din_imag (acorr_din_imag ),
|
||||
|
||||
// output data
|
||||
.dout_valid (acorr_dout_valid ),
|
||||
.dout_real (acorr_dout_real ),
|
||||
.dout_imag (acorr_dout_imag )
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////// Accumulation of Snapshot Autocorrelation Matrices ///////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// accumulation reset
|
||||
wire acc_rst; // [acc_rst] should assert before accumulation starts
|
||||
|
||||
assign acc_rst = hop_start_flag_cdc;
|
||||
|
||||
// input data
|
||||
wire accum_din_valid;
|
||||
wire [CHANNEL_NUM*CHANNEL_NUM*ACORR_WIDTH-1:0] accum_din_real;
|
||||
wire [CHANNEL_NUM*CHANNEL_NUM*ACORR_WIDTH-1:0] accum_din_imag;
|
||||
|
||||
assign accum_din_valid = acorr_dout_valid;
|
||||
assign accum_din_real = acorr_dout_real;
|
||||
assign accum_din_imag = acorr_dout_imag;
|
||||
|
||||
// output data
|
||||
wire accum_dout_valid;
|
||||
wire [CHANNEL_NUM*CHANNEL_NUM*PS_PL_WIDTH-1:0] accum_dout_real;
|
||||
wire [CHANNEL_NUM*CHANNEL_NUM*PS_PL_WIDTH-1:0] accum_dout_imag;
|
||||
|
||||
accum_cmplx_mat #(
|
||||
.ROW_NUM (CHANNEL_NUM ),
|
||||
.COL_NUM (CHANNEL_NUM ),
|
||||
.DATA_I_WIDTH (ACORR_WIDTH ),
|
||||
.DATA_ACC_WIDTH (ACCUM_WIDTH ),
|
||||
.DATA_O_WIDTH (PS_PL_WIDTH ),
|
||||
.ACC_NUM (SNAPSHOT_NUM )
|
||||
) u_accum_cmplx_mat
|
||||
(
|
||||
// clock & reset
|
||||
.clk (sys_clk ),
|
||||
.rst (sys_rst ),
|
||||
.acc_rst (acc_rst ), // [acc_rst] should assert before accumulation starts
|
||||
|
||||
// input data
|
||||
.din_valid (accum_din_valid ),
|
||||
.din_real (accum_din_real ),
|
||||
.din_imag (accum_din_imag ),
|
||||
|
||||
// output data
|
||||
.dout_valid (accum_dout_valid ),
|
||||
.dout_real (accum_dout_real ),
|
||||
.dout_imag (accum_dout_imag )
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////// 32-bit Matrix Element to 1-bit Stream Conversion ///////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// input data
|
||||
wire stream_din_valid;
|
||||
wire [CHANNEL_NUM*CHANNEL_NUM*PS_PL_WIDTH-1 : 0] stream_din_real;
|
||||
wire [CHANNEL_NUM*CHANNEL_NUM*PS_PL_WIDTH-1 : 0] stream_din_imag;
|
||||
|
||||
assign stream_din_valid = accum_dout_valid;
|
||||
assign stream_din_real = accum_dout_real;
|
||||
assign stream_din_imag = accum_dout_imag;
|
||||
|
||||
// output data
|
||||
wire stream_dout_valid;
|
||||
wire stream_dout_data;
|
||||
|
||||
assign accor_stream_valid = stream_dout_valid; // to module port
|
||||
assign accor_stream_data = stream_dout_data; // to module port
|
||||
|
||||
accor_mat_formatting #(
|
||||
.ROW_NUM (CHANNEL_NUM ),
|
||||
.COL_NUM (CHANNEL_NUM ),
|
||||
.DATA_I_WIDTH (PS_PL_WIDTH ),
|
||||
.FRAME_HEAD (ACCOR_FRAME_HEAD )
|
||||
) u_accor_mat_stream
|
||||
(
|
||||
// clock & reset
|
||||
.sys_clk (sys_clk ),
|
||||
.sys_rst (sys_rst ),
|
||||
.clk_96m (clk_96m ),
|
||||
.ant_rst (ant_rst ),
|
||||
|
||||
// input data, sync to [sys_clk]
|
||||
.din_valid (stream_din_valid ),
|
||||
.din_real (stream_din_real ),
|
||||
.din_imag (stream_din_imag ),
|
||||
.fifo_cdc_rst (fifo_cdc_rst ),
|
||||
|
||||
// output data, sync to [clk_96m]
|
||||
.dout_valid (stream_dout_valid ),
|
||||
.dout_data (stream_dout_data )
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////// 1-bit Stream to 32-bit Vector Element Conversion ///////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// input data
|
||||
wire weight_din_data;
|
||||
|
||||
assign weight_din_data = weight_stream_data;
|
||||
assign stream_din_real = accum_dout_real;
|
||||
assign stream_din_imag = accum_dout_imag;
|
||||
|
||||
// output data
|
||||
wire weight_dout_valid;
|
||||
wire [CHANNEL_NUM*WEIGHT_TRUNC_WIDTH-1 : 0] weight_dout_real;
|
||||
wire [CHANNEL_NUM*WEIGHT_TRUNC_WIDTH-1 : 0] weight_dout_imag;
|
||||
|
||||
weight_vec_formatting #(
|
||||
.COL_NUM (CHANNEL_NUM ),
|
||||
.WEIGHT_WIDTH (PS_PL_WIDTH ),
|
||||
.DATA_O_WIDTH (WEIGHT_TRUNC_WIDTH ),
|
||||
.FRAME_HEAD (WEIGHT_FRAME_HEAD )
|
||||
) u_weight_vec_formatting
|
||||
(
|
||||
// clock & reset
|
||||
.sys_clk (sys_clk ),
|
||||
.sys_rst (sys_rst ),
|
||||
.clk_96m (clk_96m ),
|
||||
.ant_rst (ant_rst ),
|
||||
|
||||
// input data, sync to [clk_96m]
|
||||
.din_data (weight_din_data ),
|
||||
|
||||
// sync to [sys_clk]
|
||||
.fifo_cdc_rst (fifo_cdc_rst ),
|
||||
|
||||
// output data, sync to [sys_clk]
|
||||
.dout_valid (weight_dout_valid ),
|
||||
.dout_real (weight_dout_real ),
|
||||
.dout_imag (weight_dout_imag )
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////// Spatial Filter ////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// input weight vector
|
||||
wire filter_weight_valid;
|
||||
wire [CHANNEL_NUM*WEIGHT_TRUNC_WIDTH-1 : 0] filter_weight_real;
|
||||
wire [CHANNEL_NUM*WEIGHT_TRUNC_WIDTH-1 : 0] filter_weight_imag;
|
||||
|
||||
assign filter_weight_valid = weight_dout_valid;
|
||||
assign filter_weight_real = weight_dout_real;
|
||||
assign filter_weight_imag = weight_dout_imag;
|
||||
|
||||
// input adc data
|
||||
wire filter_adc_valid;
|
||||
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] filter_adc_real;
|
||||
wire [CHANNEL_NUM*ADC_DATA_WIDTH-1 : 0] filter_adc_imag;
|
||||
|
||||
assign filter_adc_valid = phase_comp_dout_valid;
|
||||
assign filter_adc_real = phase_comp_dout_data_real;
|
||||
assign filter_adc_imag = phase_comp_dout_data_imag;
|
||||
|
||||
// output data
|
||||
wire filter_dout_valid;
|
||||
wire [OUTPUT_DATA_WIDTH-1 : 0] filter_dout_real;
|
||||
wire [OUTPUT_DATA_WIDTH-1 : 0] filter_dout_imag;
|
||||
|
||||
assign rx_data_valid = filter_dout_valid;
|
||||
assign rx_data_i = filter_dout_real;
|
||||
assign rx_data_q = filter_dout_imag;
|
||||
|
||||
spatial_filter #(
|
||||
.CHANNEL_NUM (CHANNEL_NUM ),
|
||||
.WEIGHT_WIDTH (WEIGHT_TRUNC_WIDTH ),
|
||||
.ADC_WIDTH (ADC_DATA_WIDTH ),
|
||||
.FILTER_O_WIDTH (OUTPUT_DATA_WIDTH )
|
||||
) u_spatial_filter
|
||||
(
|
||||
// clock & reset
|
||||
.clk (sys_clk ),
|
||||
.rst (sys_rst ),
|
||||
|
||||
// input weight vector
|
||||
.din_weight_valid (filter_weight_valid),
|
||||
.din_weight_real (filter_weight_real ),
|
||||
.din_weight_imag (filter_weight_imag ),
|
||||
|
||||
// input adc data
|
||||
.hop_start_flag (hop_start_flag_cdc ),
|
||||
.din_adc_valid (filter_adc_valid ),
|
||||
.din_adc_real (filter_adc_real ),
|
||||
.din_adc_imag (filter_adc_imag ),
|
||||
|
||||
// output data
|
||||
.dout_valid (filter_dout_valid ),
|
||||
.dout_real (filter_dout_real ),
|
||||
.dout_imag (filter_dout_imag )
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,250 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/11/16 11:18:28
|
||||
// Design Name:
|
||||
// Module Name: rx_pre_test
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module rx_pre_test
|
||||
#(
|
||||
parameter ADC_DATA_WIDTH = 12,
|
||||
parameter BYPASS_CAL = 0
|
||||
)
|
||||
(
|
||||
// clock & reset
|
||||
input sys_clk ,
|
||||
input sys_clk_4x ,
|
||||
input sys_rst ,
|
||||
// calc result
|
||||
input ad9361_cal_result ,
|
||||
input ad9361_cal_valid ,
|
||||
//
|
||||
input hop_trigger ,
|
||||
input hop_trigger_en ,
|
||||
// output test data
|
||||
output [ADC_DATA_WIDTH-1:0] rx_ch1_i ,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_ch1_q ,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_ch2_i ,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_ch2_q ,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_ch3_i ,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_ch3_q ,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_ch4_i ,
|
||||
output [ADC_DATA_WIDTH-1:0] rx_ch4_q ,
|
||||
output hop_start_flag
|
||||
);
|
||||
|
||||
localparam HOP_CNT_MOD_192M = 192*200;
|
||||
localparam HOP_CNT_MOD_48M = 48*200;
|
||||
|
||||
// data valid cdc
|
||||
wire ad9361_cal_valid_cdc;
|
||||
|
||||
xpm_cdc_single #(
|
||||
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.SIM_ASSERT_CHK (0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
.SRC_INPUT_REG (1) // DECIMAL; 0=do not register input, 1=register input
|
||||
) u_ad9361_cal_valid_cdc
|
||||
(
|
||||
.dest_out (ad9361_cal_valid_cdc ), // 1-bit output: src_in synchronized to the destination clock domain. This output is
|
||||
// registered.
|
||||
.dest_clk (sys_clk_4x ), // 1-bit input: Clock signal for the destination clock domain.
|
||||
.src_clk (sys_clk ), // 1-bit input: optional; required when SRC_INPUT_REG = 1
|
||||
.src_in (ad9361_cal_valid ) // 1-bit input: Input signal to be synchronized to dest_clk domain.
|
||||
);
|
||||
|
||||
// auto hop flag generation
|
||||
reg [$clog2(HOP_CNT_MOD_192M)-1 : 0] hop_cnt_192m = 'b0;
|
||||
reg hop_flag_auto = 'b0;
|
||||
|
||||
always @(posedge sys_clk_4x) begin
|
||||
if (sys_rst) begin
|
||||
hop_cnt_192m = 'b0;
|
||||
hop_flag_auto = 'b0;
|
||||
end
|
||||
else if (ad9361_cal_valid_cdc) begin
|
||||
hop_cnt_192m <= (hop_cnt_192m == HOP_CNT_MOD_192M-1) ? 'b0 : hop_cnt_192m + 1'b1;
|
||||
hop_flag_auto <= (hop_cnt_192m == 20) ? 1'b1 : 1'b0;
|
||||
end
|
||||
else begin
|
||||
hop_cnt_192m <= 'b0;
|
||||
hop_flag_auto = 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// manual hop flag generation
|
||||
reg hop_flag_manual = 'b0;
|
||||
reg hop_trigger_d1 = 'b0;
|
||||
|
||||
always @(posedge sys_clk_4x) begin
|
||||
hop_trigger_d1 <= hop_trigger;
|
||||
end
|
||||
|
||||
always @(posedge sys_clk_4x) begin
|
||||
if (sys_rst) begin
|
||||
hop_flag_manual <= 'b0;
|
||||
end
|
||||
else if (ad9361_cal_valid_cdc) begin
|
||||
if (~hop_trigger_d1 && hop_trigger) begin
|
||||
hop_flag_manual <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
hop_flag_manual <= 1'b0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
hop_flag_manual <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// output hop flag
|
||||
reg hop_start_flag_buf = 'b0;
|
||||
|
||||
assign hop_start_flag = hop_start_flag_buf;
|
||||
|
||||
always @(posedge sys_clk_4x) begin
|
||||
if (sys_rst) begin
|
||||
hop_start_flag_buf <= 'b0;
|
||||
end
|
||||
else begin
|
||||
if (hop_trigger_en) begin
|
||||
hop_start_flag_buf <= hop_flag_manual;
|
||||
end
|
||||
else begin
|
||||
hop_start_flag_buf <= hop_flag_auto;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// hop flag cdc
|
||||
wire hop_flag_cdc;
|
||||
|
||||
xpm_cdc_pulse #(
|
||||
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.REG_OUTPUT (0), // DECIMAL; 0=disable registered output, 1=enable registered output
|
||||
.RST_USED (1), // DECIMAL; 0=no reset, 1=implement reset
|
||||
.SIM_ASSERT_CHK (0) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
) u_hop_flag_cdc
|
||||
(
|
||||
.dest_pulse (hop_flag_cdc ), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
|
||||
// transfer is correctly initiated on src_pulse input. This output is
|
||||
// combinatorial unless REG_OUTPUT is set to 1.
|
||||
.dest_clk (sys_clk ), // 1-bit input: Destination clock.
|
||||
.dest_rst (sys_rst ), // 1-bit input: optional; required when RST_USED = 1
|
||||
.src_clk (sys_clk_4x ), // 1-bit input: Source clock.
|
||||
.src_pulse (hop_start_flag_buf ), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
|
||||
// destination clock domain. The minimum gap between each pulse transfer must be
|
||||
// at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
|
||||
// between the falling edge of a src_pulse to the rising edge of the next
|
||||
// src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
|
||||
// will generate a pulse the size of one dest_clk period in the destination
|
||||
// clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
|
||||
// src_rst and/or dest_rst are asserted.
|
||||
.src_rst (sys_rst ) // 1-bit input: optional; required when RST_USED = 1
|
||||
);
|
||||
|
||||
// data rom address counter
|
||||
reg [$clog2(HOP_CNT_MOD_48M)-1 : 0] hop_cnt_48m = 'b0;
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
hop_cnt_48m <= 2'd2;
|
||||
end
|
||||
else if (ad9361_cal_valid) begin
|
||||
if (hop_flag_cdc) begin
|
||||
hop_cnt_48m = 2'd2;
|
||||
end
|
||||
else begin
|
||||
hop_cnt_48m <= (hop_cnt_48m == HOP_CNT_MOD_48M-1 || hop_flag_cdc) ? 'b0 : hop_cnt_48m + 1'b1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
hop_cnt_48m <= 2'd2;
|
||||
end
|
||||
end
|
||||
|
||||
// rom interface
|
||||
wire [95:0] hop_data;
|
||||
|
||||
wire [11:0] rom_ch1_i,rom_ch2_i,rom_ch3_i,rom_ch4_i;
|
||||
wire [11:0] rom_ch1_q,rom_ch2_q,rom_ch3_q,rom_ch4_q;
|
||||
|
||||
assign {rom_ch1_i,rom_ch2_i,rom_ch3_i,rom_ch4_i,
|
||||
rom_ch1_q,rom_ch2_q,rom_ch3_q,rom_ch4_q} = hop_data;
|
||||
|
||||
rom_hop_data u_rom_hop_data
|
||||
(
|
||||
.clka (sys_clk ), // input wire clka
|
||||
.addra (hop_cnt_48m), // input wire [13 : 0] addra
|
||||
.douta (hop_data ) // output wire [95 : 0] douta
|
||||
);
|
||||
|
||||
reg [11:0] rom_ch1_i_buf,rom_ch2_i_buf,rom_ch3_i_buf,rom_ch4_i_buf;
|
||||
reg [11:0] rom_ch1_q_buf,rom_ch2_q_buf,rom_ch3_q_buf,rom_ch4_q_buf;
|
||||
|
||||
assign rx_ch1_i = rom_ch1_i_buf;
|
||||
assign rx_ch1_q = rom_ch1_q_buf;
|
||||
assign rx_ch2_i = rom_ch2_i_buf;
|
||||
assign rx_ch2_q = rom_ch2_q_buf;
|
||||
assign rx_ch3_i = rom_ch3_i_buf;
|
||||
assign rx_ch3_q = rom_ch3_q_buf;
|
||||
assign rx_ch4_i = rom_ch4_i_buf;
|
||||
assign rx_ch4_q = rom_ch4_q_buf;
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (BYPASS_CAL) begin
|
||||
rom_ch1_i_buf <= rom_ch1_i;
|
||||
rom_ch1_q_buf <= rom_ch1_q;
|
||||
rom_ch2_i_buf <= rom_ch2_i;
|
||||
rom_ch2_q_buf <= rom_ch2_q;
|
||||
rom_ch3_i_buf <= rom_ch3_i;
|
||||
rom_ch3_q_buf <= rom_ch3_q;
|
||||
rom_ch4_i_buf <= rom_ch4_i;
|
||||
rom_ch4_q_buf <= rom_ch4_q;
|
||||
end
|
||||
else begin
|
||||
if (ad9361_cal_result) begin
|
||||
rom_ch1_i_buf <= rom_ch1_i;
|
||||
rom_ch1_q_buf <= rom_ch1_q;
|
||||
rom_ch2_i_buf <= -rom_ch2_i;
|
||||
rom_ch2_q_buf <= -rom_ch2_q;
|
||||
rom_ch3_i_buf <= -rom_ch3_i;
|
||||
rom_ch3_q_buf <= -rom_ch3_q;
|
||||
rom_ch4_i_buf <= rom_ch4_i;
|
||||
rom_ch4_q_buf <= rom_ch4_q;
|
||||
end
|
||||
else begin
|
||||
rom_ch1_i_buf <= rom_ch1_i;
|
||||
rom_ch1_q_buf <= rom_ch1_q;
|
||||
rom_ch2_i_buf <= -rom_ch2_i;
|
||||
rom_ch2_q_buf <= -rom_ch2_q;
|
||||
rom_ch3_i_buf <= rom_ch3_i;
|
||||
rom_ch3_q_buf <= rom_ch3_q;
|
||||
rom_ch4_i_buf <= -rom_ch4_i;
|
||||
rom_ch4_q_buf <= -rom_ch4_q;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,270 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/11/11 17:05:31
|
||||
// Design Name:
|
||||
// Module Name: spatial_filter
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// 20230404-1037 - 将权矢量和数据对齐，增加 [last_hop_weight_d1] 补偿 RAM 读数
|
||||
// 的延迟。
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module spatial_filter
|
||||
#(
|
||||
parameter CHANNEL_NUM = 4,
|
||||
parameter WEIGHT_WIDTH = 16,
|
||||
parameter ADC_WIDTH = 12,
|
||||
parameter FILTER_O_WIDTH = ADC_WIDTH
|
||||
)
|
||||
(
|
||||
// clock & reset
|
||||
input clk,
|
||||
input rst,
|
||||
|
||||
// input weight vector
|
||||
input din_weight_valid,
|
||||
input [CHANNEL_NUM*WEIGHT_WIDTH-1 : 0] din_weight_real,
|
||||
input [CHANNEL_NUM*WEIGHT_WIDTH-1 : 0] din_weight_imag,
|
||||
|
||||
// input adc data
|
||||
input hop_start_flag,
|
||||
input din_adc_valid,
|
||||
input [CHANNEL_NUM*ADC_WIDTH-1 : 0] din_adc_real,
|
||||
input [CHANNEL_NUM*ADC_WIDTH-1 : 0] din_adc_imag,
|
||||
|
||||
// output data
|
||||
output dout_valid,
|
||||
output [FILTER_O_WIDTH-1 : 0] dout_real,
|
||||
output [FILTER_O_WIDTH-1 : 0] dout_imag
|
||||
);
|
||||
|
||||
localparam RAM_HOP_DEPTH = 9728;
|
||||
localparam CMPLX_DIM = 2;
|
||||
|
||||
localparam FILTER_MULT_FULL_WIDTH = WEIGHT_WIDTH+ADC_WIDTH+1;
|
||||
localparam FILTER_MULT_VALID_WIDTH = WEIGHT_WIDTH+ADC_WIDTH;
|
||||
localparam FILTER_SUM_WIDTH = FILTER_MULT_VALID_WIDTH+$clog2(CHANNEL_NUM);
|
||||
localparam AXIS_WEIGHT_WIDTH = 8*((WEIGHT_WIDTH-1)/8+1); // axis data width of input weight vector real/image data
|
||||
localparam AXIS_ADC_I_WIDTH = 8*((ADC_WIDTH-1)/8+1) ; // axis data width of input adc real/image data
|
||||
localparam AXIS_FILTER_WIDTH = 8*((FILTER_MULT_FULL_WIDTH-1)/8+1) ; // axis data width of cmpy output real/image data
|
||||
|
||||
genvar i;
|
||||
|
||||
|
||||
// store current hop & restore last hop weight
|
||||
reg [CMPLX_DIM*CHANNEL_NUM*WEIGHT_WIDTH-1 : 0] current_hop_weight = 'b0;
|
||||
reg [CMPLX_DIM*CHANNEL_NUM*WEIGHT_WIDTH-1 : 0] last_hop_weight = 'b0;
|
||||
reg [CMPLX_DIM*CHANNEL_NUM*WEIGHT_WIDTH-1 : 0] last_hop_weight_d1 = 'b0; // wait for ram data
|
||||
|
||||
wire [CHANNEL_NUM*WEIGHT_WIDTH-1 : 0] last_weight_real;
|
||||
wire [CHANNEL_NUM*WEIGHT_WIDTH-1 : 0] last_weight_imag;
|
||||
|
||||
assign {last_weight_imag,last_weight_real} = last_hop_weight_d1;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
current_hop_weight <= 'b0;
|
||||
end
|
||||
else begin
|
||||
current_hop_weight <= (din_weight_valid) ? {din_weight_imag,din_weight_real} : current_hop_weight;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
last_hop_weight <= 'b0;
|
||||
end
|
||||
else begin
|
||||
last_hop_weight <= (hop_start_flag) ? current_hop_weight : last_hop_weight;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
last_hop_weight_d1 <= 'b0;
|
||||
end
|
||||
else begin
|
||||
last_hop_weight_d1 <= last_hop_weight;
|
||||
end
|
||||
end
|
||||
|
||||
// store current hop & restore last hop data
|
||||
wire [CMPLX_DIM*CHANNEL_NUM*ADC_WIDTH-1 : 0] current_hop_data;
|
||||
reg last_hop_valid = 'b0;
|
||||
wire [CMPLX_DIM*CHANNEL_NUM*ADC_WIDTH-1 : 0] last_hop_data;
|
||||
|
||||
wire [CHANNEL_NUM*ADC_WIDTH-1 : 0] last_data_real;
|
||||
wire [CHANNEL_NUM*ADC_WIDTH-1 : 0] last_data_imag;
|
||||
|
||||
reg [$clog2(RAM_HOP_DEPTH)-1 : 0] hop_data_cnt = 'b0;
|
||||
|
||||
assign current_hop_data = {din_adc_imag,din_adc_real};
|
||||
assign {last_data_imag,last_data_real} = last_hop_data;
|
||||
|
||||
always @(posedge clk) begin
|
||||
last_hop_valid <= din_adc_valid;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
hop_data_cnt <= 'b0;
|
||||
end
|
||||
else if(din_adc_valid) begin
|
||||
if (hop_start_flag) begin
|
||||
hop_data_cnt <= 'b0;
|
||||
end
|
||||
else if (hop_data_cnt == RAM_HOP_DEPTH-1) begin
|
||||
hop_data_cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
hop_data_cnt <= hop_data_cnt + 1'b1;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
hop_data_cnt <= hop_data_cnt;
|
||||
end
|
||||
end
|
||||
|
||||
ram_hop_data u_ram_hop_data
|
||||
(
|
||||
.clka (clk ), // input wire clka
|
||||
.wea (din_adc_valid ), // input wire [0 : 0] wea
|
||||
.addra(hop_data_cnt ), // input wire [13 : 0] addra
|
||||
.dina (current_hop_data ), // input wire [95 : 0] dina
|
||||
.douta(last_hop_data ) // output wire [95 : 0] douta
|
||||
);
|
||||
|
||||
// prepare cmpy input data
|
||||
wire [AXIS_WEIGHT_WIDTH-1:0] din_weight_real_array [0:CHANNEL_NUM-1];
|
||||
wire [AXIS_WEIGHT_WIDTH-1:0] din_weight_imag_array [0:CHANNEL_NUM-1];
|
||||
|
||||
wire [AXIS_ADC_I_WIDTH-1:0] din_adc_real_array [0:CHANNEL_NUM-1];
|
||||
wire [AXIS_ADC_I_WIDTH-1:0] din_adc_imag_array [0:CHANNEL_NUM-1];
|
||||
|
||||
generate
|
||||
for(i = 0; i < CHANNEL_NUM; i = i + 1) begin: weight_array_convert
|
||||
// Sign extension to fit 8-bit axis data format
|
||||
assign din_weight_real_array[i] = {{(AXIS_WEIGHT_WIDTH-WEIGHT_WIDTH){last_weight_real[(i+1)*WEIGHT_WIDTH-1]}},last_weight_real[i*WEIGHT_WIDTH +: WEIGHT_WIDTH]};
|
||||
assign din_weight_imag_array[i] = {{(AXIS_WEIGHT_WIDTH-WEIGHT_WIDTH){last_weight_imag[(i+1)*WEIGHT_WIDTH-1]}},last_weight_imag[i*WEIGHT_WIDTH +: WEIGHT_WIDTH]};
|
||||
|
||||
assign din_adc_real_array[i] = {{(AXIS_ADC_I_WIDTH-ADC_WIDTH){last_data_real[(i+1)*ADC_WIDTH-1]}},last_data_real[i*ADC_WIDTH +: ADC_WIDTH]};
|
||||
assign din_adc_imag_array[i] = {{(AXIS_ADC_I_WIDTH-ADC_WIDTH){last_data_imag[(i+1)*ADC_WIDTH-1]}},last_data_imag[i*ADC_WIDTH +: ADC_WIDTH]};
|
||||
end
|
||||
endgenerate
|
||||
|
||||
// complex multiplication, spatial filtering
|
||||
wire [AXIS_FILTER_WIDTH-1:0] cmpy_real_array [0:CHANNEL_NUM-1];
|
||||
wire [AXIS_FILTER_WIDTH-1:0] cmpy_imag_array [0:CHANNEL_NUM-1];
|
||||
|
||||
wire [FILTER_MULT_VALID_WIDTH-1:0] weight_adc_real_array [0:CHANNEL_NUM-1];
|
||||
wire [FILTER_MULT_VALID_WIDTH-1:0] weight_adc_imag_array [0:CHANNEL_NUM-1];
|
||||
|
||||
wire weight_adc_valid;
|
||||
wire [CHANNEL_NUM*FILTER_MULT_VALID_WIDTH-1:0] weight_adc_real;
|
||||
wire [CHANNEL_NUM*FILTER_MULT_VALID_WIDTH-1:0] weight_adc_imag;
|
||||
|
||||
generate
|
||||
for(i = 0; i < CHANNEL_NUM; i = i + 1) begin: spatial_filter_cmpy
|
||||
wire [2*AXIS_WEIGHT_WIDTH-1:0] cmpy_a;
|
||||
wire [2*AXIS_ADC_I_WIDTH-1:0] cmpy_b;
|
||||
wire [2*AXIS_FILTER_WIDTH-1:0] cmpy_p;
|
||||
wire cmpy_p_vld;
|
||||
|
||||
assign cmpy_a = {-din_weight_imag_array[i],din_weight_real_array[i]};
|
||||
assign cmpy_b = {din_adc_imag_array[i],din_adc_real_array[i]};
|
||||
assign {cmpy_imag_array[i],cmpy_real_array[i]} = cmpy_p;
|
||||
|
||||
assign weight_adc_real_array[i] = cmpy_real_array[i][0 +: FILTER_MULT_VALID_WIDTH];
|
||||
assign weight_adc_imag_array[i] = cmpy_imag_array[i][0 +: FILTER_MULT_VALID_WIDTH];
|
||||
|
||||
assign weight_adc_real[i*FILTER_MULT_VALID_WIDTH +: FILTER_MULT_VALID_WIDTH] = weight_adc_real_array[i];
|
||||
assign weight_adc_imag[i*FILTER_MULT_VALID_WIDTH +: FILTER_MULT_VALID_WIDTH] = weight_adc_imag_array[i];
|
||||
|
||||
cmpy_16x12 u_cmpy_16x12
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_a_tvalid (last_hop_valid ), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid (last_hop_valid ), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata (cmpy_b ), // input wire [31 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign weight_adc_valid = spatial_filter_cmpy[0].cmpy_p_vld;
|
||||
|
||||
// multi-channel sum
|
||||
wire weight_adc_sum_valid;
|
||||
wire [FILTER_SUM_WIDTH-1 : 0] weight_adc_sum_real;
|
||||
wire [FILTER_SUM_WIDTH-1 : 0] weight_adc_sum_imag;
|
||||
|
||||
adder_tree_ppl #(
|
||||
.DATA_I_WIDTH (FILTER_MULT_VALID_WIDTH),
|
||||
.DATA_NUM (CHANNEL_NUM )
|
||||
) u_multi_ch_add_ppl_i (
|
||||
// clock & reset
|
||||
.clk (clk ),
|
||||
.rst (rst ),
|
||||
|
||||
// input data
|
||||
.din_valid (weight_adc_valid ),
|
||||
.din_data (weight_adc_real ),
|
||||
|
||||
// output data
|
||||
.dout_valid (weight_adc_sum_valid ),
|
||||
.dout_data (weight_adc_sum_real )
|
||||
);
|
||||
|
||||
adder_tree_ppl #(
|
||||
.DATA_I_WIDTH (FILTER_MULT_VALID_WIDTH),
|
||||
.DATA_NUM (CHANNEL_NUM )
|
||||
) u_multi_ch_add_ppl_q (
|
||||
// clock & reset
|
||||
.clk (clk ),
|
||||
.rst (rst ),
|
||||
|
||||
// input data
|
||||
.din_valid (weight_adc_valid ),
|
||||
.din_data (weight_adc_imag ),
|
||||
|
||||
// output data
|
||||
.dout_valid ( ),
|
||||
.dout_data (weight_adc_sum_imag )
|
||||
);
|
||||
|
||||
// output filtered signal
|
||||
assign dout_valid = weight_adc_sum_valid;
|
||||
|
||||
if (FILTER_O_WIDTH <= FILTER_SUM_WIDTH) begin
|
||||
assign dout_real = weight_adc_sum_real[FILTER_SUM_WIDTH-1 -: FILTER_O_WIDTH];
|
||||
assign dout_imag = weight_adc_sum_imag[FILTER_SUM_WIDTH-1 -: FILTER_O_WIDTH];
|
||||
end
|
||||
else begin
|
||||
assign dout_real = {{(FILTER_O_WIDTH-FILTER_SUM_WIDTH){weight_adc_sum_real[FILTER_SUM_WIDTH-1]}},weight_adc_sum_real};
|
||||
assign dout_imag = {{(FILTER_O_WIDTH-FILTER_SUM_WIDTH){weight_adc_sum_imag[FILTER_SUM_WIDTH-1]}},weight_adc_sum_imag};
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
// This module has been tested during the simulation of [rx_pre_process]
|
||||
@@ -0,0 +1,410 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/11/10 11:48:23
|
||||
// Design Name:
|
||||
// Module Name: weight_vec_formatting
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: Format the input 1-bit stream to weight vector.
|
||||
// Parameter:
|
||||
// COL_NUM: Column number of output vector.
|
||||
// WEIGHT_WIDTH: Bit width of input weight vector element (retrieve from
|
||||
// stream data).
|
||||
// DATA_O_WIDTH: Bit width of output vector element, and bit width of
|
||||
// FRAME_HEAD: Frame head indicate weight vector frame.
|
||||
// FIFO_CDC_DEPTH: Depth of [clk_96m] to [sys_clk] cdc fifo.
|
||||
// Data format:
|
||||
// din_data: Suppose the output vector x = [x11 x21 x31 x41]^T, then
|
||||
// din_data = {FRAME_HEAD[msb], ..., FRAME_HEAD[lsb], FRAME_LEN[msb],
|
||||
// ..., FRAME_LEN[lsb], Re{x11}[msb], ..., Re{x11}[lsb], Im{x11}[msb], ...,
|
||||
// Im{x11}[lsb], ..., Re{x41}[msb], ......, Im{x41}[lsb]}
|
||||
// dout_valid: Indicate [dout_data] is valid.
|
||||
// dout_real/imag:
|
||||
// dout_real = {Re{x41}, Re{x31}, Re{x21}, Re{x11}}
|
||||
// dout_imag = {Im{x41}, Im{x31}, Im{x21}, Im{x11}}
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module weight_vec_formatting
|
||||
#(
|
||||
parameter COL_NUM = 4,
|
||||
parameter WEIGHT_WIDTH = 32,
|
||||
parameter DATA_O_WIDTH = 16,
|
||||
parameter FRAME_HEAD = 32'h7E7E7E7E,
|
||||
parameter FIFO_CDC_DEPTH = 32
|
||||
)
|
||||
(
|
||||
// clock & reset
|
||||
input sys_clk,
|
||||
input sys_rst,
|
||||
input clk_96m,
|
||||
input ant_rst,
|
||||
|
||||
// input data
|
||||
input din_data,
|
||||
|
||||
input fifo_cdc_rst,
|
||||
|
||||
// output data
|
||||
output dout_valid,
|
||||
output [COL_NUM*DATA_O_WIDTH-1 : 0] dout_real,
|
||||
output [COL_NUM*DATA_O_WIDTH-1 : 0] dout_imag
|
||||
);
|
||||
|
||||
localparam CMPLX_DIM = 2;
|
||||
localparam FRAME_LEN = COL_NUM*CMPLX_DIM;
|
||||
localparam BYTE_LEN = 4 * (COL_NUM*CMPLX_DIM + 2);
|
||||
|
||||
// available state
|
||||
localparam STATE_NUM_DIN = 3;
|
||||
localparam STATE_IDLE_DIN = 0;
|
||||
localparam STATE_LEN_DIN = 1;
|
||||
localparam STATE_DATA_DIN = 2;
|
||||
|
||||
localparam STATE_NUM_DOUT = 2;
|
||||
localparam STATE_IDLE_DOUT = 0;
|
||||
localparam STATE_READ_DOUT = 1;
|
||||
|
||||
genvar i;
|
||||
integer m;
|
||||
|
||||
// input data shift register
|
||||
reg [WEIGHT_WIDTH-1 : 0] din_shift = 'b0;
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
din_shift <= 'b0;
|
||||
end
|
||||
else begin
|
||||
din_shift <= {din_shift[WEIGHT_WIDTH-2 : 0],din_data};
|
||||
end
|
||||
end
|
||||
|
||||
// input data center state machine & counter
|
||||
reg [$clog2(STATE_NUM_DIN)-1 : 0] state_din = STATE_IDLE_DIN;
|
||||
reg [$clog2(WEIGHT_WIDTH)-1 : 0] bit_cnt = 'b0; // bit counter within one frame
|
||||
reg [$clog2(FRAME_LEN)-1 : 0] frame_cnt = 'b0; // frame counter
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
state_din <= STATE_IDLE_DIN;
|
||||
end
|
||||
else begin
|
||||
case (state_din)
|
||||
STATE_IDLE_DIN: state_din <= (din_shift == FRAME_HEAD) ? STATE_LEN_DIN : STATE_IDLE_DIN;
|
||||
STATE_LEN_DIN : begin
|
||||
if (bit_cnt == WEIGHT_WIDTH-1) begin
|
||||
state_din <= (din_shift == BYTE_LEN) ? STATE_DATA_DIN : STATE_IDLE_DIN;
|
||||
end
|
||||
else begin
|
||||
state_din <= STATE_LEN_DIN;
|
||||
end
|
||||
end
|
||||
STATE_DATA_DIN: state_din <= (frame_cnt == FRAME_LEN-1 && bit_cnt == WEIGHT_WIDTH-1) ? STATE_IDLE_DIN : STATE_DATA_DIN;
|
||||
default: state_din <= STATE_IDLE_DIN;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
bit_cnt <= 'b0;
|
||||
end
|
||||
else if (state_din == STATE_IDLE_DIN) begin
|
||||
bit_cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
bit_cnt <= (bit_cnt == WEIGHT_WIDTH-1) ? 'b0 : bit_cnt + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
frame_cnt <= 'b0;
|
||||
end
|
||||
else if (state_din == STATE_IDLE_DIN) begin
|
||||
frame_cnt <= 'b0;
|
||||
end
|
||||
else if (state_din == STATE_DATA_DIN && bit_cnt == WEIGHT_WIDTH-1) begin
|
||||
frame_cnt <= frame_cnt + 1'b1;
|
||||
end
|
||||
else begin
|
||||
frame_cnt <= frame_cnt;
|
||||
end
|
||||
end
|
||||
|
||||
// clock domain crossing fifo, write channel
|
||||
reg [DATA_O_WIDTH-1 : 0] fifo_din = 'b0;
|
||||
reg fifo_wr_en = 'b0;
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
fifo_din <= 'b0;
|
||||
fifo_wr_en <= 'b0;
|
||||
end
|
||||
else if (state_din == STATE_DATA_DIN && bit_cnt == DATA_O_WIDTH-1) begin
|
||||
fifo_din <= din_shift[DATA_O_WIDTH-1 -: DATA_O_WIDTH];
|
||||
fifo_wr_en <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
fifo_din <= fifo_din;
|
||||
fifo_wr_en <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// clock domain crossing fifo, read channel
|
||||
reg fifo_rd_en = 'b0;
|
||||
reg fifo_rd_en_d1 = 'b0;
|
||||
reg [$clog2(COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt = 'b0;
|
||||
reg [$clog2(COL_NUM*CMPLX_DIM)-1 : 0] fifo_rd_cnt_d1 = 'b0; // read data latency
|
||||
reg fifo_rd_valid = 'b0;
|
||||
wire [DATA_O_WIDTH-1 : 0] fifo_dout;
|
||||
wire [$clog2(COL_NUM*CMPLX_DIM*2)-1 : 0] fifo_rd_num;
|
||||
wire fifo_full;
|
||||
wire fifo_empty;
|
||||
reg [DATA_O_WIDTH-1 : 0] dout_array_cdc [0 : COL_NUM*CMPLX_DIM-1];
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
fifo_rd_en <= 'b0;
|
||||
end
|
||||
else if (fifo_rd_num == COL_NUM*CMPLX_DIM) begin
|
||||
fifo_rd_en <= 1'b1;
|
||||
end
|
||||
else if (fifo_rd_cnt == COL_NUM*CMPLX_DIM-1) begin
|
||||
fifo_rd_en <= 'b0;
|
||||
end
|
||||
else begin
|
||||
fifo_rd_en <= fifo_rd_en;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
fifo_rd_en_d1 <= 'b0;
|
||||
end
|
||||
else begin
|
||||
fifo_rd_en_d1 <= fifo_rd_en;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
fifo_rd_cnt <= 'b0;
|
||||
end
|
||||
else if (fifo_rd_en) begin
|
||||
fifo_rd_cnt <= fifo_rd_cnt + 1'b1;
|
||||
end
|
||||
else begin
|
||||
fifo_rd_cnt <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
fifo_rd_cnt_d1 <= 'b0;
|
||||
end
|
||||
else begin
|
||||
fifo_rd_cnt_d1 <= fifo_rd_cnt;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
fifo_rd_valid <= 'b0;
|
||||
end
|
||||
else if (fifo_rd_cnt_d1 == COL_NUM*CMPLX_DIM-1) begin
|
||||
fifo_rd_valid <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
fifo_rd_valid <= 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
for (m = 0; m < COL_NUM*CMPLX_DIM; m = m + 1) begin
|
||||
dout_array_cdc[m] <= 'b0;
|
||||
end
|
||||
end
|
||||
else if (fifo_rd_en_d1) begin
|
||||
dout_array_cdc[fifo_rd_cnt_d1] <= fifo_dout;
|
||||
end
|
||||
else begin
|
||||
for (m = 0; m < COL_NUM*CMPLX_DIM; m = m + 1) begin
|
||||
dout_array_cdc[m] <= dout_array_cdc[m];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
fifo_weight_cdc u_fifo_weight_cdc
|
||||
(
|
||||
.rst (fifo_cdc_rst ), // input wire rd_rst
|
||||
.wr_clk (clk_96m ), // input wire wr_clk
|
||||
.rd_clk (sys_clk ), // input wire rd_clk
|
||||
.din (fifo_din ), // input wire [15 : 0] din
|
||||
.wr_en (fifo_wr_en ), // input wire wr_en
|
||||
.rd_en (fifo_rd_en ), // input wire rd_en
|
||||
.dout (fifo_dout ), // output wire [15 : 0] dout
|
||||
.full (fifo_full ), // output wire full
|
||||
.empty (fifo_empty ), // output wire empty
|
||||
.rd_data_count (fifo_rd_num ) // output wire [3 : 0] rd_data_count
|
||||
);
|
||||
|
||||
// format output data array
|
||||
wire [DATA_O_WIDTH-1 : 0] dout_real_array [0 : COL_NUM-1];
|
||||
wire [DATA_O_WIDTH-1 : 0] dout_imag_array [0 : COL_NUM-1];
|
||||
|
||||
generate
|
||||
for(i = 0; i < COL_NUM; i = i + 1) begin: array_convert_stg1
|
||||
assign dout_real_array[i] = dout_array_cdc[2*i];
|
||||
assign dout_imag_array[i] = dout_array_cdc[2*i+1];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
for(i = 0; i < COL_NUM; i = i + 1) begin: array_convert_stg2
|
||||
assign dout_real[i*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_real_array[i];
|
||||
assign dout_imag[i*DATA_O_WIDTH +: DATA_O_WIDTH] = dout_imag_array[i];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
assign dout_valid = fifo_rd_valid;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/10/30 20:46:26
|
||||
// Design Name:
|
||||
// Module Name: tb_wvec_format
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: Testbench for [weight_vec_formatting]
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
// -------------------------------
|
||||
// MATLAB Code for data generation
|
||||
// -------------------------------
|
||||
// COLUMN_NUM = 4;
|
||||
// DATA_O_WIDTH = 32;
|
||||
|
||||
// rng(0);
|
||||
// data = rand(4,2)*2-1;
|
||||
// d_32b = round(data.*(2^(DATA_O_WIDTH-1)-1));
|
||||
// d_32b_cmplx = d_32b(:,1) + 1i*d_32b(:,2);
|
||||
|
||||
|
||||
// module tb_wvec_format;
|
||||
|
||||
// localparam ROW_NUM = 1;
|
||||
// localparam COL_NUM = 4;
|
||||
// localparam WEIGHT_WIDTH = 32;
|
||||
// localparam DATA_O_WIDTH = 16;
|
||||
// localparam FRAME_HEAD = 32'b10110011100011110000111000110010;
|
||||
// localparam FRAME_BITS = (2+COL_NUM*2)*WEIGHT_WIDTH + 1024;
|
||||
|
||||
// reg sys_clk = 1'b1;
|
||||
// reg sys_rst = 1'b1;
|
||||
// reg clk_96m = 1'b1;
|
||||
// reg ant_rst = 1'b1;
|
||||
// wire din_data;
|
||||
// reg [FRAME_BITS-1 : 0] din_buf =
|
||||
// {
|
||||
// FRAME_HEAD, 32'd40,
|
||||
// 32'd1351727940, 32'd568478634,
|
||||
// 32'd1742863098, -32'd1728550798,
|
||||
// -32'd1602079424, -32'd951342906,
|
||||
// 32'd1775435782, 32'd201354592,
|
||||
// 1024'd0
|
||||
// };
|
||||
|
||||
|
||||
// wire dout_valid;
|
||||
// wire [COL_NUM*DATA_O_WIDTH-1:0] dout_real, dout_imag;
|
||||
|
||||
// weight_vec_formatting #(
|
||||
// .COL_NUM (COL_NUM),
|
||||
// .DATA_O_WIDTH (DATA_O_WIDTH),
|
||||
// .WEIGHT_WIDTH (WEIGHT_WIDTH),
|
||||
// .FRAME_HEAD (FRAME_HEAD )
|
||||
// ) u_weight_vec_formatting
|
||||
// (
|
||||
// // clock & reset
|
||||
// .sys_clk (sys_clk ), // input sys_clk
|
||||
// .sys_rst (sys_rst ), // input sys_rst
|
||||
// .clk_96m (clk_96m ), // input clk_96m
|
||||
// .ant_rst (ant_rst ), // input ant_rst
|
||||
|
||||
// // input data
|
||||
// .din_data (din_data ),
|
||||
|
||||
// // output data
|
||||
// .dout_valid (dout_valid ),
|
||||
// .dout_real (dout_real ),
|
||||
// .dout_imag (dout_imag )
|
||||
// );
|
||||
|
||||
// always begin
|
||||
// #20 sys_clk = ~sys_clk;
|
||||
// end
|
||||
|
||||
// always begin
|
||||
// #7;
|
||||
// clk_96m = ~clk_96m;
|
||||
// #3;
|
||||
// end
|
||||
|
||||
// initial begin
|
||||
// #102
|
||||
// sys_rst = 1'b0;
|
||||
// ant_rst = 1'b0;
|
||||
// end
|
||||
|
||||
// reg [$clog2(FRAME_BITS)-1 : 0] din_cnt;
|
||||
|
||||
// always @(posedge clk_96m) begin
|
||||
// if (sys_rst) begin
|
||||
// din_cnt <= 'b0;
|
||||
// end
|
||||
// else begin
|
||||
// din_cnt <= (din_cnt == FRAME_BITS-1) ? 'b0 : din_cnt + 1'b1;
|
||||
// end
|
||||
// end
|
||||
|
||||
// assign din_data = din_buf[FRAME_BITS-1-din_cnt];
|
||||
|
||||
// endmodule
|
||||
@@ -0,0 +1,989 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2021/12/14 15:54:11
|
||||
// Design Name:
|
||||
// Module Name: system_top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module system_top
|
||||
(
|
||||
/***************************************************************************
|
||||
* Contents
|
||||
* 01. Clocks
|
||||
* 02. AD9516 Interface
|
||||
* 03. AD9361-1 Interface
|
||||
* 04. AD9361-2 Interface
|
||||
* 05. Phased-Array Control
|
||||
* 06. RF Synthesizer Control
|
||||
* 07. LVDS for Time Synchronization
|
||||
* 08. Debug IO
|
||||
**************************************************************************/
|
||||
|
||||
// *************************************************************************
|
||||
// ******************************** Clocks *********************************
|
||||
// *************************************************************************
|
||||
// power-up configure clock
|
||||
input clk_25m ,
|
||||
// 250mhz backup clock
|
||||
input clk_250m_p , // generated by ad9516, 250mhz
|
||||
input clk_250m_n ,
|
||||
// ad9361 buffered clock
|
||||
input ad9361_1_buffer_clk , // derived from ad9361 input clock
|
||||
input ad9361_2_buffer_clk , // derived from ad9361 input clock
|
||||
// *************************************************************************
|
||||
// *************************** AD9516 Interface ****************************
|
||||
// *************************************************************************
|
||||
// spi interface
|
||||
output ad9516_spi_clk ,
|
||||
output ad9516_spi_csn ,
|
||||
inout ad9516_spi_mosi ,
|
||||
input ad9516_spi_miso ,
|
||||
// control signals
|
||||
input ad9516_refmon , // ad9516 reference clock monitor
|
||||
input ad9516_ld , // ad9516 lock detect
|
||||
input ad9516_status , // ad9516 multiple selectable status output
|
||||
output ad9516_pd_b , // ad9516 active-low power down control
|
||||
output ad9516_reset_b , // ad9516 active-low reset control
|
||||
output ad9516_sync_b , // ad9516 active-low manual synchronization control
|
||||
// *************************************************************************
|
||||
// ************************** AD9361-1 Interface ***************************
|
||||
// *************************************************************************
|
||||
// rx data (rx channels are tied to ground physically)
|
||||
input ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
|
||||
input ad9361_1_rx_frame ,
|
||||
input [11:0] ad9361_1_rx_data ,
|
||||
// tx data
|
||||
output ad9361_1_tx_fb_clk ,
|
||||
output ad9361_1_tx_frame ,
|
||||
output [11:0] ad9361_1_tx_data ,
|
||||
// spi interface
|
||||
output ad9361_1_spi_clk ,
|
||||
output ad9361_1_spi_csn ,
|
||||
inout ad9361_1_spi_mosi ,
|
||||
input ad9361_1_spi_miso ,
|
||||
// control signals
|
||||
output ad9361_1_reset_b , // ad9361 active-low reset control
|
||||
output ad9361_1_en_agc , // ad9361 manual agc control
|
||||
output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
output [ 3:0] ad9361_1_ctrl_in ,
|
||||
input [ 7:0] ad9361_1_ctrl_out ,
|
||||
output ad9361_sync ,
|
||||
// *************************************************************************
|
||||
// ************************** AD9361-2 Interface ***************************
|
||||
// *************************************************************************
|
||||
// rx data (rx channels are tied to ground physically)
|
||||
input ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz
|
||||
input ad9361_2_rx_frame ,
|
||||
input [11:0] ad9361_2_rx_data ,
|
||||
// tx data
|
||||
output ad9361_2_tx_fb_clk ,
|
||||
output ad9361_2_tx_frame ,
|
||||
output [11:0] ad9361_2_tx_data ,
|
||||
// spi interface
|
||||
output ad9361_2_spi_clk ,
|
||||
output ad9361_2_spi_csn ,
|
||||
inout ad9361_2_spi_mosi ,
|
||||
input ad9361_2_spi_miso ,
|
||||
// control signals
|
||||
output ad9361_2_reset_b , // ad9361 active-low reset control
|
||||
output ad9361_2_en_agc , // ad9361 manual agc control
|
||||
output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
|
||||
output [ 3:0] ad9361_2_ctrl_in ,
|
||||
input [ 7:0] ad9361_2_ctrl_out ,
|
||||
// *************************************************************************
|
||||
// ************************* Phased-Array Control **************************
|
||||
// *************************************************************************
|
||||
output ant_cin ,
|
||||
output ant_din0 ,
|
||||
output ant_din1 ,
|
||||
input ant_cout ,
|
||||
input ant_dout0 ,
|
||||
input ant_dout1 ,
|
||||
output ant_tr ,
|
||||
output ant_dary ,
|
||||
// *************************************************************************
|
||||
// ************************ RF Synthesizer Control *************************
|
||||
// *************************************************************************
|
||||
output rf_standby ,
|
||||
output rf_sw_pll ,
|
||||
output rf_t ,
|
||||
output rf_r ,
|
||||
output rf_sw_bpf ,
|
||||
output rf_sclk1 ,
|
||||
output rf_sdio1 ,
|
||||
output rf_cs1 ,
|
||||
input rf_ld1 ,
|
||||
output rf_sclk2 ,
|
||||
output rf_sdio2 ,
|
||||
output rf_cs2 ,
|
||||
input rf_ld2 ,
|
||||
output rf_sclk3 ,
|
||||
output rf_sdio3 ,
|
||||
output rf_cs3 ,
|
||||
input rf_ld3 ,
|
||||
output rf_tmgc_16 ,
|
||||
output rf_tmgc_8 ,
|
||||
output rf_tmgc_4 ,
|
||||
output rf_tmgc_2 ,
|
||||
output rf_tmgc_1 ,
|
||||
output rf_rmgc_16 ,
|
||||
output rf_rmgc_8 ,
|
||||
output rf_rmgc_4 ,
|
||||
output rf_rmgc_2 ,
|
||||
output rf_rmgc_1 ,
|
||||
output rf_enable ,
|
||||
output rf_sc ,
|
||||
output rf_sd ,
|
||||
output rf_endsyn ,
|
||||
input rf_sdout ,
|
||||
inout rf_dq_wd ,
|
||||
output rf_sw_rx ,
|
||||
// *************************************************************************
|
||||
// ********************* LVDS for Time Synchronization *********************
|
||||
// *************************************************************************
|
||||
// 1st group
|
||||
input lvds_in_1 ,
|
||||
output lvds_out_1 ,
|
||||
// 2nd group (these pins can be disconnected physically)
|
||||
input lvds_in_2 ,
|
||||
output lvds_out_2 ,
|
||||
// *************************************************************************
|
||||
// ******************************* Debug IO ********************************
|
||||
// *************************************************************************
|
||||
// 3.3v ports
|
||||
output uart1_txd ,
|
||||
input uart1_rxd ,
|
||||
output uart2_txd ,
|
||||
input uart2_rxd ,
|
||||
output uart3_txd ,
|
||||
input uart3_rxd ,
|
||||
inout debug_io_1 ,
|
||||
inout debug_io_2 ,
|
||||
inout debug_io_3 ,
|
||||
inout debug_io_4 ,
|
||||
inout debug_io_5 ,
|
||||
inout debug_io_6 ,
|
||||
inout debug_io_7 ,
|
||||
inout debug_io_8 ,
|
||||
// 1.8v ports
|
||||
inout debug_io_00_p ,
|
||||
inout debug_io_01_p ,
|
||||
inout debug_io_02_p ,
|
||||
inout debug_io_03_p ,
|
||||
inout debug_io_04_p ,
|
||||
inout debug_io_05_p ,
|
||||
inout debug_io_06_p ,
|
||||
inout debug_io_07_p ,
|
||||
inout debug_io_08_p
|
||||
);
|
||||
|
||||
/*******************************************************************************
|
||||
* Contents
|
||||
* 01. Input/Output Buffer
|
||||
* 02. System Clock Generation
|
||||
* 03. Block Design Interface
|
||||
* 04. Phased-Array Control
|
||||
* 05. RF Synthesizer Control
|
||||
* 06. LVDS for Time Synchronization
|
||||
* 07. Tx Signals
|
||||
* 08. Rx Signals
|
||||
* 09. ILAs and VIOs
|
||||
******************************************************************************/
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////// System Clock Generation ////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// global reset
|
||||
wire sys_rst ; // global reset signal, active high
|
||||
wire ant_rst ; // phased-array & rf control reset signal, active high
|
||||
|
||||
// pl signal processing clock
|
||||
wire sys_clk ; // 48MHz 41.6667MHz
|
||||
wire sys_clk_2x ; // 96MHz 83.3333MHz
|
||||
wire sys_clk_3x ; // 144MHz 125MHz
|
||||
wire sys_clk_4x ; // 192MHz 166.6667MHz
|
||||
wire sys_clk_ld ; // system main clock locked indicator
|
||||
|
||||
// ad9361-1 clocks
|
||||
wire ad9361_1_clk ; // 48MHz 41.6667MHz
|
||||
wire ad9361_1_clk_2x ; // 96MHz 83.3333MHz
|
||||
wire ad9361_1_clk_3x ; // 144MHz 125MHz
|
||||
wire ad9361_1_clk_4x ; // 192MHz 166.6667MHz
|
||||
wire ad9361_1_clk_ld ; // ad9361-1 clock group locked indicator
|
||||
|
||||
// ad9361-2 clocks
|
||||
wire ad9361_2_clk ; // 48MHz 41.6667MHz
|
||||
wire ad9361_2_clk_2x ; // 96MHz 83.3333MHz
|
||||
wire ad9361_2_clk_3x ; // 144MHz 125MHz
|
||||
wire ad9361_2_clk_4x ; // 192MHz 166.6667MHz
|
||||
wire ad9361_2_clk_ld ; // ad9361-2 clock group locked indicator
|
||||
|
||||
// phased-array & rf control clocks
|
||||
wire clk_96m ;
|
||||
wire clk_48m ;
|
||||
wire clk_32m ;
|
||||
wire clk_19p2m ;
|
||||
|
||||
clk_dist u_clk_dist
|
||||
(
|
||||
// input clocks
|
||||
.clk_250m_p (clk_250m_p ), // generated by ad9516, 250mhz
|
||||
.clk_250m_n (clk_250m_n ),
|
||||
.ad9361_1_rx_data_clk(ad9361_1_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
|
||||
.ad9361_2_rx_data_clk(ad9361_2_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
|
||||
|
||||
// output clocks & reset
|
||||
// global reset
|
||||
.sys_rst (sys_rst ), // global reset signal, active high
|
||||
.ant_rst (ant_rst ), // phased-array & rf control reset signal, active high
|
||||
|
||||
// pl signal processing clock
|
||||
.sys_clk (sys_clk ), // 48MHz 41.6667MHz
|
||||
.sys_clk_2x (sys_clk_2x ), // 96MHz 83.3333MHz
|
||||
.sys_clk_3x (sys_clk_3x ), // 144MHz 125MHz
|
||||
.sys_clk_4x (sys_clk_4x ), // 192MHz 166.6667MHz
|
||||
.sys_clk_ld (sys_clk_ld ), // system main clock locked indicator
|
||||
|
||||
// ad9361-1 clocks
|
||||
.ad9361_1_clk (ad9361_1_clk ), // 48MHz 41.6667MHz
|
||||
.ad9361_1_clk_2x (ad9361_1_clk_2x ), // 96MHz 83.3333MHz
|
||||
.ad9361_1_clk_3x (ad9361_1_clk_3x ), // 144MHz 125MHz
|
||||
.ad9361_1_clk_4x (ad9361_1_clk_4x ), // 192MHz 166.6667MHz
|
||||
.ad9361_1_clk_ld (ad9361_1_clk_ld ), // ad9361-1 clock group locked indicator
|
||||
|
||||
// ad9361-2 clocks
|
||||
.ad9361_2_clk (ad9361_2_clk ), // 48MHz 41.6667MHz
|
||||
.ad9361_2_clk_2x (ad9361_2_clk_2x ), // 96MHz 83.3333MHz
|
||||
.ad9361_2_clk_3x (ad9361_2_clk_3x ), // 144MHz 125MHz
|
||||
.ad9361_2_clk_4x (ad9361_2_clk_4x ), // 192MHz 166.6667MHz
|
||||
.ad9361_2_clk_ld (ad9361_2_clk_ld ), // ad9361-2 clock group locked indicator
|
||||
|
||||
// phased-array & rf control clocks
|
||||
.clk_96m (clk_96m ),
|
||||
.clk_48m (clk_48m ),
|
||||
.clk_32m (clk_32m ),
|
||||
.clk_19p2m (clk_19p2m )
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////// Block Design Interface ////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// gpio
|
||||
wire [31:0] gpio_i;
|
||||
wire [31:0] gpio_o;
|
||||
wire ad9361_rx_fifo_rst;
|
||||
wire ad9361_1_cal_start;
|
||||
wire ad9361_1_cal_done;
|
||||
wire ad9361_2_cal_start;
|
||||
wire ad9361_2_cal_done;
|
||||
wire ad9361_cal_result;
|
||||
wire ad9361_recal;
|
||||
|
||||
assign ad9516_pd_b = gpio_o[ 0];
|
||||
assign ad9516_reset_b = gpio_o[ 1];
|
||||
assign ad9516_sync_b = gpio_o[ 2];
|
||||
assign ad9361_1_txnrx = gpio_o[ 3]; // ad9361 enable state machine control
|
||||
assign ad9361_1_enable = gpio_o[ 4]; // ad9361 enable state machine control
|
||||
assign ad9361_1_en_agc = gpio_o[ 5]; // ad9361 agc control
|
||||
assign ad9361_1_reset_b = gpio_o[ 6]; // ad9361 reset
|
||||
assign ad9361_1_ctrl_in = gpio_o[10:7];
|
||||
assign ad9361_2_txnrx = gpio_o[11]; // ad9361 enable state machine control
|
||||
assign ad9361_2_enable = gpio_o[12]; // ad9361 enable state machine control
|
||||
assign ad9361_2_en_agc = gpio_o[13]; // ad9361 agc control
|
||||
assign ad9361_2_reset_b = gpio_o[14]; // ad9361 reset
|
||||
assign ad9361_2_ctrl_in = gpio_o[18:15];
|
||||
assign ad9361_sync = gpio_o[19];
|
||||
assign ad9361_rx_fifo_rst = gpio_o[20];
|
||||
assign ad9361_1_cal_start = gpio_o[21];
|
||||
assign ad9361_2_cal_start = gpio_o[22];
|
||||
assign ad9361_recal = gpio_o[23];
|
||||
assign ad9361_tx_switch = gpio_o[24];
|
||||
|
||||
assign gpio_i[ 7:0] = ad9361_1_ctrl_out;
|
||||
assign gpio_i[15:8] = ad9361_2_ctrl_out;
|
||||
assign gpio_i[16] = ad9516_refmon;
|
||||
assign gpio_i[17] = ad9516_ld;
|
||||
assign gpio_i[18] = ad9516_status;
|
||||
assign gpio_i[19] = ad9361_1_cal_done;
|
||||
assign gpio_i[20] = ad9361_2_cal_done;
|
||||
assign gpio_i[21] = ad9361_cal_result;
|
||||
|
||||
// spi interface
|
||||
wire spi_sclk ;
|
||||
wire [ 2:0] spi_cs ;
|
||||
reg spi_sdi ;
|
||||
wire spi_sdo ;
|
||||
wire spi_sdo_t ;
|
||||
wire spi_three_wire;
|
||||
wire spi_active ;
|
||||
|
||||
// ad9516 - three-wire spi or four-wire spi
|
||||
assign ad9516_spi_clk = spi_sclk;
|
||||
assign ad9516_spi_csn = spi_cs[0];
|
||||
assign ad9516_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// ad9361-1 - three-wire spi or four-wire spi
|
||||
assign ad9361_1_spi_clk = spi_sclk;
|
||||
assign ad9361_1_spi_csn = spi_cs[1];
|
||||
assign ad9361_1_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// ad9361-2 - three-wire spi or four-wire spi
|
||||
assign ad9361_2_spi_clk = spi_sclk;
|
||||
assign ad9361_2_spi_csn = spi_cs[2];
|
||||
assign ad9361_2_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
|
||||
// select sdi signal
|
||||
always @(*) begin
|
||||
if (~ad9516_spi_csn)
|
||||
spi_sdi = spi_three_wire ? ad9516_spi_mosi : ad9516_spi_miso;
|
||||
else if (~ad9361_1_spi_csn)
|
||||
spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso;
|
||||
else if (~ad9361_2_spi_csn)
|
||||
spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso;
|
||||
else
|
||||
spi_sdi = 1'bz;
|
||||
end
|
||||
|
||||
// ps clock
|
||||
wire ps_clk_25M;
|
||||
|
||||
system_bd_wrapper u_system_bd_wrapper
|
||||
(
|
||||
// ps system clock input
|
||||
.clk_25MHz (clk_25m ), // input clk_25MHz
|
||||
.ps_clk_25M (ps_clk_25M ), // output ps_clk_25M
|
||||
|
||||
// gpio, for control signals
|
||||
.gpio_i (gpio_i ), // input [31:0]gpio_i
|
||||
.gpio_o (gpio_o ), // output [31:0]gpio_o
|
||||
|
||||
// spi interface
|
||||
.spi_sclk (spi_sclk ), // output spi_sclk
|
||||
.spi_cs (spi_cs ), // output [2:0]spi_cs
|
||||
.spi_sdi (spi_sdi ), // input [0:0]spi_sdi
|
||||
.spi_sdo (spi_sdo ), // output spi_sdo
|
||||
.spi_sdo_t (spi_sdo_t ), // output spi_sdo_t
|
||||
.spi_three_wire (spi_three_wire ), // output spi_three_wire
|
||||
.spi_active (spi_active ) // output spi_active
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////// Phased-Array & RF Synthesizer Control & C2C //////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// antenna & rf interface
|
||||
wire rf_clk ;
|
||||
wire rf_en ;
|
||||
wire rf_data;
|
||||
wire rf_tr ;
|
||||
wire rf_dary;
|
||||
wire rf_dout;
|
||||
|
||||
// nulling algorithm
|
||||
wire accor_stream_valid;
|
||||
wire accor_stream_data;
|
||||
reg weight_stream_data = 'b0 ;
|
||||
|
||||
// buffer output data
|
||||
reg ant_din1_buf = 'b0;
|
||||
reg ant_tr_buf = 'b0;
|
||||
reg ant_dary_buf = 'b0;
|
||||
|
||||
assign ant_cin = clk_96m ;
|
||||
assign ant_din1 = ant_din1_buf;
|
||||
assign ant_tr = ant_tr_buf ;
|
||||
assign ant_dary = ant_dary_buf;
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
ant_din1_buf <= 'b0;
|
||||
ant_tr_buf <= 'b0;
|
||||
ant_dary_buf <= 'b0;
|
||||
end
|
||||
else begin
|
||||
ant_din1_buf <= (accor_stream_valid) ? accor_stream_data : rf_data;
|
||||
ant_tr_buf <= rf_tr;
|
||||
ant_dary_buf <= rf_dary;
|
||||
end
|
||||
end
|
||||
|
||||
// input data
|
||||
reg ant_dout1_d1 = 'b0;
|
||||
reg ant_dout1_d2 = 'b0;
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (ant_rst) begin
|
||||
ant_dout1_d1 <= 'b0;
|
||||
ant_dout1_d2 <= 'b0;
|
||||
weight_stream_data <= 'b0;
|
||||
end
|
||||
else begin
|
||||
ant_dout1_d1 <= ant_dout1;
|
||||
ant_dout1_d2 <= ant_dout1_d1;
|
||||
weight_stream_data <= ant_dout1_d2;
|
||||
end
|
||||
end
|
||||
|
||||
ant_rf_ctrl u_ant_rf_ctrl
|
||||
(
|
||||
.clk_48m (clk_48m ), // input clk_48m
|
||||
.clk_96m (clk_96m ), // input clk_96m
|
||||
.clk_32m (clk_32m ), // input clk_32m
|
||||
.clk_19p2m (clk_19p2m ), // input clk_19p2m
|
||||
.sys_rst (ant_rst ), // input sys_rst
|
||||
|
||||
.ant_clk (rf_clk ), // output ant_clk
|
||||
.ant_en (rf_en ), // output ant_en
|
||||
.ant_data (rf_data ), // output ant_data
|
||||
.ant_tr (rf_tr ), // output ant_tr
|
||||
.ant_dary (rf_dary ), // output ant_dary
|
||||
.ant_dout (ant_dout1_d2), // input ant_dout
|
||||
|
||||
.rf_standby (rf_standby ), // output rf_standby
|
||||
.rf_sw_pll (rf_sw_pll ), // output rf_sw_pll
|
||||
.rf_t (rf_t ), // output rf_t
|
||||
.rf_r (rf_r ), // output rf_r
|
||||
.rf_sw_bpf (rf_sw_bpf ), // output rf_sw_bpf
|
||||
.rf_sclk1 (rf_sclk1 ), // output rf_sclk1
|
||||
.rf_sdio1 (rf_sdio1 ), // output rf_sdio1
|
||||
.rf_cs1 (rf_cs1 ), // output rf_cs1
|
||||
.rf_ld1 (rf_ld1 ), // input rf_ld1
|
||||
.rf_sclk2 (rf_sclk2 ), // output rf_sclk2
|
||||
.rf_sdio2 (rf_sdio2 ), // output rf_sdio2
|
||||
.rf_cs2 (rf_cs2 ), // output rf_cs2
|
||||
.rf_ld2 (rf_ld2 ), // input rf_ld2
|
||||
.rf_sclk3 (rf_sclk3 ), // output rf_sclk3
|
||||
.rf_sdio3 (rf_sdio3 ), // output rf_sdio3
|
||||
.rf_cs3 (rf_cs3 ), // output rf_cs3
|
||||
.rf_ld3 (rf_ld3 ), // input rf_ld3
|
||||
.rf_tmgc_16 (rf_tmgc_16 ), // output rf_tmgc_16
|
||||
.rf_tmgc_8 (rf_tmgc_8 ), // output rf_tmgc_8
|
||||
.rf_tmgc_4 (rf_tmgc_4 ), // output rf_tmgc_4
|
||||
.rf_tmgc_2 (rf_tmgc_2 ), // output rf_tmgc_2
|
||||
.rf_tmgc_1 (rf_tmgc_1 ), // output rf_tmgc_1
|
||||
.rf_rmgc_16 (rf_rmgc_16 ), // output rf_rmgc_16
|
||||
.rf_rmgc_8 (rf_rmgc_8 ), // output rf_rmgc_8
|
||||
.rf_rmgc_4 (rf_rmgc_4 ), // output rf_rmgc_4
|
||||
.rf_rmgc_2 (rf_rmgc_2 ), // output rf_rmgc_2
|
||||
.rf_rmgc_1 (rf_rmgc_1 ), // output rf_rmgc_1
|
||||
.rf_enable (rf_enable ), // output rf_enable
|
||||
.rf_sc (rf_sc ), // output rf_sc
|
||||
.rf_sd (rf_sd ), // output rf_sd
|
||||
.rf_endsyn (rf_endsyn ), // output rf_endsyn
|
||||
.rf_sdout (rf_sdout ), // input rf_sdout
|
||||
.rf_dq_wd (rf_dq_wd ), // inout rf_dq_wd
|
||||
.rf_sw_rx (rf_sw_rx ) // output rf_sw_rx
|
||||
);
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////// LVDS for Time Synchronization /////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// Tx Signals //////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// baseband signal
|
||||
wire [11:0] tx_data_i;
|
||||
wire [11:0] tx_data_q;
|
||||
wire [11:0] tx_ch1_i;
|
||||
wire [11:0] tx_ch1_q;
|
||||
wire [11:0] tx_ch2_i;
|
||||
wire [11:0] tx_ch2_q;
|
||||
|
||||
ad9361_tx_map_cmos_dual u_ad9361_tx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.tx_data_clk (sys_clk ), // input tx_data_clk
|
||||
.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
|
||||
|
||||
.tx_ch1_i (tx_ch1_i ), // input [11:0] tx_ch1_i
|
||||
.tx_ch1_q (tx_ch1_q ), // input [11:0] tx_ch1_q
|
||||
.tx_ch2_i (tx_ch2_i ), // input [11:0] tx_ch2_i
|
||||
.tx_ch2_q (tx_ch2_q ), // input [11:0] tx_ch2_q
|
||||
.clk_out (ad9361_1_tx_fb_clk ), // output clk_out
|
||||
.tx_frame (ad9361_1_tx_frame ), // output tx_frame
|
||||
.tx_data (ad9361_1_tx_data ) // output [11:0] tx_data
|
||||
);
|
||||
|
||||
assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk;
|
||||
// assign ad9361_2_tx_frame = ad9361_1_tx_frame ;
|
||||
// assign ad9361_2_tx_data = ad9361_1_tx_data ;
|
||||
|
||||
tx_pre_process #(
|
||||
.CAL_MOD_FINE (0)
|
||||
) u_tx_pre_process
|
||||
(
|
||||
// clock & reset
|
||||
.clk (sys_clk ),
|
||||
.rst (sys_rst ),
|
||||
// input data
|
||||
.tx_data_ch1_i (tx_data_i ),
|
||||
.tx_data_ch1_q (tx_data_q ),
|
||||
.tx_data_ch2_i (tx_data_i ),
|
||||
.tx_data_ch2_q (tx_data_q ),
|
||||
// ad9361 calibration interface
|
||||
.ad9361_tx_switch (ad9361_tx_switch ),
|
||||
//
|
||||
.bb_rshift (1'b0 ),
|
||||
// output data
|
||||
.tx_ch1_i (tx_ch1_i ),
|
||||
.tx_ch1_q (tx_ch1_q ),
|
||||
.tx_ch2_i (tx_ch2_i ),
|
||||
.tx_ch2_q (tx_ch2_q )
|
||||
);
|
||||
|
||||
// <--------------------------------------------------------------------------->
|
||||
// <--------------------- insert transmitter logic below ---------------------->
|
||||
// <--------------------------------------------------------------------------->
|
||||
wire [ 1:0] waveform_sel;
|
||||
wire sweep_on ;
|
||||
wire [31:0] freq_set ;
|
||||
wire [ 1:0] iq_sel ;
|
||||
wire [ 3:0] bb_rshift ;
|
||||
|
||||
tx_qpsk u_tx_qpsk
|
||||
(
|
||||
.clk (sys_clk ), // input clk
|
||||
.rst (sys_rst ), // input rst
|
||||
.tx_data_i (tx_data_i ), // output [11:0] tx_data_i
|
||||
.tx_data_q (tx_data_q ), // output [11:0] tx_data_q
|
||||
// debug ports
|
||||
.waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel
|
||||
.sweep_on (sweep_on ), // input sweep_on
|
||||
.freq_set (freq_set ), // input [31:0] freq_set
|
||||
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
|
||||
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
|
||||
);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
////////////////////////////////// Rx Signals //////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
reg [11:0] rx_ch1_i, rx_ch1_q;
|
||||
reg [11:0] rx_ch2_i, rx_ch2_q;
|
||||
reg [11:0] rx_ch3_i, rx_ch3_q;
|
||||
reg [11:0] rx_ch4_i, rx_ch4_q;
|
||||
|
||||
wire [11:0] rx_ch1_i_9361, rx_ch1_q_9361;
|
||||
wire [11:0] rx_ch2_i_9361, rx_ch2_q_9361;
|
||||
wire [11:0] rx_ch3_i_9361, rx_ch3_q_9361;
|
||||
wire [11:0] rx_ch4_i_9361, rx_ch4_q_9361;
|
||||
|
||||
wire [11:0] rx_ch1_i_test, rx_ch1_q_test;
|
||||
wire [11:0] rx_ch2_i_test, rx_ch2_q_test;
|
||||
wire [11:0] rx_ch3_i_test, rx_ch3_q_test;
|
||||
wire [11:0] rx_ch4_i_test, rx_ch4_q_test;
|
||||
|
||||
wire [15:0] phase_ch1, phase_ch2, phase_ch3, phase_ch4;
|
||||
|
||||
wire rx_data_valid;
|
||||
wire [29:0] rx_data_i, rx_data_q;
|
||||
|
||||
wire hop_trigger;
|
||||
wire hop_trigger_en;
|
||||
wire rx_test_en;
|
||||
|
||||
wire hop_start_flag ;
|
||||
// wire accor_stream_valid ;
|
||||
// wire accor_stream_data ;
|
||||
// wire weight_stream_data ;
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (sys_rst) begin
|
||||
rx_ch1_i <= 'b0;
|
||||
rx_ch2_i <= 'b0;
|
||||
rx_ch3_i <= 'b0;
|
||||
rx_ch4_i <= 'b0;
|
||||
rx_ch1_q <= 'b0;
|
||||
rx_ch2_q <= 'b0;
|
||||
rx_ch3_q <= 'b0;
|
||||
rx_ch4_q <= 'b0;
|
||||
end
|
||||
else if (rx_test_en && ad9361_cal_valid) begin
|
||||
rx_ch1_i <= rx_ch1_i_test;
|
||||
rx_ch2_i <= rx_ch2_i_test;
|
||||
rx_ch3_i <= rx_ch3_i_test;
|
||||
rx_ch4_i <= rx_ch4_i_test;
|
||||
rx_ch1_q <= rx_ch1_q_test;
|
||||
rx_ch2_q <= rx_ch2_q_test;
|
||||
rx_ch3_q <= rx_ch3_q_test;
|
||||
rx_ch4_q <= rx_ch4_q_test;
|
||||
end
|
||||
else begin
|
||||
rx_ch1_i <= rx_ch1_i_9361;
|
||||
rx_ch2_i <= rx_ch2_i_9361;
|
||||
rx_ch3_i <= rx_ch3_i_9361;
|
||||
rx_ch4_i <= rx_ch4_i_9361;
|
||||
rx_ch1_q <= rx_ch1_q_9361;
|
||||
rx_ch2_q <= rx_ch2_q_9361;
|
||||
rx_ch3_q <= rx_ch3_q_9361;
|
||||
rx_ch4_q <= rx_ch4_q_9361;
|
||||
end
|
||||
end
|
||||
|
||||
ad9361_rx_map_cmos_dual u_ad9361_1_rx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_1_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_1_rx_data ), // input [11:0] rx_data
|
||||
.rx_ch1_i (rx_ch1_i_9361 ), // output [11:0] rx_ch1_i
|
||||
.rx_ch1_q (rx_ch1_q_9361 ), // output [11:0] rx_ch1_q
|
||||
.rx_ch2_i (rx_ch2_i_9361 ), // output [11:0] rx_ch2_i
|
||||
.rx_ch2_q (rx_ch2_q_9361 ) // output [11:0] rx_ch2_q
|
||||
);
|
||||
|
||||
ad9361_rx_map_cmos_dual u_ad9361_2_rx_map
|
||||
(
|
||||
.clk_2x_in (ad9361_2_clk_2x ), // input clk_2x_in
|
||||
.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
|
||||
|
||||
.rx_data_clk (sys_clk ), // input rx_data_clk
|
||||
.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
|
||||
|
||||
.rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst
|
||||
|
||||
.rx_frame (ad9361_2_rx_frame ), // input rx_frame
|
||||
.rx_data (ad9361_2_rx_data ), // input [11:0] rx_data
|
||||
.rx_ch1_i (rx_ch3_i_9361 ), // output [11:0] rx_ch1_i
|
||||
.rx_ch1_q (rx_ch3_q_9361 ), // output [11:0] rx_ch1_q
|
||||
.rx_ch2_i (rx_ch4_i_9361 ), // output [11:0] rx_ch2_i
|
||||
.rx_ch2_q (rx_ch4_q_9361 ) // output [11:0] rx_ch2_q
|
||||
);
|
||||
|
||||
rx_pre_process #(
|
||||
.OUTPUT_DATA_WIDTH (30 )
|
||||
) u_rx_pre_process
|
||||
(
|
||||
// clock & reset
|
||||
.sys_clk (sys_clk ), // sync to adc data
|
||||
.sys_clk_4x (sys_clk_4x ), // sync to physical layer
|
||||
.sys_rst (sys_rst ), // sync to [sys_clk]
|
||||
.clk_96m (clk_96m ), // sync to c2c data
|
||||
.ant_rst (ant_rst ), // sync to [clk_96m]
|
||||
// input data interface
|
||||
.rx_ch1_i (rx_ch1_i ),
|
||||
.rx_ch1_q (rx_ch1_q ),
|
||||
.rx_ch2_i (rx_ch2_i ),
|
||||
.rx_ch2_q (rx_ch2_q ),
|
||||
.rx_ch3_i (rx_ch3_i ),
|
||||
.rx_ch3_q (rx_ch3_q ),
|
||||
.rx_ch4_i (rx_ch4_i ),
|
||||
.rx_ch4_q (rx_ch4_q ),
|
||||
// input phase
|
||||
.phase_ch1 (phase_ch1 ),
|
||||
.phase_ch2 (phase_ch2 ),
|
||||
.phase_ch3 (phase_ch3 ),
|
||||
.phase_ch4 (phase_ch4 ),
|
||||
// ad9361 calibration interface
|
||||
.ad9361_1_cal_start (ad9361_1_cal_start ),
|
||||
.ad9361_1_cal_done (ad9361_1_cal_done ),
|
||||
.ad9361_2_cal_start (ad9361_2_cal_start ),
|
||||
.ad9361_2_cal_done (ad9361_2_cal_done ),
|
||||
.ad9361_cal_result (ad9361_cal_result ),
|
||||
.ad9361_cal_valid (ad9361_cal_valid ),
|
||||
.ad9361_recal (ad9361_recal ),
|
||||
// nulling algorithm interface
|
||||
.hop_start_flag (hop_start_flag ), // sync to [sys_clk_4x]
|
||||
.accor_stream_valid (accor_stream_valid ), // sync to [clk_96m]
|
||||
.accor_stream_data (accor_stream_data ), // sync to [clk_96m]
|
||||
.weight_stream_data (weight_stream_data ), // sync to [clk_96m]
|
||||
.rx_data_valid (rx_data_valid ), // sync to [sys_clk]
|
||||
.rx_data_i (rx_data_i ), // sync to [sys_clk]
|
||||
.rx_data_q (rx_data_q ) // sync to [sys_clk]
|
||||
);
|
||||
|
||||
// temporary test cases
|
||||
rx_pre_test u_rx_pre_test
|
||||
(
|
||||
// clock & reset
|
||||
.sys_clk (sys_clk ),
|
||||
.sys_clk_4x (sys_clk_4x ),
|
||||
.sys_rst (sys_rst ),
|
||||
.hop_trigger (hop_trigger ),
|
||||
.hop_trigger_en (hop_trigger_en ),
|
||||
// calc result
|
||||
.ad9361_cal_result (ad9361_cal_result ),
|
||||
.ad9361_cal_valid (ad9361_cal_valid ),
|
||||
// output test data
|
||||
.rx_ch1_i (rx_ch1_i_test ),
|
||||
.rx_ch1_q (rx_ch1_q_test ),
|
||||
.rx_ch2_i (rx_ch2_i_test ),
|
||||
.rx_ch2_q (rx_ch2_q_test ),
|
||||
.rx_ch3_i (rx_ch3_i_test ),
|
||||
.rx_ch3_q (rx_ch3_q_test ),
|
||||
.rx_ch4_i (rx_ch4_i_test ),
|
||||
.rx_ch4_q (rx_ch4_q_test ),
|
||||
.hop_start_flag (hop_start_flag )
|
||||
);
|
||||
|
||||
// <--------------------------------------------------------------------------->
|
||||
// <----------------------- insert receiver logic below ----------------------->
|
||||
// <--------------------------------------------------------------------------->
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
//////////////////////////////// ILAs and VIOs /////////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// vio_clk_ld_rd u_vio_clk_ld_rd
|
||||
// (
|
||||
// .clk (sys_clk ),
|
||||
// .probe_in0 (ad9361_1_clk_ld),
|
||||
// .probe_in1 (ad9361_2_clk_ld)
|
||||
// );
|
||||
|
||||
vio_rfcontrl u_vio_rfcontrl
|
||||
(
|
||||
.clk (clk_48m ), // input wire clk
|
||||
.probe_out0 (u_ant_rf_ctrl.vio_switch ), // output wire [0 : 0] probe_out0
|
||||
.probe_out1 (u_ant_rf_ctrl.vio_trdirection ), // output wire [0 : 0] probe_out1
|
||||
.probe_out2 (u_ant_rf_ctrl.vio_frequency[15:0] ), // output wire [15 : 0] probe_out2
|
||||
.probe_out3 (u_ant_rf_ctrl.vio_emitMGC[7:0] ), // output wire [7 : 0] probe_out3
|
||||
.probe_out4 (u_ant_rf_ctrl.vio_ch01MGC[3:0] ), // output wire [3 : 0] probe_out4
|
||||
.probe_out5 (u_ant_rf_ctrl.vio_ch02MGC[3:0] ), // output wire [3 : 0] probe_out5
|
||||
.probe_out6 (u_ant_rf_ctrl.vio_ch03MGC[3:0] ), // output wire [3 : 0] probe_out6
|
||||
.probe_out7 (u_ant_rf_ctrl.vio_ch04MGC[3:0] ), // output wire [3 : 0] probe_out7
|
||||
.probe_out8 (u_ant_rf_ctrl.vio_recvMGC[7:0] ), // output wire [7 : 0] probe_out8
|
||||
.probe_out9 (u_ant_rf_ctrl.vio_AntMod[7:0] ), // output wire [7 : 0] probe_out9
|
||||
.probe_out10(u_ant_rf_ctrl.vio_AntOffAxis[15:0] ), // output wire [15 : 0] probe_out10
|
||||
.probe_out11(u_ant_rf_ctrl.vio_AntYaw[15:0] ), // output wire [15 : 0] probe_out11
|
||||
.probe_out12(u_ant_rf_ctrl.vio_PrecessTime[15:0] ) // output wire [15 : 0] probe_out12
|
||||
);
|
||||
|
||||
vio_ant_test u_vio_ant_test
|
||||
(
|
||||
.clk (clk_48m ),
|
||||
.probe_out0 (u_ant_rf_ctrl.vio_mode_ant ),
|
||||
.probe_out1 (u_ant_rf_ctrl.vio_hop_start ),
|
||||
.probe_out2 (u_ant_rf_ctrl.vio_standby ),
|
||||
.probe_out3 (u_ant_rf_ctrl.vio_hoptime[15:0] )
|
||||
);
|
||||
|
||||
ila_rfcontrl u_ila_rfcontrl
|
||||
(
|
||||
.clk (clk_48m ), // input wire clk
|
||||
.probe0 (u_ant_rf_ctrl.SPI_MOSI_F ), // input wire [0:0]
|
||||
.probe1 (u_ant_rf_ctrl.SPI_MISO_F ), // input wire [0:0]
|
||||
.probe2 (u_ant_rf_ctrl.SPI_SYN_F ), // input wire [0:0]
|
||||
.probe3 (u_ant_rf_ctrl.TP_EN_F ), // input wire [0:0]
|
||||
.probe4 (u_ant_rf_ctrl.TR_MGC_F ), // input wire [0:0]
|
||||
.probe5 (u_ant_rf_ctrl.CAL_F ), // input wire [0:0]
|
||||
.probe6 (u_ant_rf_ctrl.PRF ), // input wire [0:0]
|
||||
.probe7 (u_ant_rf_ctrl.rf_standby ), // input wire [0:0]
|
||||
.probe8 (u_ant_rf_ctrl.rf_sw_pll ), // input wire [0:0]
|
||||
.probe9 (u_ant_rf_ctrl.rf_t ), // input wire [0:0]
|
||||
.probe10(u_ant_rf_ctrl.rf_r ), // input wire [0:0]
|
||||
.probe11(u_ant_rf_ctrl.rf_sw_bpf ), // input wire [0:0]
|
||||
.probe12(u_ant_rf_ctrl.rf_sclk1 ), // input wire [0:0]
|
||||
.probe13(u_ant_rf_ctrl.rf_sdio1 ), // input wire [0:0]
|
||||
.probe14(u_ant_rf_ctrl.rf_cs1 ), // input wire [0:0]
|
||||
.probe15(u_ant_rf_ctrl.rf_ld1 ), // input wire [0:0]
|
||||
.probe16(u_ant_rf_ctrl.rf_sclk2 ), // input wire [0:0]
|
||||
.probe17(u_ant_rf_ctrl.rf_sdio2 ), // input wire [0:0]
|
||||
.probe18(u_ant_rf_ctrl.rf_cs2 ), // input wire [0:0]
|
||||
.probe19(u_ant_rf_ctrl.rf_ld2 ), // input wire [0:0]
|
||||
.probe20(u_ant_rf_ctrl.rf_sclk3 ), // input wire [0:0]
|
||||
.probe21(u_ant_rf_ctrl.rf_sdio3 ), // input wire [0:0]
|
||||
.probe22(u_ant_rf_ctrl.rf_cs3 ), // input wire [0:0]
|
||||
.probe23(u_ant_rf_ctrl.rf_ld3 ), // input wire [0:0]
|
||||
.probe24(u_ant_rf_ctrl.rf_tmgc_16 ), // input wire [0:0]
|
||||
.probe25(u_ant_rf_ctrl.rf_tmgc_8 ), // input wire [0:0]
|
||||
.probe26(u_ant_rf_ctrl.rf_tmgc_4 ), // input wire [0:0]
|
||||
.probe27(u_ant_rf_ctrl.rf_tmgc_2 ), // input wire [0:0]
|
||||
.probe28(u_ant_rf_ctrl.rf_tmgc_1 ), // input wire [0:0]
|
||||
.probe29(u_ant_rf_ctrl.rf_rmgc_16 ), // input wire [0:0]
|
||||
.probe30(u_ant_rf_ctrl.rf_rmgc_8 ), // input wire [0:0]
|
||||
.probe31(u_ant_rf_ctrl.rf_rmgc_4 ), // input wire [0:0]
|
||||
.probe32(u_ant_rf_ctrl.rf_rmgc_2 ), // input wire [0:0]
|
||||
.probe33(u_ant_rf_ctrl.rf_rmgc_1 ), // input wire [0:0]
|
||||
.probe34(u_ant_rf_ctrl.rf_enable ), // input wire [0:0]
|
||||
.probe35(u_ant_rf_ctrl.rf_sc ), // input wire [0:0]
|
||||
.probe36(u_ant_rf_ctrl.rf_sd ), // input wire [0:0]
|
||||
.probe37(u_ant_rf_ctrl.rf_endsyn ), // input wire [0:0]
|
||||
.probe38(u_ant_rf_ctrl.rf_sdout ), // input wire [0:0]
|
||||
.probe39(u_ant_rf_ctrl.state_rfdata[1:0] ), // input wire [0:0]
|
||||
.probe40(u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [0:0]
|
||||
.probe41(u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [0:0]
|
||||
.probe42(u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [0:0]
|
||||
.probe43(u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [0:0]
|
||||
.probe44(u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [0:0]
|
||||
.probe45(u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [0:0]
|
||||
.probe46(u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [0:0]
|
||||
.probe47(u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [0:0]
|
||||
.probe48(u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [0:0]
|
||||
.probe49(u_ant_rf_ctrl.RF_RecvWord[95:0] ) // input wire [0:0]
|
||||
);
|
||||
|
||||
ila_AntCtrl u_ila_AntCtrl
|
||||
(
|
||||
.clk (clk_96m ), // input wire clk
|
||||
.probe0 (u_ant_rf_ctrl.ant_clk ), // input wire [0:0] probe0
|
||||
.probe1 (u_ant_rf_ctrl.ant_en ), // input wire [0:0] probe1
|
||||
.probe2 (u_ant_rf_ctrl.ant_data ), // input wire [0:0] probe2
|
||||
.probe3 (u_ant_rf_ctrl.ant_tr ), // input wire [0:0] probe3
|
||||
.probe4 (u_ant_rf_ctrl.ant_dary ), // input wire [0:0] probe4
|
||||
.probe5 (u_ant_rf_ctrl.ant_dout ), // input wire [0:0] probe5
|
||||
.probe6 (u_ant_rf_ctrl.state_antdata[1:0] ), // input wire [0:0] probe5
|
||||
.probe7 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [0:0] probe5
|
||||
.probe8 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [0:0] probe5
|
||||
.probe9 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [0:0] probe5
|
||||
.probe10(u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [0:0] probe5
|
||||
.probe11(u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [0:0] probe5
|
||||
.probe12(u_ant_rf_ctrl.Ant_RecvWord[95:0] ) // input wire [0:0] probe5
|
||||
);
|
||||
|
||||
vio_rf_rd u_vio_rf_rd (
|
||||
.clk (clk_96m ), // input wire clk
|
||||
.probe_in0 (u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [7 : 0] probe_in0
|
||||
.probe_in1 (u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [7 : 0] probe_in1
|
||||
.probe_in2 (u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [7 : 0] probe_in2
|
||||
.probe_in3 (u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [7 : 0] probe_in3
|
||||
.probe_in4 (u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [3 : 0] probe_in4
|
||||
.probe_in5 (u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [3 : 0] probe_in5
|
||||
.probe_in6 (u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [3 : 0] probe_in6
|
||||
.probe_in7 (u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [3 : 0] probe_in7
|
||||
.probe_in8 (u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [31 : 0] probe_in8
|
||||
.probe_in9 (u_ant_rf_ctrl.RF_RecvWord_last ) // input wire [95 : 0] probe_in9
|
||||
);
|
||||
|
||||
// vio_ant_rd u_vio_ant_rd (
|
||||
// .clk (clk_96m ), // input wire clk
|
||||
// .probe_in0 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [7 : 0] probe_in0
|
||||
// .probe_in1 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [7 : 0] probe_in1
|
||||
// .probe_in2 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [7 : 0] probe_in2
|
||||
// .probe_in3 (u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [7 : 0] probe_in3
|
||||
// .probe_in4 (u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [31 : 0] probe_in4
|
||||
// .probe_in5 (u_ant_rf_ctrl.Ant_RecvWord_last ) // input wire [127 : 0] probe_in5
|
||||
// );
|
||||
|
||||
ila_2x12x1024 u_ila_tx
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe0 (tx_ch1_i ), // input wire [11:0] probe0
|
||||
.probe1 (tx_ch1_q ) // input wire [11:0] probe1
|
||||
);
|
||||
|
||||
ila_8x12_2x30_8192 u_ila_rx
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe0 (u_rx_pre_process.rx_cal_ch1_i ), // input wire [11:0] probe0
|
||||
.probe1 (u_rx_pre_process.rx_cal_ch1_q ), // input wire [11:0] probe1
|
||||
.probe2 (u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe2
|
||||
.probe3 (u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe3
|
||||
.probe4 (u_rx_pre_process.rx_cal_ch3_i ), // input wire [11:0] probe4
|
||||
.probe5 (u_rx_pre_process.rx_cal_ch3_q ), // input wire [11:0] probe5
|
||||
.probe6 (u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe6
|
||||
.probe7 (u_rx_pre_process.rx_cal_ch4_q ), // input wire [11:0] probe7
|
||||
.probe8 (rx_data_i ), // input wire [29:0] probe8
|
||||
.probe9 (rx_data_q ) // input wire [29:0] probe9
|
||||
);
|
||||
|
||||
ila_cal u_ila_cal
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe0 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_start_d2 ), // input wire [0:0] probe0
|
||||
.probe1 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_1_cal_done ), // input wire [0:0] probe1
|
||||
.probe2 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_start_d2 ), // input wire [0:0] probe2
|
||||
.probe3 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_2_cal_done ), // input wire [0:0] probe3
|
||||
.probe4 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_cal_result ), // input wire [0:0] probe4
|
||||
.probe5 (u_rx_pre_process.u_ad9361_phase_cal.ad9361_recal_d2 ), // input wire [0:0] probe5
|
||||
.probe6 (u_rx_pre_process.u_ad9361_phase_cal.curr_state ), // input wire [1:0] probe6
|
||||
.probe7 (rx_ch2_i ), // input wire [11:0] probe7
|
||||
.probe8 (rx_ch2_q ), // input wire [11:0] probe8
|
||||
.probe9 (rx_ch4_i ), // input wire [11:0] probe9
|
||||
.probe10(rx_ch4_q ), // input wire [11:0] probe10
|
||||
.probe11(u_rx_pre_process.rx_cal_ch2_i ), // input wire [11:0] probe11
|
||||
.probe12(u_rx_pre_process.rx_cal_ch2_q ), // input wire [11:0] probe12
|
||||
.probe13(u_rx_pre_process.rx_cal_ch4_i ), // input wire [11:0] probe13
|
||||
.probe14(u_rx_pre_process.rx_cal_ch4_q ) // input wire [11:0] probe14
|
||||
);
|
||||
|
||||
ila_rx_pre_sys u_ila_rx_pre_sys
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe0 (u_rx_pre_process.hop_start_flag_cdc ), // input wire [0:0] probe0
|
||||
.probe1 (u_rx_pre_process.fifo_cdc_rst ), // input wire [0:0] probe1
|
||||
.probe2 (u_rx_pre_process.u_accor_mat_stream.fifo_wr_en ), // input wire [0:0] probe2
|
||||
.probe3 (u_rx_pre_process.u_accor_mat_stream.fifo_din ), // input wire [31:0] probe3
|
||||
.probe4 (u_rx_pre_process.u_accor_mat_stream.fifo_full ), // input wire [0:0] probe4
|
||||
.probe5 (u_rx_pre_process.u_weight_vec_formatting.fifo_rd_en ), // input wire [0:0] probe5
|
||||
.probe6 (u_rx_pre_process.u_weight_vec_formatting.fifo_dout ), // input wire [15:0] probe6
|
||||
.probe7 (u_rx_pre_process.u_weight_vec_formatting.fifo_empty ), // input wire [0:0] probe7
|
||||
.probe8 (u_rx_pre_process.u_weight_vec_formatting.fifo_rd_num ) // input wire [3:0] probe8
|
||||
);
|
||||
|
||||
ila_rx_pre_ant u_ila_rx_pre_ant
|
||||
(
|
||||
.clk (clk_96m ), // input wire clk
|
||||
.probe0 (u_rx_pre_process.hop_start_flag_cdc ), // input wire [0:0] probe0
|
||||
.probe1 (accor_stream_valid ), // input wire [0:0] probe1
|
||||
.probe2 (accor_stream_data ), // input wire [0:0] probe2
|
||||
.probe3 (weight_stream_data ), // input wire [0:0] probe3
|
||||
.probe4 (u_rx_pre_process.fifo_cdc_rst ), // input wire [0:0] probe4
|
||||
.probe5 (u_rx_pre_process.u_accor_mat_stream.fifo_rd_en ), // input wire [0:0] probe5
|
||||
.probe6 (u_rx_pre_process.u_accor_mat_stream.fifo_dout ), // input wire [31:0] probe6
|
||||
.probe7 (u_rx_pre_process.u_accor_mat_stream.fifo_empty ), // input wire [0:0] probe7
|
||||
.probe8 (u_rx_pre_process.u_accor_mat_stream.fifo_rd_num ), // input wire [4:0] probe8
|
||||
.probe9 (u_rx_pre_process.u_weight_vec_formatting.fifo_wr_en), // input wire [0:0] probe9
|
||||
.probe10(u_rx_pre_process.u_weight_vec_formatting.fifo_din ), // input wire [15:0] probe10
|
||||
.probe11(u_rx_pre_process.u_weight_vec_formatting.fifo_full ) // input wire [0:0] probe11
|
||||
);
|
||||
|
||||
vio_manual_ctrl u_vio_manual_ctrl
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe_out0 (waveform_sel[1:0] ), // output wire [1 : 0] probe_out0
|
||||
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
|
||||
.probe_out2 (freq_set[31:0] ), // output wire [31 : 0] probe_out2
|
||||
.probe_out3 (iq_sel[1:0] ), // output wire [1 : 0] probe_out3
|
||||
.probe_out4 (bb_rshift[3:0] ), // output wire [3 : 0] probe_out4
|
||||
.probe_out5 (rx_test_en ) // output wire [0 : 0] probe_out5
|
||||
);
|
||||
|
||||
vio_hop u_vio_hop
|
||||
(
|
||||
.clk (sys_clk_4x ), // input wire clk
|
||||
.probe_out0 (hop_trigger ), // output wire [0 : 0] probe_out1
|
||||
.probe_out1 (hop_trigger_en ) // output wire [0 : 0] probe_out2
|
||||
);
|
||||
|
||||
vio_null_phase u_vio_null_phase
|
||||
(
|
||||
.clk (sys_clk ), // input wire clk
|
||||
.probe_out0 (phase_ch1 ), // output wire [15 : 0] probe_out0
|
||||
.probe_out1 (phase_ch2 ), // output wire [15 : 0] probe_out1
|
||||
.probe_out2 (phase_ch3 ), // output wire [15 : 0] probe_out2
|
||||
.probe_out3 (phase_ch4 ) // output wire [15 : 0] probe_out3
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,93 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 2023/03/06 16:15:00
|
||||
// Design Name:
|
||||
// Module Name: tx_control
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tx_control
|
||||
(
|
||||
input clk ,
|
||||
input rst ,
|
||||
output [11:0] tx_data_i ,
|
||||
output [11:0] tx_data_q ,
|
||||
// debug ports
|
||||
input [ 2:0] waveform_sel,
|
||||
input sweep_on ,
|
||||
input [31:0] freq_set ,
|
||||
input [ 1:0] iq_sel ,
|
||||
input [ 3:0] bb_rshift
|
||||
);
|
||||
|
||||
wire [11:0] gmsk_12m_i, gmsk_12m_q;
|
||||
wire [11:0] gmsk_1p5m_i, gmsk_1p5m_q;
|
||||
wire [11:0] qpsk_i, qpsk_q;
|
||||
|
||||
GMSK_send u_GMSK_send
|
||||
(
|
||||
.clk_48M (clk ),
|
||||
.rst (rst ),
|
||||
.gmsk_12M_i (gmsk_12m_i ),
|
||||
.gmsk_12M_q (gmsk_12m_q ),
|
||||
.gmsk_1p5m_i (gmsk_1p5m_i ),
|
||||
.gmsk_1p5m_q (gmsk_1p5m_q )
|
||||
);
|
||||
|
||||
tx_qpsk u_tx_qpsk
|
||||
(
|
||||
.clk (clk ), // input clk
|
||||
.rst (rst ), // input rst
|
||||
.tx_data_i (qpsk_i ), // output [11:0] tx_data_i
|
||||
.tx_data_q (qpsk_q ), // output [11:0] tx_data_q
|
||||
// debug ports
|
||||
.waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel
|
||||
.sweep_on (sweep_on ), // input sweep_on
|
||||
.freq_set (freq_set ), // input [31:0] freq_set
|
||||
.iq_sel (iq_sel ), // input [ 1:0] iq_sel
|
||||
.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
|
||||
);
|
||||
|
||||
// tx buf
|
||||
reg [11:0] tx_data_i_buf = 'b0;
|
||||
reg [11:0] tx_data_q_buf = 'b0;
|
||||
|
||||
assign tx_data_i = tx_data_i_buf;
|
||||
assign tx_data_q = tx_data_q_buf;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
tx_data_i_buf <= 'b0;
|
||||
tx_data_q_buf <= 'b0;
|
||||
end
|
||||
else casex (waveform_sel)
|
||||
3'b10x: begin
|
||||
tx_data_i_buf <= gmsk_12m_i;
|
||||
tx_data_q_buf <= gmsk_12m_q;
|
||||
end
|
||||
3'b11x: begin
|
||||
tx_data_i_buf <= gmsk_1p5m_i;
|
||||
tx_data_q_buf <= gmsk_1p5m_q;
|
||||
end
|
||||
default: begin
|
||||
tx_data_i_buf <= qpsk_i;
|
||||
tx_data_q_buf <= qpsk_q;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,138 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 2023/02/25 15:20:22
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// Design Name:
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// Module Name: tx_pre_process
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tx_pre_process
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#(
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parameter ADC_DATA_WIDTH = 12,
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parameter PRBS = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
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parameter PRBS_LEN = 128, // length of pseudorandom bit sequence
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parameter INTERP_FACTOR = 8, // interpolation factor, max inter-channel delay ranges in [-INTERP_FACTOR+1,INTERP_FACTOR-1]
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parameter CAL_MOD_FINE = 1
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)
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(
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// clock & reset
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input clk ,
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input rst ,
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// input data
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input [ADC_DATA_WIDTH-1:0] tx_data_ch1_i ,
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input [ADC_DATA_WIDTH-1:0] tx_data_ch1_q ,
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input [ADC_DATA_WIDTH-1:0] tx_data_ch2_i ,
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input [ADC_DATA_WIDTH-1:0] tx_data_ch2_q ,
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// ad9361 calibration interface
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input ad9361_tx_switch ,
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//
|
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input [$clog2(ADC_DATA_WIDTH)-1:0] bb_rshift,
|
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// output data
|
||||
output [ADC_DATA_WIDTH-1:0] tx_ch1_i ,
|
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output [ADC_DATA_WIDTH-1:0] tx_ch1_q ,
|
||||
output [ADC_DATA_WIDTH-1:0] tx_ch2_i ,
|
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output [ADC_DATA_WIDTH-1:0] tx_ch2_q
|
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);
|
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integer i;
|
||||
|
||||
// square shaped bpsk signal
|
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reg [$clog2(PRBS_LEN*INTERP_FACTOR)-1 : 0] chip_interp_cnt = 'b0;
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reg signed [ADC_DATA_WIDTH-1:0] tx_pn_i = 'b0;
|
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reg signed [ADC_DATA_WIDTH-1:0] tx_pn_q = 'b0;
|
||||
|
||||
if (CAL_MOD_FINE == 1) begin
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
chip_interp_cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
chip_interp_cnt <= chip_interp_cnt + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
tx_pn_i <= 'b0;
|
||||
tx_pn_q <= 'b0;
|
||||
end
|
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else begin
|
||||
tx_pn_i <= PRBS[chip_interp_cnt[$clog2(PRBS_LEN*INTERP_FACTOR)-1 -: $clog2(PRBS_LEN)]] ? {1'b0,{(ADC_DATA_WIDTH-1){1'b1}}} : {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1}; // (1 or 0) ? 4'b0111 : 4'b1001
|
||||
tx_pn_q <= PRBS[chip_interp_cnt[$clog2(PRBS_LEN*INTERP_FACTOR)-1 -: $clog2(PRBS_LEN)]] ? {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1} : {1'b0,{(ADC_DATA_WIDTH-1){1'b1}}}; // (1 or 0) ? 4'b1001 : 4'b0111
|
||||
end
|
||||
end
|
||||
|
||||
end // if (CAL_MOD_FINE == 1)
|
||||
|
||||
// buffer input control signals (clock domain crossing from ps to pl clock domain)
|
||||
reg ad9361_tx_switch_d1 = 'b0;
|
||||
reg ad9361_tx_switch_d2 = 'b0;
|
||||
|
||||
wire signed [ADC_DATA_WIDTH-1:0] tx_dc_i = {1'b0,{(ADC_DATA_WIDTH-2){1'b1}},1'b1};
|
||||
wire signed [ADC_DATA_WIDTH-1:0] tx_dc_q = {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1};
|
||||
|
||||
always @(posedge clk) begin
|
||||
ad9361_tx_switch_d1 <= ad9361_tx_switch;
|
||||
ad9361_tx_switch_d2 <= ad9361_tx_switch_d1;
|
||||
end
|
||||
|
||||
reg [ADC_DATA_WIDTH-1 : 0] tx_ch1_i_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1 : 0] tx_ch1_q_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1 : 0] tx_ch2_i_buf = 'b0;
|
||||
reg [ADC_DATA_WIDTH-1 : 0] tx_ch2_q_buf = 'b0;
|
||||
|
||||
assign tx_ch1_i = tx_ch1_i_buf;
|
||||
assign tx_ch1_q = tx_ch1_q_buf;
|
||||
assign tx_ch2_i = tx_ch2_i_buf;
|
||||
assign tx_ch2_q = tx_ch2_q_buf;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
tx_ch1_i_buf <= 'b0;
|
||||
tx_ch1_q_buf <= 'b0;
|
||||
tx_ch2_i_buf <= 'b0;
|
||||
tx_ch2_q_buf <= 'b0;
|
||||
end
|
||||
else if (ad9361_tx_switch_d2) begin
|
||||
if (CAL_MOD_FINE == 1) begin
|
||||
tx_ch1_i_buf <= tx_pn_i >>> bb_rshift;
|
||||
tx_ch1_q_buf <= tx_pn_q >>> bb_rshift;
|
||||
tx_ch2_i_buf <= tx_pn_i >>> bb_rshift;
|
||||
tx_ch2_q_buf <= tx_pn_q >>> bb_rshift;
|
||||
end // CAL_MOD_FINE == 1
|
||||
else begin
|
||||
tx_ch1_i_buf <= tx_dc_i >>> bb_rshift;
|
||||
tx_ch1_q_buf <= tx_dc_q >>> bb_rshift;
|
||||
tx_ch2_i_buf <= tx_dc_i >>> bb_rshift;
|
||||
tx_ch2_q_buf <= tx_dc_q >>> bb_rshift;
|
||||
end // CAL_MOD_FINE != 1
|
||||
end
|
||||
else begin
|
||||
tx_ch1_i_buf <= tx_data_ch1_i;
|
||||
tx_ch1_q_buf <= tx_data_ch1_q;
|
||||
tx_ch2_i_buf <= tx_data_ch2_i;
|
||||
tx_ch2_q_buf <= tx_data_ch2_q;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user