Archived
add sampled data; add new online acq proj
the function of dmf is correct
This commit is contained in:
@@ -0,0 +1,135 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 04/25/2023 04:04:33 PM
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// Design Name:
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// Module Name: tb_phase_compensation
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description: testbench for [phase_compensation]
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_phase_compensation;
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localparam DATA_WIDTH = 20;
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localparam PHASE_WIDTH = 16;
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localparam CHANNEL_NUM = 4;
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reg clk = 1'b1;
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reg rst = 1'b1;
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reg din_valid = 1'b0;
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wire dout_valid;
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reg [DATA_WIDTH-1 : 0] din_ch1_i = 'b0;
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reg [DATA_WIDTH-1 : 0] din_ch1_q = 'b0;
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reg [DATA_WIDTH-1 : 0] din_ch2_i = 'b0;
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reg [DATA_WIDTH-1 : 0] din_ch2_q = 'b0;
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reg [DATA_WIDTH-1 : 0] din_ch3_i = 'b0;
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reg [DATA_WIDTH-1 : 0] din_ch3_q = 'b0;
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reg [DATA_WIDTH-1 : 0] din_ch4_i = 'b0;
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reg [DATA_WIDTH-1 : 0] din_ch4_q = 'b0;
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reg [PHASE_WIDTH-1 : 0] din_phase_ch1 = 'b0;
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reg [PHASE_WIDTH-1 : 0] din_phase_ch2 = 'b0;
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reg [PHASE_WIDTH-1 : 0] din_phase_ch3 = 'b0;
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reg [PHASE_WIDTH-1 : 0] din_phase_ch4 = 'b0;
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wire [DATA_WIDTH-1 : 0] dout_ch1_i;
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wire [DATA_WIDTH-1 : 0] dout_ch1_q;
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wire [DATA_WIDTH-1 : 0] dout_ch2_i;
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wire [DATA_WIDTH-1 : 0] dout_ch2_q;
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wire [DATA_WIDTH-1 : 0] dout_ch3_i;
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wire [DATA_WIDTH-1 : 0] dout_ch3_q;
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wire [DATA_WIDTH-1 : 0] dout_ch4_i;
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wire [DATA_WIDTH-1 : 0] dout_ch4_q;
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// initial
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initial begin
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#102;
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rst = 1'b0;
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#100;
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din_valid = 1'b1;
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din_ch1_i = 20'd107;
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din_ch1_q = 20'd222;
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din_ch2_i = -20'd253;
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din_ch2_q = 20'd812;
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din_ch3_i = 20'd752;
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din_ch3_q = -20'd563;
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din_ch4_i = -20'd785;
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din_ch4_q = -20'd1024;
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din_phase_ch1 = 16'b001_00000_00000_000; // $+\pi$
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din_phase_ch2 = 16'b000_10000_00000_000; // $+\pi/2$
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din_phase_ch3 = 16'b111_00000_00000_000; // $-\pi$
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din_phase_ch4 = 16'b111_10000_00000_000; // $-\pi/2$
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#20
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din_valid = 1'b0;
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#100;
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din_valid = 1'b1;
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din_ch4_i = 20'd107;
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din_ch4_q = 20'd222;
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din_ch3_i = -20'd253;
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din_ch3_q = 20'd812;
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din_ch2_i = 20'd752;
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din_ch2_q = -20'd563;
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din_ch1_i = -20'd785;
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din_ch1_q = -20'd1024;
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din_phase_ch1 = 16'b000_01000_00000_000; // $+\pi/4$
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din_phase_ch2 = 16'b000_00100_00000_000; // $+\pi/8$
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din_phase_ch3 = 16'b111_11000_00000_000; // $-\pi/4$
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din_phase_ch4 = 16'b111_11100_00000_000; // $-\pi/8$
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#20
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din_valid = 1'b0;
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end
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always #10 clk = ~clk;
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// module & port
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wire [CHANNEL_NUM*DATA_WIDTH - 1 : 0] din_data_real;
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wire [CHANNEL_NUM*DATA_WIDTH - 1 : 0] din_data_imag;
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wire [CHANNEL_NUM*DATA_WIDTH - 1 : 0] dout_data_real;
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wire [CHANNEL_NUM*DATA_WIDTH - 1 : 0] dout_data_imag;
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wire [CHANNEL_NUM*PHASE_WIDTH-1 : 0] din_phase;
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assign din_data_real = {din_ch4_i, din_ch3_i, din_ch2_i, din_ch1_i};
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assign din_data_imag = {din_ch4_q, din_ch3_q, din_ch2_q, din_ch1_q};
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assign din_phase = {din_phase_ch4, din_phase_ch3, din_phase_ch2, din_phase_ch1};
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assign {dout_ch4_i, dout_ch3_i, dout_ch2_i, dout_ch1_i} = dout_data_real;
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assign {dout_ch4_q, dout_ch3_q, dout_ch2_q, dout_ch1_q} = dout_data_imag;
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phase_compensation #(
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.DATA_WIDTH (DATA_WIDTH ),
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.PHASE_WIDTH (PHASE_WIDTH ),
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.CHANNEL_NUM (CHANNEL_NUM )
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) u_phase_compensation
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(
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// clock & reset
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.clk (clk ),
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.rst (rst ),
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// input data
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.din_valid (din_valid ),
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.din_data_real (din_data_real ),
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.din_data_imag (din_data_imag ),
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.din_phase (din_phase ),
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// output data
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.dout_valid (dout_valid ),
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.dout_data_real (dout_data_real ),
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.dout_data_imag (dout_data_imag )
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);
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endmodule
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@@ -0,0 +1,77 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 04/25/2023 06:48:44 PM
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// Design Name:
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// Module Name: tb_rx_dmf
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_rx_dmf;
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reg clk = 1'b1;
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reg rst = 1'b1;
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wire [11:0] tx_data_i, tx_data_q;
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wire dout_valid;
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wire [18 : 0] dout_real;
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wire [18 : 0] dout_imag;
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initial begin
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#102;
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rst = 1'b0;
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end
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always #10 clk = ~clk;
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tx_qpsk u_tx_qpsk
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(
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.clk (clk ),
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.rst (rst ),
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.tx_data_i (tx_data_i ),
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.tx_data_q (tx_data_q ),
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// debug ports
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.waveform_sel (2'd1 ),
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.sweep_on (1'b0 ),
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.freq_set ('b0 ),
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.iq_sel (2'b11 ),
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.bb_rshift (4'd0 )
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);
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rx_dmf #(
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.CHANNEL_NUM (1 )
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)u_rx_dmf
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(
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.clk (clk ),
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.rst (rst ),
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.din_valid (~rst ),
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.din_real (tx_data_i ),
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.din_imag (tx_data_q ),
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.dout_valid (dout_valid ),
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.dout_real (dout_real ),
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.dout_imag (dout_imag ),
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.peak_index (),
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.peak_value_i (),
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.peak_value_q (),
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.peak_valid ()
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);
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endmodule
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@@ -0,0 +1,110 @@
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%%%%%%%%%%%%%%%%%%%%%%%%%%
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%本仿真基于以下环境，64元矩形方阵，每若干个阵元通过TR通道和合路器，合成一路子阵信号，然后AD采样进入阵列信号处理单元；
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% - 子阵分割均匀，（16，16，16，16），共有4个子阵
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% - 1个已知方向的期望来波，3个未知方向的干扰信号；
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% - 信干比60dB；
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%θ表示俯仰角（来波与Z轴正向夹角）；φ表示方位角（来波在XOY平面投影与X轴正向夹角）；X轴与阵列每列平行，Y轴与阵列每行平行
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%通过空域滤波得到抑制干扰后的信号
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%%%%%%%%%%%%%%%%%%%%%%%%
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clc;
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clear all;
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Tt=256;%快拍数，用于阵列信号处理的采样点数
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Tmax = 32768;
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t=1:Tmax;
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%%%%%%%%%此处假设来波均为单频信号，可按自身定义修改
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f1=0.1*pi;
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f2=0.2*pi;
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f3=0.3*pi;
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f4=0.4*pi;
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%% 通信基带信号
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%% 窄带白噪声干扰信号
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filter_name = 'lpf_fs100_fpass5_fstop6.mat';
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%%
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snr=0;%信噪比可根据应用场景确定
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sjr=(60+snr);%干信比
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s1=sqrt(2*10^(snr/10))*exp(1i*f1*t);
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s2=sqrt(2*10^(sjr/10))*exp(1i*f2*t);
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s3=sqrt(2*10^(sjr/10))*exp(1i*f3*t);
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s4=sqrt(2*10^(sjr/10))*exp(1i*f4*t);
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%%%%%%%由信噪比和干信比计算出信号的幅度
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lamuda=1;%当前载频的波长，可根据载频输入实际值d
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d=0.5;%阵元间距，需小于最高工作频率半波长，可根据实际情况输入实际值
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theta1=20;%期望来波俯仰角
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phi1=30;%期望来波方位角
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theta2=-20;%干扰1俯仰角
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phi2=50;%干扰1方位角
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theta3=-40;%干扰2俯仰角
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phi3=80;%干扰2方位角
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theta4=-60;%干扰3俯仰角
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phi4=120;%干扰3方位角
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%%%%%%%%
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m=8;%列
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n=8;%行
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L=m*n;
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a1=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta1/180*pi)*sin(phi1/180*pi));
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b1=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta1/180*pi)*cos(phi1/180*pi));
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A1=kron(b1,a1);
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a2=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta2/180*pi)*sin(phi2/180*pi));
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b2=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta2/180*pi)*cos(phi2/180*pi));
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A2=kron(b2,a2);
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a3=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta3/180*pi)*sin(phi3/180*pi));
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b3=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta3/180*pi)*cos(phi3/180*pi));
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A3=kron(b3,a3);
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a4=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta4/180*pi)*sin(phi4/180*pi));
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b4=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta4/180*pi)*cos(phi4/180*pi));
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A4=kron(b4,a4);
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As=[A1,A2,A3,A4];%阵列流型
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rng(0);
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x=As*[s1;s2;s3;s4]+randn(L,Tmax);
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%%%%%%%%%%%%%%%4元子阵
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%
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N1=4;
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C1=zeros(N1,64);
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D1=zeros(N1,64);
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for kk=0:3
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C1(1,(kk*8+1):(kk*8+4))=ones(1,4);
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C1(2,(kk*8+5):(kk*8+8))=ones(1,4);
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C1(3,(kk*8+33):(kk*8+36))=ones(1,4);
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C1(4,(kk*8+37):(kk*8+40))=ones(1,4);
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end
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%}
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%%%%%%%%%%%%%%%%%%%%%%
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D1=C1*diag(A1');%4元 阵元通道移相后，每16路合路为一个子阵
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% D2=C2*diag(A1');%6元 阵元通道移相后，每(16,8)路合路为一个子阵
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% D3=C3*diag(A1');%8元 阵元通道移相后，每8路合路为一个子阵
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% %%%%%%%%%%%%%%%%%
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xs1=D1*x(:,1:Tt);
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Rx1=xs1*xs1';%4元子阵协方差矩阵
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Ax1=D1*A1;%期望来波方向的子阵导向矢量
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wx1=inv(Rx1)*Ax1/(Ax1'*inv(Rx1)*Ax1);%4子阵的LCMV权值
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xs1_long = D1*x;
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s_new1=wx1'*xs1_long;%4子阵情况下的空域滤波后的信号
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% s_new1=[1,1,1,1]*xs1;
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%% 数据导出
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xs1_long_12b = round(xs1_long/max(max(abs(xs1_long)))*(2^11-1));
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xs1_real_12b = real(xs1_long_12b);
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xs1_imag_12b = imag(xs1_long_12b);
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% writematrix(xs1_real_12b,'./xs1_real.csv');
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% writematrix(xs1_imag_12b,'./xs1_imag.csv');
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tb_snap = xs1_long_12b(:,(0:255)+54);
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tb_acorr = tb_snap*tb_snap';
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wx1_32b = round(wx1/max(abs(wx1))*(2^31-1));
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wx1_16b = floor(wx1_32b/2^16);
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s_new1_30b = wx1_16b'*xs1_long_12b;
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s_new1_12b = s_new1_30b/2^18;
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@@ -0,0 +1,255 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 2022/09/15 11:12:45
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// Last Modified Data: 2022/11/02
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// Design Name:
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// Module Name: tb_ad9361_cal
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description: testbench for [rx_pre_process]
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//
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// Dependencies:
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//
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||||
// Revision:
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||||
// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_rx_pre;
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localparam COL_NUM = 4;
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localparam PS_PL_WIDTH = 32;
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localparam OUTPUT_DATA_WIDTH = 30;
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localparam FRAME_HEAD = 32'b10110011100011110000111000110010;
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localparam FRAME_BITS = (2+COL_NUM*2)*PS_PL_WIDTH;
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reg [FRAME_BITS-1 : 0] weight_stream_buf =
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{
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FRAME_HEAD, 32'd40,
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-32'd1145474114, 32'd1816473250 ,
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32'd2059208152, -32'd254581925 ,
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32'd2062565030, 32'd244279278 ,
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-32'd1154406364, -32'd1806170603
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};
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reg sys_clk = 1'b1;
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reg sys_clk_4x = 1'b1;
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reg sys_rst = 1'b1;
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reg clk_96m = 1'b1;
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reg ant_rst = 1'b1;
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reg ad9361_1_cal_start = 'b0;
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wire ad9361_1_cal_done ;
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reg ad9361_2_cal_start = 'b0;
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wire ad9361_2_cal_done ;
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wire ad9361_cal_result ;
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wire ad9361_cal_valid ;
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reg ad9361_recal = 'b0;
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// phase difference of 0 degree
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wire [11:0] rx_ch1_i;
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wire [11:0] rx_ch1_q;
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wire [11:0] rx_ch2_i;
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wire [11:0] rx_ch2_q;
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wire [11:0] rx_ch3_q;
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wire [11:0] rx_ch3_i;
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wire [11:0] rx_ch4_i;
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wire [11:0] rx_ch4_q;
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reg hop_start_flag = 1'b0;
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wire accor_stream_valid;
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wire accor_stream_data;
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wire weight_stream_data;
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wire rx_data_valid;
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wire [OUTPUT_DATA_WIDTH-1:0] rx_data_i, rx_data_q;
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rx_pre_process #(
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.OUTPUT_DATA_WIDTH (OUTPUT_DATA_WIDTH )
|
||||
) u_rx_pre_process
|
||||
(
|
||||
// clock & reset
|
||||
.sys_clk (sys_clk ), // input sys_clk
|
||||
.sys_clk_4x (sys_clk_4x ), // input sys_clk_4x
|
||||
.sys_rst (sys_rst ), // input sys_rst
|
||||
.clk_96m (clk_96m ), // input clk_96m
|
||||
.ant_rst (ant_rst ), // input ant_rst
|
||||
// input data interface
|
||||
.rx_ch1_i (rx_ch1_i ), // input [11:0] rx_ch1_i
|
||||
.rx_ch1_q (rx_ch1_q ), // input [11:0] rx_ch1_q
|
||||
.rx_ch2_i (-rx_ch2_i ), // input [11:0] rx_ch2_i
|
||||
.rx_ch2_q (-rx_ch2_q ), // input [11:0] rx_ch2_q
|
||||
.rx_ch3_i (rx_ch3_i ), // input [11:0] rx_ch3_i
|
||||
.rx_ch3_q (rx_ch3_q ), // input [11:0] rx_ch3_q
|
||||
.rx_ch4_i (-rx_ch4_i ), // input [11:0] rx_ch4_i
|
||||
.rx_ch4_q (-rx_ch4_q ), // input [11:0] rx_ch4_q
|
||||
// ad9361 calibration interface
|
||||
.ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start
|
||||
.ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done
|
||||
.ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start
|
||||
.ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done
|
||||
.ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result
|
||||
.ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid
|
||||
.ad9361_recal (ad9361_recal ), // input ad9361_recal
|
||||
// nulling algotithm interface
|
||||
.hop_start_flag (hop_start_flag ), // input hop_start_flag
|
||||
.accor_stream_valid (accor_stream_valid ), // output accor_stream_valid
|
||||
.accor_stream_data (accor_stream_data ), // output accor_stream_data
|
||||
.weight_stream_data (weight_stream_data ), // input weight_stream_data
|
||||
.rx_data_valid (rx_data_valid ),
|
||||
.rx_data_i (rx_data_i ),
|
||||
.rx_data_q (rx_data_q )
|
||||
);
|
||||
|
||||
// system clock generation
|
||||
always begin
|
||||
#6;
|
||||
sys_clk = ~sys_clk;
|
||||
#14;
|
||||
end
|
||||
|
||||
always begin
|
||||
#5 sys_clk_4x = ~sys_clk_4x;
|
||||
end
|
||||
|
||||
always begin
|
||||
#7;
|
||||
clk_96m = ~clk_96m;
|
||||
#3;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#102
|
||||
sys_rst = 1'b0;
|
||||
ant_rst = 1'b0;
|
||||
#100
|
||||
ad9361_1_cal_start = 1'b1;
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (ad9361_1_cal_done) begin
|
||||
ad9361_2_cal_start <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
ad9361_2_cal_start <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
integer r_file_real;
|
||||
integer r_file_imag;
|
||||
|
||||
reg signed [11:0] rx_ch1_i_data = 'b0, rx_ch1_q_data = 'b0;
|
||||
reg signed [11:0] rx_ch2_i_data = 'b0, rx_ch2_q_data = 'b0;
|
||||
reg signed [11:0] rx_ch3_i_data = 'b0, rx_ch3_q_data = 'b0;
|
||||
reg signed [11:0] rx_ch4_i_data = 'b0, rx_ch4_q_data = 'b0;
|
||||
|
||||
reg [11:0] rx_ch1_i_cal = 12'd2047;
|
||||
reg [11:0] rx_ch1_q_cal = 12'd2047;
|
||||
reg [11:0] rx_ch2_i_cal = -12'd2047;
|
||||
reg [11:0] rx_ch2_q_cal = -12'd2047;
|
||||
reg [11:0] rx_ch3_q_cal = 12'd2047;
|
||||
reg [11:0] rx_ch3_i_cal = 12'd2047;
|
||||
reg [11:0] rx_ch4_i_cal = -12'd2047;
|
||||
reg [11:0] rx_ch4_q_cal = -12'd2047;
|
||||
|
||||
assign rx_ch1_i = ad9361_cal_valid ? rx_ch1_i_data : rx_ch1_i_cal;
|
||||
assign rx_ch1_q = ad9361_cal_valid ? rx_ch1_q_data : rx_ch1_q_cal;
|
||||
assign rx_ch2_i = ad9361_cal_valid ? rx_ch2_i_data : rx_ch2_i_cal;
|
||||
assign rx_ch2_q = ad9361_cal_valid ? rx_ch2_q_data : rx_ch2_q_cal;
|
||||
assign rx_ch3_i = ad9361_cal_valid ? rx_ch3_i_data : rx_ch3_i_cal;
|
||||
assign rx_ch3_q = ad9361_cal_valid ? rx_ch3_q_data : rx_ch3_q_cal;
|
||||
assign rx_ch4_i = ad9361_cal_valid ? rx_ch4_i_data : rx_ch4_i_cal;
|
||||
assign rx_ch4_q = ad9361_cal_valid ? rx_ch4_q_data : rx_ch4_q_cal;
|
||||
|
||||
initial begin
|
||||
forever begin
|
||||
@(posedge sys_clk)
|
||||
// 校准数据
|
||||
#720
|
||||
rx_ch1_i_cal = ~rx_ch1_i_cal;
|
||||
rx_ch2_i_cal = ~rx_ch2_i_cal;
|
||||
rx_ch3_i_cal = ~rx_ch3_i_cal;
|
||||
rx_ch4_i_cal = ~rx_ch4_i_cal;
|
||||
#240
|
||||
rx_ch1_q_cal = ~rx_ch1_q_cal;
|
||||
rx_ch2_q_cal = ~rx_ch2_q_cal;
|
||||
rx_ch3_q_cal = ~rx_ch3_q_cal;
|
||||
rx_ch4_q_cal = ~rx_ch4_q_cal;
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
r_file_real = $fopen("../../../../../testbenches/xs1_real.csv","r");
|
||||
r_file_imag = $fopen("../../../../../testbenches/xs1_imag.csv","r");
|
||||
|
||||
@(posedge ad9361_cal_valid)
|
||||
|
||||
forever begin
|
||||
@(posedge sys_clk)
|
||||
$fscanf(r_file_real,"%d,%d,%d,%d",
|
||||
rx_ch1_i_data,
|
||||
rx_ch2_i_data,
|
||||
rx_ch3_i_data,
|
||||
rx_ch4_i_data);
|
||||
$fscanf(r_file_imag,"%d,%d,%d,%d",
|
||||
rx_ch1_q_data,
|
||||
rx_ch2_q_data,
|
||||
rx_ch3_q_data,
|
||||
rx_ch4_q_data);
|
||||
end
|
||||
end
|
||||
|
||||
// hop flag counter
|
||||
reg [$clog2(38400)-1 : 0] hop_cnt = 'b0;
|
||||
|
||||
always @(posedge sys_clk_4x) begin
|
||||
if (sys_rst) begin
|
||||
hop_cnt <= 'b0;
|
||||
hop_start_flag <= 1'b0;
|
||||
end
|
||||
else if (ad9361_cal_valid) begin
|
||||
hop_cnt <= (hop_cnt == 38399) ? 'b0 : hop_cnt + 1'b1;
|
||||
hop_start_flag <= (hop_cnt == 1'b1) ? 1'b1 : 1'b0;
|
||||
end
|
||||
else begin
|
||||
hop_cnt <= hop_cnt;
|
||||
hop_start_flag <= hop_start_flag;
|
||||
end
|
||||
end
|
||||
|
||||
//
|
||||
reg weight_stream_valid = 'b0;
|
||||
|
||||
always @(negedge accor_stream_valid) begin
|
||||
#((48*50)*40+18); // 50us of 48M clock
|
||||
weight_stream_valid = 'b1;
|
||||
#(FRAME_BITS*20);
|
||||
weight_stream_valid = 'b0;
|
||||
end
|
||||
|
||||
reg [$clog2(FRAME_BITS)-1 : 0] weight_stream_cnt;
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (sys_rst) begin
|
||||
weight_stream_cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
weight_stream_cnt <= (weight_stream_valid & ~(weight_stream_cnt == FRAME_BITS - 1)) ? weight_stream_cnt + 1'b1 : 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign weight_stream_data = weight_stream_buf[FRAME_BITS-1-weight_stream_cnt];
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,255 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/11/16 15:58:28
|
||||
// Design Name:
|
||||
// Module Name: tb_rx_pre_test
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: Co-simulation testbench for [rx_pre_process] and [rx_pre_test]
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb_rx_pre_test;
|
||||
|
||||
localparam COL_NUM = 4;
|
||||
localparam PS_PL_WIDTH = 32;
|
||||
|
||||
localparam FRAME_HEAD = 32'h7E7E7E7E;
|
||||
localparam FRAME_BITS = (2+COL_NUM*2)*PS_PL_WIDTH;
|
||||
|
||||
reg [FRAME_BITS-1 : 0] weight_stream_buf =
|
||||
{
|
||||
FRAME_HEAD, 32'd40,
|
||||
-32'd1145474114, 32'd1816473250,
|
||||
32'd2059208152, -32'd254581925 ,
|
||||
32'd2062565030, 32'd244279278 ,
|
||||
-32'd1154406364, -32'd1806170603
|
||||
};
|
||||
|
||||
reg sys_clk = 1'b1;
|
||||
reg sys_clk_2x = 1'b1;
|
||||
reg sys_clk_4x = 1'b1;
|
||||
reg sys_rst = 1'b1;
|
||||
wire clk_96m;
|
||||
wire ant_rst;
|
||||
|
||||
reg ad9361_1_cal_start = 'b0;
|
||||
wire ad9361_1_cal_done ;
|
||||
reg ad9361_2_cal_start = 'b0;
|
||||
wire ad9361_2_cal_done ;
|
||||
wire ad9361_cal_result ;
|
||||
wire ad9361_cal_valid ;
|
||||
reg ad9361_recal = 'b0;
|
||||
|
||||
// phase difference of 0 degree
|
||||
reg [11:0] rx_ch1_i = 0, rx_ch1_q = 0;
|
||||
reg [11:0] rx_ch2_i = 0, rx_ch2_q = 0;
|
||||
reg [11:0] rx_ch3_i = 0, rx_ch3_q = 0;
|
||||
reg [11:0] rx_ch4_i = 0, rx_ch4_q = 0;
|
||||
|
||||
wire [11:0] rx_ch1_i_test, rx_ch1_q_test;
|
||||
wire [11:0] rx_ch2_i_test, rx_ch2_q_test;
|
||||
wire [11:0] rx_ch3_i_test, rx_ch3_q_test;
|
||||
wire [11:0] rx_ch4_i_test, rx_ch4_q_test;
|
||||
|
||||
reg [11:0] rx_ch1_i_cal = 12'd2047;
|
||||
reg [11:0] rx_ch1_q_cal = 12'd2047;
|
||||
reg [11:0] rx_ch2_i_cal = -12'd2047;
|
||||
reg [11:0] rx_ch2_q_cal = -12'd2047;
|
||||
reg [11:0] rx_ch3_q_cal = 12'd2047;
|
||||
reg [11:0] rx_ch3_i_cal = 12'd2047;
|
||||
reg [11:0] rx_ch4_i_cal = -12'd2047;
|
||||
reg [11:0] rx_ch4_q_cal = -12'd2047;
|
||||
|
||||
wire hop_start_flag;
|
||||
wire accor_stream_valid;
|
||||
wire accor_stream_data;
|
||||
wire weight_stream_data;
|
||||
wire rx_data_valid;
|
||||
wire [29:0] rx_data_i, rx_data_q;
|
||||
|
||||
reg hop_trigger = 1'b0;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////////////// Clock Generation ///////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
always #5 sys_clk_4x = ~sys_clk_4x;
|
||||
|
||||
always @(posedge sys_clk_4x) begin
|
||||
sys_clk_2x <= ~sys_clk_2x;
|
||||
end
|
||||
|
||||
always @(posedge sys_clk_2x) begin
|
||||
sys_clk <= ~sys_clk;
|
||||
end
|
||||
|
||||
assign #3 clk_96m = sys_clk_2x;
|
||||
assign #3 ant_rst = sys_rst;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////////////// Stimulus Generation //////////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
initial begin
|
||||
#102
|
||||
sys_rst = 1'b0;
|
||||
#100
|
||||
ad9361_1_cal_start = 1'b1;
|
||||
wait(ad9361_cal_valid);
|
||||
#1000
|
||||
hop_trigger = 1'b1;
|
||||
#100
|
||||
hop_trigger = 1'b0;
|
||||
#(19600*40-100) // after a long time, trig again
|
||||
hop_trigger = 1'b1;
|
||||
#100
|
||||
hop_trigger = 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (ad9361_1_cal_done) begin
|
||||
ad9361_2_cal_start <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
ad9361_2_cal_start <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge sys_clk) begin
|
||||
if (ad9361_cal_valid) begin
|
||||
rx_ch1_i <= rx_ch1_i_test;
|
||||
rx_ch1_q <= rx_ch1_q_test;
|
||||
rx_ch2_i <= rx_ch2_i_test;
|
||||
rx_ch2_q <= rx_ch2_q_test;
|
||||
rx_ch3_i <= rx_ch3_i_test;
|
||||
rx_ch3_q <= rx_ch3_q_test;
|
||||
rx_ch4_i <= rx_ch4_i_test;
|
||||
rx_ch4_q <= rx_ch4_q_test;
|
||||
end
|
||||
else begin
|
||||
rx_ch1_i <= rx_ch1_i_cal;
|
||||
rx_ch1_q <= rx_ch1_q_cal;
|
||||
rx_ch2_i <= rx_ch2_i_cal;
|
||||
rx_ch2_q <= rx_ch2_q_cal;
|
||||
rx_ch3_i <= rx_ch3_i_cal;
|
||||
rx_ch3_q <= rx_ch3_q_cal;
|
||||
rx_ch4_i <= rx_ch4_i_cal;
|
||||
rx_ch4_q <= rx_ch4_q_cal;
|
||||
end
|
||||
end
|
||||
|
||||
// 校准数据
|
||||
always @(posedge sys_clk) begin
|
||||
rx_ch1_i_cal = ~rx_ch1_i_cal;
|
||||
rx_ch1_q_cal = ~rx_ch1_q_cal;
|
||||
rx_ch2_i_cal = ~rx_ch2_i_cal;
|
||||
rx_ch2_q_cal = ~rx_ch2_q_cal;
|
||||
rx_ch3_i_cal = ~rx_ch3_i_cal;
|
||||
rx_ch3_q_cal = ~rx_ch3_q_cal;
|
||||
rx_ch4_i_cal = ~rx_ch4_i_cal;
|
||||
rx_ch4_q_cal = ~rx_ch4_q_cal;
|
||||
end
|
||||
|
||||
reg weight_stream_valid = 'b0;
|
||||
|
||||
always @(negedge accor_stream_valid) begin
|
||||
#((48*50)*40+18); // 50us of 48M clock
|
||||
weight_stream_valid = 'b1;
|
||||
#(FRAME_BITS*20);
|
||||
weight_stream_valid = 'b0;
|
||||
end
|
||||
|
||||
reg [$clog2(FRAME_BITS)-1 : 0] weight_stream_cnt;
|
||||
|
||||
always @(posedge clk_96m) begin
|
||||
if (sys_rst) begin
|
||||
weight_stream_cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
weight_stream_cnt <= (weight_stream_valid & ~(weight_stream_cnt == FRAME_BITS - 1)) ? weight_stream_cnt + 1'b1 : 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
assign weight_stream_data = weight_stream_buf[FRAME_BITS-1-weight_stream_cnt];
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/////////////////////// Simulation Module Instantiation ////////////////////////
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
rx_pre_process #(
|
||||
.OUTPUT_DATA_WIDTH (30 )
|
||||
) u_rx_pre_process
|
||||
(
|
||||
// clock & reset
|
||||
.sys_clk (sys_clk ), // sync to adc data
|
||||
.sys_clk_4x (sys_clk_4x ), // sync to physical layer
|
||||
.sys_rst (sys_rst ), // sync to [sys_clk]
|
||||
.clk_96m (clk_96m ), // sync to c2c data
|
||||
.ant_rst (ant_rst ), // sync to [clk_96m]
|
||||
// input data interface
|
||||
.rx_ch1_i (rx_ch1_i ),
|
||||
.rx_ch1_q (rx_ch1_q ),
|
||||
.rx_ch2_i (rx_ch2_i ),
|
||||
.rx_ch2_q (rx_ch2_q ),
|
||||
.rx_ch3_i (rx_ch3_i ),
|
||||
.rx_ch3_q (rx_ch3_q ),
|
||||
.rx_ch4_i (rx_ch4_i ),
|
||||
.rx_ch4_q (rx_ch4_q ),
|
||||
// ad9361 calibration interface
|
||||
.ad9361_1_cal_start (ad9361_1_cal_start ),
|
||||
.ad9361_1_cal_done (ad9361_1_cal_done ),
|
||||
.ad9361_2_cal_start (ad9361_2_cal_start ),
|
||||
.ad9361_2_cal_done (ad9361_2_cal_done ),
|
||||
.ad9361_cal_result (ad9361_cal_result ),
|
||||
.ad9361_cal_valid (ad9361_cal_valid ),
|
||||
.ad9361_recal (ad9361_recal ),
|
||||
// nulling algotithm interface
|
||||
.hop_start_flag (hop_start_flag ), // sync to [sys_clk_4x]
|
||||
.accor_stream_valid (accor_stream_valid ), // sync to [clk_96m]
|
||||
.accor_stream_data (accor_stream_data ), // sync to [clk_96m]
|
||||
.weight_stream_data (weight_stream_data ), // sync to [clk_96m]
|
||||
.rx_data_valid (rx_data_valid ), // sync to [sys_clk]
|
||||
.rx_data_i (rx_data_i ), // sync to [sys_clk]
|
||||
.rx_data_q (rx_data_q ) // sync to [sys_clk]
|
||||
);
|
||||
|
||||
// temporary test cases
|
||||
rx_pre_test u_rx_pre_test
|
||||
(
|
||||
// clock & reset
|
||||
.sys_clk (sys_clk ),
|
||||
.sys_rst (sys_rst ),
|
||||
.sys_clk_4x (sys_clk_4x ),
|
||||
.hop_trigger (hop_trigger ),
|
||||
.hop_trigger_en (1'b1 ),
|
||||
// calc result
|
||||
.ad9361_cal_result (ad9361_cal_result ),
|
||||
.ad9361_cal_valid (ad9361_cal_valid ),
|
||||
// output test data
|
||||
.rx_ch1_i (rx_ch1_i_test ),
|
||||
.rx_ch1_q (rx_ch1_q_test ),
|
||||
.rx_ch2_i (rx_ch2_i_test ),
|
||||
.rx_ch2_q (rx_ch2_q_test ),
|
||||
.rx_ch3_i (rx_ch3_i_test ),
|
||||
.rx_ch3_q (rx_ch3_q_test ),
|
||||
.rx_ch4_i (rx_ch4_i_test ),
|
||||
.rx_ch4_q (rx_ch4_q_test ),
|
||||
.hop_start_flag (hop_start_flag )
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,117 @@
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
%本仿真基于以下环境，64元矩形方阵，每若干个阵元通过TR通道和合路器，合成一路子阵信号，然后AD采样进入阵列信号处理单元；
|
||||
% - 子阵分割均匀，（16，16，16，16），共有4个子阵
|
||||
% - 1个已知方向的期望来波，3个未知方向的干扰信号；
|
||||
% - 信干比60dB；
|
||||
%θ表示俯仰角（来波与Z轴正向夹角）；φ表示方位角（来波在XOY平面投影与X轴正向夹角）；X轴与阵列每列平行，Y轴与阵列每行平行
|
||||
%通过空域滤波得到抑制干扰后的信号
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
clc;
|
||||
clear all;
|
||||
Tt=256;%快拍数，用于阵列信号处理的采样点数
|
||||
Tmax = 32768;
|
||||
t=1:Tmax;
|
||||
%%%%%%%%%此处假设来波均为单频信号，可按自身定义修改
|
||||
f1=0.1*pi;
|
||||
f2=0.2*pi;
|
||||
f3=0.3*pi;
|
||||
f4=0.4*pi;
|
||||
|
||||
%% 通信基带信号
|
||||
|
||||
%% 窄带白噪声干扰信号
|
||||
filter_name = 'lpf_fs100_fpass5_fstop6.mat';
|
||||
%%
|
||||
snr=0;%信噪比可根据应用场景确定
|
||||
sjr=(60+snr);%干信比
|
||||
s1=sqrt(2*10^(snr/10))*exp(1i*f1*t);
|
||||
s2=sqrt(2*10^(sjr/10))*exp(1i*f2*t);
|
||||
s3=sqrt(2*10^(sjr/10))*exp(1i*f3*t);
|
||||
s4=sqrt(2*10^(sjr/10))*exp(1i*f4*t);
|
||||
%%%%%%%由信噪比和干信比计算出信号的幅度
|
||||
lamuda=1;%当前载频的波长，可根据载频输入实际值d
|
||||
d=0.5;%阵元间距，需小于最高工作频率半波长，可根据实际情况输入实际值
|
||||
|
||||
theta1=20;%期望来波俯仰角
|
||||
phi1=30;%期望来波方位角
|
||||
|
||||
theta2=-20;%干扰1俯仰角
|
||||
phi2=50;%干扰1方位角
|
||||
|
||||
theta3=-40;%干扰2俯仰角
|
||||
phi3=80;%干扰2方位角
|
||||
|
||||
theta4=-60;%干扰3俯仰角
|
||||
phi4=120;%干扰3方位角
|
||||
|
||||
%%%%%%%%
|
||||
m=8;%列
|
||||
n=8;%行
|
||||
L=m*n;
|
||||
a1=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta1/180*pi)*sin(phi1/180*pi));
|
||||
b1=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta1/180*pi)*cos(phi1/180*pi));
|
||||
A1=kron(b1,a1);
|
||||
|
||||
a2=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta2/180*pi)*sin(phi2/180*pi));
|
||||
b2=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta2/180*pi)*cos(phi2/180*pi));
|
||||
A2=kron(b2,a2);
|
||||
|
||||
a3=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta3/180*pi)*sin(phi3/180*pi));
|
||||
b3=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta3/180*pi)*cos(phi3/180*pi));
|
||||
A3=kron(b3,a3);
|
||||
|
||||
a4=exp(1i*2*pi*d/lamuda*(-(m/2-1/2):1:(m/2-1/2)).'*sin(theta4/180*pi)*sin(phi4/180*pi));
|
||||
b4=exp(1i*2*pi*d/lamuda*(-(n/2-1/2):1:(n/2-1/2)).'*sin(theta4/180*pi)*cos(phi4/180*pi));
|
||||
A4=kron(b4,a4);
|
||||
|
||||
As=[A1,A2,A3,A4];%阵列流型
|
||||
rng(0);
|
||||
x=As*[s1;s2;s3;s4]+randn(L,Tmax);
|
||||
%%%%%%%%%%%%%%%4元子阵
|
||||
%
|
||||
N1=4;
|
||||
C1=zeros(N1,64);
|
||||
D1=zeros(N1,64);
|
||||
for kk=0:3
|
||||
C1(1,(kk*8+1):(kk*8+4))=ones(1,4);
|
||||
C1(2,(kk*8+5):(kk*8+8))=ones(1,4);
|
||||
C1(3,(kk*8+33):(kk*8+36))=ones(1,4);
|
||||
C1(4,(kk*8+37):(kk*8+40))=ones(1,4);
|
||||
end
|
||||
%}
|
||||
%%%%%%%%%%%%%%%%%%%%%%
|
||||
D1=C1*diag(A1');%4元 阵元通道移相后，每16路合路为一个子阵
|
||||
% D2=C2*diag(A1');%6元 阵元通道移相后，每(16,8)路合路为一个子阵
|
||||
% D3=C3*diag(A1');%8元 阵元通道移相后，每8路合路为一个子阵
|
||||
% %%%%%%%%%%%%%%%%%
|
||||
xs1=D1*x(:,1:Tt);
|
||||
Rx1=xs1*xs1';%4元子阵协方差矩阵
|
||||
Ax1=D1*A1;%期望来波方向的子阵导向矢量
|
||||
wx1=inv(Rx1)*Ax1/(Ax1'*inv(Rx1)*Ax1);%4子阵的LCMV权值
|
||||
|
||||
xs1_long = D1*x;
|
||||
s_new1=wx1'*xs1_long;%4子阵情况下的空域滤波后的信号
|
||||
% s_new1=[1,1,1,1]*xs1;
|
||||
|
||||
%% 数据导出
|
||||
xs1_long_12b = round(xs1_long/max(max(abs(xs1_long)))*(2^11-1));
|
||||
xs1_real_12b = real(xs1_long_12b);
|
||||
xs1_imag_12b = imag(xs1_long_12b);
|
||||
|
||||
xs1_12b_bin_join = strings(9600,96);
|
||||
|
||||
for i = 1:9600
|
||||
xs1_real_12b_bin = dec2bin(xs1_real_12b(:,i),16);
|
||||
xs1_real_12b_bin_join_tmp = '';
|
||||
xs1_imag_12b_bin = dec2bin(xs1_imag_12b(:,i),16);
|
||||
xs1_imag_12b_bin_join_tmp = '';
|
||||
for j = 1:4
|
||||
xs1_real_12b_bin_trunc = xs1_real_12b_bin(j,5:16);
|
||||
xs1_real_12b_bin_join_tmp = [xs1_real_12b_bin_join_tmp,xs1_real_12b_bin_trunc];
|
||||
xs1_imag_12b_bin_trunc = xs1_imag_12b_bin(j,5:16);
|
||||
xs1_imag_12b_bin_join_tmp = [xs1_imag_12b_bin_join_tmp,xs1_imag_12b_bin_trunc];
|
||||
end
|
||||
xs1_12b_bin_join(i) = [xs1_real_12b_bin_join_tmp,xs1_imag_12b_bin_join_tmp];
|
||||
end
|
||||
|
||||
coe
|
||||
@@ -0,0 +1,85 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2022/11/16 15:08:02
|
||||
// Design Name:
|
||||
// Module Name: tb_rx_test
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description: testbench for [rx_pre_test]
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb_rx_test;
|
||||
|
||||
reg sys_clk = 1'b1;
|
||||
reg sys_clk_4x = 1'b1;
|
||||
reg sys_rst = 1'b1;
|
||||
reg hop_trigger = 1'b0;
|
||||
|
||||
reg ad9361_cal_result = 1'b0;
|
||||
reg ad9361_cal_valid = 1'b0;
|
||||
|
||||
wire [11:0] rx_ch1_i;
|
||||
wire [11:0] rx_ch1_q;
|
||||
wire [11:0] rx_ch2_i;
|
||||
wire [11:0] rx_ch2_q;
|
||||
wire [11:0] rx_ch3_i;
|
||||
wire [11:0] rx_ch3_q;
|
||||
wire [11:0] rx_ch4_i;
|
||||
wire [11:0] rx_ch4_q;
|
||||
wire hop_start_flag;
|
||||
|
||||
rx_pre_test u_rx_pre_test
|
||||
(
|
||||
// clock & reset
|
||||
.clk (sys_clk ),
|
||||
.rst (sys_rst ),
|
||||
.hop_trigger (hop_trigger ),
|
||||
// calc result
|
||||
.ad9361_cal_result (ad9361_cal_result ),
|
||||
.ad9361_cal_valid (ad9361_cal_valid ),
|
||||
// output test data
|
||||
.rx_ch1_i (rx_ch1_i ),
|
||||
.rx_ch1_q (rx_ch1_q ),
|
||||
.rx_ch2_i (rx_ch2_i ),
|
||||
.rx_ch2_q (rx_ch2_q ),
|
||||
.rx_ch3_i (rx_ch3_i ),
|
||||
.rx_ch3_q (rx_ch3_q ),
|
||||
.rx_ch4_i (rx_ch4_i ),
|
||||
.rx_ch4_q (rx_ch4_q ),
|
||||
.hop_start_flag (hop_start_flag )
|
||||
);
|
||||
|
||||
// system clock generation
|
||||
always begin
|
||||
#5 sys_clk = ~sys_clk;
|
||||
end
|
||||
|
||||
initial begin
|
||||
#102
|
||||
sys_rst = 1'b0;
|
||||
#100
|
||||
ad9361_cal_valid = 1'b1;
|
||||
#1000
|
||||
hop_trigger = 1'b1;
|
||||
#100
|
||||
hop_trigger = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,93 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
// _ _ ____
|
||||
// | | ___ ___| |__ / ___| __ _ ___
|
||||
// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
|
||||
// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
|
||||
// \___/ \___/|___/_| |_| \____|\__,_|\___/
|
||||
//
|
||||
// Create Date: 2023/02/25 15:50:45
|
||||
// Design Name:
|
||||
// Module Name: tb_tx_pre_process
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb_tx_pre_process;
|
||||
|
||||
reg clk = 1'b1;
|
||||
reg rst = 1'b1;
|
||||
|
||||
reg [11:0] tx_data_ch1_i = 'b0;
|
||||
reg [11:0] tx_data_ch1_q = 'b0;
|
||||
reg [11:0] tx_data_ch2_i = 'b0;
|
||||
reg [11:0] tx_data_ch2_q = 'b0;
|
||||
|
||||
reg ad9361_tx_switch = 1'b0;
|
||||
|
||||
reg [3:0] bb_rshift = 4'd3;
|
||||
|
||||
wire [11:0] tx_ch1_i;
|
||||
wire [11:0] tx_ch1_q;
|
||||
wire [11:0] tx_ch2_i;
|
||||
wire [11:0] tx_ch2_q;
|
||||
|
||||
tx_pre_process #(
|
||||
.CAL_MOD_FINE (1 )
|
||||
) u_tx_pre_process
|
||||
(
|
||||
// clock & reset
|
||||
.clk (clk ),
|
||||
.rst (rst ),
|
||||
// input data
|
||||
.tx_data_ch1_i (tx_data_ch1_i ),
|
||||
.tx_data_ch1_q (tx_data_ch1_q ),
|
||||
.tx_data_ch2_i (tx_data_ch2_i ),
|
||||
.tx_data_ch2_q (tx_data_ch2_q ),
|
||||
// ad9361 calibration interface
|
||||
.ad9361_tx_switch (ad9361_tx_switch ),
|
||||
//
|
||||
.bb_rshift (bb_rshift ),
|
||||
// output data
|
||||
.tx_ch1_i (tx_ch1_i ),
|
||||
.tx_ch1_q (tx_ch1_q ),
|
||||
.tx_ch2_i (tx_ch2_i ),
|
||||
.tx_ch2_q (tx_ch2_q )
|
||||
);
|
||||
|
||||
initial begin
|
||||
#102 rst = 1'b0;
|
||||
#100 ad9361_tx_switch = 1'b1;
|
||||
#10000 ad9361_tx_switch = 1'b0;
|
||||
end
|
||||
|
||||
always #10 clk = ~clk;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
tx_data_ch1_i <= 'b0;
|
||||
tx_data_ch1_q <= 'b0;
|
||||
tx_data_ch2_i <= 'b0;
|
||||
tx_data_ch2_q <= 'b0;
|
||||
end
|
||||
else begin
|
||||
tx_data_ch1_i <= tx_data_ch1_i + 12'd1;
|
||||
tx_data_ch1_q <= tx_data_ch1_q + 12'd2;
|
||||
tx_data_ch2_i <= tx_data_ch2_i + 12'd3;
|
||||
tx_data_ch2_q <= tx_data_ch2_q + 12'd4;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,86 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 03/29/2023 09:02:30 PM
|
||||
// Design Name:
|
||||
// Module Name: tb_xpm_cdc_pulse
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module tb_xpm_cdc_pulse;
|
||||
|
||||
reg sys_clk = 1'b1;
|
||||
reg sys_clk_4x = 1'b1;
|
||||
reg sys_rst = 1'b1;
|
||||
|
||||
reg src_pulse = 1'b0;
|
||||
wire dest_pulse;
|
||||
|
||||
xpm_cdc_pulse #(
|
||||
.DEST_SYNC_FF (4), // DECIMAL; range: 2-10
|
||||
.INIT_SYNC_FF (0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values
|
||||
.REG_OUTPUT (1), // DECIMAL; 0=disable registered output, 1=enable registered output
|
||||
.RST_USED (1), // DECIMAL; 0=no reset, 1=implement reset
|
||||
.SIM_ASSERT_CHK (1) // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||
) u_xpm_cdc_pulse
|
||||
(
|
||||
.dest_pulse (dest_pulse ), // 1-bit output: Outputs a pulse the size of one dest_clk period when a pulse
|
||||
// transfer is correctly initiated on src_pulse input. This output is
|
||||
// combinatorial unless REG_OUTPUT is set to 1.
|
||||
.dest_clk (sys_clk ), // 1-bit input: Destination clock.
|
||||
.dest_rst (sys_rst ), // 1-bit input: optional; required when RST_USED = 1
|
||||
.src_clk (sys_clk_4x ), // 1-bit input: Source clock.
|
||||
.src_pulse (src_pulse ), // 1-bit input: Rising edge of this signal initiates a pulse transfer to the
|
||||
// destination clock domain. The minimum gap between each pulse transfer must be
|
||||
// at the minimum 2*(larger(src_clk period, dest_clk period)). This is measured
|
||||
// between the falling edge of a src_pulse to the rising edge of the next
|
||||
// src_pulse. This minimum gap will guarantee that each rising edge of src_pulse
|
||||
// will generate a pulse the size of one dest_clk period in the destination
|
||||
// clock domain. When RST_USED = 1, pulse transfers will not be guaranteed while
|
||||
// src_rst and/or dest_rst are asserted.
|
||||
.src_rst (sys_rst ) // 1-bit input: optional; required when RST_USED = 1
|
||||
);
|
||||
|
||||
initial begin
|
||||
#102;
|
||||
sys_rst = 1'b0;
|
||||
end
|
||||
|
||||
always begin
|
||||
#3;
|
||||
sys_clk = ~sys_clk;
|
||||
#37;
|
||||
end
|
||||
|
||||
always begin
|
||||
#5;
|
||||
sys_clk_4x = ~sys_clk_4x;
|
||||
end
|
||||
|
||||
reg [3:0] pulse_cnt = 'b0;
|
||||
|
||||
always @(posedge sys_clk_4x) begin
|
||||
if (sys_rst) begin
|
||||
src_pulse <= 1'b0;
|
||||
pulse_cnt <= 'b0;
|
||||
end
|
||||
else begin
|
||||
pulse_cnt <= pulse_cnt + 1'b1;
|
||||
src_pulse <= (pulse_cnt == 4'd15) ? 1'b1 : 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
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Reference in New Issue
Block a user