diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_sim_netlist.v b/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_sim_netlist.v new file mode 100644 index 00000000..a2b1ae36 --- /dev/null +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:898978d4f3b5a64415c6692f23de0e59488da509f2eb0fc37e6c3f23fe0e2ec9 +size 1343965 diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_sim_netlist.vhdl b/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_sim_netlist.vhdl new file mode 100644 index 00000000..92907bdd --- /dev/null +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:45af4a0c37b40c26a44a084d79f5bf4f2e909db830a3fd4ee931dea7753ab9e4 +size 2153323 diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_stub.v b/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_stub.v index dc976c9b..c11093f1 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_stub.v +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Wed Apr 12 20:00:12 2023 +// Date : Mon Jun 5 20:29:00 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.v diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_stub.vhdl b/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_stub.vhdl index dbde49e4..8e407dc6 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_stub.vhdl +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/atan2_16b_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Wed Apr 12 20:00:12 2023 +-- Date : Mon Jun 5 20:29:01 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.vhdl diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/demo_tb/tb_atan2_16b.vhd b/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/demo_tb/tb_atan2_16b.vhd new file mode 100644 index 00000000..16c2ffa8 --- /dev/null +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/demo_tb/tb_atan2_16b.vhd @@ -0,0 +1,376 @@ +-------------------------------------------------------------------------------- +-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- Description: +-- This is an example testbench for the CORDIC IP core. +-- The testbench has been generated by Vivado to accompany the IP core +-- instance you have generated. +-- +-- This testbench is for demonstration purposes only. See note below for +-- instructions on how to use it with your core. +-- +-- See the CORDIC product guide for further information +-- about this core. +-- +-------------------------------------------------------------------------------- +-- Using this testbench +-- +-- This testbench instantiates your generated CORDIC core +-- instance named "atan2_16b". +-- +-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado +-- documentation for details. +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity tb_atan2_16b is +end tb_atan2_16b; + +architecture tb of tb_atan2_16b is + + ----------------------------------------------------------------------- + -- Timing constants + ----------------------------------------------------------------------- + constant CLOCK_PERIOD : time := 100 ns; + constant T_HOLD : time := 10 ns; + constant T_STROBE : time := CLOCK_PERIOD - (1 ns); + constant TEST_CYCLES : integer := 3000; + constant PHASE_CYCLES : integer := 1000; + + ----------------------------------------------------------------------- + -- DUT input signals + ----------------------------------------------------------------------- + + -- General inputs + signal aclk : std_logic := '0'; -- the master clock + + -- Slave channel CARTESIAN inputs + signal s_axis_cartesian_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_CARTESIAN + signal s_axis_cartesian_tdata : std_logic_vector(31 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_CARTESIAN + + -- Slave channel PHASE inputs + signal s_axis_phase_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_PHASE + signal s_axis_phase_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_PHASE + + ----------------------------------------------------------------------- + -- DUT output signals + ----------------------------------------------------------------------- + + -- Master channel DOUT outputs + signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel M_AXIS_DOUT + signal m_axis_dout_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- TDATA for channel M_AXIS_DOUT + + ----------------------------------------------------------------------- + -- Aliases for AXI channel TDATA fields + -- These are a convenience for viewing data in a simulator waveform viewer. + -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command + -- to prevent the simulator optimizing away these signals. + ----------------------------------------------------------------------- + signal s_axis_cartesian_tdata_real : std_logic_vector(15 downto 0) := (others => '0'); + signal s_axis_cartesian_tdata_imag : std_logic_vector(15 downto 0) := (others => '0'); + signal s_axis_phase_tdata_real : std_logic_vector(15 downto 0) := (others => '0'); + + signal m_axis_dout_tdata_real : std_logic_vector(15 downto 0) := (others => '0'); + signal m_axis_dout_tdata_imag : std_logic_vector(15 downto 0) := (others => '0'); + signal m_axis_dout_tdata_phase : std_logic_vector(15 downto 0) := (others => '0'); + ----------------------------------------------------------------------- + -- Testbench signals + ----------------------------------------------------------------------- + + signal cycles : integer := 0; -- Clock cycle counter + + ----------------------------------------------------------------------- + -- Constants, types and functions to create input data + -- The CORDIC is fed two sinusoids exp(+/-jwt) of different frequencies and amplitudes: + -- channel CARTESIAN: exp(+jwt), frequency = clock / 30, + -- channel PHASE: exp(-jwt), frequency = clock / 32, + ----------------------------------------------------------------------- + + constant IP_CARTESIAN_DEPTH : integer := 30; + constant IP_CARTESIAN_WIDTH : integer := 16; + constant IP_CARTESIAN_SHIFT : integer := 3; -- bit shift for amplitude + constant IP_PHASE_DEPTH : integer := 32; + constant IP_PHASE_WIDTH : integer := 16; + constant IP_PHASE_SHIFT : integer := 0; -- no bit shift, max amplitude + type T_IP_INT_ENTRY is record + re : integer; + im : integer; + end record; + type T_IP_CARTESIAN_ENTRY is record + re : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0); + im : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0); + end record; + type T_IP_PHASE_ENTRY is record + re : std_logic_vector(IP_PHASE_WIDTH-1 downto 0); + end record; + type T_IP_CARTESIAN_TABLE is array (0 to IP_CARTESIAN_DEPTH-1) of T_IP_CARTESIAN_ENTRY; + type T_IP_PHASE_TABLE is array (0 to IP_PHASE_DEPTH-1) of T_IP_PHASE_ENTRY; + + -- Common function to calculate sine and cosine values + function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is + variable result : T_IP_INT_ENTRY; + variable theta : real; + variable limited_width : integer := width - 2; + begin + if limited_width > 30 then + limited_width := 30; --avoid integer overflow + end if; + theta := real(index) / real(depth) * 2.0 * MATH_PI; + result.re := integer(round(cos(theta) * real(2**limited_width))); + result.im := integer(round(sin(theta) * real(2**limited_width))); + return result; + end function create_ip_entry; + + -- Use separate functions to calculate channel S_AXIS_CARTESIAN and S_AXIS_PHASE sinusoids as they return different types + function create_ip_cartesian_table return T_IP_CARTESIAN_TABLE is + variable result : T_IP_CARTESIAN_TABLE; + variable entry_int : T_IP_INT_ENTRY; + begin + for i in 0 to IP_CARTESIAN_DEPTH-1 loop + entry_int := create_ip_entry(i, IP_CARTESIAN_DEPTH, IP_CARTESIAN_WIDTH - IP_CARTESIAN_SHIFT); + result(i).re := std_logic_vector(to_signed(entry_int.re, IP_CARTESIAN_WIDTH)); + result(i).im := std_logic_vector(to_signed(entry_int.im, IP_CARTESIAN_WIDTH)); + end loop; + return result; + end function create_ip_cartesian_table; + + function create_ip_phase_table return T_IP_PHASE_TABLE is + variable result : T_IP_PHASE_TABLE; + variable entry_int : T_IP_INT_ENTRY; + begin + for i in 0 to IP_PHASE_DEPTH-1 loop + entry_int := create_ip_entry(IP_PHASE_DEPTH-1-i, IP_PHASE_DEPTH, IP_PHASE_WIDTH - IP_PHASE_SHIFT); -- note rotation direction + result(i).re := std_logic_vector(to_signed(entry_int.re, IP_PHASE_WIDTH)); + end loop; + return result; + end function create_ip_phase_table; + + -- Call the functions to create the data + constant IP_CARTESIAN_DATA : T_IP_CARTESIAN_TABLE := create_ip_cartesian_table; + constant IP_PHASE_DATA : T_IP_PHASE_TABLE := create_ip_phase_table; + + +begin + + ----------------------------------------------------------------------- + -- Instantiate the DUT + ----------------------------------------------------------------------- + + dut : entity work.atan2_16b + port map ( + aclk => aclk, + s_axis_cartesian_tvalid => s_axis_cartesian_tvalid, + s_axis_cartesian_tdata => s_axis_cartesian_tdata, + m_axis_dout_tvalid => m_axis_dout_tvalid, + m_axis_dout_tdata => m_axis_dout_tdata + ); + + ----------------------------------------------------------------------- + -- Generate clock + ----------------------------------------------------------------------- + + clock_gen : process + begin + aclk <= '0'; + wait for CLOCK_PERIOD; + loop + cycles <= cycles + 1; + aclk <= '0'; + wait for CLOCK_PERIOD/2; + aclk <= '1'; + wait for CLOCK_PERIOD/2; + if cycles >= TEST_CYCLES then + report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure; + wait; + end if; + end loop; + end process clock_gen; + + ----------------------------------------------------------------------- + -- Generate inputs + ----------------------------------------------------------------------- + + stimuli : process + variable ip_cartesian_index : integer := 0; + variable ip_phase_index : integer := 0; + variable cartesian_tvalid_nxt : std_logic := '0'; + variable phase_tvalid_nxt : std_logic := '0'; + variable phase2_cycles : integer := 1; + variable phase2_count : integer := 0; + constant PHASE2_LIMIT : integer := 30; + begin + + -- Test is stopped in clock_gen process, use endless loop here + loop + + -- Drive inputs T_HOLD time after rising edge of clock + wait until rising_edge(aclk); + wait for T_HOLD; + + -- Drive AXI TVALID signals to demonstrate different types of operation + case cycles is -- do different types of operation at different phases of the test + when 0 to PHASE_CYCLES * 1 - 1 => + -- Phase 1: inputs always valid, no missing input data + cartesian_tvalid_nxt := '1'; + phase_tvalid_nxt := '1'; + when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 => + -- Phase 2: deprive channel S_AXIS_CARTESIAN of valid transactions at an increasing rate + phase_tvalid_nxt := '1'; + if phase2_count < phase2_cycles then + cartesian_tvalid_nxt := '0'; + else + cartesian_tvalid_nxt := '1'; + end if; + phase2_count := phase2_count + 1; + if phase2_count >= PHASE2_LIMIT then + phase2_count := 0; + phase2_cycles := phase2_cycles + 1; + end if; + when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 => + -- Phase 3: deprive channel S_AXIS_CARTESIAN of 1 out of 2 transactions, and channel S_AXIS_PHASE of 1 out of 3 transactions + if cycles mod 2 = 0 then + cartesian_tvalid_nxt := '0'; + else + cartesian_tvalid_nxt := '1'; + end if; + if cycles mod 3 = 0 then + phase_tvalid_nxt := '0'; + else + phase_tvalid_nxt := '1'; + end if; + when others => + -- Test will stop imminently - do nothing + null; + end case; + + -- Drive handshake signals with local variable values + s_axis_cartesian_tvalid <= cartesian_tvalid_nxt; + s_axis_phase_tvalid <= phase_tvalid_nxt; + + -- Drive AXI slave channel CARTESIAN payload + -- Drive 'X's on payload signals when not valid + if cartesian_tvalid_nxt /= '1' then + s_axis_cartesian_tdata <= (others => 'X'); + else + -- TDATA: Real and imaginary components are each 16 bits wide and byte-aligned at their LSBs + s_axis_cartesian_tdata(15 downto 0) <= IP_CARTESIAN_DATA(ip_cartesian_index).re; + s_axis_cartesian_tdata(31 downto 16) <= IP_CARTESIAN_DATA(ip_cartesian_index).im; + + end if; + + -- Drive AXI slave channel PHASE payload + -- Drive 'X's on payload signals when not valid + if phase_tvalid_nxt /= '1' then + s_axis_phase_tdata <= (others => 'X'); + else + -- TDATA: Real component is 16 bits wide and byte-aligned at its LSBs + s_axis_phase_tdata(15 downto 0) <= IP_PHASE_DATA(ip_phase_index).re; + end if; + + -- Increment input data indices + if cartesian_tvalid_nxt = '1' then + ip_cartesian_index := ip_cartesian_index + 1; + if ip_cartesian_index = IP_CARTESIAN_DEPTH then + ip_cartesian_index := 0; + end if; + end if; + if phase_tvalid_nxt = '1' then + ip_phase_index := ip_phase_index + 1; + if ip_phase_index = IP_PHASE_DEPTH then + ip_phase_index := 0; + end if; + end if; + + end loop; + + end process stimuli; + + ----------------------------------------------------------------------- + -- Check outputs + ----------------------------------------------------------------------- + + check_outputs : process + variable check_ok : boolean := true; + begin + + -- Check outputs T_STROBE time after rising edge of clock + wait until rising_edge(aclk); + wait for T_STROBE; + + -- Do not check the output payload values, as this requires the behavioral model + -- which would make this demonstration testbench unwieldy. + -- Instead, check the protocol of the DOUT channel: + -- check that the payload is valid (not X) when TVALID is high + + if m_axis_dout_tvalid = '1' then + if is_x(m_axis_dout_tdata) then + report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error; + check_ok := false; + end if; + + end if; + + assert check_ok + report "ERROR: terminating test with failures." severity failure; + + end process check_outputs; + + ----------------------------------------------------------------------- + -- Assign TDATA fields to aliases, for easy simulator waveform viewing + ----------------------------------------------------------------------- + + s_axis_cartesian_tdata_real <= s_axis_cartesian_tdata(15 downto 0); + s_axis_cartesian_tdata_imag <= s_axis_cartesian_tdata(31 downto 16); + + m_axis_dout_tdata_phase <= m_axis_dout_tdata(15 downto 0); + +end tb; + diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/sim/atan2_16b.vhd b/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/sim/atan2_16b.vhd new file mode 100644 index 00000000..23fb2ca0 --- /dev/null +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/atan2_16b/sim/atan2_16b.vhd @@ -0,0 +1,186 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:cordic:6.0 +-- IP Revision: 15 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY cordic_v6_0_15; +USE cordic_v6_0_15.cordic_v6_0_15; + +ENTITY atan2_16b IS + PORT ( + aclk : IN STD_LOGIC; + s_axis_cartesian_tvalid : IN STD_LOGIC; + s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_dout_tvalid : OUT STD_LOGIC; + m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END atan2_16b; + +ARCHITECTURE atan2_16b_arch OF atan2_16b IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF atan2_16b_arch: ARCHITECTURE IS "yes"; + COMPONENT cordic_v6_0_15 IS + GENERIC ( + C_ARCHITECTURE : INTEGER; + C_CORDIC_FUNCTION : INTEGER; + C_COARSE_ROTATE : INTEGER; + C_DATA_FORMAT : INTEGER; + C_XDEVICEFAMILY : STRING; + C_HAS_ACLKEN : INTEGER; + C_HAS_ACLK : INTEGER; + C_HAS_S_AXIS_CARTESIAN : INTEGER; + C_HAS_S_AXIS_PHASE : INTEGER; + C_HAS_ARESETN : INTEGER; + C_INPUT_WIDTH : INTEGER; + C_ITERATIONS : INTEGER; + C_OUTPUT_WIDTH : INTEGER; + C_PHASE_FORMAT : INTEGER; + C_PIPELINE_MODE : INTEGER; + C_PRECISION : INTEGER; + C_ROUND_MODE : INTEGER; + C_SCALE_COMP : INTEGER; + C_THROTTLE_SCHEME : INTEGER; + C_TLAST_RESOLUTION : INTEGER; + C_HAS_S_AXIS_PHASE_TUSER : INTEGER; + C_HAS_S_AXIS_PHASE_TLAST : INTEGER; + C_S_AXIS_PHASE_TDATA_WIDTH : INTEGER; + C_S_AXIS_PHASE_TUSER_WIDTH : INTEGER; + C_HAS_S_AXIS_CARTESIAN_TUSER : INTEGER; + C_HAS_S_AXIS_CARTESIAN_TLAST : INTEGER; + C_S_AXIS_CARTESIAN_TDATA_WIDTH : INTEGER; + C_S_AXIS_CARTESIAN_TUSER_WIDTH : INTEGER; + C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER; + C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER + ); + PORT ( + aclk : IN STD_LOGIC; + aclken : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tready : OUT STD_LOGIC; + s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_phase_tlast : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + s_axis_cartesian_tvalid : IN STD_LOGIC; + s_axis_cartesian_tready : OUT STD_LOGIC; + s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_cartesian_tlast : IN STD_LOGIC; + s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_dout_tvalid : OUT STD_LOGIC; + m_axis_dout_tready : IN STD_LOGIC; + m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_dout_tlast : OUT STD_LOGIC; + m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); + END COMPONENT cordic_v6_0_15; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_dout_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DOUT, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_cartesian_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_CARTESIAN, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF M_AXIS_DOUT:S_AXIS_PHASE:S_AXIS_CARTESIAN, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 1000000, PHASE 0.000, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; +BEGIN + U0 : cordic_v6_0_15 + GENERIC MAP ( + C_ARCHITECTURE => 2, + C_CORDIC_FUNCTION => 3, + C_COARSE_ROTATE => 1, + C_DATA_FORMAT => 0, + C_XDEVICEFAMILY => "kintex7", + C_HAS_ACLKEN => 0, + C_HAS_ACLK => 1, + C_HAS_S_AXIS_CARTESIAN => 1, + C_HAS_S_AXIS_PHASE => 0, + C_HAS_ARESETN => 0, + C_INPUT_WIDTH => 16, + C_ITERATIONS => 0, + C_OUTPUT_WIDTH => 16, + C_PHASE_FORMAT => 0, + C_PIPELINE_MODE => -2, + C_PRECISION => 0, + C_ROUND_MODE => 0, + C_SCALE_COMP => 0, + C_THROTTLE_SCHEME => 3, + C_TLAST_RESOLUTION => 0, + C_HAS_S_AXIS_PHASE_TUSER => 0, + C_HAS_S_AXIS_PHASE_TLAST => 0, + C_S_AXIS_PHASE_TDATA_WIDTH => 16, + C_S_AXIS_PHASE_TUSER_WIDTH => 1, + C_HAS_S_AXIS_CARTESIAN_TUSER => 0, + C_HAS_S_AXIS_CARTESIAN_TLAST => 0, + C_S_AXIS_CARTESIAN_TDATA_WIDTH => 32, + C_S_AXIS_CARTESIAN_TUSER_WIDTH => 1, + C_M_AXIS_DOUT_TDATA_WIDTH => 16, + C_M_AXIS_DOUT_TUSER_WIDTH => 1 + ) + PORT MAP ( + aclk => aclk, + aclken => '1', + aresetn => '1', + s_axis_phase_tvalid => '0', + s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + s_axis_phase_tlast => '0', + s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)), + s_axis_cartesian_tvalid => s_axis_cartesian_tvalid, + s_axis_cartesian_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + s_axis_cartesian_tlast => '0', + s_axis_cartesian_tdata => s_axis_cartesian_tdata, + m_axis_dout_tvalid => m_axis_dout_tvalid, + m_axis_dout_tready => '0', + m_axis_dout_tdata => m_axis_dout_tdata + ); +END atan2_16b_arch; diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/demo_tb/tb_rotate_16b.vhd b/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/demo_tb/tb_rotate_16b.vhd new file mode 100644 index 00000000..429826af --- /dev/null +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/demo_tb/tb_rotate_16b.vhd @@ -0,0 +1,380 @@ +-------------------------------------------------------------------------------- +-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-------------------------------------------------------------------------------- +-- Description: +-- This is an example testbench for the CORDIC IP core. +-- The testbench has been generated by Vivado to accompany the IP core +-- instance you have generated. +-- +-- This testbench is for demonstration purposes only. See note below for +-- instructions on how to use it with your core. +-- +-- See the CORDIC product guide for further information +-- about this core. +-- +-------------------------------------------------------------------------------- +-- Using this testbench +-- +-- This testbench instantiates your generated CORDIC core +-- instance named "rotate_16b". +-- +-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado +-- documentation for details. +-------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +entity tb_rotate_16b is +end tb_rotate_16b; + +architecture tb of tb_rotate_16b is + + ----------------------------------------------------------------------- + -- Timing constants + ----------------------------------------------------------------------- + constant CLOCK_PERIOD : time := 100 ns; + constant T_HOLD : time := 10 ns; + constant T_STROBE : time := CLOCK_PERIOD - (1 ns); + constant TEST_CYCLES : integer := 3000; + constant PHASE_CYCLES : integer := 1000; + + ----------------------------------------------------------------------- + -- DUT input signals + ----------------------------------------------------------------------- + + -- General inputs + signal aclk : std_logic := '0'; -- the master clock + + -- Slave channel CARTESIAN inputs + signal s_axis_cartesian_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_CARTESIAN + signal s_axis_cartesian_tdata : std_logic_vector(31 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_CARTESIAN + + -- Slave channel PHASE inputs + signal s_axis_phase_tvalid : std_logic := '0'; -- TVALID for channel S_AXIS_PHASE + signal s_axis_phase_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel S_AXIS_PHASE + + ----------------------------------------------------------------------- + -- DUT output signals + ----------------------------------------------------------------------- + + -- Master channel DOUT outputs + signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel M_AXIS_DOUT + signal m_axis_dout_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- TDATA for channel M_AXIS_DOUT + + ----------------------------------------------------------------------- + -- Aliases for AXI channel TDATA fields + -- These are a convenience for viewing data in a simulator waveform viewer. + -- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command + -- to prevent the simulator optimizing away these signals. + ----------------------------------------------------------------------- + signal s_axis_cartesian_tdata_real : std_logic_vector(15 downto 0) := (others => '0'); + signal s_axis_cartesian_tdata_imag : std_logic_vector(15 downto 0) := (others => '0'); + signal s_axis_phase_tdata_real : std_logic_vector(15 downto 0) := (others => '0'); + + signal m_axis_dout_tdata_real : std_logic_vector(15 downto 0) := (others => '0'); + signal m_axis_dout_tdata_imag : std_logic_vector(15 downto 0) := (others => '0'); + signal m_axis_dout_tdata_phase : std_logic_vector(15 downto 0) := (others => '0'); + ----------------------------------------------------------------------- + -- Testbench signals + ----------------------------------------------------------------------- + + signal cycles : integer := 0; -- Clock cycle counter + + ----------------------------------------------------------------------- + -- Constants, types and functions to create input data + -- The CORDIC is fed two sinusoids exp(+/-jwt) of different frequencies and amplitudes: + -- channel CARTESIAN: exp(+jwt), frequency = clock / 30, + -- channel PHASE: exp(-jwt), frequency = clock / 32, + ----------------------------------------------------------------------- + + constant IP_CARTESIAN_DEPTH : integer := 30; + constant IP_CARTESIAN_WIDTH : integer := 16; + constant IP_CARTESIAN_SHIFT : integer := 3; -- bit shift for amplitude + constant IP_PHASE_DEPTH : integer := 32; + constant IP_PHASE_WIDTH : integer := 16; + constant IP_PHASE_SHIFT : integer := 0; -- no bit shift, max amplitude + type T_IP_INT_ENTRY is record + re : integer; + im : integer; + end record; + type T_IP_CARTESIAN_ENTRY is record + re : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0); + im : std_logic_vector(IP_CARTESIAN_WIDTH-1 downto 0); + end record; + type T_IP_PHASE_ENTRY is record + re : std_logic_vector(IP_PHASE_WIDTH-1 downto 0); + end record; + type T_IP_CARTESIAN_TABLE is array (0 to IP_CARTESIAN_DEPTH-1) of T_IP_CARTESIAN_ENTRY; + type T_IP_PHASE_TABLE is array (0 to IP_PHASE_DEPTH-1) of T_IP_PHASE_ENTRY; + + -- Common function to calculate sine and cosine values + function create_ip_entry(index, depth, width : integer) return T_IP_INT_ENTRY is + variable result : T_IP_INT_ENTRY; + variable theta : real; + variable limited_width : integer := width - 2; + begin + if limited_width > 30 then + limited_width := 30; --avoid integer overflow + end if; + theta := real(index) / real(depth) * 2.0 * MATH_PI; + result.re := integer(round(cos(theta) * real(2**limited_width))); + result.im := integer(round(sin(theta) * real(2**limited_width))); + return result; + end function create_ip_entry; + + -- Use separate functions to calculate channel S_AXIS_CARTESIAN and S_AXIS_PHASE sinusoids as they return different types + function create_ip_cartesian_table return T_IP_CARTESIAN_TABLE is + variable result : T_IP_CARTESIAN_TABLE; + variable entry_int : T_IP_INT_ENTRY; + begin + for i in 0 to IP_CARTESIAN_DEPTH-1 loop + entry_int := create_ip_entry(i, IP_CARTESIAN_DEPTH, IP_CARTESIAN_WIDTH - IP_CARTESIAN_SHIFT); + result(i).re := std_logic_vector(to_signed(entry_int.re, IP_CARTESIAN_WIDTH)); + result(i).im := std_logic_vector(to_signed(entry_int.im, IP_CARTESIAN_WIDTH)); + end loop; + return result; + end function create_ip_cartesian_table; + + function create_ip_phase_table return T_IP_PHASE_TABLE is + variable result : T_IP_PHASE_TABLE; + variable entry_int : T_IP_INT_ENTRY; + begin + for i in 0 to IP_PHASE_DEPTH-1 loop + entry_int := create_ip_entry(IP_PHASE_DEPTH-1-i, IP_PHASE_DEPTH, IP_PHASE_WIDTH - IP_PHASE_SHIFT); -- note rotation direction + result(i).re := std_logic_vector(to_signed(entry_int.re, IP_PHASE_WIDTH)); + end loop; + return result; + end function create_ip_phase_table; + + -- Call the functions to create the data + constant IP_CARTESIAN_DATA : T_IP_CARTESIAN_TABLE := create_ip_cartesian_table; + constant IP_PHASE_DATA : T_IP_PHASE_TABLE := create_ip_phase_table; + + +begin + + ----------------------------------------------------------------------- + -- Instantiate the DUT + ----------------------------------------------------------------------- + + dut : entity work.rotate_16b + port map ( + aclk => aclk, + s_axis_cartesian_tvalid => s_axis_cartesian_tvalid, + s_axis_cartesian_tdata => s_axis_cartesian_tdata, + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tdata => s_axis_phase_tdata, + m_axis_dout_tvalid => m_axis_dout_tvalid, + m_axis_dout_tdata => m_axis_dout_tdata + ); + + ----------------------------------------------------------------------- + -- Generate clock + ----------------------------------------------------------------------- + + clock_gen : process + begin + aclk <= '0'; + wait for CLOCK_PERIOD; + loop + cycles <= cycles + 1; + aclk <= '0'; + wait for CLOCK_PERIOD/2; + aclk <= '1'; + wait for CLOCK_PERIOD/2; + if cycles >= TEST_CYCLES then + report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure; + wait; + end if; + end loop; + end process clock_gen; + + ----------------------------------------------------------------------- + -- Generate inputs + ----------------------------------------------------------------------- + + stimuli : process + variable ip_cartesian_index : integer := 0; + variable ip_phase_index : integer := 0; + variable cartesian_tvalid_nxt : std_logic := '0'; + variable phase_tvalid_nxt : std_logic := '0'; + variable phase2_cycles : integer := 1; + variable phase2_count : integer := 0; + constant PHASE2_LIMIT : integer := 30; + begin + + -- Test is stopped in clock_gen process, use endless loop here + loop + + -- Drive inputs T_HOLD time after rising edge of clock + wait until rising_edge(aclk); + wait for T_HOLD; + + -- Drive AXI TVALID signals to demonstrate different types of operation + case cycles is -- do different types of operation at different phases of the test + when 0 to PHASE_CYCLES * 1 - 1 => + -- Phase 1: inputs always valid, no missing input data + cartesian_tvalid_nxt := '1'; + phase_tvalid_nxt := '1'; + when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 => + -- Phase 2: deprive channel S_AXIS_CARTESIAN of valid transactions at an increasing rate + phase_tvalid_nxt := '1'; + if phase2_count < phase2_cycles then + cartesian_tvalid_nxt := '0'; + else + cartesian_tvalid_nxt := '1'; + end if; + phase2_count := phase2_count + 1; + if phase2_count >= PHASE2_LIMIT then + phase2_count := 0; + phase2_cycles := phase2_cycles + 1; + end if; + when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 => + -- Phase 3: deprive channel S_AXIS_CARTESIAN of 1 out of 2 transactions, and channel S_AXIS_PHASE of 1 out of 3 transactions + if cycles mod 2 = 0 then + cartesian_tvalid_nxt := '0'; + else + cartesian_tvalid_nxt := '1'; + end if; + if cycles mod 3 = 0 then + phase_tvalid_nxt := '0'; + else + phase_tvalid_nxt := '1'; + end if; + when others => + -- Test will stop imminently - do nothing + null; + end case; + + -- Drive handshake signals with local variable values + s_axis_cartesian_tvalid <= cartesian_tvalid_nxt; + s_axis_phase_tvalid <= phase_tvalid_nxt; + + -- Drive AXI slave channel CARTESIAN payload + -- Drive 'X's on payload signals when not valid + if cartesian_tvalid_nxt /= '1' then + s_axis_cartesian_tdata <= (others => 'X'); + else + -- TDATA: Real and imaginary components are each 16 bits wide and byte-aligned at their LSBs + s_axis_cartesian_tdata(15 downto 0) <= IP_CARTESIAN_DATA(ip_cartesian_index).re; + s_axis_cartesian_tdata(31 downto 16) <= IP_CARTESIAN_DATA(ip_cartesian_index).im; + + end if; + + -- Drive AXI slave channel PHASE payload + -- Drive 'X's on payload signals when not valid + if phase_tvalid_nxt /= '1' then + s_axis_phase_tdata <= (others => 'X'); + else + -- TDATA: Real component is 16 bits wide and byte-aligned at its LSBs + s_axis_phase_tdata(15 downto 0) <= IP_PHASE_DATA(ip_phase_index).re; + end if; + + -- Increment input data indices + if cartesian_tvalid_nxt = '1' then + ip_cartesian_index := ip_cartesian_index + 1; + if ip_cartesian_index = IP_CARTESIAN_DEPTH then + ip_cartesian_index := 0; + end if; + end if; + if phase_tvalid_nxt = '1' then + ip_phase_index := ip_phase_index + 1; + if ip_phase_index = IP_PHASE_DEPTH then + ip_phase_index := 0; + end if; + end if; + + end loop; + + end process stimuli; + + ----------------------------------------------------------------------- + -- Check outputs + ----------------------------------------------------------------------- + + check_outputs : process + variable check_ok : boolean := true; + begin + + -- Check outputs T_STROBE time after rising edge of clock + wait until rising_edge(aclk); + wait for T_STROBE; + + -- Do not check the output payload values, as this requires the behavioral model + -- which would make this demonstration testbench unwieldy. + -- Instead, check the protocol of the DOUT channel: + -- check that the payload is valid (not X) when TVALID is high + + if m_axis_dout_tvalid = '1' then + if is_x(m_axis_dout_tdata) then + report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error; + check_ok := false; + end if; + + end if; + + assert check_ok + report "ERROR: terminating test with failures." severity failure; + + end process check_outputs; + + ----------------------------------------------------------------------- + -- Assign TDATA fields to aliases, for easy simulator waveform viewing + ----------------------------------------------------------------------- + + s_axis_cartesian_tdata_real <= s_axis_cartesian_tdata(15 downto 0); + s_axis_cartesian_tdata_imag <= s_axis_cartesian_tdata(31 downto 16); + s_axis_phase_tdata_real <= s_axis_phase_tdata(15 downto 0); + + m_axis_dout_tdata_real <= m_axis_dout_tdata(15 downto 0); + m_axis_dout_tdata_imag <= m_axis_dout_tdata(31 downto 16); + +end tb; + diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_sim_netlist.v b/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_sim_netlist.v new file mode 100644 index 00000000..aa13da9e --- /dev/null +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2d8fa8632255ba3f8f9505619cc3e2a3406476260562ac1dca8430ca795f2127 +size 1501561 diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_sim_netlist.vhdl b/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_sim_netlist.vhdl new file mode 100644 index 00000000..2ec401fb --- /dev/null +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2893c0d9d73a08543c712846b8a6bd0071d9f7bba5c4ae5010f485bf3b7766e0 +size 2432935 diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_stub.v b/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_stub.v index d33c5af0..d625a06f 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_stub.v +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Wed Apr 12 20:00:10 2023 +// Date : Mon Jun 5 20:28:46 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.v diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_stub.vhdl b/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_stub.vhdl index 380c7471..647623f5 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_stub.vhdl +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/rotate_16b_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Wed Apr 12 20:00:10 2023 +-- Date : Mon Jun 5 20:28:46 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.vhdl diff --git a/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/sim/rotate_16b.vhd b/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/sim/rotate_16b.vhd new file mode 100644 index 00000000..6e3cb1c7 --- /dev/null +++ b/projects/dl814_k7/common_ip/ip_user_files/ip/rotate_16b/sim/rotate_16b.vhd @@ -0,0 +1,191 @@ +-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-- DO NOT MODIFY THIS FILE. + +-- IP VLNV: xilinx.com:ip:cordic:6.0 +-- IP Revision: 15 + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY cordic_v6_0_15; +USE cordic_v6_0_15.cordic_v6_0_15; + +ENTITY rotate_16b IS + PORT ( + aclk : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + s_axis_cartesian_tvalid : IN STD_LOGIC; + s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_dout_tvalid : OUT STD_LOGIC; + m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END rotate_16b; + +ARCHITECTURE rotate_16b_arch OF rotate_16b IS + ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; + ATTRIBUTE DowngradeIPIdentifiedWarnings OF rotate_16b_arch: ARCHITECTURE IS "yes"; + COMPONENT cordic_v6_0_15 IS + GENERIC ( + C_ARCHITECTURE : INTEGER; + C_CORDIC_FUNCTION : INTEGER; + C_COARSE_ROTATE : INTEGER; + C_DATA_FORMAT : INTEGER; + C_XDEVICEFAMILY : STRING; + C_HAS_ACLKEN : INTEGER; + C_HAS_ACLK : INTEGER; + C_HAS_S_AXIS_CARTESIAN : INTEGER; + C_HAS_S_AXIS_PHASE : INTEGER; + C_HAS_ARESETN : INTEGER; + C_INPUT_WIDTH : INTEGER; + C_ITERATIONS : INTEGER; + C_OUTPUT_WIDTH : INTEGER; + C_PHASE_FORMAT : INTEGER; + C_PIPELINE_MODE : INTEGER; + C_PRECISION : INTEGER; + C_ROUND_MODE : INTEGER; + C_SCALE_COMP : INTEGER; + C_THROTTLE_SCHEME : INTEGER; + C_TLAST_RESOLUTION : INTEGER; + C_HAS_S_AXIS_PHASE_TUSER : INTEGER; + C_HAS_S_AXIS_PHASE_TLAST : INTEGER; + C_S_AXIS_PHASE_TDATA_WIDTH : INTEGER; + C_S_AXIS_PHASE_TUSER_WIDTH : INTEGER; + C_HAS_S_AXIS_CARTESIAN_TUSER : INTEGER; + C_HAS_S_AXIS_CARTESIAN_TLAST : INTEGER; + C_S_AXIS_CARTESIAN_TDATA_WIDTH : INTEGER; + C_S_AXIS_CARTESIAN_TUSER_WIDTH : INTEGER; + C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER; + C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER + ); + PORT ( + aclk : IN STD_LOGIC; + aclken : IN STD_LOGIC; + aresetn : IN STD_LOGIC; + s_axis_phase_tvalid : IN STD_LOGIC; + s_axis_phase_tready : OUT STD_LOGIC; + s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_phase_tlast : IN STD_LOGIC; + s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + s_axis_cartesian_tvalid : IN STD_LOGIC; + s_axis_cartesian_tready : OUT STD_LOGIC; + s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + s_axis_cartesian_tlast : IN STD_LOGIC; + s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + m_axis_dout_tvalid : OUT STD_LOGIC; + m_axis_dout_tready : IN STD_LOGIC; + m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); + m_axis_dout_tlast : OUT STD_LOGIC; + m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + END COMPONENT cordic_v6_0_15; + ATTRIBUTE X_INTERFACE_INFO : STRING; + ATTRIBUTE X_INTERFACE_PARAMETER : STRING; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_dout_tvalid: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DOUT, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_cartesian_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_CARTESIAN, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TVALID"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TDATA"; + ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_phase_tvalid: SIGNAL IS "XIL_INTERFACENAME S_AXIS_PHASE, TDATA_NUM_BYTES 2, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TVALID"; + ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF M_AXIS_DOUT:S_AXIS_PHASE:S_AXIS_CARTESIAN, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 1000000, PHASE 0.000, INSERT_VIP 0"; + ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; +BEGIN + U0 : cordic_v6_0_15 + GENERIC MAP ( + C_ARCHITECTURE => 2, + C_CORDIC_FUNCTION => 0, + C_COARSE_ROTATE => 1, + C_DATA_FORMAT => 0, + C_XDEVICEFAMILY => "kintex7", + C_HAS_ACLKEN => 0, + C_HAS_ACLK => 1, + C_HAS_S_AXIS_CARTESIAN => 1, + C_HAS_S_AXIS_PHASE => 1, + C_HAS_ARESETN => 0, + C_INPUT_WIDTH => 16, + C_ITERATIONS => 0, + C_OUTPUT_WIDTH => 16, + C_PHASE_FORMAT => 0, + C_PIPELINE_MODE => -2, + C_PRECISION => 0, + C_ROUND_MODE => 0, + C_SCALE_COMP => 0, + C_THROTTLE_SCHEME => 3, + C_TLAST_RESOLUTION => 0, + C_HAS_S_AXIS_PHASE_TUSER => 0, + C_HAS_S_AXIS_PHASE_TLAST => 0, + C_S_AXIS_PHASE_TDATA_WIDTH => 16, + C_S_AXIS_PHASE_TUSER_WIDTH => 1, + C_HAS_S_AXIS_CARTESIAN_TUSER => 0, + C_HAS_S_AXIS_CARTESIAN_TLAST => 0, + C_S_AXIS_CARTESIAN_TDATA_WIDTH => 32, + C_S_AXIS_CARTESIAN_TUSER_WIDTH => 1, + C_M_AXIS_DOUT_TDATA_WIDTH => 32, + C_M_AXIS_DOUT_TUSER_WIDTH => 1 + ) + PORT MAP ( + aclk => aclk, + aclken => '1', + aresetn => '1', + s_axis_phase_tvalid => s_axis_phase_tvalid, + s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + s_axis_phase_tlast => '0', + s_axis_phase_tdata => s_axis_phase_tdata, + s_axis_cartesian_tvalid => s_axis_cartesian_tvalid, + s_axis_cartesian_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), + s_axis_cartesian_tlast => '0', + s_axis_cartesian_tdata => s_axis_cartesian_tdata, + m_axis_dout_tvalid => m_axis_dout_tvalid, + m_axis_dout_tready => '0', + m_axis_dout_tdata => m_axis_dout_tdata + ); +END rotate_16b_arch; diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/README.txt index 2991a7c5..08e0f125 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/atan2_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/atan2_16b.sh index 84f492be..6a2f8e10 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/atan2_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/atan2_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/compile.do b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/compile.do index 9b3f2754..20fdbb96 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/compile.do +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/compile.do @@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6 vmap cordic_v6_0_15 activehdl/cordic_v6_0_15 vlog -work xil_defaultlib -sv2k12 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vcom -work xbip_utils_v3_0_10 -93 \ "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/file_info.txt index b5a1cca1..d9b83eb0 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/activehdl/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/README.txt index 557bf4ba..7142d3fc 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/atan2_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/atan2_16b.sh index db241834..998a7aeb 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/atan2_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/atan2_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/file_info.txt index b5a1cca1..d9b83eb0 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/run.f b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/run.f index de3e95ff..5dffb1da 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/run.f +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/ies/run.f @@ -1,9 +1,9 @@ -makelib ies_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib ies_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib ies_lib/xbip_utils_v3_0_10 \ "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/README.txt index 2991a7c5..08e0f125 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/atan2_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/atan2_16b.sh index 1e9588e4..da23204a 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/atan2_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/atan2_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/compile.do b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/compile.do index ffe98eb4..e098a070 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/compile.do +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/compile.do @@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6 vmap cordic_v6_0_15 modelsim_lib/msim/cordic_v6_0_15 vlog -work xil_defaultlib -64 -incr -sv \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -64 -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vcom -work xbip_utils_v3_0_10 -64 -93 \ "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/file_info.txt index b5a1cca1..d9b83eb0 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/modelsim/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/README.txt index 2991a7c5..08e0f125 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/atan2_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/atan2_16b.sh index 5588c6bf..c5055d9e 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/atan2_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/atan2_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/compile.do b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/compile.do index 224d82d6..c067520c 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/compile.do +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/compile.do @@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6 vmap cordic_v6_0_15 questa_lib/msim/cordic_v6_0_15 vlog -work xil_defaultlib -64 -sv \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -64 -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vcom -work xbip_utils_v3_0_10 -64 -93 \ "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/file_info.txt index b5a1cca1..d9b83eb0 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/questa/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/README.txt index 2991a7c5..08e0f125 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/atan2_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/atan2_16b.sh index ac0b97b2..e837e891 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/atan2_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/atan2_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/compile.do b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/compile.do index d8bbda0a..3c6c6999 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/compile.do +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/compile.do @@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6 vmap cordic_v6_0_15 riviera/cordic_v6_0_15 vlog -work xil_defaultlib -sv2k12 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vcom -work xbip_utils_v3_0_10 -93 \ "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/file_info.txt index b5a1cca1..d9b83eb0 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/riviera/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/vcs/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/vcs/README.txt index 2991a7c5..08e0f125 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/vcs/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/vcs/atan2_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/vcs/atan2_16b.sh index e8f3b248..ecaf34b2 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/vcs/atan2_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/vcs/atan2_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -71,12 +71,12 @@ compile() { # Compile design files vlogan -work xil_defaultlib $vlogan_opts -sverilog \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ 2>&1 | tee -a vlogan.log vhdlan -work xpm $vhdlan_opts \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ 2>&1 | tee -a vhdlan.log vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/vcs/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/vcs/file_info.txt index b5a1cca1..d9b83eb0 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/vcs/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/vcs/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/README.txt index 557bf4ba..7142d3fc 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/atan2_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/atan2_16b.sh index 093fa725..d15d8e02 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/atan2_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/atan2_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/file_info.txt index b5a1cca1..d9b83eb0 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/run.f b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/run.f index 4e2be92a..3c78db0a 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/run.f +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xcelium/run.f @@ -1,9 +1,9 @@ -makelib xcelium_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib xcelium_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib xcelium_lib/xbip_utils_v3_0_10 \ "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xsim/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xsim/README.txt index 2991a7c5..08e0f125 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xsim/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:00:17 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:33 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xsim/atan2_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xsim/atan2_16b.sh index 4007ebfb..d481d14d 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xsim/atan2_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/atan2_16b/xsim/atan2_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:00:17 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:33 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -22,7 +22,7 @@ #********************************************************************************************************* # Command line options -xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0 xvlog_opts="--relax" xvhdl_opts="--relax" @@ -94,7 +94,7 @@ setup() copy_setup_file() { file="xsim.ini" - lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim" if [[ ($1 != "") ]]; then lib_map_path="$1" fi diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/README.txt index 243b1c5e..37c8290e 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/compile.do b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/compile.do index 6ccbf261..45af682c 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/compile.do +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/compile.do @@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 activehdl/axi_utils_v2_0_6 vmap cordic_v6_0_15 activehdl/cordic_v6_0_15 vlog -work xil_defaultlib -sv2k12 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vcom -work xbip_utils_v3_0_10 -93 \ "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/file_info.txt index c94a5df8..105b5022 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/rotate_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/rotate_16b.sh index c8a00fd6..42c09710 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/rotate_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/activehdl/rotate_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/README.txt index a41d6400..054a5864 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/file_info.txt index c94a5df8..105b5022 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/rotate_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/rotate_16b.sh index 31a2cefc..0c1b4049 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/rotate_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/rotate_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/run.f b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/run.f index f72c7329..649f7b2a 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/run.f +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/ies/run.f @@ -1,9 +1,9 @@ -makelib ies_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib ies_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib ies_lib/xbip_utils_v3_0_10 \ "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/README.txt index 243b1c5e..37c8290e 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/compile.do b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/compile.do index fa59239f..9c5b4695 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/compile.do +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/compile.do @@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6 vmap cordic_v6_0_15 modelsim_lib/msim/cordic_v6_0_15 vlog -work xil_defaultlib -64 -incr -sv \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -64 -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vcom -work xbip_utils_v3_0_10 -64 -93 \ "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/file_info.txt index c94a5df8..105b5022 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/rotate_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/rotate_16b.sh index a35646f4..ffdf34bf 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/rotate_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/modelsim/rotate_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/README.txt index 243b1c5e..37c8290e 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/compile.do b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/compile.do index 123d66e5..7918ac75 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/compile.do +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/compile.do @@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 questa_lib/msim/axi_utils_v2_0_6 vmap cordic_v6_0_15 questa_lib/msim/cordic_v6_0_15 vlog -work xil_defaultlib -64 -sv \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -64 -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vcom -work xbip_utils_v3_0_10 -64 -93 \ "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/file_info.txt index c94a5df8..105b5022 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/rotate_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/rotate_16b.sh index a8c18f24..5778c17b 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/rotate_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/questa/rotate_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/README.txt index 243b1c5e..37c8290e 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/compile.do b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/compile.do index 3d59ac26..07a93738 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/compile.do +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/compile.do @@ -30,11 +30,11 @@ vmap axi_utils_v2_0_6 riviera/axi_utils_v2_0_6 vmap cordic_v6_0_15 riviera/cordic_v6_0_15 vlog -work xil_defaultlib -sv2k12 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ vcom -work xpm -93 \ -"/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ +"/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ vcom -work xbip_utils_v3_0_10 -93 \ "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/file_info.txt index c94a5df8..105b5022 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/rotate_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/rotate_16b.sh index 1cedb7e7..851cdc79 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/rotate_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/riviera/rotate_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/vcs/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/vcs/README.txt index 243b1c5e..37c8290e 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/vcs/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/vcs/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/vcs/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/vcs/file_info.txt index c94a5df8..105b5022 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/vcs/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/vcs/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/vcs/rotate_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/vcs/rotate_16b.sh index d4f6fe1b..8d1053b8 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/vcs/rotate_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/vcs/rotate_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -71,12 +71,12 @@ compile() { # Compile design files vlogan -work xil_defaultlib $vlogan_opts -sverilog \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ 2>&1 | tee -a vlogan.log vhdlan -work xpm $vhdlan_opts \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ 2>&1 | tee -a vhdlan.log vhdlan -work xbip_utils_v3_0_10 $vhdlan_opts \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/README.txt index a41d6400..054a5864 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/file_info.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/file_info.txt index c94a5df8..105b5022 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/file_info.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/file_info.txt @@ -1,6 +1,6 @@ -xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, -xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, -xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, +xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv, +xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv, +xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../../Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd, xbip_utils_v3_0_vh_rfs.vhd,vhdl,xbip_utils_v3_0_10,../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd, c_reg_fd_v12_0_vh_rfs.vhd,vhdl,c_reg_fd_v12_0_6,../../../ipstatic/hdl/c_reg_fd_v12_0_vh_rfs.vhd, xbip_dsp48_wrapper_v3_0_vh_rfs.vhd,vhdl,xbip_dsp48_wrapper_v3_0_4,../../../ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd, diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/rotate_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/rotate_16b.sh index f972ece5..b87625ee 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/rotate_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/rotate_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/run.f b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/run.f index 56ec6293..f19a9f17 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/run.f +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xcelium/run.f @@ -1,9 +1,9 @@ -makelib xcelium_lib/xil_defaultlib -sv \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv" \ -endlib -makelib xcelium_lib/xpm \ - "/tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ + "/home/josh/Software/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd" \ -endlib -makelib xcelium_lib/xbip_utils_v3_0_10 \ "../../../ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd" \ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xsim/README.txt b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xsim/README.txt index 243b1c5e..37c8290e 100644 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xsim/README.txt +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xsim/README.txt @@ -4,7 +4,7 @@ # README.txt: Please read the sections below to understand the steps required to # run the exported script and information about the source files. # -# Generated by export_simulation on Wed Apr 12 20:01:03 CST 2023 +# Generated by export_simulation on Mon Jun 05 20:28:18 CST 2023 # ################################################################################ diff --git a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xsim/rotate_16b.sh b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xsim/rotate_16b.sh index 198b5cce..5b31f469 100755 --- a/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xsim/rotate_16b.sh +++ b/projects/dl814_k7/common_ip/ip_user_files/sim_scripts/rotate_16b/xsim/rotate_16b.sh @@ -9,7 +9,7 @@ # directory, add the library logical mappings in the simulator setup file, create default # 'do/prj' file, execute compilation, elaboration and simulation steps. # -# Generated by Vivado on Wed Apr 12 20:01:03 CST 2023 +# Generated by Vivado on Mon Jun 05 20:28:18 CST 2023 # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # # Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. @@ -22,7 +22,7 @@ #********************************************************************************************************* # Command line options -xv_boost_lib_path=/tools/Xilinx/Vivado/2019.1/tps/boost_1_64_0 +xv_boost_lib_path=/home/josh/Software/Xilinx/Vivado/2019.1/tps/boost_1_64_0 xvlog_opts="--relax" xvhdl_opts="--relax" @@ -94,7 +94,7 @@ setup() copy_setup_file() { file="xsim.ini" - lib_map_path="/tools/Xilinx/Vivado/2019.1/data/xsim" + lib_map_path="/home/josh/Software/Xilinx/Vivado/2019.1/data/xsim" if [[ ($1 != "") ]]; then lib_map_path="$1" fi diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/35ef934e18fcbb85.xci b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/35ef934e18fcbb85.xci new file mode 100644 index 00000000..36c3b48c --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/35ef934e18fcbb85.xci @@ -0,0 +1,64 @@ + + + xilinx.com + ipcache + 35ef934e18fcbb85 + 0 + + + atan2_16b + + + 1000000 + 100000000 + 100000000 + false + false + Parallel + true + No_Scale_Compensation + atan2_16b + SignedFraction + Arc_Tan + 16 + 0 + 16 + Radians + Maximum + 0 + Truncate + false + false + 1 + NonBlocking + Performance + Null + false + false + false + 1 + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 35ef934e18fcbb85 + fa73b4fd + 22 + IP_Unknown + 15 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b.dcp b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b.dcp new file mode 100644 index 00000000..8bde0441 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fd4f4e320c77b01d2196a19d3886c5d24bcd6e6304b636e836ee5e175bec1042 +size 810611 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b_sim_netlist.v b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b_sim_netlist.v new file mode 100755 index 00000000..47f51380 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:bb215f71b02a297144a5927934756cfbd120dd35ad1fc2117a6dc0313fbe99a7 +size 1373024 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b_sim_netlist.vhdl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b_sim_netlist.vhdl new file mode 100755 index 00000000..129bd463 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:bc8c13aa6006d69a8376b3d68815891bf00aa6c2ebafe449229d60815e9c7bba +size 2282411 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b_stub.v b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b_stub.v new file mode 100755 index 00000000..f7e359a0 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b_stub.v @@ -0,0 +1,25 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon Jun 5 20:29:00 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ atan2_16b_stub.v +// Design : atan2_16b +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "cordic_v6_0_15,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_cartesian_tvalid, + s_axis_cartesian_tdata, m_axis_dout_tvalid, m_axis_dout_tdata) +/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]" */; + input aclk; + input s_axis_cartesian_tvalid; + input [31:0]s_axis_cartesian_tdata; + output m_axis_dout_tvalid; + output [15:0]m_axis_dout_tdata; +endmodule diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b_stub.vhdl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b_stub.vhdl new file mode 100755 index 00000000..a261524d --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/35ef934e18fcbb85/atan2_16b_stub.vhdl @@ -0,0 +1,34 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon Jun 5 20:29:00 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ atan2_16b_stub.vhdl +-- Design : atan2_16b +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + aclk : in STD_LOGIC; + s_axis_cartesian_tvalid : in STD_LOGIC; + s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axis_dout_tvalid : out STD_LOGIC; + m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "cordic_v6_0_15,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/6d0942f1ca8f60d5.xci b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/6d0942f1ca8f60d5.xci new file mode 100644 index 00000000..dc91c060 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/6d0942f1ca8f60d5.xci @@ -0,0 +1,65 @@ + + + xilinx.com + ipcache + 6d0942f1ca8f60d5 + 0 + + + rotate_16b + + + 1000000 + 100000000 + 100000000 + 100000000 + false + false + Parallel + true + No_Scale_Compensation + rotate_16b + SignedFraction + Rotate + 16 + 0 + 16 + Radians + Maximum + 0 + Truncate + false + false + 1 + NonBlocking + Performance + Null + false + false + false + 1 + kintex7 + xc7k410t + ffg900 + VERILOG + + -2 + + + TRUE + TRUE + 6d0942f1ca8f60d5 + fa73b4fd + 24 + IP_Unknown + 15 + TRUE + . + + . + 2019.1.3 + GLOBAL + + + + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b.dcp b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b.dcp new file mode 100644 index 00000000..bdcb86ca --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:455f960a8efa57791a9b0058335580e823040d3abbdef16580b9e6c8ad3fa131 +size 900565 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b_sim_netlist.v b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b_sim_netlist.v new file mode 100755 index 00000000..3749233a --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b_sim_netlist.v @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:9bc1176345a762c1f9d903d12d13e5a15818b1004218447c1d225dc848c8d24b +size 1531436 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b_sim_netlist.vhdl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b_sim_netlist.vhdl new file mode 100755 index 00000000..e3976246 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b_sim_netlist.vhdl @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:8cdaa5ef74f94b7f302596866727f866daef813c0cf6cc8543bd657b5f83ae03 +size 2570752 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b_stub.v b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b_stub.v new file mode 100755 index 00000000..9e9ce677 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b_stub.v @@ -0,0 +1,28 @@ +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +// Date : Mon Jun 5 20:28:45 2023 +// Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_16b_stub.v +// Design : rotate_16b +// Purpose : Stub declaration of top-level module interface +// Device : xc7k410tffg900-2 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* x_core_info = "cordic_v6_0_15,Vivado 2019.1.3" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, s_axis_phase_tvalid, + s_axis_phase_tdata, s_axis_cartesian_tvalid, s_axis_cartesian_tdata, + m_axis_dout_tvalid, m_axis_dout_tdata) +/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]" */; + input aclk; + input s_axis_phase_tvalid; + input [15:0]s_axis_phase_tdata; + input s_axis_cartesian_tvalid; + input [31:0]s_axis_cartesian_tdata; + output m_axis_dout_tvalid; + output [31:0]m_axis_dout_tdata; +endmodule diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b_stub.vhdl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b_stub.vhdl new file mode 100755 index 00000000..8b077126 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/ip/2019.1.3/6d0942f1ca8f60d5/rotate_16b_stub.vhdl @@ -0,0 +1,36 @@ +-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 +-- Date : Mon Jun 5 20:28:45 2023 +-- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ rotate_16b_stub.vhdl +-- Design : rotate_16b +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7k410tffg900-2 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + aclk : in STD_LOGIC; + s_axis_phase_tvalid : in STD_LOGIC; + s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 ); + s_axis_cartesian_tvalid : in STD_LOGIC; + s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + m_axis_dout_tvalid : out STD_LOGIC; + m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_phase_tvalid,s_axis_phase_tdata[15:0],s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[31:0]"; +attribute x_core_info : string; +attribute x_core_info of stub : architecture is "cordic_v6_0_15,Vivado 2019.1.3"; +begin +end; diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf index 0cd849f9..e644baac 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/gui_handlers.wdf @@ -1,13 +1,13 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:3238:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3634:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3636:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7079697068616e646c65725f64657374696e6174696f6e5f69705f6e616d65:3132:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636f7265747265657461626c6570616e656c5f636f72655f747265655f7461626c65:3135:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:3139:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6670676163686f6f7365725f667067615f7461626c65:31:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:333138:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:39:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:333234:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6d616e6167655f6970:3130:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f6f70656e5f70726f6a656374:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67657474696e6773746172746564766965775f73746172745f7573696e675f76697661646f5f776974685f69705f636174616c6f67:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6861636763697073796d626f6c5f73686f775f64697361626c65645f706f727473:31:00:00 @@ -24,16 +24,16 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636c6f73655f70726f6a656374:3130:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f636f70795f6970:3133:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f67656e65726174655f636f6d706f736974655f66696c65:33:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f69705f6c6f636174696f6e:37:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6f70656e5f69705f6c6f636174696f6e:38:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f72657365745f636f6d706f736974655f66696c65:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f67726573736469616c6f675f6261636b67726f756e64:35:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f64656c657465:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72656d6f7665736f75726365736469616c6f675f616c736f5f64656c657465:38:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f636c6f73655f6469616c6f675f756e73617665645f6368616e6765735f77696c6c:36:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3139:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3231:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f72657365745f6f75747075745f70726f6475637473:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6164645f636f6e666967757261626c655f69705f66696c6573:3135:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6d616b655f6c6f63616c5f636f70795f6f665f74686573655f66696c65735f696e746f:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f646f63756d656e746174696f6e:3139:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f69705f6c6f636174696f6e73:36:00:00 -eof:162730464 +eof:1509944053 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf index dac092d3..fe215ef1 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/java_command_handlers.wdf @@ -6,8 +6,8 @@ version:1 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6564697464656c657465:39:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6d616e616765636f6d706f7369746574617267657473:35:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657769706c6f636174696f6e68616e646c6572:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:38:00:00 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e69706c6f636174696f6e68616e646c6572:39:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726576696f7573697068616e646c6572:36:00:00 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6f70656e70726f6a656374:31:00:00 -70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3630:00:00 -eof:63932490 +70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7265637573746f6d697a65636f7265:3632:00:00 +eof:3995730525 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc index 101cd880..b3f0e4d1 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/project.wpc @@ -1,3 +1,3 @@ version:1 -6d6f64655f636f756e7465727c4755494d6f6465:14 +6d6f64655f636f756e7465727c4755494d6f6465:15 eof: diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf index 6758ebf2..fc53cd97 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/synthesis.wdf @@ -1,7 +1,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:7863376b343130746666673930302d32:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e616d65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:696c615f387831325f38313932:00:00 +73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d746f70:6174616e325f313662:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d696e636c7564655f64697273:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d67656e65726963:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d766572696c6f675f646566696e65:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 @@ -33,7 +33,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a353873:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323332332e3438304d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3930362e3039304d42:00:00 -eof:3884629691 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313773:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323039312e3437374d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3639302e3535394d42:00:00 +eof:3006227906 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml index a79ad052..9d06f222 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -24,21 +24,21 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + - - + + @@ -55,13 +55,13 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -69,9 +69,9 @@ This means code written to parse this file will need to be revisited each subseq - + - +
diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_17.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_17.xml new file mode 100644 index 00000000..dcc7b697 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_17.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_18.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_18.xml new file mode 100644 index 00000000..479f2ff3 --- /dev/null +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/.jobs/vrs_config_18.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/gen_run.xml index 3917d7e6..6de8e637 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/add_s24_s32_s32_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/gen_run.xml index bad8c589..1a66d805 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg1_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/gen_run.xml index b088159d..0269bb2d 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ant_clk_gen_stg2_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/.vivado.begin.rst b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/.vivado.begin.rst index 46543467..6b3c550d 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/.vivado.begin.rst +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.dcp b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.dcp index f58232ad..59042e1e 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.dcp +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:8b3545bb41166cec0052b2c037f26d1024ef8e5d76a2317359e73bb7be9ebdf1 -size 817391 +oid sha256:f8336cbb7e8995023a69676ea042ceafe54b21b2ba073ff2efe3da508dcc0bb3 +size 817244 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.tcl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.tcl index 762c1739..633113f7 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.tcl +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.tcl @@ -17,8 +17,6 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } -set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin -set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin set_param project.vivado.isBlockSynthRun true set_msg_config -msgmgr_mode ooc_run create_project -in_memory -part xc7k410tffg900-2 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.vds b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.vds index 7340bec8..fb4d16e8 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.vds +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.vds @@ -2,8 +2,8 @@ # Vivado v2019.1.3 (64-bit) # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Apr 12 19:59:29 2023 -# Process ID: 277922 +# Start of session at: Mon Jun 5 20:28:34 2023 +# Process ID: 1070203 # Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1 # Command line: vivado -log atan2_16b.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source atan2_16b.tcl # Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.vds @@ -16,9 +16,9 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Device 21-403] Loading part xc7k410tffg900-2 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 278285 +INFO: Helper process launched with PID 1070336 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1824.492 ; gain = 152.719 ; free physical = 675 ; free virtual = 44056 +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1825.977 ; gain = 153.719 ; free physical = 1830 ; free virtual = 37269 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'atan2_16b' [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/atan2_16b/synth/atan2_16b.vhd:69] Parameter C_ARCHITECTURE bound to: 2 - type: integer @@ -34,7 +34,7 @@ INFO: [Synth 8-638] synthesizing module 'atan2_16b' [/home/josh/Workspace/vivado Parameter C_INPUT_WIDTH bound to: 16 - type: integer Parameter C_ITERATIONS bound to: 0 - type: integer Parameter C_OUTPUT_WIDTH bound to: 16 - type: integer - Parameter C_PHASE_FORMAT bound to: 1 - type: integer + Parameter C_PHASE_FORMAT bound to: 0 - type: integer Parameter C_PIPELINE_MODE bound to: -2 - type: integer Parameter C_PRECISION bound to: 0 - type: integer Parameter C_ROUND_MODE bound to: 0 - type: integer @@ -155,7 +155,7 @@ WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port a_s WARNING: [Synth 8-3331] design c_addsub_v12_0_13_legacy has unconnected port b_signed INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1926.211 ; gain = 254.438 ; free physical = 6153 ; free virtual = 48543 +Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1926.695 ; gain = 254.438 ; free physical = 2821 ; free virtual = 38104 --------------------------------------------------------------------------------- Report Check Netlist: @@ -168,10 +168,10 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1926.211 ; gain = 254.438 ; free physical = 6276 ; free virtual = 48667 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1926.695 ; gain = 254.438 ; free physical = 2820 ; free virtual = 38105 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1926.211 ; gain = 254.438 ; free physical = 6276 ; free virtual = 48666 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1926.695 ; gain = 254.438 ; free physical = 2820 ; free virtual = 38105 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 1931 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds @@ -185,30 +185,30 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ma Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2090.992 ; gain = 0.000 ; free physical = 6905 ; free virtual = 49302 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.477 ; gain = 0.000 ; free physical = 2695 ; free virtual = 37993 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2090.992 ; gain = 0.000 ; free physical = 6897 ; free virtual = 49296 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2091.477 ; gain = 0.000 ; free physical = 2695 ; free virtual = 37993 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 7497 ; free virtual = 49905 +Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2766 ; free virtual = 38073 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k410tffg900-2 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 7497 ; free virtual = 49905 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2766 ; free virtual = 38073 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:25 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 7496 ; free virtual = 49904 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2766 ; free virtual = 38073 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 7580 ; free virtual = 50002 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2763 ; free virtual = 38072 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -276,26 +276,25 @@ INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[17]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]' INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[18]' (FDR) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19]' INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.input_stage/gen_input_regs.phase_int_reg[19] ) -INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[0]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[0]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[10]' INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[1]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[2]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[3]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[4]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[5]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[6]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[7]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[8]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[9]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[10]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[11]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[12]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[13]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[14]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[15]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[17]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[18]' -INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[18]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[19]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[6]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[11]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[7]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[8]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[8]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[9]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[9]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[12]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[10]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[13]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[11]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[14]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[12]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[15]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[13]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[16]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[14]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[18]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[15]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[19]' +INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.output_stage/gen_rotation.gen_translate.gen_phase_rot_reg/gen_rtl.gen_reg.d_reg_reg[17]' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.input_stage/gen_rotation.gen_rot_xy.gen_data_y_int_dly/gen_rtl.gen_reg.d_reg_reg[3]' --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8146 ; free virtual = 50611 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2788 ; free virtual = 38104 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -307,13 +306,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8656 ; free virtual = 51196 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2643 ; free virtual = 37981 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:29 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8735 ; free virtual = 51282 +Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2637 ; free virtual = 37975 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -325,7 +324,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8641 ; free virtual = 51225 +Finished Technology Mapping : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2634 ; free virtual = 37976 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -349,7 +348,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8644 ; free virtual = 51253 +Finished IO Insertion : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976 --------------------------------------------------------------------------------- Report Check Netlist: @@ -362,7 +361,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8643 ; free virtual = 51252 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -374,25 +373,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8614 ; free virtual = 51232 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8609 ; free virtual = 51229 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8600 ; free virtual = 51220 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8599 ; free virtual = 51220 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -408,46 +407,46 @@ Report Cell Usage: +------+--------+------+ | |Cell |Count | +------+--------+------+ -|1 |LUT1 | 69| -|2 |LUT2 | 344| -|3 |LUT3 | 527| +|1 |LUT1 | 65| +|2 |LUT2 | 335| +|3 |LUT3 | 537| |4 |LUT4 | 32| |5 |MUXCY | 838| |6 |SRL16E | 5| |7 |SRLC32E | 1| |8 |XORCY | 806| -|9 |FDRE | 929| +|9 |FDRE | 930| +------+--------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:30 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8598 ; free virtual = 51219 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2632 ; free virtual = 37976 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 308 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:24 ; elapsed = 00:00:29 . Memory (MB): peak = 2090.992 ; gain = 254.438 ; free physical = 8624 ; free virtual = 51252 -Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:31 . Memory (MB): peak = 2090.992 ; gain = 419.219 ; free physical = 8622 ; free virtual = 51251 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 2091.477 ; gain = 254.438 ; free physical = 2684 ; free virtual = 38028 +Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2091.477 ; gain = 419.219 ; free physical = 2684 ; free virtual = 38028 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 1644 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2090.992 ; gain = 0.000 ; free physical = 9379 ; free virtual = 52041 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.477 ; gain = 0.000 ; free physical = 2623 ; free virtual = 37972 INFO: [Project 1-111] Unisim Transformation Summary: A total of 222 instances were transformed. (MUXCY,XORCY) => CARRY4: 222 instances INFO: [Common 17-83] Releasing license: Synthesis -70 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. +69 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:35 . Memory (MB): peak = 2090.992 ; gain = 697.527 ; free physical = 9577 ; free virtual = 52238 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2090.992 ; gain = 0.000 ; free physical = 9589 ; free virtual = 52251 +synth_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 2091.477 ; gain = 696.496 ; free physical = 2715 ; free virtual = 38064 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.477 ; gain = 0.000 ; free physical = 2715 ; free virtual = 38064 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP atan2_16b, cache-ID = d02f40fcf613a5a3 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP atan2_16b, cache-ID = 35ef934e18fcbb85 INFO: [Coretcl 2-1174] Renamed 350 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2115.004 ; gain = 0.000 ; free physical = 10245 ; free virtual = 52938 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2115.488 ; gain = 0.000 ; free physical = 2711 ; free virtual = 38080 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file atan2_16b_utilization_synth.rpt -pb atan2_16b_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Wed Apr 12 20:00:13 2023... +INFO: [Common 17-206] Exiting Vivado at Mon Jun 5 20:29:01 2023... diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.v b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.v index 76817d7b..a2b1ae36 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.v +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:78275070c3af54d5f76703c7dbf8c6c10ad944b812601c418cb903931d542195 -size 1346689 +oid sha256:898978d4f3b5a64415c6692f23de0e59488da509f2eb0fc37e6c3f23fe0e2ec9 +size 1343965 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.vhdl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.vhdl index cd60288a..92907bdd 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.vhdl +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:56d97a1e214c5edd418f2d2b30293a8f461622fcf64d2af491e97b8eeb34309a -size 2155333 +oid sha256:45af4a0c37b40c26a44a084d79f5bf4f2e909db830a3fd4ee931dea7753ab9e4 +size 2153323 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.v b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.v index dc976c9b..c11093f1 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.v +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Wed Apr 12 20:00:12 2023 +// Date : Mon Jun 5 20:29:00 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.v diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.vhdl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.vhdl index dbde49e4..8e407dc6 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.vhdl +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Wed Apr 12 20:00:12 2023 +-- Date : Mon Jun 5 20:29:01 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_stub.vhdl diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_utilization_synth.pb b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_utilization_synth.pb index 6748527c..e3bf96cb 100644 Binary files a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_utilization_synth.pb and b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_utilization_synth.pb differ diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_utilization_synth.rpt b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_utilization_synth.rpt index 6e404cde..267e0f6e 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_utilization_synth.rpt +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/atan2_16b_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Wed Apr 12 20:00:12 2023 +| Date : Mon Jun 5 20:29:00 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file atan2_16b_utilization_synth.rpt -pb atan2_16b_utilization_synth.pb | Design : atan2_16b @@ -30,13 +30,13 @@ Table of Contents +----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------------+------+-------+-----------+-------+ -| Slice LUTs* | 961 | 0 | 254200 | 0.38 | -| LUT as Logic | 955 | 0 | 254200 | 0.38 | +| Slice LUTs* | 958 | 0 | 254200 | 0.38 | +| LUT as Logic | 952 | 0 | 254200 | 0.37 | | LUT as Memory | 6 | 0 | 90600 | <0.01 | | LUT as Distributed RAM | 0 | 0 | | | | LUT as Shift Register | 6 | 0 | | | -| Slice Registers | 929 | 0 | 508400 | 0.18 | -| Register as Flip Flop | 929 | 0 | 508400 | 0.18 | +| Slice Registers | 930 | 0 | 508400 | 0.18 | +| Register as Flip Flop | 930 | 0 | 508400 | 0.18 | | Register as Latch | 0 | 0 | 508400 | 0.00 | | F7 Muxes | 0 | 0 | 127100 | 0.00 | | F8 Muxes | 0 | 0 | 63550 | 0.00 | @@ -59,7 +59,7 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 0 | Yes | Set | - | -| 929 | Yes | Reset | - | +| 930 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -153,11 +153,11 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| FDRE | 929 | Flop & Latch | -| LUT3 | 527 | LUT | -| LUT2 | 344 | LUT | +| FDRE | 930 | Flop & Latch | +| LUT3 | 537 | LUT | +| LUT2 | 335 | LUT | | CARRY4 | 222 | CarryLogic | -| LUT1 | 69 | LUT | +| LUT1 | 65 | LUT | | LUT4 | 32 | LUT | | SRL16E | 5 | Distributed Memory | | SRLC32E | 1 | Distributed Memory | diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/gen_run.xml index 43b85f6d..c5dcf6ff 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/gen_run.xml @@ -1,20 +1,23 @@ - - - - + + + - + + + + + - + - + @@ -27,14 +30,14 @@ - + - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/project.wdf b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/project.wdf index 128aa635..16dc28de 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/project.wdf +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/project.wdf @@ -1,13 +1,13 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3136:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3330:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3136:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3136:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3138:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3138:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 @@ -25,15 +25,24 @@ version:1 70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f6163636f725f636463:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f7765696768745f636463:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f327831327831303234:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3278313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3478313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f387831325f327833305f313331303732:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f387831325f327833305f38313932:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f387831325f38313932:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3878313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f63616c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f7072655f616e74:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f7072655f737973:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c72616d5f686f705f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c726f746174655f313662:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f7264:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f74657374:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f636c6b5f6c645f7264:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f72665f7264:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 @@ -43,12 +52,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3331:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3331:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3331:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3331:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3331:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3331:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3331:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3735:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3735:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3735:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3735:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3735:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3735:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3735:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3239373561633434643362303430613962303236326565396330623238613761:506172656e742050412070726f6a656374204944:00 -eof:2529481700 +eof:1296303891 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/rundef.js b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/rundef.js index a0464a5f..59da8a7c 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/rundef.js +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/rundef.js @@ -12,9 +12,9 @@ var WshShell = new ActiveXObject( "WScript.Shell" ); var ProcEnv = WshShell.Environment( "Process" ); var PathVal = ProcEnv("PATH"); if ( PathVal.length == 0 ) { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; + PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;"; } else { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; + PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;" + PathVal; } ProcEnv("PATH") = PathVal; diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/runme.sh b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/runme.sh index e23e0da9..359b519f 100755 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/runme.sh +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/runme.sh @@ -7,9 +7,9 @@ # if [ -z "$PATH" ]; then - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin + PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin else - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH + PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin:$PATH fi export PATH diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/vivado.pb b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/vivado.pb index 9e9ab99c..296e998c 100644 Binary files a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/vivado.pb and b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/atan2_16b_synth_1/vivado.pb differ diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_12x12_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_12x12_synth_1/gen_run.xml index 850ca9c2..e6d1c0e1 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_12x12_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_12x12_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_16x12_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_16x12_synth_1/gen_run.xml index e8a863ba..d4e79901 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_16x12_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/cmpy_16x12_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/gen_run.xml index 5e1352f0..abef7aea 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/fifo_AntCtrl_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_2x12x1024_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_2x12x1024_synth_1/gen_run.xml index dc43793a..dfa0ae10 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_2x12x1024_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_2x12x1024_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_131072_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_131072_synth_1/gen_run.xml index 06fd15ee..6943ab02 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_131072_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_131072_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_8192_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_8192_synth_1/gen_run.xml index a328d9be..b81e9054 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_8192_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_2x30_8192_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_8192_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_8192_synth_1/gen_run.xml index 5f31d51c..54556369 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_8192_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ila_8x12_8192_synth_1/gen_run.xml @@ -1,14 +1,11 @@ - - - - - - - - + + + + + @@ -56,9 +53,7 @@ - - Vivado Synthesis Defaults - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ram_hop_data_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ram_hop_data_synth_1/gen_run.xml index 47ab99f8..949cfac7 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ram_hop_data_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/ram_hop_data_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/.vivado.begin.rst b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/.vivado.begin.rst index 0e36d479..31d601b0 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/.vivado.begin.rst +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/gen_run.xml index 06562fec..21118384 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/gen_run.xml @@ -1,20 +1,23 @@ - - - - + + + - + + + + + - + - + @@ -27,14 +30,14 @@ - + - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/project.wdf b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/project.wdf index 128aa635..9511089d 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/project.wdf +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/project.wdf @@ -1,13 +1,13 @@ version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3136:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3330:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3136:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3136:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:3138:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:3138:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 @@ -25,15 +25,24 @@ version:1 70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f6163636f725f636463:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c6669666f5f67656e657261746f725f7631335f325f345c6669666f5f7765696768745f636463:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f327831327831303234:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3278313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3478313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f387831325f327833305f313331303732:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f387831325f327833305f38313932:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f387831325f38313932:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f3878313278313331303732:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f416e744374726c:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f63616c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f7072655f616e74:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c696c615f76365f325f395c696c615f72785f7072655f737973:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c626c6b5f6d656d5f67656e5f76385f345f335c72616d5f686f705f64617461:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c636f726469635f76365f305f31355c726f746174655f313662:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f7264:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f616e745f74657374:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f636c6b5f6c645f7264:636f72655f636f6e7461696e6572:74727565:00:00 +70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f6d616e75616c5f6374726c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f72665f7264:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:69705f636f72655f636f6e7461696e65725c76696f5f76335f305f32305c76696f5f7266636f6e74726c:636f72655f636f6e7461696e6572:74727565:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 @@ -43,12 +52,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3331:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3331:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3331:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3331:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3331:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3331:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3331:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:3734:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:3734:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:3734:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:3734:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:3734:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:3734:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:3734:00:00 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3239373561633434643362303430613962303236326565396330623238613761:506172656e742050412070726f6a656374204944:00 -eof:2529481700 +eof:4010926639 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.dcp b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.dcp index df3842ce..21bba31c 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.dcp +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.dcp @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:eb146b3062e893cce8d4bb33b2b0365e8022987c3762dbe973b5dfb74a124f13 -size 906310 +oid sha256:8854e6104b35d1d68488535f2f92ca467502106a4b0b54f951647b9bd27a2083 +size 906356 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.tcl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.tcl index 91138bdf..9f84615b 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.tcl +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.tcl @@ -17,8 +17,6 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } -set_param simulator.modelsimInstallPath /home/josh/Software/Mentor/modeltech/bin -set_param simulator.vcsmxInstallPath /usr/synopsys/vcs/T-2022.06/bin set_param project.vivado.isBlockSynthRun true set_msg_config -msgmgr_mode ooc_run create_project -in_memory -part xc7k410tffg900-2 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.vds b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.vds index f144b9c1..ca96ec10 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.vds +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.vds @@ -2,8 +2,8 @@ # Vivado v2019.1.3 (64-bit) # SW Build 2644227 on Wed Sep 4 09:44:18 MDT 2019 # IP Build 2633630 on Wed Sep 4 12:30:14 MDT 2019 -# Start of session at: Wed Apr 12 19:59:29 2023 -# Process ID: 277934 +# Start of session at: Mon Jun 5 20:28:19 2023 +# Process ID: 1069927 # Current directory: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1 # Command line: vivado -log rotate_16b.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source rotate_16b.tcl # Log file: /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.vds @@ -16,9 +16,9 @@ Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Device 21-403] Loading part xc7k410tffg900-2 INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 278356 +INFO: Helper process launched with PID 1070047 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1824.559 ; gain = 152.719 ; free physical = 655 ; free virtual = 44036 +Starting RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1825.973 ; gain = 153.719 ; free physical = 1803 ; free virtual = 38052 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'rotate_16b' [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/rx_pre_process/rotate_16b/synth/rotate_16b.vhd:71] Parameter C_ARCHITECTURE bound to: 2 - type: integer @@ -34,7 +34,7 @@ INFO: [Synth 8-638] synthesizing module 'rotate_16b' [/home/josh/Workspace/vivad Parameter C_INPUT_WIDTH bound to: 16 - type: integer Parameter C_ITERATIONS bound to: 0 - type: integer Parameter C_OUTPUT_WIDTH bound to: 16 - type: integer - Parameter C_PHASE_FORMAT bound to: 1 - type: integer + Parameter C_PHASE_FORMAT bound to: 0 - type: integer Parameter C_PIPELINE_MODE bound to: -2 - type: integer Parameter C_PRECISION bound to: 0 - type: integer Parameter C_ROUND_MODE bound to: 0 - type: integer @@ -132,7 +132,7 @@ WARNING: [Synth 8-3331] design cordic_v6_0_15_viv has unconnected port s_axis_ca WARNING: [Synth 8-3331] design cordic_v6_0_15_viv has unconnected port s_axis_cartesian_tlast WARNING: [Synth 8-3331] design cordic_v6_0_15_viv has unconnected port m_axis_dout_tready --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1926.277 ; gain = 254.438 ; free physical = 4487 ; free virtual = 46871 +Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1927.691 ; gain = 255.438 ; free physical = 1974 ; free virtual = 38030 --------------------------------------------------------------------------------- Report Check Netlist: @@ -145,10 +145,10 @@ Report Check Netlist: Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1926.277 ; gain = 254.438 ; free physical = 4434 ; free virtual = 46818 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1927.691 ; gain = 255.438 ; free physical = 1969 ; free virtual = 38025 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:18 . Memory (MB): peak = 1926.277 ; gain = 254.438 ; free physical = 4434 ; free virtual = 46818 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1927.691 ; gain = 255.438 ; free physical = 1969 ; free virtual = 38025 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 2136 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds @@ -162,30 +162,30 @@ Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/ma Finished Parsing XDC File [/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/dont_touch.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.059 ; gain = 0.000 ; free physical = 5179 ; free virtual = 47564 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2089.504 ; gain = 0.000 ; free physical = 1855 ; free virtual = 37773 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2091.059 ; gain = 0.000 ; free physical = 5192 ; free virtual = 47577 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2089.504 ; gain = 0.000 ; free physical = 1941 ; free virtual = 37859 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 6861 ; free virtual = 49252 +Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1845 ; free virtual = 37746 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k410tffg900-2 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 6859 ; free virtual = 49250 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1845 ; free virtual = 37745 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for U0. (constraint file /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 6859 ; free virtual = 49250 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1842 ; free virtual = 37743 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 6762 ; free virtual = 49155 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1845 ; free virtual = 37674 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -291,7 +291,7 @@ INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synt INFO: [Synth 8-3886] merging instance 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[12].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' (FDRE) to 'U0/i_synth/i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg' INFO: [Synth 8-3333] propagating constant 0 across sequential element (U0/i_synth/\i_synth/gen_cordic.cordic_engine/gen_para_arch.gen_iteration[0].eng/cntrl/engine_mode_dly/gen_rtl.gen_reg.d_reg_reg ) --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:23 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 6901 ; free virtual = 49303 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1845 ; free virtual = 37646 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -303,13 +303,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8181 ; free virtual = 50627 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1827 ; free virtual = 37278 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8146 ; free virtual = 50611 +Finished Timing Optimization : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1824 ; free virtual = 37272 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -321,7 +321,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8062 ; free virtual = 50544 +Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1832 ; free virtual = 37277 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -345,7 +345,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8068 ; free virtual = 50573 +Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1825 ; free virtual = 37253 --------------------------------------------------------------------------------- Report Check Netlist: @@ -358,7 +358,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:23 ; elapsed = 00:00:27 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8067 ; free virtual = 50573 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1823 ; free virtual = 37251 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -370,25 +370,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8047 ; free virtual = 50558 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1816 ; free virtual = 37240 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8046 ; free virtual = 50557 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1816 ; free virtual = 37240 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8045 ; free virtual = 50557 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1816 ; free virtual = 37240 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8043 ; free virtual = 50556 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1815 ; free virtual = 37239 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -417,17 +417,17 @@ Report Cell Usage: |11 |FDRE | 1105| +------+--------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8043 ; free virtual = 50556 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1815 ; free virtual = 37239 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 321 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:26 . Memory (MB): peak = 2091.059 ; gain = 254.438 ; free physical = 8084 ; free virtual = 50598 -Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:28 . Memory (MB): peak = 2091.059 ; gain = 419.219 ; free physical = 8084 ; free virtual = 50598 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2089.504 ; gain = 255.438 ; free physical = 1866 ; free virtual = 37290 +Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 2089.504 ; gain = 417.250 ; free physical = 1866 ; free virtual = 37290 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 1888 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.059 ; gain = 0.000 ; free physical = 8651 ; free virtual = 51195 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2089.504 ; gain = 0.000 ; free physical = 1903 ; free virtual = 37167 INFO: [Project 1-111] Unisim Transformation Summary: A total of 257 instances were transformed. (MUXCY,XORCY) => CARRY4: 257 instances @@ -435,17 +435,17 @@ INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Common 17-83] Releasing license: Synthesis 66 Infos, 100 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:28 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.059 ; gain = 698.051 ; free physical = 8736 ; free virtual = 51283 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2091.059 ; gain = 0.000 ; free physical = 8736 ; free virtual = 51283 +synth_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 2089.504 ; gain = 694.527 ; free physical = 1998 ; free virtual = 37256 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2089.504 ; gain = 0.000 ; free physical = 1998 ; free virtual = 37256 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.dcp' has been generated. WARNING: [Common 17-576] 'use_project_ipc' is deprecated. This option is deprecated and no longer used. -INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rotate_16b, cache-ID = 2387465c02ffa019 +INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP rotate_16b, cache-ID = 6d0942f1ca8f60d5 INFO: [Coretcl 2-1174] Renamed 371 cell refs. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2115.070 ; gain = 0.000 ; free physical = 8680 ; free virtual = 51280 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2113.516 ; gain = 0.000 ; free physical = 1975 ; free virtual = 37247 WARNING: [Constraints 18-5210] No constraints selected for write. Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. INFO: [Common 17-1381] The checkpoint '/home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file rotate_16b_utilization_synth.rpt -pb rotate_16b_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Wed Apr 12 20:00:11 2023... +INFO: [Common 17-206] Exiting Vivado at Mon Jun 5 20:28:47 2023... diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.v b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.v index 76808654..aa13da9e 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.v +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.v @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0be16eb37d8248ffc1106840a4c21e009320ec552ccd67691ba624e646408d65 -size 1501691 +oid sha256:2d8fa8632255ba3f8f9505619cc3e2a3406476260562ac1dca8430ca795f2127 +size 1501561 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.vhdl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.vhdl index 4b76e14e..2ec401fb 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.vhdl +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_sim_netlist.vhdl @@ -1,3 +1,3 @@ version https://git-lfs.github.com/spec/v1 -oid sha256:0ffe5dea9fbbc0bffbde62e434e309a6c0543f4ae7bab872ae0d9df7e29c7907 +oid sha256:2893c0d9d73a08543c712846b8a6bd0071d9f7bba5c4ae5010f485bf3b7766e0 size 2432935 diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.v b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.v index d33c5af0..d625a06f 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.v +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -// Date : Wed Apr 12 20:00:10 2023 +// Date : Mon Jun 5 20:28:46 2023 // Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS // Command : write_verilog -force -mode synth_stub // /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.v diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.vhdl b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.vhdl index 380c7471..647623f5 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.vhdl +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 --- Date : Wed Apr 12 20:00:10 2023 +-- Date : Mon Jun 5 20:28:46 2023 -- Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/josh/Workspace/vivado-git/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_stub.vhdl diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_utilization_synth.rpt b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_utilization_synth.rpt index 0c61ca78..9b224180 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_utilization_synth.rpt +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rotate_16b_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2019.1.3 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019 -| Date : Wed Apr 12 20:00:10 2023 +| Date : Mon Jun 5 20:28:46 2023 | Host : JOSH-ASUS-Z690 running 64-bit Ubuntu 20.04.6 LTS | Command : report_utilization -file rotate_16b_utilization_synth.rpt -pb rotate_16b_utilization_synth.pb | Design : rotate_16b diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rundef.js b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rundef.js index adb39e3c..cac74990 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rundef.js +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/rundef.js @@ -12,9 +12,9 @@ var WshShell = new ActiveXObject( "WScript.Shell" ); var ProcEnv = WshShell.Environment( "Process" ); var PathVal = ProcEnv("PATH"); if ( PathVal.length == 0 ) { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;"; + PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;"; } else { - PathVal = "/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2019.1/bin;" + PathVal; + PathVal = "/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64;/home/josh/Software/Xilinx/Vivado/2019.1/bin;" + PathVal; } ProcEnv("PATH") = PathVal; diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/runme.sh b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/runme.sh index 41c8f2fb..78983c1a 100755 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/runme.sh +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/runme.sh @@ -7,9 +7,9 @@ # if [ -z "$PATH" ]; then - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin + PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin else - PATH=/tools/Xilinx/SDK/2019.1/bin:/tools/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2019.1/bin:$PATH + PATH=/home/josh/Software/Xilinx/SDK/2019.1/bin:/home/josh/Software/Xilinx/Vivado/2019.1/ids_lite/ISE/bin/lin64:/home/josh/Software/Xilinx/Vivado/2019.1/bin:$PATH fi export PATH diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/vivado.pb b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/vivado.pb index 9238c80f..fc27e950 100644 Binary files a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/vivado.pb and b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/rotate_16b_synth_1/vivado.pb differ diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/gen_run.xml index fecb9acc..21f1f99b 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_rd_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_test_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_test_synth_1/gen_run.xml index 5fffc742..1139622c 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_test_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_ant_test_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rf_rd_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rf_rd_synth_1/gen_run.xml index 0ad9ede3..15e03312 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rf_rd_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rf_rd_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml index 8eccd470..b6c1cc72 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.runs/vio_rfcontrl_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.xpr b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.xpr index 47ff6937..ed4573c0 100644 --- a/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.xpr +++ b/projects/dl814_k7/common_ip/managed_ip_project/managed_ip_project.xpr @@ -39,13 +39,13 @@