analog.com user axi_ad7616 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_ad7616 xilinx_anylanguagesynthesis_analog_com_user_spi_engine_execution_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_axi_spi_engine_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_spi_engine_offload_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_spi_engine_interconnect_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 8ac2383c xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_ad7616 xilinx_anylanguagebehavioralsimulation_analog_com_user_spi_engine_execution_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_spi_engine_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_spi_engine_offload_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_spi_engine_interconnect_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 8ac2383c xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_spi_engine_execution_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_axi_spi_engine_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_spi_engine_offload_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_spi_engine_interconnect_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum babc35ad rx_sclk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_cs_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_sdo out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_sdi in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 rx_db_o out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_db_i in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 rx_db_t out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_rd_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_wr_n out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_cnvst out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation rx_busy in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 adc_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_sync out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation irq out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ID Id 0 IF_TYPE If Type 1 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset ../common/ad_edge_detect.v verilogSource axi_ad7616_control.v verilogSource axi_ad7616_maxis2wrfifo.v verilogSource axi_ad7616_pif.v verilogSource ../common/up_axi.v verilogSource axi_ad7616.v verilogSource CHECKSUM_c7d332ef xilinx_anylanguagesynthesis_analog_com_user_spi_engine_execution_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_axi_spi_engine_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_spi_engine_offload_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_spi_engine_interconnect_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_edge_detect.v verilogSource axi_ad7616_control.v verilogSource axi_ad7616_maxis2wrfifo.v verilogSource axi_ad7616_pif.v verilogSource ../common/up_axi.v verilogSource axi_ad7616.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_spi_engine_execution_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_spi_engine_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_spi_engine_offload_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_spi_engine_interconnect_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/axi_ad7616_v1_0.tcl tclSource CHECKSUM_babc35ad XGUI_VERSION_2 xilinx_xpgui_analog_com_user_spi_engine_execution_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_axi_spi_engine_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_spi_engine_offload_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_spi_engine_interconnect_1_0__ref_view_fileset axi_ad7616_v1_0 ID Id 0 IF_TYPE If Type 1 Component_Name axi_ad7616_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_ad7616_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:08:15Z 2019.1.3