analog.com user jesd204_tx_static_config 1.0 tx_cfg lanes_disable cfg_lanes_disable beats_per_multiframe cfg_beats_per_multiframe octets_per_frame cfg_octets_per_frame lmfc_offset cfg_lmfc_offset sysref_oneshot cfg_sysref_oneshot sysref_disable cfg_sysref_disable continuous_cgs cfg_continuous_cgs continuous_ilas cfg_continuous_ilas skip_ilas cfg_skip_ilas mframes_per_ilas cfg_mframes_per_ilas disable_char_replacement cfg_disable_char_replacement disable_scrambler cfg_disable_scrambler tx_ilas_config rd ilas_config_rd addr ilas_config_addr data ilas_config_data tx_cfg_tx_ilas_config_signal_clock tx_cfg_tx_ilas_config_signal_clock CLK core_clk ASSOCIATED_BUSIF tx_cfg:tx_ilas_config xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog jesd204_tx_static_config xilinx_anylanguagesynthesis_view_fileset viewChecksum 292df020 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog jesd204_tx_static_config xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 292df020 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 16e9ebca clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_lanes_disable out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_links_disable out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_beats_per_multiframe out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_octets_per_frame out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_lmfc_offset out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_sysref_oneshot out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_sysref_disable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_continuous_cgs out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_continuous_ilas out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_skip_ilas out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_mframes_per_ilas out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_char_replacement out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cfg_disable_scrambler out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_rd in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_addr in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ilas_config_data out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 OCTETS_PER_FRAME Octets Per Frame 1 FRAMES_PER_MULTIFRAME Frames Per Multiframe 32 NUM_CONVERTERS Num Converters 1 N N 16 NP Np 16 HIGH_DENSITY High Density 1 SCR Scr 1 LINK_MODE Link Mode 1 xilinx_anylanguagesynthesis_view_fileset jesd204_ilas_cfg_static.v verilogSource jesd204_tx_static_config.v verilogSource CHECKSUM_0ae87234 xilinx_anylanguagebehavioralsimulation_view_fileset jesd204_ilas_cfg_static.v verilogSource jesd204_tx_static_config.v verilogSource xilinx_xpgui_view_fileset xgui/jesd204_tx_static_config_v1_0.tcl tclSource CHECKSUM_16e9ebca XGUI_VERSION_2 jesd204_tx_static_config_v1_0 NUM_LANES Num Lanes 1 NUM_LINKS Num Links 1 OCTETS_PER_FRAME Octets Per Frame 1 FRAMES_PER_MULTIFRAME Frames Per Multiframe 32 NUM_CONVERTERS Num Converters 1 N N 16 NP Np 16 HIGH_DENSITY High Density 1 SCR Scr 1 LINK_MODE Link Mode 1 Component_Name jesd204_tx_static_config_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices jesd204_tx_static_config_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:17:46Z 2019.1.3