analog.com user axi_spi_engine 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready true s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW spi_engine_ctrl CMD_READY cmd_ready CMD_VALID cmd_valid CMD_DATA cmd_data SDO_READY sdo_data_ready SDO_VALID sdo_data_valid SDO_DATA sdo_data SDI_READY sdi_data_ready SDI_VALID sdi_data_valid SDI_DATA sdi_data SYNC_READY sync_ready SYNC_VALID sync_valid SYNC_DATA sync_data spi_engine_ctrl_signal_clock spi_engine_ctrl_signal_clock CLK spi_clk ASSOCIATED_BUSIF spi_engine_ctrl ASSOCIATED_RESET spi_resetn spi_engine_ctrl_signal_reset spi_engine_ctrl_signal_reset RST spi_resetn POLARITY ACTIVE_LOW spi_engine_offload_ctrl0 CMD_WR_EN offload0_cmd_wr_en CMD_WR_DATA offload0_cmd_wr_data SDO_WR_EN offload0_sdo_wr_en SDO_WR_DATA offload0_sdo_wr_data ENABLE offload0_enable ENABLED offload0_enabled MEM_RESET offload0_mem_reset SYNC_READY offload_sync_ready SYNC_VALID offload_sync_valid SYNC_DATA offload_sync_data false spi_engine_offload_ctrl0_s_axi_signal_clock spi_engine_offload_ctrl0_s_axi_signal_clock CLK s_axi_aclk ASSOCIATED_BUSIF spi_engine_offload_ctrl0:s_axi ASSOCIATED_RESET s_axi_aresetn spi_engine_offload_ctrl0_s_axi_signal_reset spi_engine_offload_ctrl0_s_axi_signal_reset RST s_axi_aresetn POLARITY ACTIVE_LOW s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_spi_engine xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 789411fa xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_spi_engine xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 21dd247c xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum ff0f3bd6 xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true up_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false up_rstn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false up_wreq in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false up_waddr in 13 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false up_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false up_wack out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false up_rreq in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false up_raddr in 13 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false up_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false up_rack out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false irq out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_resetn out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_data out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_data_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdo_data_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdi_data_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdi_data_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdi_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sync_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 offload0_cmd_wr_en out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation offload0_cmd_wr_data out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation offload0_sdo_wr_en out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation offload0_sdo_wr_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation offload0_mem_reset out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation offload0_enable out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation offload0_enabled in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation offload_sync_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation offload_sync_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 offload_sync_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 CMD_FIFO_ADDRESS_WIDTH Cmd Fifo Address Width 4 SYNC_FIFO_ADDRESS_WIDTH Sync Fifo Address Width 4 SDO_FIFO_ADDRESS_WIDTH Sdo Fifo Address Width 5 SDI_FIFO_ADDRESS_WIDTH Sdi Fifo Address Width 5 MM_IF_TYPE Mm If Type 0 ASYNC_SPI_CLK Async Spi Clk false NUM_OFFLOAD Num Offload 0 OFFLOAD0_CMD_MEM_ADDRESS_WIDTH Offload0 Cmd Mem Address Width 4 false OFFLOAD0_SDO_MEM_ADDRESS_WIDTH Offload0 Sdo Mem Address Width 4 false ID Id 0 DATA_WIDTH Data Width 8 NUM_OF_SDI Num Of Sdi 1 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_a1d277e1 0 1 xilinx_anylanguagesynthesis_view_fileset axi_spi_engine_constr.ttcl ttcl ../../xilinx/common/ad_rst_constr.xdc xdc ../../common/ad_rst.v verilogSource ../../common/up_axi.v verilogSource axi_spi_engine.v verilogSource CHECKSUM_0646b330 xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../../common/ad_rst.v verilogSource ../../common/up_axi.v verilogSource axi_spi_engine.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/axi_spi_engine_v1_0.tcl tclSource CHECKSUM_1a1413bd XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_utilityxitfiles_view_fileset gui/axi_spi_engine_v1_0.gtcl GTCL axi_spi_engine_v1_0 CMD_FIFO_ADDRESS_WIDTH Command FIFO address width 4 SYNC_FIFO_ADDRESS_WIDTH SYNC FIFO address width 4 SDO_FIFO_ADDRESS_WIDTH MOSI FIFO address width 5 SDI_FIFO_ADDRESS_WIDTH MISO FIFO address width 5 MM_IF_TYPE Memory Mapped Interface Type 0 ASYNC_SPI_CLK Asynchronous core clock false NUM_OFFLOAD Number of offloads 0 OFFLOAD0_CMD_MEM_ADDRESS_WIDTH Offload command FIFO address width 4 false OFFLOAD0_SDO_MEM_ADDRESS_WIDTH Offload MOSI FIFO address width 4 false ID Core ID 0 DATA_WIDTH Parallel data width 8 NUM_OF_SDI Number of MISO lines 1 Component_Name axi_spi_engine_v1_0 virtex7 aartix7 akintex7 artix7 artix7l aspartan7 azynq azynquplus kintex7 kintex7l kintexu kintexuplus qartix7 qkintex7 qkintex7l qkintexu qkintexuplus qrkintexu qvirtex7 qvirtexuplus qzynq qzynquplus qzynquplusRFSOC spartan7 virtexu virtexuplus virtexuplus58g virtexuplusHBM zynq zynquplus zynquplusRFSOC /Analog_Devices axi_spi_engine_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:07:42Z 2019.1.3