analog.com user util_cpack2 1.0 packed_fifo_wr EN packed_fifo_wr_en DATA packed_fifo_wr_data OVERFLOW packed_fifo_wr_overflow SYNC packed_fifo_wr_sync packed_fifo_wr_signal_clock packed_fifo_wr_signal_clock CLK clk ASSOCIATED_BUSIF packed_fifo_wr ASSOCIATED_RESET reset packed_fifo_wr_signal_reset packed_fifo_wr_signal_reset RST reset POLARITY ACTIVE_HIGH xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_cpack2 xilinx_anylanguagesynthesis_view_fileset viewChecksum 77439c2c xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_cpack2 xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 77439c2c xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 31df22aa clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation enable_0 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation enable_1 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true enable_2 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true enable_3 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation true enable_4 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_5 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_6 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_7 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_8 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_9 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_10 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_11 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_12 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_13 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_14 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_15 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_16 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_17 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_18 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_19 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_20 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_21 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_22 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_23 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_24 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_25 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_26 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_27 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_28 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_29 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_30 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_31 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_32 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_33 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_34 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_35 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_36 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_37 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_38 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_39 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_40 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_41 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_42 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_43 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_44 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_45 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_46 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_47 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_48 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_49 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_50 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_51 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_52 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_53 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_54 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_55 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_56 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_57 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_58 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_59 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_60 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_61 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_62 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false enable_63 in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation false fifo_wr_en in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 fifo_wr_overflow out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifo_wr_data_0 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 fifo_wr_data_1 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true fifo_wr_data_2 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true fifo_wr_data_3 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 true fifo_wr_data_4 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_5 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_6 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_7 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_8 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_9 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_10 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_11 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_12 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_13 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_14 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_15 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_16 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_17 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_18 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_19 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_20 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_21 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_22 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_23 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_24 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_25 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_26 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_27 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_28 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_29 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_30 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_31 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_32 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_33 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_34 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_35 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_36 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_37 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_38 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_39 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_40 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_41 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_42 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_43 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_44 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_45 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_46 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_47 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_48 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_49 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_50 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_51 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_52 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_53 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_54 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_55 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_56 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_57 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_58 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_59 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_60 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_61 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_62 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false fifo_wr_data_63 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false packed_fifo_wr_en out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation packed_fifo_wr_overflow in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 packed_fifo_wr_sync out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation packed_fifo_wr_data out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation NUM_OF_CHANNELS Num Of Channels 4 SAMPLES_PER_CHANNEL Samples Per Channel 1 SAMPLE_DATA_WIDTH Sample Data Width 16 xilinx_anylanguagesynthesis_view_fileset ../../common/ad_perfect_shuffle.v verilogSource ../util_pack_common/pack_ctrl.v verilogSource ../util_pack_common/pack_interconnect.v verilogSource ../util_pack_common/pack_network.v verilogSource ../util_pack_common/pack_shell.v verilogSource util_cpack2_impl.v verilogSource util_cpack2.v verilogSource CHECKSUM_c55a5d6e xilinx_anylanguagebehavioralsimulation_view_fileset ../../common/ad_perfect_shuffle.v verilogSource ../util_pack_common/pack_ctrl.v verilogSource ../util_pack_common/pack_interconnect.v verilogSource ../util_pack_common/pack_network.v verilogSource ../util_pack_common/pack_shell.v verilogSource util_cpack2_impl.v verilogSource util_cpack2.v verilogSource xilinx_xpgui_view_fileset xgui/util_cpack2_v1_0.tcl tclSource CHECKSUM_31df22aa XGUI_VERSION_2 util_cpack2_v1_0 NUM_OF_CHANNELS Number of Channels 4 SAMPLES_PER_CHANNEL Samples per Channel 1 SAMPLE_DATA_WIDTH Sample Width 16 Component_Name util_cpack2_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices util_cpack2_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-08T02:23:54Z 2019.1.3