analog.com user axi_mc_current_monitor 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW ref_clk CLK ref_clk adc_clk_i CLK adc_clk_i adc_clk_o CLK adc_clk_o s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_mc_current_monitor xilinx_anylanguagesynthesis_view_fileset viewChecksum 6b969d5b xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_mc_current_monitor xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum cb74f52c xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 adc_ia_dat_i in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_ia out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_ib_dat_i in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_ib out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_vbus_dat_i in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_vbus out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_clk_o out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ref_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_clk_i in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ia_o out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ib_o out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation vbus_o out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation i_ready_o out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axi_mc_current_monitor_constr.xdc xdc ad7401.v verilogSource ../common/ad_rst.v verilogSource dec256sinc24b.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_mc_current_monitor.v verilogSource CHECKSUM_885fc6e8 xilinx_anylanguagebehavioralsimulation_view_fileset ad7401.v verilogSource ../common/ad_rst.v verilogSource dec256sinc24b.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_mc_current_monitor.v verilogSource xilinx_xpgui_view_fileset xgui/axi_mc_current_monitor_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 axi_mc_current_monitor_v1_0 Component_Name axi_mc_current_monitor_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_mc_current_monitor_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:16:05Z 2019.1.3