`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // _ _ ____ // | | ___ ___| |__ / ___| __ _ ___ // _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ // | |_| | (_) \__ \ | | | | |_| | (_| | (_) | // \___/ \___/|___/_| |_| \____|\__,_|\___/ // // Create Date: 2022/06/07 21:17:23 // Design Name: // Module Name: system_top // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module system_top ( // ************************************************************************* // *************************** Clocks and Resets *************************** // ************************************************************************* input sysclk_p , // FPGA_LOGIC_CLK_IN, derived from ad9528, 122.88mhz input sysclk_n , input refclk_p , // FPGA_JESD204B_CLK_IN_1, derived from ad9528, 122.88mhz input refclk_n , input sysref_p , input sysref_n , // ************************************************************************* // *************************** AD9528 Interface **************************** // ************************************************************************* // spi interface output spi_csn_ad9528 , output spi_clk_ad9528 , output spi_mosi_ad9528 , input spi_miso_ad9528 , // control signals output ad9528_reset_b , output ad9528_sysref_req , // ************************************************************************* // *************************** AD9371 Interface **************************** // ************************************************************************* // 204b interface, only lane 0 and lane 1 are used output rx_sync_p , output rx_sync_n , input tx_sync_p , input tx_sync_n , input [ 1:0] rx_data_p , input [ 1:0] rx_data_n , output [ 1:0] tx_data_p , output [ 1:0] tx_data_n , // spi interface output spi_csn_ad9371 , output spi_clk_ad9371 , output spi_mosi_ad9371 , input spi_miso_ad9371 , // control signals output ad9371_test , output ad9371_reset_b , input ad9371_gpint , // ************************************************************************* // ****************************** RF Control ******************************* // ************************************************************************* output tx_gain_5bit , output tx_gain_6bit , output rx_gain_3bit , output rx_gain_4bit , output rx_gain_5bit , output tx_gain_on , output rx_gain_on , output [10:0] freq_hop_words , output hop_words_valid , output freq_hop_switch , // ************************************************************************* // ******************* DDR and Fixed-io (Do NOT Modify) ******************** // ************************************************************************* // ddr inout [14:0] ddr_addr , inout [ 2:0] ddr_ba , inout ddr_cas_n , inout ddr_ck_n , inout ddr_ck_p , inout ddr_cke , inout ddr_cs_n , inout [ 3:0] ddr_dm , inout [31:0] ddr_dq , inout [ 3:0] ddr_dqs_n , inout [ 3:0] ddr_dqs_p , inout ddr_odt , inout ddr_ras_n , inout ddr_reset_n , inout ddr_we_n , // fixed-io inout fixed_io_ddr_vrn , inout fixed_io_ddr_vrp , inout [53:0] fixed_io_mio , inout fixed_io_ps_clk , inout fixed_io_ps_porb , inout fixed_io_ps_srstb , // ************************************************************************* // ************************* Sync Signal *********************************** // ************************************************************************* output sync_signal_out , output reg sync_gnd = 1'b0 ); //////////////////////////////////////////////////////////////////////////////// /////////////////////////// System Clock Generation //////////////////////////// //////////////////////////////////////////////////////////////////////////////// // system main clock, mmcm is included in block design wire sys_clk ; // 122.88mhz wire sys_clk_2x ; // 245.76mhz wire sys_rst ; // optional siganl clock, can be changed to whatever frequency you want wire sig_clk ; // 245.76mhz wire sig_clk_ld ; wire sig_rst ; assign sig_rst = ~sig_clk_ld; sig_clk_gen u_sig_clk_gen ( // Clock out ports .clk_out1 (sig_clk ), // output clk_out1 // Status and control signals .reset (sys_rst ), // input reset .locked (sig_clk_ld ), // output locked // Clock in ports .clk_in1 (sys_clk ) // input clk_in1 ); //////////////////////////////////////////////////////////////////////////////// //////////////////////////// Block Design Interface //////////////////////////// //////////////////////////////////////////////////////////////////////////////// // gpio wire [15:0] gpio_i ; wire [15:0] gpio_o ; assign gpio_i[15:5] = gpio_o[15:5]; assign ad9528_reset_b = gpio_o[4]; // ad9528 reset pin assign ad9528_sysref_req = gpio_o[3]; // ad9528 sysref requset pin assign ad9371_test = gpio_o[2]; assign ad9371_reset_b = gpio_o[1]; assign gpio_i[0] = ad9371_gpint ; // ad9371 gpio interrupt pin // ad9371 jesd204b signals wire rx_rstn ; wire [63:0] rx_tdata ; wire rx_tvalid ; wire tx_rstn ; wire [63:0] tx_tdata ; wire tx_tready ; // spi interface wire spi_clk ; wire spi_mosi ; reg spi_miso ; assign spi_clk_ad9528 = spi_clk ; assign spi_clk_ad9371 = spi_clk ; assign spi_mosi_ad9528 = spi_mosi ; assign spi_mosi_ad9371 = spi_mosi ; always @(*) begin if (~spi_csn_ad9528) spi_miso = spi_miso_ad9528; else if (~spi_csn_ad9371) spi_miso = spi_miso_ad9371; else spi_miso = 1'bz; end system_bd_wrapper u_system_bd ( // ddr .ddr_addr (ddr_addr ), // inout [14:0]ddr_addr .ddr_ba (ddr_ba ), // inout [2:0]ddr_ba .ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n .ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n .ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p .ddr_cke (ddr_cke ), // inout ddr_cke .ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n .ddr_dm (ddr_dm ), // inout [3:0]ddr_dm .ddr_dq (ddr_dq ), // inout [31:0]ddr_dq .ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n .ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p .ddr_odt (ddr_odt ), // inout ddr_odt .ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n .ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n .ddr_we_n (ddr_we_n ), // inout ddr_we_n // fixed io .fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn .fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp .fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio .fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk .fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb .fixed_io_ps_srstb (fixed_io_ps_srstb ), // inout fixed_io_ps_srstb // gpio, for control signals .gpio_i (gpio_i[15:0] ), // input [15:0]gpio_i .gpio_o (gpio_o[15:0] ), // output [15:0]gpio_o // spi interface .spi_miso (spi_miso ), // input spi_miso .spi_mosi (spi_mosi ), // output spi_mosi .spi_sclk (spi_clk ), // output spi_sclk .spi_ss_0 (spi_csn_ad9528 ), // output spi_ss_0 .spi_ss_1 (spi_csn_ad9371 ), // output spi_ss_1 .spi_ss_2 ( ), // output spi_ss_2 // system main clock .sysclk_p (sysclk_p ), // input sysclk_p .sysclk_n (sysclk_n ), // input sysclk_n .sys_clk (sys_clk ), // output sys_clk .sys_rst (sys_rst ), // output sys_rst // jesd 204b interface .refclk_p (refclk_p ), // input refclk_p .refclk_n (refclk_n ), // input refclk_n .sysref_p (sysref_p ), // input sysref_p .sysref_n (sysref_n ), // input sysref_n .rxp_in (rx_data_p[1:0] ), // input [1:0]rxp_in .rxn_in (rx_data_n[1:0] ), // input [1:0]rxn_in .rx_sync_p (rx_sync_p ), // output rx_sync_p .rx_sync_n (rx_sync_n ), // output rx_sync_n .rx_rstn (rx_rstn ), // output rx_rstn .rx_tdata (rx_tdata[63:0] ), // output [63:0]rx_tdata .rx_tvalid (rx_tvalid ), // output rx_tvalid .txp_out (tx_data_p[1:0] ), // output [1:0]txp_out .txn_out (tx_data_n[1:0] ), // output [1:0]txn_out .tx_sync_p (tx_sync_p ), // input tx_sync_p .tx_sync_n (tx_sync_n ), // input tx_sync_n .tx_rstn (tx_rstn ), // output tx_rstn .tx_tdata (tx_tdata[63:0] ), // input [63:0]tx_tdata .tx_tready (tx_tready ) // output tx_tready ); //////////////////////////////////////////////////////////////////////////////// //////////////////////////// RF Control Interface ////////////////////////////// //////////////////////////////////////////////////////////////////////////////// wire gain_on_vio ; wire [1:0] rf_txrx_vio ; wire rf_vio_set ; wire [5:0] tx_gain_manual ; wire [5:0] rx_gain_manual ; wire [10:0] freq_hop_words_vio ; wire hop_words_valid_vio ; wire freq_hop_switch_vio ; wire freq_hop_switch_out ; wire [11:0] tx_gain; wire [11:0] rx_gain; assign tx_gain_5bit = tx_gain[5]; assign tx_gain_6bit = tx_gain[6]; assign rx_gain_5bit = rx_gain[5]; assign rx_gain_4bit = rx_gain[4]; assign rx_gain_3bit = rx_gain[3]; // rf auto switch frequency function wire auto_test_enable_vio; wire rf_auto_start_vio ; wire rf_ctrl_mode_vio ; wire switch_next_freq_vio; wire switch_last_freq_vio; wire [31:0] cnt_valid_to_switch_vio; wire [31:0] test_slot_length_vio; wire [10:0] freq_hop_words_auto ; wire hop_words_valid_auto; wire freq_hop_switch_auto; rf_auto_switch_freq u_rf_auto_switch_freq( .clk (sys_clk ), .rst (sys_rst ), // vio control .start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first .auto_test_enable (auto_test_enable_vio ), // rise-edge active .rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch .switch_next_freq (switch_next_freq_vio ), // rise-edge active .switch_last_freq (switch_last_freq_vio ), // rise-edge active .cnt_valid_to_switch (cnt_valid_to_switch_vio ), // the clock number from valid to switch .test_slot_length (test_slot_length_vio[31:0] ), // input .freq_hop_words_vio (freq_hop_words_vio[10:0] ), .hop_words_valid_vio (hop_words_valid_vio ), .freq_hop_switch_vio (freq_hop_switch_vio ), // output .freq_hop_words_auto (freq_hop_words_auto[10:0] ), .hop_words_valid_auto (hop_words_valid_auto ), .freq_hop_switch_auto (freq_hop_switch_auto ), .sync_signal (sync_signal_out ) ); rf_control u_rf_control( .clk (sys_clk ), .rst (sys_rst ), //input .gain_on_vio (gain_on_vio ), .rf_txrx_vio (rf_txrx_vio[1:0] ), .rf_txrx_net (2'd0 ), .tx_gain_manual (tx_gain_manual[5:0] ), .rx_gain_manual (rx_gain_manual[5:0] ), //0:net->control 1:vio->control .rf_vio_set (rf_vio_set ), //vio hop control .freq_hop_words_vio (freq_hop_words_auto[10:0] ), .hop_words_valid_vio (hop_words_valid_auto ), .freq_hop_switch_vio (freq_hop_switch_auto ), //tx hop control .tx_freq_hop_words (11'b0 ), .tx_hop_words_valid (1'b0 ), .tx_freq_hop_switch (1'b0 ), //rx hop control .rx_freq_hop_words (11'b0 ), .rx_hop_words_valid (1'b0 ), .rx_freq_hop_switch (1'b0 ), //output .tx_gain (tx_gain[11:0] ), .tx_gain_on (tx_gain_on ), .rx_gain (rx_gain[9:0] ), .rx_gain_on (rx_gain_on ), .freq_hop_words (freq_hop_words[10:0] ), .hop_words_valid (hop_words_valid ), .freq_hop_switch (freq_hop_switch ), .freq_hop_switch_out (freq_hop_switch_out ) ); //////////////////////////////////////////////////////////////////////////////// ///////////////////////////// Tx Baseband Signals ////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // baseband signal wire [15:0] tx_1_i; wire [15:0] tx_1_q; wire [15:0] tx_2_i; wire [15:0] tx_2_q; assign tx_tdata = { tx_2_q[7:0], tx_2_q[15:8], tx_2_i[7:0], tx_2_i[15:8], tx_1_q[7:0], tx_1_q[15:8], tx_1_i[7:0], tx_1_i[15:8] }; wire [15:0] tx_data_i; wire [15:0] tx_data_q; assign tx_1_i = tx_data_i; assign tx_1_q = tx_data_q; assign tx_2_i = tx_data_i; assign tx_2_q = tx_data_q; // <---------------------------------------------------------------------------> // <--------------------- insert transmitter logic below ----------------------> // <---------------------------------------------------------------------------> wire [ 2:0] waveform_sel; wire sweep_on ; wire [31:0] freq_set ; wire [ 1:0] iq_sel ; wire [ 3:0] bb_rshift ; tx_control u_tx_wave ( .sys_clk (sys_clk ), // input sys_clk .sys_rst (sys_rst ), // input sys_rst .sig_clk (sig_clk ), // input sig_clk .sig_rst (sig_rst ), // input sig_rst .tx_data_i (tx_data_i ), // output [15:0] tx_data_i .tx_data_q (tx_data_q ), // output [15:0] tx_data_q // debug ports .waveform_sel (waveform_sel ), // input [ 2:0] waveform_sel .sweep_on (sweep_on ), // input sweep_on .freq_set (freq_set ), // input [31:0] freq_set .iq_sel (iq_sel ), // input [ 1:0] iq_sel .bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift ); //////////////////////////////////////////////////////////////////////////////// ///////////////////////////// Rx Baseband Signals ////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // rx signal wire [15:0] rx_1_i; wire [15:0] rx_1_q; wire [15:0] rx_2_i; wire [15:0] rx_2_q; assign rx_1_i = { rx_tdata[ 7: 0] , rx_tdata[15: 8]}; assign rx_1_q = { rx_tdata[23:16] , rx_tdata[31:24]}; assign rx_2_i = { rx_tdata[39:32] , rx_tdata[47:40]}; assign rx_2_q = { rx_tdata[55:48] , rx_tdata[63:56]}; // <---------------------------------------------------------------------------> // <----------------------- insert receiver logic below -----------------------> // <---------------------------------------------------------------------------> //////////////////////////////////////////////////////////////////////////////// //////////////////////////////// ILAs and VIOs ///////////////////////////////// //////////////////////////////////////////////////////////////////////////////// ila_2x16x131072 u_ila_tx ( .clk (sys_clk ), // input wire clk .probe0 (tx_data_i ), // input wire [15:0] probe0 .probe1 (tx_data_q ) // input wire [15:0] probe1 ); ila_4x16x131072 u_ila_rx ( .clk (sys_clk ), // input wire clk .probe0 (rx_1_i ), // input wire [15:0] probe0 .probe1 (rx_1_q ), // input wire [15:0] probe1 .probe2 (rx_2_i ), // input wire [15:0] probe2 .probe3 (rx_2_q ) // input wire [15:0] probe3 ); ila_ctrl_signal u_ila_ctrl_signal ( .clk (sys_clk ), // input wire clk .probe0 (u_system_bd.system_bd_i.jesd204b.jesd_reset ), // input wire [0:0] probe0 .probe1 (u_system_bd.system_bd_i.jesd204b.rx_sync ), // input wire [0:0] probe1 .probe2 (rx_rstn ), // input wire [0:0] probe2 .probe3 (u_system_bd.system_bd_i.jesd204b.tx_sync ), // input wire [0:0] probe3 .probe4 (tx_rstn ), // input wire [0:0] probe4 .probe5 (u_system_bd.system_bd_i.jesd204b.sysref ) // input wire [0:0] probe5 ); vio_manual_ctrl u_vio_manual_ctrl ( .clk (sys_clk ), // input wire clk .probe_out0 (waveform_sel ), // output wire [2 : 0] probe_out0 .probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1 .probe_out2 (freq_set ), // output wire [31 : 0] probe_out2 .probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3 .probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4 ); vio_rf_control u_vio_rf_control ( .clk (sys_clk ), // input wire clk .probe_out0 (gain_on_vio ), // output wire [0 : 0] probe_out0 .probe_out1 (rf_txrx_vio[1:0] ), // output wire [1 : 0] probe_out1 .probe_out2 (rf_vio_set ), // output wire [0 : 0] probe_out2 .probe_out3 (tx_gain_manual[5:0] ), // output wire [5 : 0] probe_out3 .probe_out4 (rx_gain_manual[5:0] ), // output wire [5 : 0] probe_out4 .probe_out5 (freq_hop_words_vio[10:0] ), // output wire [10 : 0] probe_out5 .probe_out6 (hop_words_valid_vio ), // output wire [0 : 0] probe_out6 .probe_out7 (freq_hop_switch_vio ), // output wire [0 : 0] probe_out7 .probe_out8 (self_check_dout ), // output wire [0 : 0] probe_out8 .probe_out9 (rf_auto_start_vio ), // output wire [0 : 0] probe_out9 .probe_out10 (rf_ctrl_mode_vio ), // output wire [0 : 0] probe_out10 .probe_out11 (switch_next_freq_vio ), // output wire [0 : 0] probe_out11 .probe_out12 (switch_last_freq_vio ), // output wire [0 : 0] probe_out12 .probe_out13 (cnt_valid_to_switch_vio[31:0] ), // output wire [31: 0] probe_out13 .probe_out14 (auto_test_enable_vio ), // output wire [0 : 0] probe_out14 .probe_out15 (test_slot_length_vio[31:0] ), // output wire [31: 0] probe_out15 .probe_in0 (freq_hop_words_auto[10:0] ) // input wire [10: 0] probe_in0 ); endmodule