analog.com user spi_engine_offload 1.0 spi_engine_ctrl CMD_READY cmd_ready CMD_VALID cmd_valid CMD_DATA cmd SDO_READY sdo_data_ready SDO_VALID sdo_data_valid SDO_DATA sdo_data SDI_READY sdi_data_ready SDI_VALID sdi_data_valid SDI_DATA sdi_data SYNC_READY sync_ready SYNC_VALID sync_valid SYNC_DATA sync_data spi_engine_offload_ctrl CMD_WR_EN ctrl_cmd_wr_en CMD_WR_DATA ctrl_cmd_wr_data SDO_WR_EN ctrl_sdo_wr_en SDO_WR_DATA ctrl_sdo_wr_data ENABLE ctrl_enable ENABLED ctrl_enabled MEM_RESET ctrl_mem_reset SYNC_READY status_sync_ready SYNC_VALID status_sync_valid SYNC_DATA status_sync_data offload_sdi TVALID offload_sdi_valid TREADY offload_sdi_ready TDATA offload_sdi_data spi_engine_ctrl_offload_sdi_signal_clock spi_engine_ctrl_offload_sdi_signal_clock CLK spi_clk ASSOCIATED_BUSIF spi_engine_ctrl:offload_sdi ASSOCIATED_RESET spi_resetn spi_engine_ctrl_offload_sdi_signal_reset spi_engine_ctrl_offload_sdi_signal_reset RST spi_resetn POLARITY ACTIVE_LOW spi_engine_offload_ctrl_signal_clock spi_engine_offload_ctrl_signal_clock CLK ctrl_clk ASSOCIATED_BUSIF spi_engine_offload_ctrl xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog spi_engine_offload xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum b415a00b xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog spi_engine_offload xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum b415a00b xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum 9caa5391 ctrl_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_cmd_wr_en in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ctrl_cmd_wr_data in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ctrl_sdo_wr_en in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ctrl_sdo_wr_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ctrl_enable in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_enabled out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ctrl_mem_reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_sync_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation status_sync_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 status_sync_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation spi_resetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation cmd out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_data_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdo_data_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdo_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdi_data_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sdi_data_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sdi_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 sync_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation sync_data in 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 offload_sdi_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation offload_sdi_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation offload_sdi_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ASYNC_SPI_CLK Async Spi Clk false ASYNC_TRIG Async Trig false CMD_MEM_ADDRESS_WIDTH Cmd Mem Address Width 4 SDO_MEM_ADDRESS_WIDTH Sdo Mem Address Width 4 DATA_WIDTH Data Width 8 NUM_OF_SDI Num Of Sdi 1 xilinx_anylanguagesynthesis_view_fileset spi_engine_offload_constr.ttcl ttcl spi_engine_offload.v verilogSource CHECKSUM_b415a00b xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset spi_engine_offload.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/spi_engine_offload_v1_0.tcl tclSource CHECKSUM_1ce3c7e4 XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset spi_engine_offload_v1_0 ASYNC_SPI_CLK Asynchronous core clock false ASYNC_TRIG Asynchronous trigger false CMD_MEM_ADDRESS_WIDTH Command FIFO address width 4 SDO_MEM_ADDRESS_WIDTH MOSI FIFO address width 4 DATA_WIDTH Shift register's data width 8 NUM_OF_SDI Number of MISO lines 1 Component_Name spi_engine_offload_v1_0 virtex7 aartix7 akintex7 artix7 artix7l aspartan7 azynq azynquplus kintex7 kintex7l kintexu kintexuplus qartix7 qkintex7 qkintex7l qkintexu qkintexuplus qrkintexu qvirtex7 qvirtexuplus qzynq qzynquplus qzynquplusRFSOC spartan7 virtexu virtexuplus virtexuplus58g virtexuplusHBM zynq zynquplus zynquplusRFSOC /Analog_Devices spi_engine_offload_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:08:04Z 2019.1.3