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xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_adcfifo xilinx_anylanguagesynthesis_view_fileset viewChecksum ed53a4ab xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_adcfifo xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 0ae38148 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 9aae2ee9 adc_rst in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_wr in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_wdata in 127 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_wovf out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_wr out std_logic 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Enable 1 AXI_SIZE Axi Size 2 AXI_LENGTH Axi Length 16 AXI_ADDRESS Axi Address 0x00000000 AXI_ADDRESS_LIMIT Axi Address Limit 0xFFFFFFFF choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset axi_adcfifo_constr.xdc xdc ../../common/ad_axis_inf_rx.v verilogSource ../../common/ad_mem.v verilogSource ../../common/ad_mem_asym.v verilogSource axi_adcfifo_adc.v verilogSource axi_adcfifo_dma.v verilogSource axi_adcfifo_rd.v verilogSource axi_adcfifo_wr.v verilogSource ../../common/up_xfer_status.v verilogSource axi_adcfifo.v verilogSource CHECKSUM_3b0cd2a4 xilinx_anylanguagebehavioralsimulation_view_fileset ../../common/ad_axis_inf_rx.v verilogSource ../../common/ad_mem.v verilogSource ../../common/ad_mem_asym.v verilogSource axi_adcfifo_adc.v verilogSource axi_adcfifo_dma.v verilogSource axi_adcfifo_rd.v verilogSource axi_adcfifo_wr.v verilogSource ../../common/up_xfer_status.v verilogSource axi_adcfifo.v verilogSource xilinx_xpgui_view_fileset xgui/axi_adcfifo_v1_0.tcl tclSource CHECKSUM_9aae2ee9 XGUI_VERSION_2 axi_adcfifo_v1_0 ADC_DATA_WIDTH Adc Data Width 128 DMA_DATA_WIDTH Dma Data Width 64 AXI_DATA_WIDTH Axi Data Width 512 DMA_READY_ENABLE Dma Ready Enable 1 AXI_SIZE Axi Size 2 AXI_LENGTH Axi Length 16 AXI_ADDRESS Axi Address 0x00000000 AXI_ADDRESS_LIMIT Axi Address Limit 0xFFFFFFFF Component_Name axi_adcfifo_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_adcfifo_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:20:07Z 2019.1.3