analog.com user axi_adc_trigger 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW clk CLK clk ASSOCIATED_RESET reset reset RST reset s_axi axi_lite 0 128 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_adc_trigger xilinx_anylanguagesynthesis_view_fileset viewChecksum 7e5a5e09 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_adc_trigger xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 23b3ccdb xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 8991825b clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger_i in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger_o out 1 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger_t out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_a in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_b in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_valid_a in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_valid_b in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_a_trig out 15 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_b_trig out 15 0 reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_valid_a_trig out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation data_valid_b_trig out reg xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger_out out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger_out_la out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation fifo_depth out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 6 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 6 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 SIGN_BITS Sign Bits 2 OUT_PIN_HOLD_N Out Pin Hold N 100000 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset ../xilinx/common/up_xfer_cntrl_constr.xdc xdc axi_adc_trigger_constr.xdc xdc axi_adc_trigger_reg.v verilogSource ../common/up_axi.v verilogSource ../common/up_xfer_cntrl.v verilogSource axi_adc_trigger.v verilogSource CHECKSUM_07c0bc03 xilinx_anylanguagebehavioralsimulation_view_fileset axi_adc_trigger_reg.v verilogSource ../common/up_axi.v verilogSource ../common/up_xfer_cntrl.v verilogSource axi_adc_trigger.v verilogSource xilinx_xpgui_view_fileset xgui/axi_adc_trigger_v1_0.tcl tclSource CHECKSUM_8991825b XGUI_VERSION_2 axi_adc_trigger_v1_0 SIGN_BITS Sign Bits 2 OUT_PIN_HOLD_N Out Pin Hold N 100000 Component_Name axi_adc_trigger_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_adc_trigger_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:13:04Z 2019.1.3