analog.com user util_axis_fifo 1.0 s_axis TVALID s_axis_valid TREADY s_axis_ready TDATA s_axis_data m_axis TVALID m_axis_valid TREADY m_axis_ready TDATA m_axis_data m_axis_signal_clock m_axis_signal_clock CLK m_axis_aclk ASSOCIATED_BUSIF m_axis ASSOCIATED_RESET m_axis_aresetn m_axis_signal_reset m_axis_signal_reset RST m_axis_aresetn POLARITY ACTIVE_LOW s_axis_signal_clock s_axis_signal_clock CLK s_axis_aclk ASSOCIATED_BUSIF s_axis ASSOCIATED_RESET m_axis_aresetn s_axis_signal_reset s_axis_signal_reset RST m_axis_aresetn POLARITY ACTIVE_LOW xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_axis_fifo xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagesynthesis_view_fileset viewChecksum 06baaa8c xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_axis_fifo xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 06baaa8c xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset viewChecksum 13c68e4c m_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_data out 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation m_axis_level out 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_ready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_valid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_data in 63 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axis_empty out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axis_room out 4 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation DATA_WIDTH Data Width 64 ASYNC_CLK Async Clk 1 ADDRESS_WIDTH Address Width 4 S_AXIS_REGISTERED S Axis Registered 1 xilinx_anylanguagesynthesis_view_fileset ../common/ad_mem.v verilogSource address_gray_pipelined.v verilogSource address_sync.v verilogSource util_axis_fifo.v verilogSource CHECKSUM_2ed7e789 xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_mem.v verilogSource address_gray_pipelined.v verilogSource address_sync.v verilogSource util_axis_fifo.v verilogSource xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset xilinx_xpgui_view_fileset xgui/util_axis_fifo_v1_0.tcl tclSource CHECKSUM_13c68e4c XGUI_VERSION_2 xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset util_axis_fifo_v1_0 DATA_WIDTH Data Width 64 ASYNC_CLK Async Clk 1 ADDRESS_WIDTH Address Width 4 S_AXIS_REGISTERED S Axis Registered 1 Component_Name util_axis_fifo_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices util_axis_fifo_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-08T02:22:35Z 2019.1.3