analog.com
user
axi_ad9144
1.0
s_axi
AWADDR
s_axi_awaddr
AWPROT
s_axi_awprot
AWVALID
s_axi_awvalid
AWREADY
s_axi_awready
WDATA
s_axi_wdata
WSTRB
s_axi_wstrb
WVALID
s_axi_wvalid
WREADY
s_axi_wready
BRESP
s_axi_bresp
BVALID
s_axi_bvalid
BREADY
s_axi_bready
ARADDR
s_axi_araddr
ARPROT
s_axi_arprot
ARVALID
s_axi_arvalid
ARREADY
s_axi_arready
RDATA
s_axi_rdata
RRESP
s_axi_rresp
RVALID
s_axi_rvalid
RREADY
s_axi_rready
s_axi_aclk
CLK
s_axi_aclk
ASSOCIATED_BUSIF
s_axi
ASSOCIATED_RESET
s_axi_aresetn
s_axi_aresetn
RST
s_axi_aresetn
POLARITY
ACTIVE_LOW
tx_clk
CLK
tx_clk
s_axi
axi_lite
0
4096
0
xilinx_anylanguagesynthesis
Synthesis
:vivado.xilinx.com:synthesis
Verilog
axi_ad9144
xilinx_anylanguagesynthesis_analog_com_user_ad_ip_jesd204_tpl_dac_1_0__ref_view_fileset
xilinx_anylanguagesynthesis_view_fileset
viewChecksum
61b7e1e3
xilinx_anylanguagebehavioralsimulation
Simulation
:vivado.xilinx.com:simulation
Verilog
axi_ad9144
xilinx_anylanguagebehavioralsimulation_analog_com_user_ad_ip_jesd204_tpl_dac_1_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_view_fileset
viewChecksum
61b7e1e3
xilinx_xpgui
UI Layout
:vivado.xilinx.com:xgui.ui
xilinx_xpgui_analog_com_user_ad_ip_jesd204_tpl_dac_1_0__ref_view_fileset
xilinx_xpgui_view_fileset
viewChecksum
52ec81f7
xilinx_blockdiagram
Block Diagram
:vivado.xilinx.com:block.diagram
xilinx_blockdiagram_analog_com_user_ad_ip_jesd204_tpl_dac_1_0__ref_view_fileset
xilinx_blockdiagram_view_fileset
tx_clk
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
tx_valid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
tx_data
out
255
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
tx_ready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
dac_clk
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dac_valid_0
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dac_enable_0
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dac_ddata_0
in
63
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dac_valid_1
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dac_enable_1
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dac_ddata_1
in
63
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
dac_valid_2
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
true
dac_enable_2
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
true
dac_ddata_2
in
63
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
true
dac_valid_3
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
true
dac_enable_3
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
true
dac_ddata_3
in
63
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
true
dac_dunf
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_aclk
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_aresetn
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_awvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_awaddr
in
11
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_awprot
in
2
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_awready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_wvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_wdata
in
31
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_wstrb
in
3
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
1
s_axi_wready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_bvalid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_bresp
out
1
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_bready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_arvalid
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_araddr
in
11
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_arprot
in
2
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
s_axi_arready
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_rvalid
out
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_rdata
out
31
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_rresp
out
1
0
std_logic_vector
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
s_axi_rready
in
std_logic
xilinx_anylanguagesynthesis
xilinx_anylanguagebehavioralsimulation
0
ID
Id
0
FPGA_TECHNOLOGY
Fpga Technology
0
FPGA_FAMILY
Fpga Family
0
SPEED_GRADE
Speed Grade
0
DEV_PACKAGE
Dev Package
0
QUAD_OR_DUAL_N
Quad Or Dual N
1
DAC_DDS_TYPE
Dac Dds Type
1
DAC_DDS_CORDIC_DW
Dac Dds Cordic Dw
20
DAC_DDS_CORDIC_PHASE_DW
Dac Dds Cordic Phase Dw
18
DAC_DATAPATH_DISABLE
Dac Datapath Disable
0
choice_list_74b5137e
ACTIVE_HIGH
ACTIVE_LOW
choice_pairs_38e7dd38
0
1
2
3
4
choice_pairs_68effc1b
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
choice_pairs_a535243b
0
10
11
12
13
14
20
21
22
30
choice_pairs_aee923ef
0
1
2
3
xilinx_anylanguagesynthesis_view_fileset
axi_ad9144.v
verilogSource
CHECKSUM_61b7e1e3
xilinx_anylanguagesynthesis_analog_com_user_ad_ip_jesd204_tpl_dac_1_0__ref_view_fileset
xilinx_anylanguagebehavioralsimulation_view_fileset
axi_ad9144.v
verilogSource
xilinx_anylanguagebehavioralsimulation_analog_com_user_ad_ip_jesd204_tpl_dac_1_0__ref_view_fileset
xilinx_xpgui_view_fileset
xgui/axi_ad9144_v1_0.tcl
tclSource
CHECKSUM_3f220d97
XGUI_VERSION_2
xilinx_xpgui_analog_com_user_ad_ip_jesd204_tpl_dac_1_0__ref_view_fileset
xilinx_blockdiagram_view_fileset
bd/bd.tcl
tclSource
xilinx_blockdiagram_analog_com_user_ad_ip_jesd204_tpl_dac_1_0__ref_view_fileset
axi_ad9144_v1_0
ID
Id
0
FPGA_TECHNOLOGY
Fpga Technology
0
FPGA_FAMILY
Fpga Family
0
SPEED_GRADE
Speed Grade
0
DEV_PACKAGE
Dev Package
0
QUAD_OR_DUAL_N
Quad Or Dual N
1
DAC_DDS_TYPE
Dac Dds Type
1
DAC_DDS_CORDIC_DW
Dac Dds Cordic Dw
20
DAC_DDS_CORDIC_PHASE_DW
Dac Dds Cordic Phase Dw
18
DAC_DATAPATH_DISABLE
Dac Datapath Disable
0
Component_Name
axi_ad9144_v1_0
virtex7
qvirtex7
kintex7
kintex7l
qkintex7
qkintex7l
akintex7
artix7
artix7l
aartix7
qartix7
zynq
qzynq
azynq
spartan7
aspartan7
virtexu
zynquplus
virtexuplus
virtexuplusHBM
virtexuplus58g
kintexuplus
kintexu
azynquplus
qkintexu
qkintexuplus
qrkintexu
qvirtexuplus
qzynquplus
qzynquplusRFSOC
zynquplusRFSOC
/Analog_Devices
axi_ad9144_v1_0
package_project
Analog Devices
http://www.analog.com
1
2021-12-09T07:09:04Z
2019.1.3