analog.com user axi_ad9684 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW adc_clk_in_p CLK adc_clk_in_p ASSOCIATED_RESET adc_rst adc_clk_in_n CLK adc_clk_in_n delay_clk CLK delay_clk adc_clk CLK adc_clk adc_rst RST adc_rst s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_ad9684 xilinx_anylanguagesynthesis_view_fileset viewChecksum 92ee39fe xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_ad9684 xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 8392cc79 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 8c2384ff xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_view_fileset adc_clk_in_p in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_clk_in_n in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_in_p in 13 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 adc_data_in_n in 13 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 adc_data_or_p in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 adc_data_or_n in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 adc_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_rst out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_valid_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_0 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_valid_1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_1 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_1 out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_dovf in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 delay_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 IO_DELAY_GROUP Io Delay Group dev_if_delay_group OR_STATUS Or Status 1 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_38e7dd38 0 1 2 3 4 choice_pairs_68effc1b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 choice_pairs_a535243b 0 10 11 12 13 14 20 21 22 30 choice_pairs_aee923ef 0 1 2 3 xilinx_anylanguagesynthesis_view_fileset ../xilinx/common/up_xfer_cntrl_constr.xdc xdc ../xilinx/common/ad_rst_constr.xdc xdc ../xilinx/common/up_xfer_status_constr.xdc xdc ../xilinx/common/up_clock_mon_constr.xdc xdc axi_ad9684_constr.xdc xdc ../common/ad_datafmt.v verilogSource ../xilinx/common/ad_mmcm_drp.v verilogSource ../common/ad_pnmon.v verilogSource ../common/ad_rst.v verilogSource ../xilinx/common/ad_serdes_clk.v verilogSource ../xilinx/common/ad_serdes_in.v verilogSource axi_ad9684_channel.v verilogSource axi_ad9684_if.v verilogSource axi_ad9684_pnmon.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_delay_cntrl.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_ad9684.v verilogSource CHECKSUM_2e91d160 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_datafmt.v verilogSource ../xilinx/common/ad_mmcm_drp.v verilogSource ../common/ad_pnmon.v verilogSource ../common/ad_rst.v verilogSource ../xilinx/common/ad_serdes_clk.v verilogSource ../xilinx/common/ad_serdes_in.v verilogSource axi_ad9684_channel.v verilogSource axi_ad9684_if.v verilogSource axi_ad9684_pnmon.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_delay_cntrl.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_ad9684.v verilogSource xilinx_xpgui_view_fileset xgui/axi_ad9684_v1_0.tcl tclSource CHECKSUM_24eac1f4 XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource axi_ad9684_v1_0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 IO_DELAY_GROUP Io Delay Group dev_if_delay_group OR_STATUS Or Status 1 Component_Name axi_ad9684_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_ad9684_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:11:52Z 2019.1.3