analog.com user axi_ad9963 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW trx_clk CLK trx_clk tx_clk CLK tx_clk delay_clk CLK delay_clk adc_clk CLK adc_clk ASSOCIATED_RESET adc_rst adc_rst RST adc_rst dac_clk CLK dac_clk ASSOCIATED_RESET dac_rst dac_rst RST dac_rst s_axi axi_lite 0 65536 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_ad9963 xilinx_anylanguagesynthesis_view_fileset viewChecksum e893479a xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_ad9963 xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 96f2876e xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum cdeb984c xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_view_fileset trx_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trx_iq in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trx_data in 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 tx_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx_iq out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation tx_data out 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_sync_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_sync_out out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation delay_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 false adc_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_clk out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_rst out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_rst out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_i out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_valid_i out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_i out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_enable_q out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_valid_q out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_data_q out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation adc_dovf in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_enable_i out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_valid_i out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_data_i in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dma_valid_i in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_enable_q out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_valid_q out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_data_q in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dma_valid_q in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_dunf in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 hold_last_sample in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 ADC_IODELAY_ENABLE Adc Iodelay Enable 0 IO_DELAY_GROUP Io Delay Group dev_if_delay_group IODELAY_ENABLE Iodelay Enable 0 DAC_DDS_TYPE Dac Dds Type 1 DAC_DDS_CORDIC_DW Dac Dds Cordic Dw 14 DAC_DDS_CORDIC_PHASE_DW Dac Dds Cordic Phase Dw 13 DAC_DATAPATH_DISABLE Dac Datapath Disable 0 ADC_USERPORTS_DISABLE Adc Userports Disable 0 ADC_DATAFORMAT_DISABLE Adc Dataformat Disable 0 ADC_DCFILTER_DISABLE Adc Dcfilter Disable 0 ADC_IQCORRECTION_DISABLE Adc Iqcorrection Disable 0 ADC_SCALECORRECTION_ONLY Adc Scalecorrection Only 1 DELAY_REFCLK_FREQUENCY Delay Refclk Frequency 200 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_38e7dd38 0 1 2 3 4 choice_pairs_68effc1b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 choice_pairs_a535243b 0 10 11 12 13 14 20 21 22 30 choice_pairs_aee923ef 0 1 2 3 xilinx_anylanguagesynthesis_view_fileset ../xilinx/common/up_xfer_cntrl_constr.xdc xdc ../xilinx/common/ad_rst_constr.xdc xdc ../xilinx/common/up_xfer_status_constr.xdc xdc ../xilinx/common/up_clock_mon_constr.xdc xdc axi_ad9963_constr.xdc xdc ../xilinx/common/ad_data_in.v verilogSource ../common/ad_datafmt.v verilogSource ../xilinx/common/ad_dcfilter.v verilogSource ../common/ad_dds.v verilogSource ../common/ad_dds_1.v verilogSource ../common/ad_dds_2.v verilogSource ../common/ad_dds_cordic_pipe.v verilogSource ../common/ad_dds_sine.v verilogSource ../common/ad_dds_sine_cordic.v verilogSource ../common/ad_iqcor.v verilogSource ../xilinx/common/ad_mul.v verilogSource ../common/ad_pnmon.v verilogSource ../common/ad_rst.v verilogSource axi_ad9963_if.v verilogSource axi_ad9963_rx.v verilogSource axi_ad9963_rx_channel.v verilogSource axi_ad9963_rx_pnmon.v verilogSource axi_ad9963_tx.v verilogSource axi_ad9963_tx_channel.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_dac_channel.v verilogSource ../common/up_dac_common.v verilogSource ../common/up_delay_cntrl.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_ad9963.v verilogSource CHECKSUM_b40edb41 xilinx_anylanguagebehavioralsimulation_view_fileset ../xilinx/common/ad_data_in.v verilogSource ../common/ad_datafmt.v verilogSource ../xilinx/common/ad_dcfilter.v verilogSource ../common/ad_dds.v verilogSource ../common/ad_dds_1.v verilogSource ../common/ad_dds_2.v verilogSource ../common/ad_dds_cordic_pipe.v verilogSource ../common/ad_dds_sine.v verilogSource ../common/ad_dds_sine_cordic.v verilogSource ../common/ad_iqcor.v verilogSource ../xilinx/common/ad_mul.v verilogSource ../common/ad_pnmon.v verilogSource ../common/ad_rst.v verilogSource axi_ad9963_if.v verilogSource axi_ad9963_rx.v verilogSource axi_ad9963_rx_channel.v verilogSource axi_ad9963_rx_pnmon.v verilogSource axi_ad9963_tx.v verilogSource axi_ad9963_tx_channel.v verilogSource ../common/up_adc_channel.v verilogSource ../common/up_adc_common.v verilogSource ../common/up_axi.v verilogSource ../common/up_clock_mon.v verilogSource ../common/up_dac_channel.v verilogSource ../common/up_dac_common.v verilogSource ../common/up_delay_cntrl.v verilogSource ../common/up_xfer_cntrl.v verilogSource ../common/up_xfer_status.v verilogSource axi_ad9963.v verilogSource xilinx_xpgui_view_fileset xgui/axi_ad9963_v1_0.tcl tclSource CHECKSUM_dc697a44 XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource axi_ad9963_v1_0 ID Id 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 ADC_IODELAY_ENABLE Adc Iodelay Enable 0 IO_DELAY_GROUP Io Delay Group dev_if_delay_group IODELAY_ENABLE Iodelay Enable 0 DAC_DDS_TYPE Dac Dds Type 1 DAC_DDS_CORDIC_DW Dac Dds Cordic Dw 14 DAC_DDS_CORDIC_PHASE_DW Dac Dds Cordic Phase Dw 13 DAC_DATAPATH_DISABLE Dac Datapath Disable 0 ADC_USERPORTS_DISABLE Adc Userports Disable 0 ADC_DATAFORMAT_DISABLE Adc Dataformat Disable 0 ADC_DCFILTER_DISABLE Adc Dcfilter Disable 0 ADC_IQCORRECTION_DISABLE Adc Iqcorrection Disable 0 ADC_SCALECORRECTION_ONLY Adc Scalecorrection Only 1 DELAY_REFCLK_FREQUENCY Delay Refclk Frequency 200 Component_Name axi_ad9963_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_ad9963_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:12:35Z 2019.1.3