analog.com user axi_dac_interpolate 1.0 s_axi AWADDR s_axi_awaddr AWPROT s_axi_awprot AWVALID s_axi_awvalid AWREADY s_axi_awready WDATA s_axi_wdata WSTRB s_axi_wstrb WVALID s_axi_wvalid WREADY s_axi_wready BRESP s_axi_bresp BVALID s_axi_bvalid BREADY s_axi_bready ARADDR s_axi_araddr ARPROT s_axi_arprot ARVALID s_axi_arvalid ARREADY s_axi_arready RDATA s_axi_rdata RRESP s_axi_rresp RVALID s_axi_rvalid RREADY s_axi_rready s_axi_aclk CLK s_axi_aclk ASSOCIATED_BUSIF s_axi ASSOCIATED_RESET s_axi_aresetn s_axi_aresetn RST s_axi_aresetn POLARITY ACTIVE_LOW dac_clk CLK dac_clk ASSOCIATED_RESET dac_rst dac_rst RST dac_rst s_axi axi_lite 0 128 0 xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog axi_dac_interpolate xilinx_anylanguagesynthesis_view_fileset viewChecksum 056983d7 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_dac_interpolate xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum bfe85dc3 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 18feff19 dac_clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_rst in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_data_a in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_data_b in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 dac_valid_a in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_valid_b in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_valid_a in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_valid_b in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_ready_a out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dma_ready_b out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_enable_a in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_enable_b in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_int_data_a out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_int_data_b out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_valid_out_a out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dac_valid_out_b out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation hold_last_sample out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation underflow out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger_i in 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger_adc in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation trigger_la in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aclk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_aresetn in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_awvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awaddr in 6 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_awready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_wvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wdata in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_wstrb in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 1 s_axi_wready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_bready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arvalid in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_araddr in 6 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arprot in 2 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s_axi_arready out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rvalid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rdata out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rresp out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s_axi_rready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 CORRECTION_DISABLE Correction Disable 1 choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset ../xilinx/common/up_xfer_cntrl_constr.xdc xdc axi_dac_interpolate_constr.xdc xdc ../common/ad_iqcor.v verilogSource ../xilinx/common/ad_mul.v verilogSource axi_dac_interpolate_filter.v verilogSource axi_dac_interpolate_reg.v verilogSource cic_interp.v verilogSource fir_interp.v verilogSource ../common/up_axi.v verilogSource ../common/up_xfer_cntrl.v verilogSource axi_dac_interpolate.v verilogSource CHECKSUM_c5d82d69 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/ad_iqcor.v verilogSource ../xilinx/common/ad_mul.v verilogSource axi_dac_interpolate_filter.v verilogSource axi_dac_interpolate_reg.v verilogSource cic_interp.v verilogSource fir_interp.v verilogSource ../common/up_axi.v verilogSource ../common/up_xfer_cntrl.v verilogSource axi_dac_interpolate.v verilogSource xilinx_xpgui_view_fileset xgui/axi_dac_interpolate_v1_0.tcl tclSource CHECKSUM_18feff19 XGUI_VERSION_2 axi_dac_interpolate_v1_0 CORRECTION_DISABLE Correction Disable 1 Component_Name axi_dac_interpolate_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices axi_dac_interpolate_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:14:13Z 2019.1.3