`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/05/16 02:00:43
// Design Name: 
// Module Name: phase_compensate
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module phase_compensate(
    input               clk                     , 
    input               rst                     ,
    input       [11:0]  vio_sin_0               ,
    input       [11:0]  vio_sin_1               ,
    input       [11:0]  vio_sin_2               ,
    input       [11:0]  vio_sin_3               ,
    input       [11:0]  vio_cos_0               ,
    input       [11:0]  vio_cos_1               ,
    input       [11:0]  vio_cos_2               ,
    input       [11:0]  vio_cos_3               ,
    input       [11:0]  din_i_0                 ,
    input       [11:0]  din_i_1                 ,
    input       [11:0]  din_i_2                 ,
    input       [11:0]  din_i_3                 ,
    input       [11:0]  din_q_0                 ,
    input       [11:0]  din_q_1                 ,
    input       [11:0]  din_q_2                 ,
    input       [11:0]  din_q_3                 ,
    input       [4:0]   vio_trunc               ,
    
    output      [15:0]  dout_i                  ,
    output      [15:0]  dout_q                  ,
    output              trunc_overflow
);
    
    wire [63:0] dout_comp_0;
    wire [63:0] dout_comp_1;
    wire [63:0] dout_comp_2;
    wire [63:0] dout_comp_3;
    cmpy_12_12 cmpy_12_12_0 (
    .aclk(clk),                              // input wire aclk
    .s_axis_a_tvalid(1'd1),        // input wire s_axis_a_tvalid
    .s_axis_a_tdata({{4{vio_sin_0[11]}},vio_sin_0[11:0],{4{vio_cos_0[11]}},vio_cos_0[11:0]}),          // input wire [31 : 0] s_axis_a_tdata
    .s_axis_b_tvalid(1'd1),        // input wire s_axis_b_tvalid
    .s_axis_b_tdata({{4{din_q_0[11]}},din_q_0[11:0],{4{din_i_0[11]}},din_i_0[11:0]}),          // input wire [31 : 0] s_axis_b_tdata
    .m_axis_dout_tvalid(),  // output wire m_axis_dout_tvalid
    .m_axis_dout_tdata(dout_comp_0)    // output wire [63 : 0] m_axis_dout_tdata
    );
    
    cmpy_12_12 cmpy_12_12_1 (
    .aclk(clk),                              // input wire aclk
    .s_axis_a_tvalid(1'd1),        // input wire s_axis_a_tvalid
    .s_axis_a_tdata({{4{vio_sin_1[11]}},vio_sin_1[11:0],{4{vio_cos_1[11]}},vio_cos_1[11:0]}),          // input wire [31 : 0] s_axis_a_tdata
    .s_axis_b_tvalid(1'd1),        // input wire s_axis_b_tvalid
    .s_axis_b_tdata({{4{din_q_1[11]}},din_q_1[11:0],{4{din_i_1[11]}},din_i_1[11:0]}),          // input wire [31 : 0] s_axis_b_tdata
    .m_axis_dout_tvalid(),  // output wire m_axis_dout_tvalid
    .m_axis_dout_tdata(dout_comp_1)    // output wire [63 : 0] m_axis_dout_tdata
    );
    
    cmpy_12_12 cmpy_12_12_2 (
    .aclk(clk),                              // input wire aclk
    .s_axis_a_tvalid(1'd1),        // input wire s_axis_a_tvalid
    .s_axis_a_tdata({{4{vio_sin_2[11]}},vio_sin_2[11:0],{4{vio_cos_2[11]}},vio_cos_2[11:0]}),          // input wire [31 : 0] s_axis_a_tdata
    .s_axis_b_tvalid(1'd1),        // input wire s_axis_b_tvalid
    .s_axis_b_tdata({{4{din_q_2[11]}},din_q_2[11:0],{4{din_i_2[11]}},din_i_2[11:0]}),          // input wire [31 : 0] s_axis_b_tdata
    .m_axis_dout_tvalid(),  // output wire m_axis_dout_tvalid
    .m_axis_dout_tdata(dout_comp_2)    // output wire [63 : 0] m_axis_dout_tdata
    );
    
    cmpy_12_12 cmpy_12_12_3 (
    .aclk(clk),                              // input wire aclk
    .s_axis_a_tvalid(1'd1),        // input wire s_axis_a_tvalid
    .s_axis_a_tdata({{4{vio_sin_3[11]}},vio_sin_3[11:0],{4{vio_cos_3[11]}},vio_cos_3[11:0]}),          // input wire [31 : 0] s_axis_a_tdata
    .s_axis_b_tvalid(1'd1),        // input wire s_axis_b_tvalid
    .s_axis_b_tdata({{4{din_q_3[11]}},din_q_3[11:0],{4{din_i_3[11]}},din_i_3[11:0]}),          // input wire [31 : 0] s_axis_b_tdata
    .m_axis_dout_tvalid(),  // output wire m_axis_dout_tvalid
    .m_axis_dout_tdata(dout_comp_3)    // output wire [63 : 0] m_axis_dout_tdata
    );
    wire [11:0] dout_trunc_0i, dout_trunc_0q;
    wire [11:0] dout_trunc_1i, dout_trunc_1q;
    wire [11:0] dout_trunc_2i, dout_trunc_2q;
    wire [11:0] dout_trunc_3i, dout_trunc_3q;
    wire [11:0] trunc_overflow_0i, trunc_overflow_0q;
    wire [11:0] trunc_overflow_1i, trunc_overflow_1q;
    wire [11:0] trunc_overflow_2i, trunc_overflow_2q;
    wire [11:0] trunc_overflow_3i, trunc_overflow_3q;
    trunc_32bit_to_12bit trunc_32bit_to_12bit_0i(
    .clk(clk),
    .rst(rst),
    .trunc_32bit_in({{7{dout_comp_0[24]}},dout_comp_0[24:0]}),
    .vio_trunc(vio_trunc),
    
    .trunc_12bit_out(dout_trunc_0i),
    .trunc_overflow(trunc_overflow_0i)
    );
    
    trunc_32bit_to_12bit trunc_32bit_to_12bit_0q(
    .clk(clk),
    .rst(rst),
    .trunc_32bit_in({{7{dout_comp_0[56]}},dout_comp_0[56:32]}),
    .vio_trunc(vio_trunc),
    
    .trunc_12bit_out(dout_trunc_0q),
    .trunc_overflow(trunc_overflow_0q)
    );
    
    trunc_32bit_to_12bit trunc_32bit_to_12bit_1i(
    .clk(clk),
    .rst(rst),
    .trunc_32bit_in({{7{dout_comp_1[24]}},dout_comp_1[24:0]}),
    .vio_trunc(vio_trunc),
    
    .trunc_12bit_out(dout_trunc_1i),
    .trunc_overflow(trunc_overflow_1i)
    );
    
    trunc_32bit_to_12bit trunc_32bit_to_12bit_1q(
    .clk(clk),
    .rst(rst),
    .trunc_32bit_in({{7{dout_comp_1[56]}},dout_comp_1[56:32]}),
    .vio_trunc(vio_trunc),
    
    .trunc_12bit_out(dout_trunc_1q),
    .trunc_overflow(trunc_overflow_1q)
    );
    
    trunc_32bit_to_12bit trunc_32bit_to_12bit_2i(
    .clk(clk),
    .rst(rst),
    .trunc_32bit_in({{7{dout_comp_2[24]}},dout_comp_2[24:0]}),
    .vio_trunc(vio_trunc),
    
    .trunc_12bit_out(dout_trunc_2i),
    .trunc_overflow(trunc_overflow_2i)
    );
    
    trunc_32bit_to_12bit trunc_32bit_to_12bit_2q(
    .clk(clk),
    .rst(rst),
    .trunc_32bit_in({{7{dout_comp_2[56]}},dout_comp_2[56:32]}),
    .vio_trunc(vio_trunc),
    
    .trunc_12bit_out(dout_trunc_2q),
    .trunc_overflow(trunc_overflow_2q)
    );
    
    trunc_32bit_to_12bit trunc_32bit_to_12bit_3i(
    .clk(clk),
    .rst(rst),
    .trunc_32bit_in({{7{dout_comp_3[24]}},dout_comp_3[24:0]}),
    .vio_trunc(vio_trunc),
    
    .trunc_12bit_out(dout_trunc_3i),
    .trunc_overflow(trunc_overflow_3i)
    );
    
    trunc_32bit_to_12bit trunc_32bit_to_12bit_3q(
    .clk(clk),
    .rst(rst),
    .trunc_32bit_in({{7{dout_comp_3[56]}},dout_comp_3[56:32]}),
    .vio_trunc(vio_trunc),
    
    .trunc_12bit_out(dout_trunc_3q),
    .trunc_overflow(trunc_overflow_3q)
    );
     
    reg [15:0] data_i_combine = 16'd0;
    reg [15:0] data_q_combine = 16'd0;
    always @ (posedge clk) begin
        if(rst) begin
            data_i_combine[15:0] <= 16'd0;
            data_q_combine[15:0] <= 16'd0;
        end
        else begin
            data_i_combine[15:0] <= {{4{dout_trunc_0i[11]}},dout_trunc_0i[11:0]} + {{4{dout_trunc_1i[11]}},dout_trunc_1i[11:0]} + {{4{dout_trunc_2i[11]}},dout_trunc_2i[11:0]} + {{4{dout_trunc_3i[11]}},dout_trunc_3i[11:0]};
            data_q_combine[15:0] <= {{4{dout_trunc_0q[11]}},dout_trunc_0q[11:0]} + {{4{dout_trunc_1q[11]}},dout_trunc_1q[11:0]} + {{4{dout_trunc_2q[11]}},dout_trunc_2q[11:0]} + {{4{dout_trunc_3q[11]}},dout_trunc_3q[11:0]};
        end
    end    
    
    assign dout_i[15:0] = data_i_combine[15:0];
    assign dout_q[15:0] = data_q_combine[15:0];
    assign trunc_overflow = trunc_overflow_3q || trunc_overflow_2q || trunc_overflow_1q || trunc_overflow_0q || trunc_overflow_3i || trunc_overflow_2i || trunc_overflow_1i || trunc_overflow_0i;
endmodule