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xilinx_anylanguagebehavioralsimulation s1_sdi_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_sdi_data out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_sync_valid out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation s1_sync_ready in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 s1_sync out 7 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation DATA_WIDTH Data Width 8 NUM_OF_SDI Num Of Sdi 1 xilinx_anylanguagesynthesis_view_fileset spi_engine_interconnect.v verilogSource CHECKSUM_582b051e xilinx_anylanguagebehavioralsimulation_view_fileset spi_engine_interconnect.v verilogSource xilinx_xpgui_view_fileset xgui/spi_engine_interconnect_v1_0.tcl tclSource CHECKSUM_d9e58594 XGUI_VERSION_2 spi_engine_interconnect_v1_0 DATA_WIDTH Parallel data width 8 NUM_OF_SDI Number of MISO lines 1 Component_Name spi_engine_interconnect_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices spi_engine_interconnect_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:07:57Z 2019.1.3