`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/03/21 18:35:38
// Design Name:
// Module Name: tx_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module tx_control
(
    input           sys_clk         , // 122.88MHz
    input           sys_rst         ,
    input           sig_clk         , // 48MHz
    input           sig_rst         ,

    output  [15:0]  tx_data_i       ,
    output  [15:0]  tx_data_q       ,
    // debug ports
    input   [ 2:0]  waveform_sel    ,
    input           sweep_on        ,
    input   [31:0]  freq_set        ,
    input   [ 1:0]  iq_sel          ,
    input   [ 3:0]  bb_rshift
);

// pn seq
wire [15:0] tx_pn_seq_i;
wire [15:0] tx_pn_seq_q;

tx_pn_seq_6mcps #(
    .DATA_WIDTH     (16),
    .BIT_DATA       (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
    .BIT_DATA_LEN   (1024)
) u_tx_pn_seq
(
    .sys_clk    (sys_clk    ), // 122.88MHz
    .sys_rst    (sys_rst    ),
    .sig_clk    (sig_clk    ), // 48MHz
    .sig_rst    (sig_rst    ),

    .tx_data_i  (tx_pn_seq_i),
    .tx_data_q  (tx_pn_seq_q)
);

// qpsk
wire [15:0] tx_qpsk_i;
wire [15:0] tx_qpsk_q;

tx_qpsk #(
    .DATA_WIDTH     (16         ),
    .SQUARE_INTERP  (32         ),
    .CLK_FREQ       (122880000  )
) u_tx_qpsk
(
    .clk            (sys_clk            ),
    .rst            (sys_rst            ),
    .tx_data_i      (tx_qpsk_i          ),
    .tx_data_q      (tx_qpsk_q          ),
    // debug ports
    .waveform_sel   (waveform_sel[1:0]  ),
    .sweep_on       (sweep_on           ),
    .freq_set       (freq_set           ),
    .iq_sel         (iq_sel             ),
    .bb_rshift      (bb_rshift          )
);

// output
reg [15:0] tx_data_buf_i = 'b0;
reg [15:0] tx_data_buf_q = 'b0;

assign tx_data_i = tx_data_buf_i;
assign tx_data_q = tx_data_buf_q;

always @(posedge sys_clk) begin
    if (sys_rst) begin
        tx_data_buf_i <= 'b0;
        tx_data_buf_q <= 'b0;
    end
    else if (waveform_sel[2]) begin
        tx_data_buf_i <= tx_pn_seq_i;
        tx_data_buf_q <= tx_pn_seq_q;
    end
    else begin
        tx_data_buf_i <= tx_qpsk_i;
        tx_data_buf_q <= tx_qpsk_q;
    end
end

endmodule