`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2022/07/13 14:20:24
// Design Name:
// Module Name: ant_rf_ctrl
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module ant_rf_ctrl
(
    input           clk_48m         ,
    input           clk_96m         ,
    input           clk_32m         ,
    input           clk_19p2m       ,
    input           sys_rst         ,

    output          ant_clk         ,
    output          ant_en          ,
    output          ant_data        ,
    output          ant_tr          ,
    output          ant_dary        ,
    input           ant_dout        ,

    output          rf_standby      ,
    output          rf_sw_pll       ,
    output          rf_t            ,
    output          rf_r            ,
    output          rf_sw_bpf       ,
    output          rf_sclk1        ,
    output          rf_sdio1        ,
    output          rf_cs1          ,
    input           rf_ld1          ,
    output          rf_sclk2        ,
    output          rf_sdio2        ,
    output          rf_cs2          ,
    input           rf_ld2          ,
    output          rf_sclk3        ,
    output          rf_sdio3        ,
    output          rf_cs3          ,
    input           rf_ld3          ,
    output          rf_tmgc_16      ,
    output          rf_tmgc_8       ,
    output          rf_tmgc_4       ,
    output          rf_tmgc_2       ,
    output          rf_tmgc_1       ,
    output          rf_rmgc_16      ,
    output          rf_rmgc_8       ,
    output          rf_rmgc_4       ,
    output          rf_rmgc_2       ,
    output          rf_rmgc_1       ,
    output          rf_enable       ,
    output          rf_sc           ,
    output          rf_sd           ,
    output          rf_endsyn       ,
    input           rf_sdout        ,
    inout           rf_dq_wd        ,
    output          rf_sw_rx
);


(*dont_touch = "true"*) wire        vio_switch      ; // 键控开关，沿有效
(*dont_touch = "true"*) wire        vio_trdirection ; // 收发方向
(*dont_touch = "true"*) wire [15:0] vio_frequency   ; // 收发频率
(*dont_touch = "true"*) wire [ 7:0] vio_emitMGC     ; // 发送MGC
(*dont_touch = "true"*) wire [ 3:0] vio_ch01MGC     ; // 1通道校准MGC
(*dont_touch = "true"*) wire [ 3:0] vio_ch02MGC     ; // 2通道校准MGC
(*dont_touch = "true"*) wire [ 3:0] vio_ch03MGC     ; // 3通道校准MGC
(*dont_touch = "true"*) wire [ 3:0] vio_ch04MGC     ; // 4通道校准MGC
(*dont_touch = "true"*) wire [ 7:0] vio_recvMGC     ; // 接收MGC
(*dont_touch = "true"*) wire [ 7:0] vio_AntMod      ; // 天线工作模式
(*dont_touch = "true"*) wire [15:0] vio_AntOffAxis  ; // 天线离轴角
(*dont_touch = "true"*) wire [15:0] vio_AntYaw      ; // 天线偏航角
(*dont_touch = "true"*) wire [15:0] vio_PrecessTime ; // 处理时间，从EN拉低到DARY拉低

(*dont_touch = "true"*)wire         vio_mode_ant    ; // 0定频手动，1扫频模式
(*dont_touch = "true"*)wire         vio_hop_start   ; // 0跳频终止，1重新跳频
(*dont_touch = "true"*)wire         vio_standby     ; // 0待机模式，1工作模式
(*dont_touch = "true"*)wire  [15:0] vio_hoptime     ; // 单跳时间计数器

reg Ant_switch_D1 = 0;
reg data_valid = 0;
reg switch_valid = 0;
reg [95:0] RF_CtrlWord = 0;
reg [127:0] Ant_CtrlWord = 0;
reg [15:0] data_valid_countdown = 0;
reg [15:0] rst_countdown = 100;
reg [95:0] RF_CtrlWord_running = 0;
reg [127:0] Ant_CtrlWord_running = 0;
reg rst_n = 0;
reg SPI_SYN_F = 1;
reg SPI_MOSI_F = 1;
reg TP_EN_F = 0;
reg TR_MGC_F = 0;
reg CAL_F = 0;
reg PRF = 0;
wire SPI_MISO_F;
reg Ant_DATA = 0;
reg Ant_EN = 0;
reg Ant_DARY = 0;
reg Ant_TR = 0;



//相控阵测试程序
reg 	[15:0] 	cnt_freq_change = 16'd0;

reg  			Ant_switch	 ; // 键控开关，沿有效
reg  	[15:0] 	Ant_frequency; // 收发频率
reg		[ 7:0]  Ant_mode	 ; // 相控阵模式
reg		[ 7:0]  RF_mode		 ; // 射频模式

always @ (posedge clk_48m) begin
    if(sys_rst) begin
        Ant_switch            <=  1'b0;
        cnt_freq_change[15:0] <= 16'd0;
        Ant_frequency[15:0]   <= 16'd0;
        RF_mode[7:0]          <= 8'h10;
        Ant_mode[7:0]         <= 8'h0f;
    end
    else begin
        if(vio_mode_ant) begin
            if(vio_hop_start) begin
                if(cnt_freq_change[15:0] == (vio_hoptime[15:0] - 16'd1)) begin
                    Ant_switch            <= ~Ant_switch;
                    if(Ant_frequency[15:0] == 16'd3500) begin
                        Ant_frequency[15:0]   <= 16'd0;
                    end
                    else begin
                        Ant_frequency[15:0]   <= Ant_frequency[15:0] + 16'd1;
                    end
                    cnt_freq_change[15:0] <= 16'd0;
                end
                else begin
                    Ant_switch            <= Ant_switch;
                    Ant_frequency[15:0]   <= Ant_frequency[15:0];
                    cnt_freq_change[15:0] <= cnt_freq_change[15:0] + 16'd1;
                end
            end
            else begin
                Ant_switch            <= Ant_switch;
                Ant_frequency[15:0]   <= 16'd0;
                cnt_freq_change[15:0] <= 16'd0;
            end
        end
        else begin
            Ant_switch            <= vio_switch;
            Ant_frequency[15:0]   <= vio_frequency[15:0];
            cnt_freq_change[15:0] <= 16'd0;
        end

        if(vio_standby) begin
            RF_mode[7:0]  <= 8'h10;
            Ant_mode[7:0] <= 8'h0f;
        end
        else begin
            RF_mode[7:0]  <= 8'h00;
            Ant_mode[7:0] <= vio_AntMod[7:0];
        end
    end

end

always @(posedge clk_48m)
	begin
		Ant_switch_D1 <= Ant_switch;
		if(Ant_switch_D1 != Ant_switch)
			switch_valid <= 1'b1;
		else
			switch_valid <= 1'b0;

		if(switch_valid)
			begin
			RF_CtrlWord[95:88] <= 8'hAA;
			RF_CtrlWord[87:80] <= RF_mode[7:0];
			RF_CtrlWord[79:64] <= Ant_frequency[15:0];
			RF_CtrlWord[63:56] <= vio_emitMGC[7:0];
			RF_CtrlWord[55:52] <= vio_ch01MGC[3:0];
			RF_CtrlWord[51:48] <= vio_ch02MGC[3:0];
			RF_CtrlWord[47:44] <= vio_ch03MGC[3:0];
			RF_CtrlWord[43:40] <= vio_ch04MGC[3:0];
			RF_CtrlWord[39:32] <= vio_recvMGC[7:0];
			RF_CtrlWord[31:8] <= 24'h00_0000;
			RF_CtrlWord[7:0] <= 8'hCC;

			Ant_CtrlWord[127:120] <= 8'hAA;
			Ant_CtrlWord[119:112] <= 8'h00;
			Ant_CtrlWord[111:104] <= Ant_mode[7:0];
			Ant_CtrlWord[103: 88] <= vio_AntOffAxis[15:0];
			Ant_CtrlWord[ 87: 72] <= vio_AntYaw[15:0];
			Ant_CtrlWord[ 71: 56] <= Ant_frequency[15:0];
			Ant_CtrlWord[ 55:  8] <= 48'h00_00_00_00_00_00;
			Ant_CtrlWord[  7:  0] <= 8'hCC;
			end
		else
			begin
			RF_CtrlWord[95:0] <= RF_CtrlWord[95:0];
			Ant_CtrlWord[127:0] <= Ant_CtrlWord[127:0];
			end

		if(switch_valid)
			data_valid_countdown[15:0] <= vio_PrecessTime[15:0];
		else if(data_valid_countdown[15:0] != 16'd0)
			data_valid_countdown[15:0] <= data_valid_countdown[15:0] - 16'd1;


		// RF控制
		if(data_valid_countdown[15:0] == vio_PrecessTime[15:0])
			RF_CtrlWord_running[95:0] <= RF_CtrlWord[95:0];
		else
			RF_CtrlWord_running[95:0] <= {RF_CtrlWord_running[94:0],1'b0};

		if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd96 && data_valid_countdown[15:0] < vio_PrecessTime[15:0])
			begin
				SPI_SYN_F <= 1'b0;
				SPI_MOSI_F <= RF_CtrlWord_running[95];
			end
		else
			begin
				SPI_SYN_F <= 1'b1;
				SPI_MOSI_F <= 1'b0;
			end


		if(data_valid_countdown[15:0] <= 16'd128 && data_valid_countdown[15:0] > 16'd80)
			CAL_F <= 1'b1;
		else
			CAL_F <= 1'b0;

		if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0)
			begin
				TP_EN_F <= 1'b1;
				TR_MGC_F <= 1'b1;
			end
		else
			begin
				TP_EN_F <= 1'b0;
				TR_MGC_F <= 1'b0;
			end

		if(data_valid_countdown[15:0] == 16'd48)
			PRF <= vio_trdirection;
		else
			PRF <= PRF;

		if(sys_rst)
			rst_countdown[15:0] <= 16'd100;
		else if(rst_countdown[15:0] != 0)
			begin
			rst_countdown[15:0] <= rst_countdown[15:0] - 16'd1;
			rst_n <= 1'b0;
			end
		else
			begin
			rst_countdown[15:0] <= rst_countdown[15:0];
			rst_n <= 1'b1;
			end

		// 天线控制
		if(data_valid_countdown[15:0] == vio_PrecessTime[15:0])
			Ant_CtrlWord_running[127:0] <= Ant_CtrlWord[127:0];
		else
			Ant_CtrlWord_running[127:0] <= {Ant_CtrlWord_running[126:0],1'b0};

		if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd128 && data_valid_countdown[15:0] < vio_PrecessTime[15:0])
			begin
				Ant_EN <= 1'b0;
				Ant_DATA <= Ant_CtrlWord_running[127];
			end
		else
			begin
				Ant_EN <= 1'b1;
				Ant_DATA <= 1'b0;
			end

		if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0)
			Ant_DARY <= 1'b0;
		else
			Ant_DARY <= 1'b1;

		if(data_valid_countdown[15:0] == 16'd48)
			Ant_TR <= vio_trdirection;
		else
			Ant_TR <= Ant_TR;
	end


//RF recv_data
reg [1:0] state_rfdata;
reg SPI_SYN_F_d1 = 1'b0;
reg [15:0] cnt_rfdata = 16'd0;
reg [95:0] RF_RecvWord = 96'd0;
reg [95:0] RF_RecvWord_last = 96'd0;

reg [7:0]  RF_temperature = 8'd0  ;
reg [7:0]  RF_IFlocked    = 8'd0  ;
reg [7:0]  RF_RFAlocked   = 8'd0  ;
reg [7:0]  RF_RFBlocked   = 8'd0  ;
reg [3:0]  RF_ch1mgc      = 4'd0  ;
reg [3:0]  RF_ch2mgc      = 4'd0  ;
reg [3:0]  RF_ch3mgc      = 4'd0  ;
reg [3:0]  RF_ch4mgc      = 4'd0  ;
reg [31:0] RF_Framecount  = 32'd0 ;

always @ (posedge clk_48m) begin
    if(sys_rst) begin
        state_rfdata[1:0]    <= 2'd0;
        SPI_SYN_F_d1         <= 1'b0;
		RF_RecvWord[95:0]    <= 96'd0;
		cnt_rfdata[15:0]     <= 16'd0;
		RF_temperature[7:0]  <= 8'd0 ;
        RF_IFlocked[7:0]     <= 8'd0 ;
        RF_RFAlocked[7:0]    <= 8'd0 ;
        RF_RFBlocked[7:0]    <= 8'd0 ;
        RF_ch1mgc[3:0]       <= 4'd0 ;
        RF_ch2mgc[3:0]       <= 4'd0 ;
        RF_ch3mgc[3:0]       <= 4'd0 ;
        RF_ch4mgc[3:0]       <= 4'd0 ;
        RF_Framecount[31:0]  <= 32'd0;
    end
    else begin
		RF_RecvWord[95:0] <= {RF_RecvWord[94:0],SPI_MISO_F};

		if (RF_RecvWord[95:88] == 8'hAA && RF_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾
			RF_temperature[7:0]  <= RF_RecvWord[87:80];
			RF_IFlocked[7:0]     <= RF_RecvWord[79:72];
			RF_RFAlocked[7:0]    <= RF_RecvWord[71:64];
			RF_RFBlocked[7:0]    <= RF_RecvWord[63:56];
			RF_ch1mgc[3:0]       <= RF_RecvWord[55:52];
			RF_ch2mgc[3:0]       <= RF_RecvWord[51:48];
			RF_ch3mgc[3:0]       <= RF_RecvWord[47:44];
			RF_ch4mgc[3:0]       <= RF_RecvWord[43:40];
			RF_Framecount[31:0]  <= RF_RecvWord[39:8];
			RF_RecvWord_last <= RF_RecvWord;
		end
		else begin // hold otherwise
			RF_temperature[7:0]  <= RF_temperature[7:0];
			RF_IFlocked[7:0]     <= RF_IFlocked[7:0]   ;
			RF_RFAlocked[7:0]    <= RF_RFAlocked[7:0]  ;
			RF_RFBlocked[7:0]    <= RF_RFBlocked[7:0]  ;
			RF_ch1mgc[3:0]       <= RF_ch1mgc[3:0]     ;
			RF_ch2mgc[3:0]       <= RF_ch2mgc[3:0]     ;
			RF_ch3mgc[3:0]       <= RF_ch3mgc[3:0]     ;
			RF_ch4mgc[3:0]       <= RF_ch4mgc[3:0]     ;
			RF_Framecount[31:0]  <= RF_Framecount[31:0];
			RF_RecvWord_last <= RF_RecvWord_last;
		end
    end
end
// 天线的输出时钟转换
reg Ant_dclk_96m = 1;
wire [3:0] fifo_wr_din, fifo_rd_dout;
wire fifo_full, fifo_empty;
reg Ant_EN_96m = 0;
reg Ant_DATA_96m = 0;
reg Ant_DARY_96m = 1;
reg Ant_TR_96m = 0;
assign fifo_wr_din[3] = Ant_EN;
assign fifo_wr_din[2] = Ant_DATA;
assign fifo_wr_din[1] = Ant_DARY;
assign fifo_wr_din[0] = Ant_TR;
reg fifo_rd_en = 0;
reg fifo_rst = 0;
reg [8:0] Ant_clk_countdown = 0;
always @(posedge clk_96m)
	begin
		fifo_rst <= sys_rst;

		fifo_rd_en <= (fifo_rst == 1'b1)? 1'b0:!fifo_rd_en;

		if(fifo_rd_en)
			{Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= fifo_rd_dout[3:0];
		else
			{Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= {Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m};

		if(fifo_rd_en && Ant_EN_96m && !fifo_rd_dout[3])
			Ant_clk_countdown[8:0] <= 9'd276;
		else if(Ant_clk_countdown[8:0] != 9'd0)
			Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0] - 9'd1;
		else
			Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0];
	end
assign ant_clk = !Ant_clk_countdown[0];
assign ant_en = Ant_EN_96m;
assign ant_data = Ant_DATA_96m;
assign ant_tr = Ant_TR_96m;
assign ant_dary = Ant_DARY_96m;

fifo_AntCtrl fifo_AntCtrl
(
    .rst    (fifo_rst           ), // input wire rst
    .wr_clk (clk_48m            ), // input wire wr_clk
    .rd_clk (clk_96m            ), // input wire rd_clk
    .din    (fifo_wr_din[3:0]   ), // input wire [3 : 0] din
    .wr_en  (!fifo_rst          ), // input wire wr_en
    .rd_en  (fifo_rd_en         ), // input wire rd_en
    .dout   (fifo_rd_dout[3:0]  ), // output wire [3 : 0] dout
    .full   (fifo_full          ), // output wire full
    .empty  (fifo_empty         )  // output wire empty
);
//Ant recv_data
reg [1:0] state_antdata;
reg Ant_EN_96m_d1 = 1'b0;
reg [15:0] cnt_antdata = 16'd0;
reg [95:0] Ant_RecvWord = 'b0;
reg [95:0] Ant_RecvWord_last = 'b0;

reg [7:0]  Ant_Ant_Volt    = 8'd0  ;
reg [7:0]  Ant_RF_Volt     = 8'd0  ;
reg [7:0]  Ant_IF_Volt     = 8'd0  ;
reg [7:0]  Ant_state       = 8'd0  ;
reg [31:0] Ant_Framecount  = 32'd0 ;

always @ (posedge clk_96m) begin
    if(sys_rst) begin
        state_antdata[1:0]   <= 2'd0;
        Ant_EN_96m_d1        <= 1'b0;
		Ant_RecvWord[95:0]   <= 'd0;
		cnt_antdata[15:0]    <= 16'd0;
		Ant_Ant_Volt[7:0]    <= 8'd0 ;
        Ant_RF_Volt[7:0]     <= 8'd0 ;
        Ant_IF_Volt[7:0]     <= 8'd0 ;
        Ant_state[7:0]       <= 8'd0 ;
        Ant_Framecount[31:0] <= 32'd0;
    end
    else begin
		Ant_RecvWord[95:0] <= {Ant_RecvWord[94:0],ant_dout};

		if(Ant_RecvWord[95:88] == 8'hAA && Ant_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾
			Ant_Ant_Volt[7:0]    <= Ant_RecvWord[87:80];
			Ant_RF_Volt[7:0]     <= Ant_RecvWord[79:72];
			Ant_IF_Volt[7:0]     <= Ant_RecvWord[71:64];
			Ant_state[7:0]       <= Ant_RecvWord[47:40];
			Ant_Framecount[31:0] <= Ant_RecvWord[39:8] ;
			Ant_RecvWord_last 	 <= Ant_RecvWord		 ;
		end
		else begin // hold otherwise
			Ant_Ant_Volt[7:0]    <= Ant_Ant_Volt[7:0]    ;
			Ant_RF_Volt[7:0]     <= Ant_RF_Volt[7:0]     ;
			Ant_IF_Volt[7:0]     <= Ant_IF_Volt[7:0]     ;
			Ant_state[7:0]       <= Ant_state[7:0]       ;
			Ant_Framecount[31:0] <= Ant_Framecount[31:0] ;
			Ant_RecvWord_last 	<= Ant_RecvWord_last	 ;
		end
    end

end
Sisyif uut(
	.clk_40m(clk_32m),
	.clk_20m(clk_19p2m),
	.SPI_CLK_F(clk_48m),
	.rst_n(rst_n),
	.SPI_SYN_F(SPI_SYN_F),
	.SPI_MOSI_F(SPI_MOSI_F),
	.SPI_MISO_F(SPI_MISO_F),
	.TP_EN_F(TP_EN_F),
	.TR_MGC_F(TR_MGC_F),
	.CAL_F(CAL_F),
	.PRF(PRF),
	.standby(rf_standby),
	.SW_PLL(rf_sw_pll),
	.T(rf_t),
	.R(rf_r),
	.SW_BPF(rf_sw_bpf),
	.SCLK1(rf_sclk1),
	.SDIO1(rf_sdio1),
	.CS1(rf_cs1),
	.LD1(rf_ld1),
	.SCLK2(rf_sclk2),
	.SDIO2(rf_sdio2),
	.CS2(rf_cs2),
	.LD2(rf_ld2),
	.SCLK3(rf_sclk3),
	.SDIO3(rf_sdio3),
	.CS3(rf_cs3),
	.LD3(rf_ld3),
	.TMGC_16db(rf_tmgc_16),
	.TMGC_8db(rf_tmgc_8),
	.TMGC_4db(rf_tmgc_4),
	.TMGC_2db(rf_tmgc_2),
	.TMGC_1db(rf_tmgc_1),
	.RMGC_16db(rf_rmgc_16),
	.RMGC_8db(rf_rmgc_8),
	.RMGC_4db(rf_rmgc_4),
	.RMGC_2db(rf_rmgc_2),
	.RMGC_1db(rf_rmgc_1),
	.ENABLE(rf_enable),
	.SC(rf_sc),
	.SD(rf_sd),
	.END_SYN(rf_endsyn),
	.SDOUT(rf_sdout),
	.DQ_WD(rf_dq_wd),
	.SW_RX(rf_sw_rx)
	);

endmodule