analog.com user util_delay 1.0 clk CLK clk ASSOCIATED_RESET reset reset RST reset xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis Verilog util_delay xilinx_anylanguagesynthesis_view_fileset viewChecksum 8c2d4c90 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog util_delay xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 8c2d4c90 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum b1d00148 clk in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation reset in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation din in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation dout out 0 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation DATA_WIDTH Data Width 1 DELAY_CYCLES Delay Cycles 1 xilinx_anylanguagesynthesis_view_fileset ../common/util_delay.v verilogSource CHECKSUM_8c2d4c90 xilinx_anylanguagebehavioralsimulation_view_fileset ../common/util_delay.v verilogSource xilinx_xpgui_view_fileset xgui/util_delay_v1_0.tcl tclSource CHECKSUM_b1d00148 XGUI_VERSION_2 util_delay_v1_0 DATA_WIDTH Data Width 1 DELAY_CYCLES Delay Cycles 1 Component_Name util_delay_v1_0 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l akintex7 artix7 artix7l aartix7 qartix7 zynq qzynq azynq spartan7 aspartan7 virtexu zynquplus virtexuplus virtexuplusHBM virtexuplus58g kintexuplus kintexu azynquplus qkintexu qkintexuplus qrkintexu qvirtexuplus qzynquplus qzynquplusRFSOC zynquplusRFSOC /Analog_Devices util_delay_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-09T07:18:44Z 2019.1.3