# df_z7100_2ad9361 ## Timing Assertions Section ## Physical Constraints Section # Clocks set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS } [get_ports clk_250m_p ] ;# FPGA_DAC_LOGIC_CLK_C_P set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# AD9361_CLK_OUT set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# B_AD9361_CLK_OUT # HMC7044-1 Interface set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_clk ] ;# HMC7044_1_SCLK set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_csn ] ;# HMC7044_1_SLEN set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_sdio ] ;# HMC7044_1_DATA set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports hmc7044_reset ] ;# HMC7044_1_RESET set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS33} [get_ports hmc7044_sync ] ;# HMC7044_1_SYNC set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[0] ] ;# HMC7044_1_GPIO1 set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[1] ] ;# HMC7044_1_GPIO2 set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[2] ] ;# HMC7044_1_GPIO3 set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[3] ] ;# HMC7044_1_GPIO4 # AD9361-1 Interface set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# AD9361_DATA_CLK_P set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# AD9361_RX_FRAME_P set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# AD9361_TX_00_D0_N set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# AD9361_TX_01_D0_P set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# AD9361_TX_02_D1_N set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# AD9361_TX_03_D1_P set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# AD9361_TX_04_D2_N set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# AD9361_TX_05_D2_P set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# AD9361_TX_06_D3_N set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# AD9361_TX_07_D3_P set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# AD9361_TX_08_D4_N set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# AD9361_TX_09_D4_P set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# AD9361_TX_10_D5_N set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# AD9361_TX_11_D5_P set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# AD9361_FB_CLK_P set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# AD9361_TX_FRAME_P set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# AD9361_RX_00_D0_N set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# AD9361_RX_01_D0_P set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# AD9361_RX_02_D1_N set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# AD9361_RX_03_D1_P set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# AD9361_RX_04_D2_N set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# AD9361_RX_05_D2_P set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# AD9361_RX_06_D3_N set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# AD9361_RX_07_D3_P set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# AD9361_RX_08_D4_N set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# AD9361_RX_09_D4_P set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# AD9361_RX_10_D5_N set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# AD9361_RX_11_D5_P set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# AD9361_SPI_CLK set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# AD9361_SPI_ENB set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# AD9361_SPI_DI set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# AD9361_SPI_DO set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# AD9361_RESETB set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# AD9361_EN_AGC set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# AD9361_ENABLE set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# AD9361_TXNRX set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# AD9361_CTRL_IN0 set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# AD9361_CTRL_IN1 set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# AD9361_CTRL_IN2 set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# AD9361_CTRL_IN3 set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# AD9361_CTRL_OUT0 set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# AD9361_CTRL_OUT1 set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# AD9361_CTRL_OUT2 set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# AD9361_CTRL_OUT3 set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# AD9361_CTRL_OUT4 set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# AD9361_CTRL_OUT5 set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# AD9361_CTRL_OUT6 set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# AD9361_CTRL_OUT7 # AD9361-2 Interface set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# B_AD9361_DATA_CLK_P set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# B_AD9361_RX_FRAME_P set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# B_AD9361_TX_00_D0_N set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# B_AD9361_TX_01_D0_P set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# B_AD9361_TX_02_D1_N set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# B_AD9361_TX_03_D1_P set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# B_AD9361_TX_04_D2_N set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# B_AD9361_TX_05_D2_P set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# B_AD9361_TX_06_D3_N set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# B_AD9361_TX_07_D3_P set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# B_AD9361_TX_08_D4_N set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# B_AD9361_TX_09_D4_P set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# B_AD9361_TX_10_D5_N set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# B_AD9361_TX_11_D5_P set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# B_AD9361_FB_CLK_P set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# B_AD9361_TX_FRAME_P set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# B_AD9361_RX_00_D0_N set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# B_AD9361_RX_01_D0_P set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# B_AD9361_RX_02_D1_N set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# B_AD9361_RX_03_D1_P set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# B_AD9361_RX_04_D2_N set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# B_AD9361_RX_05_D2_P set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# B_AD9361_RX_06_D3_N set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# B_AD9361_RX_07_D3_P set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# B_AD9361_RX_08_D4_N set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# B_AD9361_RX_09_D4_P set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# B_AD9361_RX_10_D5_N set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# B_AD9361_RX_11_D5_P set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# B_AD9361_SPI_CLK set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# B_AD9361_SPI_ENB set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# B_AD9361_SPI_DI set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# B_AD9361_SPI_DO set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B_AD9361_RESETB set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B_AD9361_EN_AGC set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B_AD9361_ENABLE set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B_AD9361_TXNRX set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B_AD9361_CTRL_IN0 set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# B_AD9361_CTRL_IN1 set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# B_AD9361_CTRL_IN2 set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# B_AD9361_CTRL_IN3 set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# B_AD9361_CTRL_OUT0 set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# B_AD9361_CTRL_OUT1 set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# B_AD9361_CTRL_OUT2 set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# B_AD9361_CTRL_OUT3 set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# B_AD9361_CTRL_OUT4 set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# B_AD9361_CTRL_OUT5 set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# B_AD9361_CTRL_OUT6 set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# B_AD9361_CTRL_OUT7 # Phased-Array Control set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVTTL } [get_ports ant_clk ] ;# ANT_CLK set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVTTL } [get_ports ant_en ] ;# ANT_EN set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVTTL } [get_ports ant_data ] ;# ANT_DATA set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVTTL } [get_ports ant_tr ] ;# ANT_TR set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVTTL } [get_ports ant_dary ] ;# ANT_DARY set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVTTL } [get_ports ant_dout ] ;# ANT_DOUT # RF Synthesizer Control set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports rf_standby ] ;# ANT_standby_R set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports rf_sw_pll ] ;# ANT_SW_PLL_R set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports rf_t ] ;# ANT_T_R set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS33} [get_ports rf_r ] ;# ANT_R_R set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports rf_sw_bpf ] ;# ANT_SW_BPF_R set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports rf_sclk1 ] ;# ANT_SCLK1_R set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33} [get_ports rf_sdio1 ] ;# ANT_SDIO1_R set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports rf_cs1 ] ;# ANT_CS1_R set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS33} [get_ports rf_ld1 ] ;# ANT_LD1_R set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS33} [get_ports rf_sclk2 ] ;# ANT_SCLK2_R set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS33} [get_ports rf_sdio2 ] ;# ANT_SDIO2_R set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS33} [get_ports rf_cs2 ] ;# ANT_CS2_R set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS33} [get_ports rf_ld2 ] ;# ANT_LD2_R set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVCMOS33} [get_ports rf_sclk3 ] ;# ANT_SCLK3_R set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS33} [get_ports rf_sdio3 ] ;# ANT_SDIO3_R set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS33} [get_ports rf_cs3 ] ;# ANT_CS3_R set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS33} [get_ports rf_ld3 ] ;# ANT_LD3_R set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_16 ] ;# ANT_TMGC_16_R set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_8 ] ;# ANT_TMGC_8_R set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_4 ] ;# ANT_TMGC_4_R set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_2 ] ;# ANT_TMGC_2_R set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_1 ] ;# ANT_TMGC_1_R set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_16 ] ;# ANT_RMGC_16_R set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_8 ] ;# ANT_RMGC_8_R set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_4 ] ;# ANT_RMGC_4_R set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_2 ] ;# ANT_RMGC_2_R set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_1 ] ;# ANT_RMGC_1_R set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS33} [get_ports rf_enable ] ;# ANT_ENABLE_R set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS33} [get_ports rf_sc ] ;# ANT_SC_R set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS33} [get_ports rf_sd ] ;# ANT_SD_R set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS33} [get_ports rf_endsyn ] ;# ANT_END/SYN_R set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS33} [get_ports rf_sdout ] ;# ANT_SDOUT_R set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS33} [get_ports rf_dq_wd ] ;# ANT_DQ-WD_R 15 set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33} [get_ports rf_sw_rx ] ;# ANT_SW_RX_R # Debug IO set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART1_TXD set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART1_RXD set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART2_TXD set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART2_RXD set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART3_TXD set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART3_RXD set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports debug_io_1 ] ;# DEBUG_IO_1 set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports debug_io_2 ] ;# DEBUG_IO_2 set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3 set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4 set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5 set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6 set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# DEBUG_IO_7