`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/06/2023 03:39:20 PM
// Design Name:
// Module Name: tb_freq_comp
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module tb_freq_comp;

reg clk = 1'b1;
reg rst = 1'b1;
reg freq_comp_start = 'b0;

wire [11:0] tx_data_i, tx_data_q;
wire [31:0] freq_target;
wire freq_target_valid;

initial begin
    #102;
    rst = 1'b0;
    #1000;
    freq_comp_start = ~freq_comp_start;
end

always #10 clk = ~clk;

tx_qpsk u_tx_qpsk
(
    .clk            (clk            ),
    .rst            (rst            ),

    .tx_data_i      (tx_data_i      ),
    .tx_data_q      (tx_data_q      ),
    // debug ports
    .waveform_sel   (2'd1           ),
    .sweep_on       (1'b0           ),
    .freq_set       ('b0            ),
    .iq_sel         (2'b11          ),
    .bb_rshift      (4'd0           )
);

freq_comp #(
    .FREQ_WORD_LOWER(-1024 ),
    .FREQ_WORD_UPPER(10000  ),
    .FREQ_WORD_STEP (1024  )
)u_freq_comp
(
    .clk                (clk                ),
    .rst                (rst                ),

    .freq_comp_start    (freq_comp_start    ),
    .freq_comp_busy     (freq_comp_busy     ),

    .rx_data_valid      (~rst               ),
    .rx_ch1_i           (tx_data_i          ),
    .rx_ch1_q           (tx_data_q          ),
    .rx_ch2_i           (tx_data_q          ),
    .rx_ch2_q           (tx_data_i          ),
    .rx_ch3_i           (tx_data_i          ),
    .rx_ch3_q           (tx_data_i          ),
    .rx_ch4_i           (tx_data_q          ),
    .rx_ch4_q           (tx_data_q          ),

    .dmf_num_per_ch     (2                  ),

    .freq_manual        (327680             ),
    .freq_manual_en     (1'b0               ),

    .freq_target        (freq_target        ),
    .freq_target_valid  (freq_target_valid  )
);

endmodule