`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // _ _ ____ // | | ___ ___| |__ / ___| __ _ ___ // _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ // | |_| | (_) \__ \ | | | | |_| | (_| | (_) | // \___/ \___/|___/_| |_| \____|\__,_|\___/ // // Create Date: 2021/12/14 15:54:11 // Design Name: // Module Name: system_top // Project Name: // Target Devices: // Tool Versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module system_top ( /*************************************************************************** * Contents * 01. Clocks * 02. HMC7044 Interface * 03. AD9361-1 Interface * 04. AD9361-2 Interface * 05. Phased-Array Control * 06. RF Synthesizer Control * 07. Debug IO * 08. DDR and Fixed-io (Do NOT Modify) **************************************************************************/ // ************************************************************************* // ******************************** Clocks ********************************* // ************************************************************************* // fpga logic clock input clk_250m_p , // generated by hmc7044, 250mhz input clk_250m_n , // ad9361 buffered clock input ad9361_1_buffer_clk , // derived from ad9361 input clock input ad9361_2_buffer_clk , // derived from ad9361 input clock // ************************************************************************* // *************************** HMC7044 Interface *************************** // ************************************************************************* // spi interface output hmc7044_spi_clk , output hmc7044_spi_csn , inout hmc7044_spi_sdio , // control signals output hmc7044_reset , // hmc7044 active-high reset signal, set to 0 in normal operation output hmc7044_sync , // hmc7044 multichip synchronization signal, set to 0 if not used // gpio inout [ 3:0] hmc7044_gpio , // ************************************************************************* // ************************** AD9361-1 Interface *************************** // ************************************************************************* // rx data (rx channels are tied to ground physically) input ad9361_1_rx_data_clk, // ad9361 rx data clock, 96mhz input ad9361_1_rx_frame , input [11:0] ad9361_1_rx_data , // tx data output ad9361_1_tx_fb_clk , output ad9361_1_tx_frame , output [11:0] ad9361_1_tx_data , // spi interface output ad9361_1_spi_clk , output ad9361_1_spi_csn , output ad9361_1_spi_mosi , input ad9361_1_spi_miso , // control signals output ad9361_1_reset_b , // ad9361 active-low reset control output ad9361_1_en_agc , // ad9361 manual agc control output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed) output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed) input [ 3:0] ad9361_1_ctrl_in , output [ 7:0] ad9361_1_ctrl_out , // ************************************************************************* // ************************** AD9361-2 Interface *************************** // ************************************************************************* // rx data (rx channels are tied to ground physically) input ad9361_2_rx_data_clk, input ad9361_2_rx_frame , input [11:0] ad9361_2_rx_data , // tx data output ad9361_2_tx_fb_clk , output ad9361_2_tx_frame , output [11:0] ad9361_2_tx_data , // spi interface output ad9361_2_spi_clk , output ad9361_2_spi_csn , output ad9361_2_spi_mosi , input ad9361_2_spi_miso , // control signals output ad9361_2_reset_b , // ad9361 active-low reset control output ad9361_2_en_agc , // ad9361 manual agc control output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed) output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed) input [ 3:0] ad9361_2_ctrl_in , output [ 7:0] ad9361_2_ctrl_out , // ************************************************************************* // ************************* Phased-Array Control ************************** // ************************************************************************* output ant_clk , output ant_en , output ant_data , output ant_tr , output ant_dary , input ant_dout , // ************************************************************************* // ************************ RF Synthesizer Control ************************* // ************************************************************************* output rf_standby , output rf_sw_pll , output rf_t , output rf_r , output rf_sw_bpf , output rf_sclk1 , output rf_sdio1 , output rf_cs1 , input rf_ld1 , output rf_sclk2 , output rf_sdio2 , output rf_cs2 , input rf_ld2 , output rf_sclk3 , output rf_sdio3 , output rf_cs3 , input rf_ld3 , output rf_tmgc_16 , output rf_tmgc_8 , output rf_tmgc_4 , output rf_tmgc_2 , output rf_tmgc_1 , output rf_rmgc_16 , output rf_rmgc_8 , output rf_rmgc_4 , output rf_rmgc_2 , output rf_rmgc_1 , output rf_enable , output rf_sc , output rf_sd , output rf_endsyn , input rf_sdout , inout rf_dq_wd , output rf_sw_rx , // ************************************************************************* // ******************************* Debug IO ******************************** // ************************************************************************* // 3.3v ports output uart1_txd , input uart1_rxd , output uart2_txd , input uart2_rxd , output uart3_txd , input uart3_rxd , // 1.8v ports inout debug_io_1 , inout debug_io_2 , // 3.3v ports inout debug_io_3 , inout debug_io_4 , inout debug_io_5 , inout debug_io_6 , inout debug_io_7 , // ************************************************************************* // ******************* DDR and Fixed-io (Do NOT Modify) ******************** // ************************************************************************* // ddr inout [14:0] ddr_addr , inout [ 2:0] ddr_ba , inout ddr_cas_n , inout ddr_ck_n , inout ddr_ck_p , inout ddr_cke , inout ddr_cs_n , inout [ 3:0] ddr_dm , inout [31:0] ddr_dq , inout [ 3:0] ddr_dqs_n , inout [ 3:0] ddr_dqs_p , inout ddr_odt , inout ddr_ras_n , inout ddr_reset_n , inout ddr_we_n , // fixed-io inout fixed_io_ddr_vrn , inout fixed_io_ddr_vrp , inout [53:0] fixed_io_mio , inout fixed_io_ps_clk , inout fixed_io_ps_porb , inout fixed_io_ps_srstb ); //////////////////////////////////////////////////////////////////////////////// /////////////////////////// System Clock Generation //////////////////////////// //////////////////////////////////////////////////////////////////////////////// // global reset wire sys_rst ; // global reset signal, active high wire ant_rst ; // phased-array & rf control reset signal, active high // pl signal processing clock wire sys_clk ; // 48MHz 41.6667MHz wire sys_clk_2x ; // 96MHz 83.3333MHz wire sys_clk_3x ; // 144MHz 125MHz wire sys_clk_4x ; // 192MHz 166.6667MHz wire sys_clk_ld ; // system main clock locked indicator // ad9361-1 clocks wire ad9361_1_clk ; // 48MHz 41.6667MHz wire ad9361_1_clk_2x ; // 96MHz 83.3333MHz wire ad9361_1_clk_3x ; // 144MHz 125MHz wire ad9361_1_clk_4x ; // 192MHz 166.6667MHz wire ad9361_1_clk_ld ; // ad9361-1 clock group locked indicator // ad9361-2 clocks wire ad9361_2_clk ; // 48MHz 41.6667MHz wire ad9361_2_clk_2x ; // 96MHz 83.3333MHz wire ad9361_2_clk_3x ; // 144MHz 125MHz wire ad9361_2_clk_4x ; // 192MHz 166.6667MHz wire ad9361_2_clk_ld ; // ad9361-2 clock group locked indicator // phased-array & rf control clocks wire clk_96m ; wire clk_48m ; wire clk_32m ; wire clk_19p2m ; clk_dist u_clk_dist ( // input clocks .clk_250m_p (clk_250m_p ), // generated by ad9516, 250mhz .clk_250m_n (clk_250m_n ), .ad9361_1_rx_data_clk(ad9361_1_rx_data_clk), // ad9361 rx data clock, 83.3333mhz .ad9361_2_rx_data_clk(ad9361_2_rx_data_clk), // ad9361 rx data clock, 83.3333mhz // output clocks & reset // global reset .sys_rst (sys_rst ), // global reset signal, active high .ant_rst (ant_rst ), // phased-array & rf control reset signal, active high // pl signal processing clock .sys_clk (sys_clk ), // 48MHz 41.6667MHz .sys_clk_2x (sys_clk_2x ), // 96MHz 83.3333MHz .sys_clk_3x (sys_clk_3x ), // 144MHz 125MHz .sys_clk_4x (sys_clk_4x ), // 192MHz 166.6667MHz .sys_clk_ld (sys_clk_ld ), // system main clock locked indicator // ad9361-1 clocks .ad9361_1_clk (ad9361_1_clk ), // 48MHz 41.6667MHz .ad9361_1_clk_2x (ad9361_1_clk_2x ), // 96MHz 83.3333MHz .ad9361_1_clk_3x (ad9361_1_clk_3x ), // 144MHz 125MHz .ad9361_1_clk_4x (ad9361_1_clk_4x ), // 192MHz 166.6667MHz .ad9361_1_clk_ld (ad9361_1_clk_ld ), // ad9361-1 clock group locked indicator // ad9361-2 clocks .ad9361_2_clk (ad9361_2_clk ), // 48MHz 41.6667MHz .ad9361_2_clk_2x (ad9361_2_clk_2x ), // 96MHz 83.3333MHz .ad9361_2_clk_3x (ad9361_2_clk_3x ), // 144MHz 125MHz .ad9361_2_clk_4x (ad9361_2_clk_4x ), // 192MHz 166.6667MHz .ad9361_2_clk_ld (ad9361_2_clk_ld ), // ad9361-2 clock group locked indicator // phased-array & rf control clocks .clk_96m (clk_96m ), .clk_48m (clk_48m ), .clk_32m (clk_32m ), .clk_19p2m (clk_19p2m ) ); //////////////////////////////////////////////////////////////////////////////// //////////////////////////// Block Design Interface //////////////////////////// //////////////////////////////////////////////////////////////////////////////// // gpio wire [47:0] gpio_i; wire [47:0] gpio_o; wire [47:0] gpio_t; wire ad9361_rx_fifo_rst; assign gpio_i[47:39] = gpio_o[47:39]; // hmc7044 assign hmc7044_reset = gpio_o[ 0]; // hmc7044 reset assign hmc7044_sync = gpio_o[ 1]; // hmc7044 multichip synchronization assign hmc7044_gpio[0] = gpio_t[ 2] ? gpio_i[ 2] : gpio_o[ 2]; assign hmc7044_gpio[1] = gpio_t[ 3] ? gpio_i[ 3] : gpio_o[ 3]; assign hmc7044_gpio[2] = gpio_t[ 4] ? gpio_i[ 4] : gpio_o[ 4]; assign hmc7044_gpio[3] = gpio_t[ 5] ? gpio_i[ 5] : gpio_o[ 5]; // ad9361-1 assign ad9361_1_txnrx = gpio_o[ 6]; // ad9361 enable state machine control assign ad9361_1_enable = gpio_o[ 7]; // ad9361 enable state machine control assign ad9361_1_en_agc = gpio_o[ 8]; // ad9361 agc control assign ad9361_1_reset_b = gpio_o[ 9]; // ad9361 reset assign ad9361_1_ctrl_out = gpio_o[17:10]; assign gpio_i[21:18] = ad9361_1_ctrl_in; // ad9361-2 assign ad9361_2_txnrx = gpio_o[22]; // ad9361 enable state machine control assign ad9361_2_enable = gpio_o[23]; // ad9361 enable state machine control assign ad9361_2_en_agc = gpio_o[24]; // ad9361 agc control assign ad9361_2_reset_b = gpio_o[25]; // ad9361 reset assign ad9361_2_ctrl_out = gpio_o[33:26]; assign gpio_i[37:34] = ad9361_2_ctrl_in; // ad9361 rx fifo reset assign ad9361_rx_fifo_rst= gpio_o[38]; // spi interface wire spi_sclk ; wire [ 2:0] spi_cs ; reg spi_sdi ; wire spi_sdo ; wire spi_sdo_t ; wire spi_three_wire; wire spi_active ; // hmc7044 - three-wire spi assign hmc7044_spi_clk = spi_sclk; assign hmc7044_spi_csn = spi_cs[0]; assign hmc7044_spi_sdio = spi_sdo_t ? 1'bz : spi_sdo; // ad9361-1 - three-wire spi or four-wire spi assign ad9361_1_spi_clk = spi_sclk; assign ad9361_1_spi_csn = spi_cs[1]; assign ad9361_1_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; // ad9361-2 - three-wire spi or four-wire spi assign ad9361_2_spi_clk = spi_sclk; assign ad9361_2_spi_csn = spi_cs[2]; assign ad9361_2_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; // select sdi signal always @(*) begin if (~hmc7044_spi_csn) spi_sdi = hmc7044_spi_sdio; else if (~ad9361_1_spi_csn) spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso; else if (~ad9361_2_spi_csn) spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso; else spi_sdi = 1'bz; end // ps clock wire ps_clk_50M; wire ps_clk_200M; system_bd_wrapper u_system_bd_wrapper ( // ddr .ddr_addr (ddr_addr ), // inout [14:0]ddr_addr .ddr_ba (ddr_ba ), // inout [2:0]ddr_ba .ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n .ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n .ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p .ddr_cke (ddr_cke ), // inout ddr_cke .ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n .ddr_dm (ddr_dm ), // inout [3:0]ddr_dm .ddr_dq (ddr_dq ), // inout [31:0]ddr_dq .ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n .ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p .ddr_odt (ddr_odt ), // inout ddr_odt .ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n .ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n .ddr_we_n (ddr_we_n ), // inout ddr_we_n // fixed-io .fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn .fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp .fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio .fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk .fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb .fixed_io_ps_srstb (fixed_io_ps_srstb ), // inout fixed_io_ps_srstb // gpio, for control signals .gpio_i (gpio_i ), // input [47:0]gpio_i .gpio_o (gpio_o ), // output [47:0]gpio_o .gpio_t (gpio_t ), // output [47:0]gpio_t // spi interface .spi_sclk (spi_sclk ), // output spi_sclk .spi_cs (spi_cs ), // output [2:0]spi_cs .spi_sdi (spi_sdi ), // input [0:0]spi_sdi .spi_sdo (spi_sdo ), // output spi_sdo .spi_sdo_t (spi_sdo_t ), // output spi_sdo_t .spi_three_wire (spi_three_wire ), // output spi_three_wire .spi_active (spi_active ), // output spi_active // ps clock .ps_clk_50M (ps_clk_50M ), // output ps_clk_50M .ps_clk_200M (ps_clk_200M ) // output ps_clk_200M ); //////////////////////////////////////////////////////////////////////////////// ////////////////////////////////// Tx Signal /////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// // baseband signal wire [11:0] tx_data_i; wire [11:0] tx_data_q; ad9361_tx_map_cmos_dual u_ad9361_tx_map ( .clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in .clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst .tx_data_clk (sys_clk ), // input tx_data_clk .tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst .tx_ch1_i (tx_data_i ), // input [11:0] tx_ch1_i .tx_ch1_q (tx_data_q ), // input [11:0] tx_ch1_q .tx_ch2_i (tx_data_i ), // input [11:0] tx_ch2_i .tx_ch2_q (tx_data_q ), // input [11:0] tx_ch2_q .clk_out (ad9361_1_tx_fb_clk ), // output clk_out .tx_frame (ad9361_1_tx_frame ), // output tx_frame .tx_data (ad9361_1_tx_data ) // output [11:0] tx_data ); assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk; // assign ad9361_2_tx_frame = ad9361_1_tx_frame ; // assign ad9361_2_tx_data = ad9361_1_tx_data ; // <---------------------------------------------------------------------------> // <--------------------- insert transmitter logic below ----------------------> // <---------------------------------------------------------------------------> wire [ 1:0] waveform_sel; wire sweep_on ; wire [31:0] freq_set ; wire [ 1:0] iq_sel ; wire [ 3:0] bb_rshift ; tx_qpsk u_tx_qpsk ( .clk (sys_clk ), // input clk .rst (sys_rst ), // input rst .tx_data_i (tx_data_i ), // output [11:0] tx_data_i .tx_data_q (tx_data_q ), // output [11:0] tx_data_q // debug ports .waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel .sweep_on (sweep_on ), // input sweep_on .freq_set (freq_set ), // input [31:0] freq_set .iq_sel (iq_sel ), // input [ 1:0] iq_sel .bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift ); //////////////////////////////////////////////////////////////////////////////// ////////////////////////////////// RF control ////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// ////////////////////////////////// Rx Signals ////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// wire [11:0] rx_ch1_i, rx_ch1_q; wire [11:0] rx_ch2_i, rx_ch2_q; wire [11:0] rx_ch3_i, rx_ch3_q; wire [11:0] rx_ch4_i, rx_ch4_q; ad9361_rx_map_cmos_dual u_ad9361_1_rx_map ( .clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in .clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst .rx_data_clk (sys_clk ), // input rx_data_clk .rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst .rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst .rx_frame (ad9361_1_rx_frame ), // input rx_frame .rx_data (ad9361_1_rx_data ), // input [11:0] rx_data .rx_ch1_i (rx_ch1_i ), // output [11:0] rx_ch1_i .rx_ch1_q (rx_ch1_q ), // output [11:0] rx_ch1_q .rx_ch2_i (rx_ch2_i ), // output [11:0] rx_ch2_i .rx_ch2_q (rx_ch2_q ) // output [11:0] rx_ch2_q ); ad9361_rx_map_cmos_dual u_ad9361_2_rx_map ( .clk_2x_in (ad9361_2_clk_2x ), // input clk_2x_in .clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst .rx_data_clk (sys_clk ), // input rx_data_clk .rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst .rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst .rx_frame (ad9361_2_rx_frame ), // input rx_frame .rx_data (ad9361_2_rx_data ), // input [11:0] rx_data .rx_ch1_i (rx_ch3_i ), // output [11:0] rx_ch1_i .rx_ch1_q (rx_ch3_q ), // output [11:0] rx_ch1_q .rx_ch2_i (rx_ch4_i ), // output [11:0] rx_ch2_i .rx_ch2_q (rx_ch4_q ) // output [11:0] rx_ch2_q ); // <---------------------------------------------------------------------------> // <----------------------- insert receiver logic below -----------------------> // <---------------------------------------------------------------------------> //////////////////////////////////////////////////////////////////////////////// //////////////////////////////// ILAs and VIOs ///////////////////////////////// //////////////////////////////////////////////////////////////////////////////// ila_2x12x131072 u_ila_tx ( .clk (sys_clk ), // input wire clk .probe0 (tx_data_i ), // input wire [11:0] probe0 .probe1 (tx_data_q ) // input wire [11:0] probe1 ); ila_8x12x131072 u_ila_rx ( .clk (sys_clk ), // input wire clk .probe0 (rx_ch1_i ), // input wire [11:0] probe0 .probe1 (rx_ch1_q ), // input wire [11:0] probe1 .probe2 (rx_ch2_i ), // input wire [11:0] probe2 .probe3 (rx_ch2_q ), // input wire [11:0] probe3 .probe4 (rx_ch3_i ), // input wire [11:0] probe4 .probe5 (rx_ch3_q ), // input wire [11:0] probe5 .probe6 (rx_ch4_i ), // input wire [11:0] probe6 .probe7 (rx_ch4_q ) // input wire [11:0] probe7 ); vio_manual_ctrl u_vio_manual_ctrl ( .clk (sys_clk ), // input wire clk .probe_out0 (waveform_sel ), // output wire [1 : 0] probe_out0 .probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1 .probe_out2 (freq_set ), // output wire [31 : 0] probe_out2 .probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3 .probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4 ); endmodule