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:vivado.xilinx.com:synthesis Verilog axi_adxcvr xilinx_anylanguagesynthesis_view_fileset viewChecksum 626f765e xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation Verilog axi_adxcvr xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 626f765e xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 31222add xilinx_blockdiagram Block Diagram :vivado.xilinx.com:block.diagram xilinx_blockdiagram_view_fileset up_cm_enb_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_cm_addr_0 out 11 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_cm_wr_0 out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_cm_wdata_0 out 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation up_cm_rdata_0 in 15 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 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std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation ID Id 0 NUM_OF_LANES Num Of Lanes 8 XCVR_TYPE Xcvr Type 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 FPGA_VOLTAGE Fpga Voltage 0 TX_OR_RX_N Tx Or Rx N 0 QPLL_ENABLE Qpll Enable 1 LPM_OR_DFE_N Lpm Or Dfe N 1 RATE Rate "000" TX_DIFFCTRL Tx Diffctrl "01000" TX_POSTCURSOR Tx Postcursor "00000" TX_PRECURSOR Tx Precursor "00000" SYS_CLK_SEL Sys Clk Sel "11" OUT_CLK_SEL Out Clk Sel "100" choice_list_74b5137e ACTIVE_HIGH ACTIVE_LOW choice_pairs_07421b06 0 1 2 3 4 5 6 7 8 9 10 choice_pairs_38e7dd38 0 1 2 3 4 choice_pairs_68effc1b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 choice_pairs_a535243b 0 10 11 12 13 14 20 21 22 30 choice_pairs_aee923ef 0 1 2 3 xilinx_anylanguagesynthesis_view_fileset axi_adxcvr_es.v verilogSource axi_adxcvr_mdrp.v verilogSource axi_adxcvr_mstatus.v verilogSource axi_adxcvr_up.v verilogSource ../../common/up_axi.v verilogSource ../../scripts/adi_xilinx_device_info_enc.tcl tclSource axi_adxcvr.v verilogSource CHECKSUM_2a1a246b xilinx_anylanguagebehavioralsimulation_view_fileset axi_adxcvr_es.v verilogSource axi_adxcvr_mdrp.v verilogSource axi_adxcvr_mstatus.v verilogSource axi_adxcvr_up.v verilogSource ../../common/up_axi.v verilogSource ../../scripts/adi_xilinx_device_info_enc.tcl tclSource axi_adxcvr.v verilogSource xilinx_xpgui_view_fileset xgui/axi_adxcvr_v1_0.tcl tclSource CHECKSUM_68b2c083 XGUI_VERSION_2 xilinx_blockdiagram_view_fileset bd/bd.tcl tclSource axi_adxcvr_v1_0 ID Id 0 NUM_OF_LANES Num Of Lanes 8 XCVR_TYPE Xcvr Type 0 FPGA_TECHNOLOGY Fpga Technology 0 FPGA_FAMILY Fpga Family 0 SPEED_GRADE Speed Grade 0 DEV_PACKAGE Dev Package 0 FPGA_VOLTAGE Fpga Voltage 0 TX_OR_RX_N Tx Or Rx N 0 QPLL_ENABLE Qpll Enable 1 LPM_OR_DFE_N Lpm Or Dfe N 1 RATE Rate "000" TX_DIFFCTRL Tx Diffctrl "01000" TX_POSTCURSOR Tx Postcursor "00000" TX_PRECURSOR Tx Precursor "00000" SYS_CLK_SEL Sys Clk Sel "11" OUT_CLK_SEL Out Clk Sel "100" Component_Name axi_adxcvr_v1_0 virtex7 aartix7 akintex7 artix7 artix7l aspartan7 azynq azynquplus kintex7 kintex7l kintexu kintexuplus qartix7 qkintex7 qkintex7l qkintexu qkintexuplus qrkintexu qvirtex7 qvirtexuplus qzynq qzynquplus qzynquplusRFSOC spartan7 virtexu virtexuplus virtexuplus58g virtexuplusHBM zynq zynquplus zynquplusRFSOC /Analog_Devices axi_adxcvr_v1_0 package_project Analog Devices http://www.analog.com 1 2021-12-08T12:25:35Z 2019.1.3