`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2023/03/06 16:15:00
// Design Name:
// Module Name: tx_control
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module tx_control
(
    input           clk         ,
    input           rst         ,
    output  [11:0]  tx_data_i   ,
    output  [11:0]  tx_data_q   ,
    // debug ports
    input   [ 2:0]  waveform_sel,
    input           sweep_on    ,
    input   [31:0]  freq_set    ,
    input   [ 1:0]  iq_sel      ,
    input   [ 3:0]  bb_rshift
);

wire [11:0] gmsk_12m_i, gmsk_12m_q;
wire [11:0] gmsk_1p5m_i, gmsk_1p5m_q;
wire [11:0] qpsk_i, qpsk_q;

GMSK_send u_GMSK_send
(
    .clk_48M        (clk                ),
    .rst            (rst                ),
    .gmsk_12M_i     (gmsk_12m_i         ),
    .gmsk_12M_q     (gmsk_12m_q         ),
    .gmsk_1p5m_i    (gmsk_1p5m_i        ),
    .gmsk_1p5m_q    (gmsk_1p5m_q        )
);

tx_qpsk u_tx_qpsk
(
    .clk            (clk                ), // input           clk
    .rst            (rst                ), // input           rst
    .tx_data_i      (qpsk_i             ), // output  [11:0]  tx_data_i
    .tx_data_q      (qpsk_q             ), // output  [11:0]  tx_data_q
    // debug ports
    .waveform_sel   (waveform_sel[1:0]  ), // input   [ 1:0]  waveform_sel
    .sweep_on       (sweep_on           ), // input           sweep_on
    .freq_set       (freq_set           ), // input   [31:0]  freq_set
    .iq_sel         (iq_sel             ), // input   [ 1:0]  iq_sel
    .bb_rshift      (bb_rshift          )  // input   [ 3:0]  bb_rshift
);

// tx buf
reg [11:0] tx_data_i_buf = 'b0;
reg [11:0] tx_data_q_buf = 'b0;

assign tx_data_i = tx_data_i_buf;
assign tx_data_q = tx_data_q_buf;

always @(posedge clk) begin
    if (rst) begin
        tx_data_i_buf <= 'b0;
        tx_data_q_buf <= 'b0;
    end
    else casex (waveform_sel)
        3'b10x: begin
            tx_data_i_buf <= gmsk_12m_i;
            tx_data_q_buf <= gmsk_12m_q;
        end
        3'b11x: begin
            tx_data_i_buf <= gmsk_1p5m_i;
            tx_data_q_buf <= gmsk_1p5m_q;
        end
        default: begin
            tx_data_i_buf <= qpsk_i;
            tx_data_q_buf <= qpsk_q;
        end
    endcase
end

endmodule