Archived
281 lines
9.0 KiB
Verilog
281 lines
9.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_laser_driver_regmap #(
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parameter ID = 0,
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parameter LASER_DRIVER_ID = 1 )(
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// control and status signals
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input clk,
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output driver_en_n,
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input driver_otw_n,
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input pulse,
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output reg irq,
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input [31:0] up_ext_clk_count,
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// TIA sequencer
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output sequence_en,
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output auto_sequence,
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output [31:0] sequence_offset,
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output [ 1:0] auto_seq0,
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output [ 1:0] auto_seq1,
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output [ 1:0] auto_seq2,
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output [ 1:0] auto_seq3,
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output [ 7:0] manual_select,
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// processor interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [13:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [13:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack
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);
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// internal registers
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reg up_driver_en_n = 1'b0;
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reg [2:0] up_irq_mask = 3'b111;
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reg [2:0] up_irq_source = 3'b000;
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reg up_driver_otw_n_int = 1'b1;
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reg up_sequence_en = 1'b0;
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reg up_auto_sequence = 1'b1;
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reg [31:0] up_sequence_offset = 32'b0;
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reg [ 1:0] up_auto_seq0 = 2'b00;
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reg [ 1:0] up_auto_seq1 = 2'b01;
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reg [ 1:0] up_auto_seq2 = 2'b10;
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reg [ 1:0] up_auto_seq3 = 2'b11;
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reg [ 7:0] up_manual_select = 8'h00;
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// internal signals
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wire up_wreq_int_s;
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wire up_rreq_int_s;
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wire up_driver_otw_n_s;
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wire [2:0] up_irq_pending_s;
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wire [2:0] up_irq_trigger_s;
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wire [2:0] up_irq_source_clear_s;
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wire up_pulse_s;
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wire up_driver_otw_n_enter_s;
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wire up_driver_otw_n_exit_s;
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// map the laser driver registers into the address space
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assign up_wreq_int_s = (up_waddr[13:5] == LASER_DRIVER_ID) ? up_wreq : 1'b0;
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assign up_rreq_int_s = (up_raddr[13:5] == LASER_DRIVER_ID) ? up_rreq : 1'b0;
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 1'b0;
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up_driver_en_n <= 1'b1; // by default laser is disabled
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up_irq_mask <= 3'b111;
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up_sequence_en <= 1'b0;
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up_auto_sequence <= 1'b1;
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up_sequence_offset <= 32'h19; // 25*4ns is the default offset for TIA selection
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up_auto_seq0 <= 2'b00;
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up_auto_seq1 <= 2'b01;
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up_auto_seq2 <= 2'b10;
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up_auto_seq3 <= 2'b11;
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up_manual_select <= 8'h00;
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end else begin
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up_wack <= up_wreq_int_s;
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if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
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up_driver_en_n <= up_wdata[0];
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end
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if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin
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up_irq_mask <= up_wdata[2:0];
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end
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if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hB)) begin
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up_sequence_en <= up_wdata[0];
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up_auto_sequence <= up_wdata[1];
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end
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if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hC)) begin
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up_sequence_offset <= up_wdata;
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end
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if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hD)) begin
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up_auto_seq0 <= up_wdata[1:0];
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up_auto_seq1 <= up_wdata[5:4];
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up_auto_seq2 <= up_wdata[9:8];
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up_auto_seq3 <= up_wdata[13:12];
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end
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if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hE)) begin
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up_manual_select <= {up_wdata[13:12],
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up_wdata[9:8],
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up_wdata[5:4],
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up_wdata[1:0]};
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end
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end
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end
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 1'b0;
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up_rdata <= 32'b0;
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end else begin
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up_rack <= up_rreq_int_s;
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if (up_rreq_int_s == 1'b1) begin
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case (up_raddr[4:0])
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5'h00: up_rdata <= {31'h0, up_driver_en_n};
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5'h01: up_rdata <= {31'h0, up_driver_otw_n_s};
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5'h02: up_rdata <= up_ext_clk_count;
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5'h08: up_rdata <= {29'h0, up_irq_mask};
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5'h09: up_rdata <= {29'h0, up_irq_source};
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5'h0A: up_rdata <= {29'h0, up_irq_pending_s};
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5'h0B: up_rdata <= {30'h0, up_auto_sequence, up_sequence_en};
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5'h0C: up_rdata <= up_sequence_offset;
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5'h0D: up_rdata <= {18'h0, up_auto_seq3,
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2'h0, up_auto_seq2,
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2'h0, up_auto_seq1,
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2'h0, up_auto_seq0};
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5'h0E: up_rdata <= {18'h0, up_manual_select[7:6],
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2'h0, up_manual_select[5:4],
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2'h0, up_manual_select[3:2],
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2'h0, up_manual_select[1:0]};
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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assign driver_en_n = up_driver_en_n;
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always @(posedge up_clk) begin
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up_driver_otw_n_int <= up_driver_otw_n_s;
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end
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// negative edge of otw_n - system enters into an over temperature state
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assign up_driver_otw_n_enter_s = ~up_driver_otw_n_s & up_driver_otw_n_int;
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// positive edge of otw_n - system exits from an over temperature state
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assign up_driver_otw_n_exit_s = up_driver_otw_n_s & ~up_driver_otw_n_int;
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// Interrupt handling - it can be generated by a generated pulse or an over
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// temperature warning signal
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assign up_irq_pending_s = ~up_irq_mask & up_irq_source;
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assign up_irq_trigger_s = {up_driver_otw_n_exit_s, up_driver_otw_n_enter_s, up_pulse_s};
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assign up_irq_source_clear_s = (up_wreq_int_s == 1'b1 && up_waddr[3:0] == 4'hA) ? up_wdata[2:0] : 3'b000;
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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irq <= 1'b0;
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end else begin
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irq <= |up_irq_pending_s;
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end
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end
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always @(posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_irq_source <= 3'b000;
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end else begin
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up_irq_source <= up_irq_trigger_s | (up_irq_source & ~up_irq_source_clear_s);
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end
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end
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// CDC logic
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sync_bits #(
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.NUM_OF_BITS (1),
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.ASYNC_CLK (1))
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i_driver_otw_sync (
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.in_bits (driver_otw_n),
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.out_clk (up_clk),
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.out_resetn (1'b1),
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.out_bits (up_driver_otw_n_s));
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sync_bits #(
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.NUM_OF_BITS (1),
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.ASYNC_CLK (1))
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i_pulse_sync (
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.in_bits (pulse),
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.out_clk (up_clk),
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.out_resetn (1'b1),
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.out_bits (up_pulse_s));
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sync_bits #(
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.NUM_OF_BITS (2),
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.ASYNC_CLK (1))
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i_sequence_control_sync (
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.in_bits ({up_auto_sequence, up_sequence_en}),
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.out_clk (clk),
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.out_resetn (1'b1),
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.out_bits ({auto_sequence, sequence_en}));
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sync_bits #(
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.NUM_OF_BITS (16),
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.ASYNC_CLK (1))
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i_sequencer_sync (
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.in_bits ({up_auto_seq3,
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up_auto_seq2,
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up_auto_seq1,
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up_auto_seq0,
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up_manual_select
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}),
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.out_clk (clk),
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.out_resetn (1'b1),
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.out_bits ({auto_seq3,
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auto_seq2,
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auto_seq1,
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auto_seq0,
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manual_select
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}));
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sync_bits #(
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.NUM_OF_BITS (32),
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.ASYNC_CLK (1))
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i_sequence_offset_sync (
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.in_bits (up_sequence_offset),
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.out_clk (clk),
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.out_resetn (1'b1),
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.out_bits (sequence_offset));
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endmodule
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