Archived
251 lines
6.6 KiB
Verilog
251 lines
6.6 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact [email protected] for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_rx_lane_64b #(
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parameter ELASTIC_BUFFER_SIZE = 256
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) (
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input clk,
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input reset,
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input [63:0] phy_data,
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input [1:0] phy_header,
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input phy_block_sync,
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output [63:0] rx_data,
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output reg buffer_ready_n = 'b1,
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input all_buffer_ready_n,
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input buffer_release_n,
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input lmfc_edge,
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output emb_lock,
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input cfg_disable_scrambler,
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input [1:0] cfg_header_mode, // 0 - CRC12 ; 1 - CRC3; 2 - FEC; 3 - CMD
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input [4:0] cfg_rx_thresh_emb_err,
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input [7:0] cfg_beats_per_multiframe,
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input ctrl_err_statistics_reset,
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input [3:0] ctrl_err_statistics_mask,
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output [31:0] status_err_statistics_cnt,
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output [2:0] status_lane_emb_state,
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output reg [7:0] status_lane_skew
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);
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reg [11:0] crc12_calculated_prev;
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wire [63:0] data_descrambled_s;
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wire [63:0] data_descrambled;
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wire [11:0] crc12_received;
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wire [11:0] crc12_calculated;
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wire event_invalid_header;
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wire event_unexpected_eomb;
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wire event_unexpected_eoemb;
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wire event_crc12_mismatch;
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wire err_cnt_rst;
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wire [63:0] rx_data_msb_s;
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wire eomb;
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wire eoemb;
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wire [7:0] sh_count;
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jesd204_rx_header i_rx_header (
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.clk(clk),
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.reset(reset),
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.sh_lock(phy_block_sync),
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.header(phy_header),
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.cfg_header_mode(cfg_header_mode),
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.cfg_rx_thresh_emb_err(cfg_rx_thresh_emb_err),
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.cfg_beats_per_multiframe(cfg_beats_per_multiframe),
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.emb_lock(emb_lock),
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.valid_eomb(eomb),
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.valid_eoemb(eoemb),
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.crc12(crc12_received),
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.crc3(),
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.fec(),
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.cmd(),
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.sh_count(sh_count),
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.status_lane_emb_state(status_lane_emb_state),
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.event_invalid_header(event_invalid_header),
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.event_unexpected_eomb(event_unexpected_eomb),
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.event_unexpected_eoemb(event_unexpected_eoemb)
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);
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jesd204_crc12 i_crc12 (
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.clk(clk),
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.reset(reset),
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.init(eomb),
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.data_in(phy_data),
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.crc12(crc12_calculated)
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);
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reg crc12_on = 'b0;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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crc12_on <= 1'b0;
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end else if (eomb) begin
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crc12_on <= 1'b1;
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end
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end
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reg crc12_rdy = 'b0;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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crc12_rdy <= 1'b0;
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end else if (crc12_on && eomb) begin
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crc12_rdy <= 1'b1;
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end
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end
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always @(posedge clk) begin
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if (eomb) begin
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crc12_calculated_prev <= crc12_calculated;
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end
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end
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assign event_crc12_mismatch = crc12_rdy && eomb && (crc12_calculated_prev != crc12_received);
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assign err_cnt_rst = reset || ctrl_err_statistics_reset;
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error_monitor #(
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.EVENT_WIDTH(4),
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.CNT_WIDTH(32)
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) i_error_monitor (
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.clk(clk),
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.reset(err_cnt_rst),
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.active(1'b1),
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.error_event({
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event_invalid_header,
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event_unexpected_eomb,
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event_unexpected_eoemb,
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event_crc12_mismatch
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}),
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.error_event_mask(ctrl_err_statistics_mask),
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.status_err_cnt(status_err_statistics_cnt)
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);
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jesd204_scrambler_64b #(
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.WIDTH(64),
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.DESCRAMBLE(1)
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) i_descrambler (
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.clk(clk),
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.reset(reset),
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.enable(~cfg_disable_scrambler),
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.data_in(phy_data),
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.data_out(data_descrambled_s)
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);
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pipeline_stage #(
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.WIDTH(64),
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.REGISTERED(1)
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) i_pipeline_stage2 (
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.clk(clk),
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.in({
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data_descrambled_s
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}),
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.out({
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data_descrambled
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})
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);
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// Control when data is written to the elastic buffer
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// Start writing to the buffer when current lane is multiblock locked, but if
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// other lanes are not writing in the next half multiblock period stop
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// writing.
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// This limits the supported lane skew to half of the multiframe
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always @(posedge clk) begin
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if (reset | ~emb_lock) begin
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buffer_ready_n <= 1'b1;
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end else if (sh_count == {1'b0,cfg_beats_per_multiframe[7:1]} && all_buffer_ready_n) begin
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buffer_ready_n <= 1'b1;
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end else if (eoemb) begin
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buffer_ready_n <= 1'b0;
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end
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end
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elastic_buffer #(
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.WIDTH(64),
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.SIZE(ELASTIC_BUFFER_SIZE)
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) i_elastic_buffer (
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.clk(clk),
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.reset(reset),
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.wr_data(data_descrambled),
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.rd_data(rx_data_msb_s),
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.ready_n(buffer_ready_n),
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.do_release_n(buffer_release_n)
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);
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// Measure the delay from the eoemb to the next LMFC edge.
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always @(posedge clk) begin
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if (lmfc_edge) begin
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status_lane_skew <= sh_count;
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end
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end
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/* Reorder octets LSB first */
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genvar i;
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generate
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for (i = 0; i < 64; i = i + 8) begin: g_link_data
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assign rx_data[i+:8] = rx_data_msb_s[64-1-i-:8];
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end
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endgenerate
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endmodule
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