Archived
135 lines
4.6 KiB
Verilog
135 lines
4.6 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact [email protected] for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module soft_pcs_8b10b_sequence_tb;
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parameter VCD_FILE = "soft_pcs_8b10b_sequence_tb.vcd";
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`include "tb_base.v"
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// Send a random sequence of characters to the decoder and make sure the
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// decoder produces the same character sequence and no disparity or
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// not-in-table errors
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wire [9:0] raw_data;
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reg [7:0] encoder_char = 'h00;
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reg encoder_charisk = 1'b0;
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wire [7:0] decoder_char;
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wire decoder_charisk;
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wire decoder_notintable;
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wire decoder_disperr;
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reg encoder_disparity = 1'b0;
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wire encoder_disparity_s;
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reg decoder_disparity = 1'b0;
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wire decoder_disparity_s;
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integer x;
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reg inject_enc_disparity_error = 1'b0;
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/*
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always @(posedge clk) begin
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if ({$random} % 256 == 0) begin
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inject_enc_disparity_error <= 1'b1;
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end else begin
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inject_enc_disparity_error <= 1'b0;
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end
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end
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*/
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always @(posedge clk) begin
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x = {$random} % (256 + 5);
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if (x < 256) begin
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encoder_char <= x & 8'hff;
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encoder_charisk <= 1'b0;
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end else begin
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case (x - 256)
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0: encoder_char <= {3'd0,5'd28};
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1: encoder_char <= {3'd3,5'd28};
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2: encoder_char <= {3'd4,5'd28};
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3: encoder_char <= {3'd5,5'd28};
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4: encoder_char <= {3'd7,5'd28};
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endcase
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encoder_charisk <= 1'b1;
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end
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encoder_disparity <= encoder_disparity_s ^ inject_enc_disparity_error;
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decoder_disparity <= decoder_disparity_s;
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end
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jesd204_8b10b_encoder i_enc (
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.in_char(encoder_char),
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.in_charisk(encoder_charisk),
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.out_char(raw_data),
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.in_disparity(encoder_disparity),
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.out_disparity(encoder_disparity_s)
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);
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jesd204_8b10b_decoder i_dec (
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.in_char(raw_data),
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.out_char(decoder_char),
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.out_notintable(decoder_notintable),
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.out_disperr(decoder_disperr),
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.out_charisk(decoder_charisk),
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.in_disparity(decoder_disparity),
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.out_disparity(decoder_disparity_s)
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);
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wire char_mismatch = encoder_char != decoder_char;
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wire charisk_mismatch = encoder_charisk != decoder_charisk;
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always @(posedge clk) begin
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if (char_mismatch == 1'b1 || charisk_mismatch == 1'b1 ||
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decoder_notintable == 1'b1 || decoder_disperr == 1'b1) begin
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failed <= 1'b1;
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end
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end
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endmodule
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