Archived
79 lines
1.4 KiB
Verilog
79 lines
1.4 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 06/11/2023 03:49:38 PM
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// Design Name:
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// Module Name: tb_var_cal
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_var_cal;
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reg clk = 1'b1;
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reg rst = 1'b1;
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reg cal_start = 1'b0;
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reg cal_auto_en = 1'b0;
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wire cal_busy;
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reg din_valid = 1'b0;
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reg [29:0] din_real = 'b0;
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reg [29:0] din_imag = 'b0;
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wire var_valid;
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wire [31:0] var;
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var_cal u_var_cal
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(
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.clk (clk ),
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.rst (rst ),
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.cal_start (cal_start ),
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.cal_auto_en(cal_auto_en),
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.cal_busy (cal_busy ),
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.din_valid (din_valid ),
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.din_real (din_real ),
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.din_imag (din_imag ),
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.var_valid (var_valid ),
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.var (var )
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);
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integer i;
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integer r_file;
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initial begin
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#102
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rst = 1'b0;
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#100
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din_valid = 1'b1;
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// cal_start = 1'b1;
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cal_auto_en = 1'b1;
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r_file = $fopen("./../../../../../testbenches/singletone.csv","r");
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for (i = 0; i <= 32768; i = i + 1) begin
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@(posedge clk)
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$fscanf(r_file,"%d,%d",din_real,din_imag);
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end
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$fclose(r_file);
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$stop;
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end
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always #10 clk = ~clk;
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endmodule
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