Archived
108 lines
4.2 KiB
Verilog
108 lines
4.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// Transmit HDMI, video dma data in, hdmi separate syncs data out.
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`timescale 1ns/100ps
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module axi_hdmi_tx_es #(
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parameter DATA_WIDTH = 32) (
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// hdmi interface
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input hdmi_clk,
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input hdmi_hs_de,
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input hdmi_vs_de,
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input [(DATA_WIDTH-1):0] hdmi_data_de,
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output reg [(DATA_WIDTH-1):0] hdmi_data);
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localparam BYTE_WIDTH = DATA_WIDTH/8;
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// internal registers
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reg hdmi_hs_de_d = 'd0;
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reg [(DATA_WIDTH-1):0] hdmi_data_d = 'd0;
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reg hdmi_hs_de_2d = 'd0;
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reg [(DATA_WIDTH-1):0] hdmi_data_2d = 'd0;
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reg hdmi_hs_de_3d = 'd0;
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reg [(DATA_WIDTH-1):0] hdmi_data_3d = 'd0;
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reg hdmi_hs_de_4d = 'd0;
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reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0;
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reg hdmi_hs_de_5d = 'd0;
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reg [(DATA_WIDTH-1):0] hdmi_data_5d = 'd0;
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// internal wires
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wire [(DATA_WIDTH-1):0] hdmi_sav_s;
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wire [(DATA_WIDTH-1):0] hdmi_eav_s;
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// hdmi embedded sync insertion
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assign hdmi_sav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h80}} : {BYTE_WIDTH{8'hab}};
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assign hdmi_eav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h9d}} : {BYTE_WIDTH{8'hb6}};
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always @(posedge hdmi_clk) begin
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hdmi_hs_de_d <= hdmi_hs_de;
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case ({hdmi_hs_de_4d, hdmi_hs_de_3d, hdmi_hs_de_2d,
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hdmi_hs_de_d, hdmi_hs_de})
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5'b11000: hdmi_data_d <= {BYTE_WIDTH{8'h00}};
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5'b11100: hdmi_data_d <= {BYTE_WIDTH{8'h00}};
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5'b11110: hdmi_data_d <= {BYTE_WIDTH{8'hff}};
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5'b10000: hdmi_data_d <= hdmi_eav_s;
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default: hdmi_data_d <= hdmi_data_de;
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endcase
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hdmi_hs_de_2d <= hdmi_hs_de_d;
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hdmi_data_2d <= hdmi_data_d;
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hdmi_hs_de_3d <= hdmi_hs_de_2d;
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hdmi_data_3d <= hdmi_data_2d;
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hdmi_hs_de_4d <= hdmi_hs_de_3d;
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hdmi_data_4d <= hdmi_data_3d;
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hdmi_hs_de_5d <= hdmi_hs_de_4d;
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hdmi_data_5d <= hdmi_data_4d;
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case ({hdmi_hs_de_5d, hdmi_hs_de_4d, hdmi_hs_de_3d,
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hdmi_hs_de_2d, hdmi_hs_de_d})
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5'b00111: hdmi_data <= {BYTE_WIDTH{8'h00}};
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5'b00011: hdmi_data <= {BYTE_WIDTH{8'h00}};
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5'b00001: hdmi_data <= {BYTE_WIDTH{8'hff}};
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5'b01111: hdmi_data <= hdmi_sav_s;
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default: hdmi_data <= hdmi_data_5d;
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endcase
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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