Archived
42 lines
929 B
Tcl
42 lines
929 B
Tcl
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create util_axis_fifo
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adi_ip_files util_axis_fifo [list \
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"address_gray.v" \
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"address_gray_pipelined.v" \
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"address_sync.v" \
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"../common/ad_mem.v" \
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"util_axis_fifo.v" \
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]
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adi_ip_properties_lite util_axis_fifo
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adi_ip_add_core_dependencies { \
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analog.com:user:util_cdc:1.0 \
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}
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adi_add_bus "s_axis" "slave" \
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"xilinx.com:interface:axis_rtl:1.0" \
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"xilinx.com:interface:axis:1.0" \
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{
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{"s_axis_valid" "TVALID"} \
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{"s_axis_ready" "TREADY"} \
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{"s_axis_data" "TDATA"} \
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}
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adi_add_bus "m_axis" "master" \
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"xilinx.com:interface:axis_rtl:1.0" \
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"xilinx.com:interface:axis:1.0" \
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{
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{"m_axis_valid" "TVALID"} \
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{"m_axis_ready" "TREADY"} \
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{"m_axis_data" "TDATA"} \
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}
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adi_add_bus_clock "m_axis_aclk" "m_axis" "m_axis_aresetn"
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adi_add_bus_clock "s_axis_aclk" "s_axis" "m_axis_aresetn"
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ipx::save_core [ipx::current_core]
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