Archived
139 lines
4.4 KiB
Verilog
139 lines
4.4 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 2023/02/25 15:20:22
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// Design Name:
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// Module Name: tx_pre_process
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tx_pre_process
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#(
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parameter ADC_DATA_WIDTH = 12,
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parameter PRBS = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)]
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parameter PRBS_LEN = 128, // length of pseudorandom bit sequence
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parameter INTERP_FACTOR = 8, // interpolation factor, max inter-channel delay ranges in [-INTERP_FACTOR+1,INTERP_FACTOR-1]
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parameter CAL_MOD_FINE = 1
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)
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(
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// clock & reset
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input clk ,
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input rst ,
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// input data
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input [ADC_DATA_WIDTH-1:0] tx_data_ch1_i ,
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input [ADC_DATA_WIDTH-1:0] tx_data_ch1_q ,
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input [ADC_DATA_WIDTH-1:0] tx_data_ch2_i ,
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input [ADC_DATA_WIDTH-1:0] tx_data_ch2_q ,
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// ad9361 calibration interface
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input ad9361_tx_switch ,
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//
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input [$clog2(ADC_DATA_WIDTH)-1:0] bb_rshift,
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// output data
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output [ADC_DATA_WIDTH-1:0] tx_ch1_i ,
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output [ADC_DATA_WIDTH-1:0] tx_ch1_q ,
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output [ADC_DATA_WIDTH-1:0] tx_ch2_i ,
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output [ADC_DATA_WIDTH-1:0] tx_ch2_q
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);
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integer i;
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// square shaped bpsk signal
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reg [$clog2(PRBS_LEN*INTERP_FACTOR)-1 : 0] chip_interp_cnt = 'b0;
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reg signed [ADC_DATA_WIDTH-1:0] tx_pn_i = 'b0;
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reg signed [ADC_DATA_WIDTH-1:0] tx_pn_q = 'b0;
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if (CAL_MOD_FINE == 1) begin
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always @(posedge clk) begin
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if (rst) begin
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chip_interp_cnt <= 'b0;
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end
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else begin
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chip_interp_cnt <= chip_interp_cnt + 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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tx_pn_i <= 'b0;
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tx_pn_q <= 'b0;
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end
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else begin
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tx_pn_i <= PRBS[chip_interp_cnt[$clog2(PRBS_LEN*INTERP_FACTOR)-1 -: $clog2(PRBS_LEN)]] ? {1'b0,{(ADC_DATA_WIDTH-1){1'b1}}} : {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1}; // (1 or 0) ? 4'b0111 : 4'b1001
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tx_pn_q <= PRBS[chip_interp_cnt[$clog2(PRBS_LEN*INTERP_FACTOR)-1 -: $clog2(PRBS_LEN)]] ? {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1} : {1'b0,{(ADC_DATA_WIDTH-1){1'b1}}}; // (1 or 0) ? 4'b1001 : 4'b0111
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end
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end
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end // if (CAL_MOD_FINE == 1)
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// buffer input control signals (clock domain crossing from ps to pl clock domain)
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reg ad9361_tx_switch_d1 = 'b0;
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reg ad9361_tx_switch_d2 = 'b0;
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wire signed [ADC_DATA_WIDTH-1:0] tx_dc_i = {1'b0,{(ADC_DATA_WIDTH-2){1'b1}},1'b1};
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wire signed [ADC_DATA_WIDTH-1:0] tx_dc_q = {1'b1,{(ADC_DATA_WIDTH-2){1'b0}},1'b1};
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always @(posedge clk) begin
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ad9361_tx_switch_d1 <= ad9361_tx_switch;
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ad9361_tx_switch_d2 <= ad9361_tx_switch_d1;
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end
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reg [ADC_DATA_WIDTH-1 : 0] tx_ch1_i_buf = 'b0;
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reg [ADC_DATA_WIDTH-1 : 0] tx_ch1_q_buf = 'b0;
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reg [ADC_DATA_WIDTH-1 : 0] tx_ch2_i_buf = 'b0;
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reg [ADC_DATA_WIDTH-1 : 0] tx_ch2_q_buf = 'b0;
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assign tx_ch1_i = tx_ch1_i_buf;
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assign tx_ch1_q = tx_ch1_q_buf;
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assign tx_ch2_i = tx_ch2_i_buf;
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assign tx_ch2_q = tx_ch2_q_buf;
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always @(posedge clk) begin
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if (rst) begin
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tx_ch1_i_buf <= 'b0;
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tx_ch1_q_buf <= 'b0;
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tx_ch2_i_buf <= 'b0;
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tx_ch2_q_buf <= 'b0;
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end
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else if (ad9361_tx_switch_d2) begin
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if (CAL_MOD_FINE == 1) begin
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tx_ch1_i_buf <= tx_pn_i >>> bb_rshift;
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tx_ch1_q_buf <= tx_pn_q >>> bb_rshift;
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tx_ch2_i_buf <= tx_pn_i >>> bb_rshift;
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tx_ch2_q_buf <= tx_pn_q >>> bb_rshift;
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end // CAL_MOD_FINE == 1
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else begin
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tx_ch1_i_buf <= tx_dc_i >>> bb_rshift;
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tx_ch1_q_buf <= tx_dc_q >>> bb_rshift;
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tx_ch2_i_buf <= tx_dc_i >>> bb_rshift;
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tx_ch2_q_buf <= tx_dc_q >>> bb_rshift;
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end // CAL_MOD_FINE != 1
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end
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else begin
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tx_ch1_i_buf <= tx_data_ch1_i;
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tx_ch1_q_buf <= tx_data_ch1_q;
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tx_ch2_i_buf <= tx_data_ch2_i;
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tx_ch2_q_buf <= tx_data_ch2_q;
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end
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end
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endmodule
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