Archived
82 lines
2.9 KiB
Tcl
82 lines
2.9 KiB
Tcl
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package require qsys
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_intel.tcl
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set_module_property NAME axi_laser_driver
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set_module_property DESCRIPTION "AXI Laser Driver IP for Lidar prototyping platform "
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME axi_laser_driver
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# source files
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ad_ip_files axi_laser_driver [list \
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"$ad_hdl_dir/library/util_cdc/sync_bits.v" \
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"$ad_hdl_dir/library/util_cdc/sync_event.v" \
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"$ad_hdl_dir/library/common/ad_rst.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/common/up_clock_mon.v" \
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"$ad_hdl_dir/library/common/util_pulse_gen.v" \
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"$ad_hdl_dir/library/axi_pulse_gen/axi_pulse_gen_regmap.v" \
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"$ad_hdl_dir/library/axi_pulse_gen/axi_pulse_gen_constr.sdc" \
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"axi_laser_driver_constr.sdc" \
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"axi_laser_driver_regmap.v" \
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"axi_laser_driver.v"]
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# IP parameters
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add_parameter ID INTEGER 0
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set_parameter_property ID DEFAULT_VALUE 0
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set_parameter_property ID DISPLAY_NAME "Core ID"
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set_parameter_property ID UNITS None
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set_parameter_property ID HDL_PARAMETER true
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add_parameter ASYNC_CLK_EN INTEGER 0
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set_parameter_property ASYNC_CLK_EN DEFAULT_VALUE 0
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set_parameter_property ASYNC_CLK_EN DISPLAY_NAME "Asynchronous Clocks"
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set_parameter_property ASYNC_CLK_EN DISPLAY_HINT boolean
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set_parameter_property ASYNC_CLK_EN ALLOWED_RANGES { "0:Disabled" "1:Enabled"}
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set_parameter_property ASYNC_CLK_EN HDL_PARAMETER true
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add_parameter PULSE_WIDTH INTEGER 0
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set_parameter_property PULSE_WIDTH DEFAULT_VALUE 0
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set_parameter_property PULSE_WIDTH DISPLAY_NAME "PWM pulse width"
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set_parameter_property PULSE_WIDTH UNITS None
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set_parameter_property PULSE_WIDTH HDL_PARAMETER true
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add_parameter PULSE_PERIOD INTEGER 0
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set_parameter_property PULSE_PERIOD DEFAULT_VALUE 0
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set_parameter_property PULSE_PERIOD DISPLAY_NAME "PWM period"
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set_parameter_property PULSE_PERIOD UNITS None
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set_parameter_property PULSE_PERIOD HDL_PARAMETER true
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# AXI4 Memory Mapped Interface
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ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 15
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# Interrupt interface
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add_interface interrupt_sender interrupt end
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set_interface_property interrupt_sender associatedAddressablePoint s_axi
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set_interface_property interrupt_sender associatedClock s_axi_clock
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set_interface_property interrupt_sender associatedReset s_axi_reset
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set_interface_property interrupt_sender ENABLED true
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set_interface_property interrupt_sender EXPORT_OF ""
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set_interface_property interrupt_sender PORT_NAME_MAP ""
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set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
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set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
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add_interface_port interrupt_sender irq irq Output 1
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# external clock and control/status ports
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ad_interface clock ext_clk input 1
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ad_interface signal driver_en_n output 1
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ad_interface signal driver_pulse output 1
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ad_interface signal driver_otw_n input 1
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ad_interface reset driver_dp_reset output 1 if_ext_clk
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ad_interface signal tia_chsel output 8
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