Archived
311 lines
11 KiB
Verilog
311 lines
11 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_logic_analyzer_reg (
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input clk,
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output reset,
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output [31:0] divider_counter_la,
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output [31:0] divider_counter_pg,
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output [15:0] io_selection,
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output [17:0] edge_detect_enable,
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output [17:0] rise_edge_enable,
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output [17:0] fall_edge_enable,
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output [17:0] low_level_enable,
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output [17:0] high_level_enable,
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output [31:0] fifo_depth,
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output [31:0] trigger_delay,
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output [ 6:0] trigger_logic,
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output clock_select,
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output [15:0] overwrite_enable,
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output [15:0] overwrite_data,
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input [15:0] input_data,
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output [15:0] od_pp_n,
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output [31:0] trigger_holdoff,
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output [19:0] pg_trigger_config,
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input triggered,
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output streaming,
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output [ 9:0] data_delay_control,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [ 4:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [ 4:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack);
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// internal registers
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reg [31:0] up_version = 32'h00020100;
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reg [31:0] up_scratch = 0;
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reg [31:0] up_divider_counter_la = 0;
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reg [31:0] up_divider_counter_pg = 0;
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reg [15:0] up_io_selection = 16'h0;
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reg [17:0] up_edge_detect_enable = 0;
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reg [17:0] up_rise_edge_enable = 0;
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reg [17:0] up_fall_edge_enable = 0;
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reg [17:0] up_low_level_enable = 0;
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reg [17:0] up_high_level_enable = 0;
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reg [31:0] up_fifo_depth = 0;
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reg [31:0] up_trigger_delay = 0;
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reg [ 6:0] up_trigger_logic = 0;
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reg up_clock_select = 0;
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reg [15:0] up_overwrite_enable = 0;
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reg [15:0] up_overwrite_data = 0;
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reg [15:0] up_od_pp_n = 0;
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reg [31:0] up_trigger_holdoff = 32'h0;
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reg [19:0] up_pg_trigger_config = 20'h0;
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reg up_triggered = 0;
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reg up_streaming = 0;
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reg [ 9:0] up_data_delay_control = 10'd0;
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wire [15:0] up_input_data;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_divider_counter_la <= 'd0;
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up_divider_counter_pg <= 'd0;
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up_edge_detect_enable <= 'd0;
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up_rise_edge_enable <= 'd0;
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up_fall_edge_enable <= 'd0;
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up_low_level_enable <= 'd0;
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up_high_level_enable <= 'd0;
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up_fifo_depth <= 'd0;
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up_trigger_delay <= 'd0;
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up_trigger_logic <= 'd0;
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up_clock_select <= 'd0;
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up_overwrite_enable <= 'd0;
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up_overwrite_data <= 'd0;
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up_io_selection <= 16'h0;
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up_od_pp_n <= 16'h0;
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up_triggered <= 1'd0;
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up_streaming <= 1'd0;
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up_trigger_holdoff <= 32'h0;
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up_pg_trigger_config <= 20'd0;
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up_data_delay_control <= 10'h0;
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end else begin
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up_wack <= up_wreq;
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h2)) begin
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up_divider_counter_la <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h3)) begin
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up_divider_counter_pg <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h4)) begin
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up_io_selection <= up_wdata[15:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h5)) begin
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up_edge_detect_enable <= up_wdata[17:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h6)) begin
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up_rise_edge_enable <= up_wdata[17:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h7)) begin
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up_fall_edge_enable <= up_wdata[17:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h8)) begin
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up_low_level_enable <= up_wdata[17:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h9)) begin
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up_high_level_enable <= up_wdata[17:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'ha)) begin
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up_fifo_depth <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hb)) begin
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up_trigger_logic <= up_wdata[6:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hc)) begin
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up_clock_select <= up_wdata[0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hd)) begin
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up_overwrite_enable <= up_wdata[15:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'he)) begin
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up_overwrite_data <= up_wdata[15:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
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up_od_pp_n <= up_wdata[15:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
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up_trigger_delay <= up_wdata;
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end
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if (triggered == 1'b1) begin
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up_triggered <= 1'b1;
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end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
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up_triggered <= up_triggered & ~up_wdata[0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
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up_streaming <= up_wdata[0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin
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up_trigger_holdoff <= up_wdata[31:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h15)) begin
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up_pg_trigger_config <= up_wdata[19:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h16)) begin
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up_data_delay_control <= up_wdata[9:0];
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq;
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if (up_rreq == 1'b1) begin
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case (up_raddr[4:0])
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5'h0: up_rdata <= up_version;
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5'h1: up_rdata <= up_scratch;
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5'h2: up_rdata <= up_divider_counter_la;
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5'h3: up_rdata <= up_divider_counter_pg;
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5'h4: up_rdata <= {16'h0,up_io_selection};
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5'h5: up_rdata <= {14'h0,up_edge_detect_enable};
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5'h6: up_rdata <= {14'h0,up_rise_edge_enable};
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5'h7: up_rdata <= {14'h0,up_fall_edge_enable};
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5'h8: up_rdata <= {14'h0,up_low_level_enable};
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5'h9: up_rdata <= {14'h0,up_high_level_enable};
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5'ha: up_rdata <= up_fifo_depth;
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5'hb: up_rdata <= {25'h0,up_trigger_logic};
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5'hc: up_rdata <= {31'h0,up_clock_select};
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5'hd: up_rdata <= {16'h0,up_overwrite_enable};
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5'he: up_rdata <= {16'h0,up_overwrite_data};
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5'hf: up_rdata <= {16'h0,up_input_data};
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5'h10: up_rdata <= {16'h0,up_od_pp_n};
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5'h11: up_rdata <= up_trigger_delay;
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5'h12: up_rdata <= {31'h0,up_triggered};
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5'h13: up_rdata <= {31'h0,up_streaming};
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5'h14: up_rdata <= up_trigger_holdoff;
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5'h15: up_rdata <= {12'h0,up_pg_trigger_config};
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5'h16: up_rdata <= {22'h0,up_data_delay_control};
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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ad_rst i_core_rst_reg (.rst_async(~up_rstn), .clk(clk), .rstn(), .rst(reset));
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up_xfer_cntrl #(.DATA_WIDTH(353)) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_streaming, // 1
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up_od_pp_n, // 16
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up_overwrite_data, // 16
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up_overwrite_enable, // 16
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up_clock_select, // 1
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up_trigger_logic, // 7
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up_fifo_depth, // 32
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up_trigger_delay, // 32
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up_trigger_holdoff, // 32
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up_high_level_enable, // 18
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up_low_level_enable, // 18
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up_fall_edge_enable, // 18
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up_rise_edge_enable, // 18
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up_edge_detect_enable, // 18
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up_io_selection, // 16
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up_pg_trigger_config, // 20
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up_divider_counter_pg, // 32
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up_divider_counter_la, // 32
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up_data_delay_control}), // 10
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.up_xfer_done (),
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.d_rst (1'b0),
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.d_clk (clk),
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.d_data_cntrl ({ streaming, // 1
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od_pp_n, // 16
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overwrite_data, // 16
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overwrite_enable, // 16
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clock_select, // 1
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trigger_logic, // 7
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fifo_depth, // 32
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trigger_delay, // 32
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trigger_holdoff, // 32
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high_level_enable, // 18
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low_level_enable, // 18
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fall_edge_enable, // 18
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rise_edge_enable, // 18
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edge_detect_enable, // 18
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io_selection, // 16
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pg_trigger_config, // 20
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divider_counter_pg, // 32
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divider_counter_la, // 32
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data_delay_control})); // 10
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up_xfer_status #(.DATA_WIDTH(16)) i_xfer_status (
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// up interface
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.up_rstn(up_rstn),
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.up_clk(up_clk),
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.up_data_status(up_input_data),
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// device interface
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.d_rst(1'd0),
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.d_clk(clk),
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.d_data_status(input_data));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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