Archived
80 lines
2.6 KiB
Verilog
80 lines
2.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_dacfifo_address_buffer #(
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parameter ADDRESS_WIDTH = 4,
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parameter DATA_WIDTH = 16)(
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input clk,
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input rst,
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input wea,
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input [DATA_WIDTH-1:0] din,
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input rea,
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output [DATA_WIDTH-1:0] dout);
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reg [ADDRESS_WIDTH-1:0] waddr;
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reg [ADDRESS_WIDTH-1:0] raddr;
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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waddr <= 0;
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raddr <= 0;
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end else begin
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waddr <= (wea == 1'b1) ? waddr + 1'b1 : waddr;
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raddr <= (rea == 1'b1) ? raddr + 1'b1 : raddr;
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end
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end
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ad_mem #(
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.DATA_WIDTH (DATA_WIDTH),
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.ADDRESS_WIDTH (ADDRESS_WIDTH))
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i_mem (
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.clka (clk),
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.wea (wea),
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.addra (waddr),
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.dina (din),
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.clkb (clk),
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.reb (1'b1),
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.addrb (raddr),
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.doutb (dout));
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endmodule
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