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josh
365a132831
1. 调零算法部分增加调零控制模块,用于各模块互联和状态控制以及数据存储,增加LCMV和DAS选通; 2. Cordic 旋转输入改为保留两个符号位,避免溢出; 3. LCMV快拍数修改为2048; 4. 修改功率计算模块,适配较小数据位宽; 5. 修改在线捕获校准程序自动校准部分VIO初值; 6. 地检新射频发端增加自动频点切换
259 lines
7.6 KiB
Verilog
259 lines
7.6 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 06/11/2023 02:41:47 PM
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// Design Name:
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// Module Name: var_cal
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// 20230730-1427 - 修改输入位宽小于乘法器位宽时的处理，由补零变为符号位扩展；
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// 修改；修改累加和输出截位方式，依托原始数据位宽进行处理。
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module var_cal
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#(
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parameter ACCUM_NUM = 16384,
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parameter DATA_I_WIDTH = 30,
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parameter DATA_O_WIDTH = 32,
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parameter CMPY_I_WIDTH = 18
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)
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(
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input clk ,
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input rst ,
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input cal_start ,
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input cal_auto_en ,
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output cal_busy ,
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input din_valid ,
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input [DATA_I_WIDTH-1 : 0] din_real ,
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input [DATA_I_WIDTH-1 : 0] din_imag ,
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output var_valid ,
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output [DATA_O_WIDTH-1 : 0] var
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);
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integer i;
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localparam CMPY_P_WIDTH = 2*CMPY_I_WIDTH+1;
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localparam AXIS_CMPY_I_WIDTH = 8*((CMPY_I_WIDTH-1)/8+1) ; // axis data width of input real/image data
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localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_WIDTH-1)/8+1); // axis data width of cmpy output real/image data
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localparam CMPY_P_VALID_WIDTH = (DATA_I_WIDTH > CMPY_I_WIDTH) ? 2*CMPY_I_WIDTH : 2*DATA_I_WIDTH;
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localparam ACCUM_WIDTH = CMPY_P_VALID_WIDTH + $clog2(ACCUM_NUM);
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// status control
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reg cal_start_auto = 'b0;
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reg cal_start_d1 = 'b0;
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reg cal_start_d2 = 'b0;
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reg cal_busy_buf = 'b0;
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reg [$clog2(ACCUM_NUM)-1 : 0] cnt_accum = 'b0;
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reg last_data = 'b0;
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reg [6:0] last_data_d = 'b0; // 1 for register input, 6 for cmpy, 1 for register output
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assign cal_busy = cal_busy_buf;
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assign var_valid = last_data_d[6];
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always @(posedge clk) begin
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if (rst) begin
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cal_start_auto <= 'b0;
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end
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else begin
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if (cal_auto_en) begin
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if (~cal_busy_buf) begin
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cal_start_auto <= ~cal_start_auto;
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end
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else begin
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cal_start_auto <= cal_start_auto;
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end
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end
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else begin
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cal_start_auto <= 'b0;
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end
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end
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end
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always @(posedge clk) begin
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cal_start_d1 <= cal_auto_en ? cal_start_auto : cal_start;
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cal_start_d2 <= cal_start_d1;
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end
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always @(posedge clk) begin
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if (rst) begin
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cal_busy_buf <= 'b0;
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end
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else begin
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if ((cal_start_d1 ^ cal_start_d2) && din_valid) begin
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cal_busy_buf <= 1'b1;
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end
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else if (cnt_accum == ACCUM_NUM-1) begin
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cal_busy_buf <= 'b0;
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end
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else begin
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cal_busy_buf <= cal_busy_buf;
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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cnt_accum <= 'b0;
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end
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else begin
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cnt_accum <= cal_busy ? (cnt_accum + 1'b1) : 'b0;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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last_data <= 'b0;
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end
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else begin
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last_data <= (cnt_accum == ACCUM_NUM-1) ? 1'b1 : 1'b0;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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last_data_d[6:0] <= 'b0;
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end
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else begin
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last_data_d[6:0] <= {last_data_d[5:0],last_data};
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end
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end
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// cmpy
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reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_real = 'b0;
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reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_imag = 'b0;
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reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_real = 'b0;
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reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_imag = 'b0;
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wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_real;
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wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_imag;
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wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_real;
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wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_imag;
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if (CMPY_I_WIDTH > DATA_I_WIDTH) begin
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// sign-bit extension to fit cmpy input data width
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always @(posedge clk) begin
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if (rst) begin
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cmpy_a_real <= 'b0;
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cmpy_a_imag <= 'b0;
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cmpy_b_real <= 'b0;
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cmpy_b_imag <= 'b0;
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end
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else begin
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cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
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cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
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cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
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cmpy_b_imag <= (din_imag == {1'b1,{(DATA_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH+1){1'b0}},{(DATA_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
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end
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end
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end
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else begin
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// truncate msb
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always @(posedge clk) begin
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if (rst) begin
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cmpy_a_real <= 'b0;
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cmpy_a_imag <= 'b0;
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cmpy_b_real <= 'b0;
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cmpy_b_imag <= 'b0;
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end
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else begin
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cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
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cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
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cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
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cmpy_b_imag <= (din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH] == {1'b1,{(CMPY_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH+1){1'b0}},{(CMPY_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
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end
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end
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end
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// truncate valid bits
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assign cmpy_p_real = cmpy_p_raw_real[0 +: CMPY_P_VALID_WIDTH];
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assign cmpy_p_imag = cmpy_p_raw_imag[0 +: CMPY_P_VALID_WIDTH];
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wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_a;
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wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_b;
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wire [2*AXIS_CMPY_P_WIDTH-1:0] cmpy_p;
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wire cmpy_p_vld;
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assign cmpy_a = {cmpy_a_imag,cmpy_a_real};
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assign cmpy_b = {cmpy_b_imag,cmpy_b_real};
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assign {cmpy_p_raw_imag,cmpy_p_raw_real} = cmpy_p;
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cmpy_18x18_mult u_cmpy_18x18
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(
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.aclk (clk ), // input wire aclk
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.s_axis_a_tvalid (cal_busy ), // input wire s_axis_a_tvalid
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.s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata
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.s_axis_b_tvalid (cal_busy ), // input wire s_axis_b_tvalid
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.s_axis_b_tdata (cmpy_b ), // input wire [31 : 0] s_axis_b_tdata
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.m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata
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);
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// accumulation
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reg [ACCUM_WIDTH-1 : 0] accum = 'b0;
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reg [DATA_O_WIDTH-1 : 0] var_buf = 'b0;
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assign var = var_buf;
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always @(posedge clk) begin
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if (rst) begin
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accum <= 'b0;
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end
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else begin
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if (cmpy_p_vld) begin
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accum <= accum + cmpy_p_real;
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end
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else begin
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accum <= 'b0;
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end
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end
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end
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if (DATA_O_WIDTH > ACCUM_WIDTH) begin
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// sign-bit extension to fit output data width
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always @(posedge clk) begin
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if (rst) begin
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var_buf <= 'b0;
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end
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else if (last_data_d[5]) begin
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var_buf <= {{(DATA_O_WIDTH-ACCUM_WIDTH){accum[ACCUM_WIDTH-1]}},accum};
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end
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end
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end
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else begin
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// truncate msb
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always @(posedge clk) begin
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if (rst) begin
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var_buf <= 'b0;
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end
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else if (last_data_d[5]) begin
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var_buf <= accum[ACCUM_WIDTH-1 -: DATA_O_WIDTH];
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end
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end
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end
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endmodule
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