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vivado-202401/adi_library/xilinx/util_clkdiv/util_clkdiv_ooc.ttcl
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2023-04-13 13:33:41 +08:00

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<: setFileUsedIn { out_of_context synthesis implementation } :>
<: ;#Component and file information :>
<: set ComponentName [getComponentNameString] :>
<: setOutputDirectory "./" :>
<: setFileName $ComponentName :>
<: setFileExtension "_ooc.xdc" :>
# This XDC is used only for OOC mode of synthesis, implementation.
# These are default values for timing driven synthesis during OOC flow.
# These values will be overwritten during implementation with information
# from top level.
create_clock -name clk -period 10 [get_ports clk]
################################################################################