Archived
289 lines
10 KiB
Verilog
289 lines
10 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adc_trigger_reg (
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input clk,
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output [ 7:0] io_selection,
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output [ 1:0] trigger_o,
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input triggered,
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output [ 1:0] low_level,
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output [ 1:0] high_level,
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output [ 1:0] any_edge,
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output [ 1:0] rise_edge,
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output [ 1:0] fall_edge,
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output [15:0] limit_a,
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output [ 1:0] function_a,
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output [31:0] hysteresis_a,
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output [ 3:0] trigger_l_mix_a,
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output [15:0] limit_b,
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output [ 1:0] function_b,
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output [31:0] hysteresis_b,
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output [ 3:0] trigger_l_mix_b,
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output [16:0] trigger_out_control,
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output [31:0] fifo_depth,
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output [31:0] trigger_delay,
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output [31:0] trigger_holdoff,
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output [19:0] trigger_out_hold_pins,
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output streaming,
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// bus interface
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input up_rstn,
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input up_clk,
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input up_wreq,
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input [ 4:0] up_waddr,
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input [31:0] up_wdata,
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output reg up_wack,
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input up_rreq,
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input [ 4:0] up_raddr,
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output reg [31:0] up_rdata,
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output reg up_rack);
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localparam DEFAULT_OUT_HOLD = 100000; // 1ms
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// internal signals
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wire [ 9:0] config_trigger_i;
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// internal registers
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reg [31:0] up_version = 32'h00030000;
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reg [31:0] up_scratch = 32'h0;
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reg [ 7:0] up_io_selection = 8'h0;
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reg [ 1:0] up_trigger_o = 2'h0;
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reg [ 9:0] up_config_trigger_i = 10'h0;
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reg [15:0] up_limit_a = 16'h0;
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reg [ 1:0] up_function_a = 2'h0;
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reg [31:0] up_hysteresis_a = 32'h0;
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reg [ 3:0] up_trigger_l_mix_a = 4'h0;
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reg [15:0] up_limit_b = 16'h0;
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reg [ 1:0] up_function_b = 2'h0;
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reg [31:0] up_hysteresis_b = 32'h0;
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reg [ 3:0] up_trigger_l_mix_b = 4'h0;
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reg [16:0] up_trigger_out_control = 17'h0;
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reg [31:0] up_fifo_depth = 32'h0;
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reg [31:0] up_trigger_delay = 32'h0;
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reg [31:0] up_trigger_holdoff = 32'h0;
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reg [19:0] up_trigger_out_hold_pins = DEFAULT_OUT_HOLD;
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reg up_triggered = 1'h0;
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reg up_streaming = 1'h0;
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assign low_level = config_trigger_i[1:0];
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assign high_level = config_trigger_i[3:2];
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assign any_edge = config_trigger_i[5:4];
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assign rise_edge = config_trigger_i[7:6];
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assign fall_edge = config_trigger_i[9:8];
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_trigger_o <= 'd0;
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up_io_selection <= 'd1;
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up_config_trigger_i <= 'd0;
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up_limit_a <= 'd0;
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up_function_a <= 'd0;
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up_hysteresis_a <= 'd0;
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up_limit_b <= 'd0;
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up_function_b <= 'd0;
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up_hysteresis_b <= 'd0;
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up_fifo_depth <= 'd0;
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up_trigger_delay <= 'd0;
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up_trigger_l_mix_a <= 'd0;
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up_trigger_l_mix_b <= 'd0;
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up_trigger_out_control <= 'd0;
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up_triggered <= 1'd0;
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up_streaming <= 1'd0;
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up_trigger_holdoff <= 32'h0;
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up_trigger_out_hold_pins <= DEFAULT_OUT_HOLD;
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end else begin
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up_wack <= up_wreq;
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
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up_scratch <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h2)) begin
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up_trigger_o <= up_wdata[1:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h3)) begin
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up_io_selection <= up_wdata[7:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h4)) begin
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up_config_trigger_i <= up_wdata[9:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h5)) begin
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up_limit_a <= up_wdata[15:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h6)) begin
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up_function_a <= up_wdata[1:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h7)) begin
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up_hysteresis_a <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h8)) begin
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up_trigger_l_mix_a <= up_wdata[3:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h9)) begin
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up_limit_b <= up_wdata[15:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'ha)) begin
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up_function_b <= up_wdata[1:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hb)) begin
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up_hysteresis_b <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hc)) begin
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up_trigger_l_mix_b <= up_wdata[3:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hd)) begin
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up_trigger_out_control <= up_wdata[16:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'he)) begin
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up_fifo_depth <= up_wdata;
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end
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if (triggered == 1'b1) begin
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up_triggered <= 1'b1;
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end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hf)) begin
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up_triggered <= up_triggered & ~up_wdata[0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
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up_trigger_delay <= up_wdata;
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
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up_streaming <= up_wdata[0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin
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up_trigger_holdoff <= up_wdata[31:0];
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end
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if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin
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up_trigger_out_hold_pins <= up_wdata[19:0];
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end
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end
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end
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq;
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if (up_rreq == 1'b1) begin
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case (up_raddr[4:0])
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5'h0: up_rdata <= up_version;
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5'h1: up_rdata <= up_scratch;
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5'h2: up_rdata <= {30'h0,up_trigger_o};
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5'h3: up_rdata <= {24'h0,up_io_selection};
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5'h4: up_rdata <= {22'h0,up_config_trigger_i};
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5'h5: up_rdata <= {16'h0,up_limit_a};
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5'h6: up_rdata <= {30'h0,up_function_a};
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5'h7: up_rdata <= up_hysteresis_a;
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5'h8: up_rdata <= {28'h0,up_trigger_l_mix_a};
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5'h9: up_rdata <= {16'h0,up_limit_b};
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5'ha: up_rdata <= {30'h0,up_function_b};
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5'hb: up_rdata <= up_hysteresis_b;
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5'hc: up_rdata <= {28'h0,up_trigger_l_mix_b};
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5'hd: up_rdata <= {15'h0,up_trigger_out_control};
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5'he: up_rdata <= up_fifo_depth;
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5'hf: up_rdata <= {31'h0,up_triggered};
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5'h10: up_rdata <= up_trigger_delay;
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5'h11: up_rdata <= {31'h0,up_streaming};
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5'h12: up_rdata <= up_trigger_holdoff;
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5'h13: up_rdata <= {12'h0,up_trigger_out_hold_pins};
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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up_xfer_cntrl #(.DATA_WIDTH(262)) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_cntrl ({ up_streaming, // 1
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up_trigger_o, // 2
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up_io_selection, // 8
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up_config_trigger_i, // 10
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up_limit_a, // 16
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up_function_a, // 2
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up_hysteresis_a, // 32
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up_trigger_l_mix_a, // 4
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up_limit_b, // 16
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up_function_b, // 2
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up_hysteresis_b, // 32
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up_trigger_l_mix_b, // 4
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up_trigger_out_control, // 17
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up_fifo_depth, // 32
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up_trigger_holdoff, // 32
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up_trigger_out_hold_pins, // 20
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up_trigger_delay}), // 32
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.up_xfer_done (),
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.d_rst (1'b0),
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.d_clk (clk),
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.d_data_cntrl ({ streaming, // 1
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trigger_o, // 2
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io_selection, // 8
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config_trigger_i, // 10
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limit_a, // 16
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function_a, // 2
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hysteresis_a, // 32
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trigger_l_mix_a, // 4
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limit_b, // 16
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function_b, // 2
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hysteresis_b, // 32
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trigger_l_mix_b, // 4
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trigger_out_control, // 17
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fifo_depth, // 32
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trigger_holdoff, // 32
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trigger_out_hold_pins, // 20
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trigger_delay})); // 32
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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