Archived
236 lines
7.2 KiB
Verilog
236 lines
7.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// Transmit HDMI, video dma data in, hdmi separate syncs data out.
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`timescale 1ns/100ps
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module axi_hdmi_tx_vdma (
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// hdmi interface
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input hdmi_fs_toggle,
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input [ 8:0] hdmi_raddr_g,
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// vdma interface
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input vdma_clk,
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input vdma_rst,
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input vdma_end_of_frame,
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input vdma_valid,
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input [63:0] vdma_data,
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output reg vdma_ready,
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output reg vdma_wr,
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output reg [ 8:0] vdma_waddr,
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output reg [47:0] vdma_wdata,
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output reg vdma_fs_ret_toggle,
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output reg [ 8:0] vdma_fs_waddr,
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output reg vdma_tpm_oos,
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output reg vdma_ovf,
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output reg vdma_unf);
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localparam BUF_THRESHOLD_LO = 9'd3;
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localparam BUF_THRESHOLD_HI = 9'd509;
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localparam RDY_THRESHOLD_LO = 9'd450;
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localparam RDY_THRESHOLD_HI = 9'd500;
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// internal registers
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reg vdma_fs_toggle_m1 = 1'd0;
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reg vdma_fs_toggle_m2 = 1'd0;
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reg vdma_fs_toggle_m3 = 1'd0;
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reg [22:0] vdma_tpm_data = 23'd0;
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reg [ 8:0] vdma_raddr_g_m1 = 9'd0;
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reg [ 8:0] vdma_raddr_g_m2 = 9'd0;
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reg [ 8:0] vdma_raddr = 9'd0;
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reg [ 8:0] vdma_addr_diff = 9'd0;
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reg vdma_almost_full = 1'd0;
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reg vdma_almost_empty = 1'd0;
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reg hdmi_fs = 1'd0;
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reg vdma_fs = 1'd0;
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reg vdma_end_of_frame_d = 1'd0;
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reg vdma_active_frame = 1'd0;
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// internal wires
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wire [47:0] vdma_tpm_data_s;
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wire vdma_tpm_oos_s;
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wire [ 9:0] vdma_addr_diff_s;
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wire vdma_ovf_s;
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wire vdma_unf_s;
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// grey to binary conversion
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function [8:0] g2b;
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input [8:0] g;
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reg [8:0] b;
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begin
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b[8] = g[8];
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b[7] = b[8] ^ g[7];
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b[6] = b[7] ^ g[6];
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b[5] = b[6] ^ g[5];
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b[4] = b[5] ^ g[4];
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b[3] = b[4] ^ g[3];
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b[2] = b[3] ^ g[2];
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b[1] = b[2] ^ g[1];
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b[0] = b[1] ^ g[0];
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g2b = b;
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end
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endfunction
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// hdmi frame sync
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always @(posedge vdma_clk) begin
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if (vdma_rst == 1'b1) begin
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vdma_fs_toggle_m1 <= 1'd0;
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vdma_fs_toggle_m2 <= 1'd0;
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vdma_fs_toggle_m3 <= 1'd0;
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end else begin
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vdma_fs_toggle_m1 <= hdmi_fs_toggle;
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vdma_fs_toggle_m2 <= vdma_fs_toggle_m1;
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vdma_fs_toggle_m3 <= vdma_fs_toggle_m2;
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end
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hdmi_fs <= vdma_fs_toggle_m2 ^ vdma_fs_toggle_m3;
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end
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// dma frame sync
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always @(posedge vdma_clk) begin
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if (vdma_rst == 1'b1) begin
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vdma_end_of_frame_d <= 1'b0;
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vdma_fs <= 1'b0;
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end else begin
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vdma_end_of_frame_d <= vdma_end_of_frame;
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vdma_fs <= vdma_end_of_frame_d;
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end
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end
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// sync dma and hdmi frames
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always @(posedge vdma_clk) begin
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if (vdma_rst == 1'b1) begin
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vdma_fs_ret_toggle = 1'b0;
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vdma_fs_waddr <= 9'b0;
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end else begin
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if (vdma_fs) begin
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vdma_fs_ret_toggle <= ~vdma_fs_ret_toggle;
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vdma_fs_waddr <= vdma_waddr ;
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end
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end
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end
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// accept new frame from dma
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always @(posedge vdma_clk) begin
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if (vdma_rst == 1'b1) begin
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vdma_active_frame <= 1'b0;
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end else begin
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if ((vdma_active_frame == 1'b1) && (vdma_end_of_frame == 1'b1)) begin
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vdma_active_frame <= 1'b0;
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end else if ((vdma_active_frame == 1'b0) && (hdmi_fs == 1'b1)) begin
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vdma_active_frame <= 1'b1;
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end
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end
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end
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// vdma write
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always @(posedge vdma_clk) begin
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vdma_wr <= vdma_valid & vdma_ready;
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if (vdma_rst == 1'b1) begin
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vdma_waddr <= 9'd0;
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end else if (vdma_wr == 1'b1) begin
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vdma_waddr <= vdma_waddr + 1'b1;
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end
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vdma_wdata <= {vdma_data[55:32], vdma_data[23:0]};
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end
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// test error conditions
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assign vdma_tpm_data_s = {vdma_tpm_data, 1'b1, vdma_tpm_data, 1'b0};
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assign vdma_tpm_oos_s = (vdma_wdata == vdma_tpm_data_s) ? 1'b0 : vdma_wr;
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always @(posedge vdma_clk) begin
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if ((vdma_rst == 1'b1) || (vdma_fs == 1'b1)) begin
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vdma_tpm_data <= 23'd0;
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vdma_tpm_oos <= 1'd0;
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end else if (vdma_wr == 1'b1) begin
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vdma_tpm_data <= vdma_tpm_data + 1'b1;
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vdma_tpm_oos <= vdma_tpm_oos_s;
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end
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end
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// overflow or underflow status
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assign vdma_addr_diff_s = {1'b1, vdma_waddr} - vdma_raddr;
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assign vdma_ovf_s = (vdma_addr_diff < BUF_THRESHOLD_LO) ? vdma_almost_full : 1'b0;
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assign vdma_unf_s = (vdma_addr_diff > BUF_THRESHOLD_HI) ? vdma_almost_empty : 1'b0;
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always @(posedge vdma_clk) begin
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if (vdma_rst == 1'b1) begin
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vdma_raddr_g_m1 <= 9'd0;
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vdma_raddr_g_m2 <= 9'd0;
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end else begin
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vdma_raddr_g_m1 <= hdmi_raddr_g;
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vdma_raddr_g_m2 <= vdma_raddr_g_m1;
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end
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end
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always @(posedge vdma_clk) begin
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vdma_raddr <= g2b(vdma_raddr_g_m2);
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vdma_addr_diff <= vdma_addr_diff_s[8:0];
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if (vdma_addr_diff >= RDY_THRESHOLD_HI) begin
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vdma_ready <= 1'b0;
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end else if (vdma_addr_diff <= RDY_THRESHOLD_LO) begin
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vdma_ready <= vdma_active_frame;
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end
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if (vdma_addr_diff > BUF_THRESHOLD_HI) begin
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vdma_almost_full <= 1'b1;
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end else begin
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vdma_almost_full <= 1'b0;
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end
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if (vdma_addr_diff < BUF_THRESHOLD_LO) begin
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vdma_almost_empty <= 1'b1;
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end else begin
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vdma_almost_empty <= 1'b0;
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end
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vdma_ovf <= vdma_ovf_s;
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vdma_unf <= vdma_unf_s;
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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