Archived
191 lines
7.4 KiB
Verilog
191 lines
7.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_logic_analyzer_trigger (
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input clk,
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input reset,
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input [15:0] data,
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input data_valid,
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input [ 1:0] trigger_i,
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input trigger_in,
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input [17:0] edge_detect_enable,
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input [17:0] rise_edge_enable,
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input [17:0] fall_edge_enable,
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input [17:0] low_level_enable,
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input [17:0] high_level_enable,
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input [ 6:0] trigger_logic,
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output reg trigger_out,
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output reg trigger_out_adc);
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reg [ 1:0] ext_t_m = 'd0;
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reg [ 1:0] ext_t_low_level_hold = 'd0;
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reg [ 1:0] ext_t_high_level_hold = 'd0;
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reg [ 1:0] ext_t_edge_detect_hold = 'd0;
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reg [ 1:0] ext_t_rise_edge_hold = 'd0;
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reg [ 1:0] ext_t_fall_edge_hold = 'd0;
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reg ext_t_low_level_ack = 'd0;
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reg ext_t_high_level_ack = 'd0;
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reg ext_t_edge_detect_ack = 'd0;
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reg ext_t_rise_edge_ack = 'd0;
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reg ext_t_fall_edge_ack = 'd0;
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reg [ 15:0] data_m1 = 'd0;
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reg [ 15:0] low_level = 'd0;
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reg [ 15:0] high_level = 'd0;
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reg [ 15:0] edge_detect = 'd0;
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reg [ 15:0] rise_edge = 'd0;
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reg [ 15:0] fall_edge = 'd0;
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reg [ 15:0] low_level_m = 'd0;
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reg [ 15:0] high_level_m = 'd0;
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reg [ 15:0] edge_detect_m = 'd0;
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reg [ 15:0] rise_edge_m = 'd0;
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reg [ 15:0] fall_edge_m = 'd0;
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reg trigger_active;
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reg trigger_active_mux;
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reg trigger_active_d1;
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always @(posedge clk) begin
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if (data_valid == 1'b1) begin
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trigger_active_d1 <= trigger_active_mux;
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trigger_out <= trigger_active_d1;
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trigger_out_adc <= trigger_active_mux;
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end
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end
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// trigger logic:
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// 0 OR
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// 1 AND
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always @(posedge clk) begin
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if (data_valid == 1'b1) begin
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case (trigger_logic[0])
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0: trigger_active = |(({ext_t_edge_detect_hold, edge_detect_m} & edge_detect_enable) |
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({ext_t_rise_edge_hold, rise_edge_m} & rise_edge_enable) |
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({ext_t_fall_edge_hold, fall_edge_m} & fall_edge_enable) |
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({ext_t_low_level_hold, low_level_m} & low_level_enable) |
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({ext_t_high_level_hold , high_level_m} & high_level_enable));
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1: trigger_active = &(({ext_t_edge_detect_hold, edge_detect_m} | ~edge_detect_enable) &
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({ext_t_rise_edge_hold, rise_edge_m} | ~rise_edge_enable) &
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({ext_t_fall_edge_hold, fall_edge_m} | ~fall_edge_enable) &
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({ext_t_low_level_hold, low_level_m} | ~low_level_enable) &
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({ext_t_high_level_hold , high_level_m} | ~high_level_enable));
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default: trigger_active = 1'b1;
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endcase
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end
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end
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always @(*) begin
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case (trigger_logic[6:4])
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3'd0: trigger_active_mux = trigger_active;
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3'd1: trigger_active_mux = trigger_in;
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3'd2: trigger_active_mux = trigger_active & trigger_in;
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3'd3: trigger_active_mux = trigger_active | trigger_in;
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3'd4: trigger_active_mux = trigger_active ^ trigger_in;
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3'd7: trigger_active_mux = 1'b0; // trigger disable
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default: trigger_active_mux = 1'b0;
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endcase
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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data_m1 <= 'd0;
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edge_detect <= 'd0;
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rise_edge <= 'd0;
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fall_edge <= 'd0;
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low_level <= 'd0;
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high_level <= 'd0;
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end else begin
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if (data_valid == 1'b1) begin
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data_m1 <= data;
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edge_detect <= data_m1 ^ data;
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rise_edge <= (data_m1 ^ data) & data;
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fall_edge <= (data_m1 ^ data) & ~data;
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low_level <= ~data;
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high_level <= data;
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edge_detect_m <= edge_detect;
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rise_edge_m <= rise_edge;
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fall_edge_m <= fall_edge;
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low_level_m <= low_level;
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high_level_m <= high_level;
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end
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end
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end
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// external trigger detect
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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ext_t_m <= 'd0;
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ext_t_edge_detect_hold <= 'd0;
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ext_t_rise_edge_hold <= 'd0;
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ext_t_fall_edge_hold <= 'd0;
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ext_t_low_level_hold <= 'd0;
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ext_t_high_level_hold <= 'd0;
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end else begin
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ext_t_m <= trigger_i;
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ext_t_edge_detect_hold <= ext_t_edge_detect_ack ? 2'b0 :
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(ext_t_m ^ trigger_i) | ext_t_edge_detect_hold;
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ext_t_rise_edge_hold <= ext_t_rise_edge_ack ? 2'b0 :
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((ext_t_m ^ trigger_i) & trigger_i) | ext_t_rise_edge_hold;
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ext_t_fall_edge_hold <= ext_t_fall_edge_ack ? 2'b0 :
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((ext_t_m ^ trigger_i) & ~trigger_i) | ext_t_fall_edge_hold;
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ext_t_low_level_hold <= ext_t_low_level_ack ? 2'b0 :
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(~trigger_i) | ext_t_low_level_hold;
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ext_t_high_level_hold <= ext_t_high_level_ack ? 2'b0 :
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(trigger_i) | ext_t_high_level_hold;
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ext_t_edge_detect_ack <= data_valid & ( |ext_t_edge_detect_hold);
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ext_t_rise_edge_ack <= data_valid & ( |ext_t_rise_edge_hold);
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ext_t_fall_edge_ack <= data_valid & ( |ext_t_fall_edge_hold);
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ext_t_low_level_ack <= data_valid & ( |ext_t_low_level_hold);
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ext_t_high_level_ack <= data_valid & ( |ext_t_high_level_hold);
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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