Archived
52 lines
1.6 KiB
Tcl
52 lines
1.6 KiB
Tcl
# ip
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
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adi_ip_create axi_spdif_rx
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adi_ip_files axi_spdif_rx [list \
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"$ad_hdl_dir/library/common/axi_ctrlif.vhd" \
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"$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \
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"$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \
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"$ad_hdl_dir/library/common/dma_fifo.vhd" \
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"rx_phase_det.vhd" \
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"rx_package.vhd" \
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"rx_decode.vhd" \
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"rx_status_reg.vhd" \
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"axi_spdif_rx.vhd" ]
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adi_ip_properties axi_spdif_rx
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adi_ip_infer_streaming_interfaces axi_spdif_rx
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adi_add_bus "dma_ack" "slave" \
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"xilinx.com:interface:axis_rtl:1.0" \
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"xilinx.com:interface:axis:1.0" \
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[list {"dma_req_davalid" "TVALID"} \
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{"dma_req_daready" "TREADY"} \
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{"dma_req_datype" "TUSER"} ]
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adi_add_bus "dma_req" "master" \
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"xilinx.com:interface:axis_rtl:1.0" \
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"xilinx.com:interface:axis:1.0" \
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[list {"dma_req_drvalid" "TVALID"} \
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{"dma_req_drready" "TREADY"} \
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{"dma_req_drtype" "TUSER"} \
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{"dma_req_drlast" "TLAST"} ]
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# Clock and reset are for both dma_req and dma_ack
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adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn"
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adi_set_bus_dependency "m_axis" "m_axis" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)"
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adi_set_bus_dependency "dma_ack" "dma_req_da" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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adi_set_bus_dependency "dma_req" "dma_req_dr" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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adi_set_ports_dependency "dma_req_aclk" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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adi_set_ports_dependency "dma_req_rstn" \
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"(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)"
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ipx::save_core [ipx::current_core]
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