Archived
164 lines
4.3 KiB
Verilog
164 lines
4.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module dmac_dma_read_shutdown_tb;
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parameter VCD_FILE = {`__FILE__,"cd"};
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`include "tb_base.v"
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localparam TRANSFER_ADDR = 32'h80000000;
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localparam TRANSFER_LEN = 24'h2ff;
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reg fifo_clk = 1'b0;
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wire awvalid;
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wire awready;
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wire [31:0] araddr;
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wire [7:0] arlen;
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wire [2:0] arsize;
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wire [1:0] arburst;
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wire [2:0] arprot;
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wire [3:0] arcache;
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wire rlast;
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wire rvalid;
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wire rready;
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wire [1:0] rresp;
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wire [31:0] rdata;
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/* Twice as fast as the AXI clk so we have lots of read requests */
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always @(*) #5 fifo_clk <= ~fifo_clk;
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axi_read_slave #(
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.DATA_WIDTH(32)
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) i_read_slave (
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.clk(clk),
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.reset(reset),
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.arvalid(arvalid),
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.arready(arready),
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.araddr(araddr),
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.arlen(arlen),
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.arsize(arsize),
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.arburst(arburst),
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.arprot(arprot),
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.arcache(arcache),
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.rready(rready),
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.rvalid(rvalid),
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.rdata(rdata),
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.rresp(rresp),
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.rlast(rlast)
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);
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wire [11:0] dbg_status;
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reg ctrl_enable = 1'b0;
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initial begin
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#1000
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@(posedge clk) ctrl_enable <= 1'b1;
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#3000
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@(posedge clk) ctrl_enable <= 1'b0;
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end
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always @(posedge clk) begin
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/*
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* When disabled the DMA should eventually end up in an idle state and all
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* requests that were sent out need to be accepted
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*/
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failed <= ctrl_enable == 1'b0 && (
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dbg_status !== 12'h701 ||
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i_read_slave.i_axi_slave.req_fifo_level !== 'h00);
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end
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axi_dmac_transfer #(
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.DMA_TYPE_SRC(0),
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.DMA_TYPE_DEST(2),
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.DMA_DATA_WIDTH_SRC(32),
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.DMA_DATA_WIDTH_DEST(32),
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.FIFO_SIZE(8),
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.DMA_LENGTH_ALIGN(2)
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) i_transfer (
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.m_src_axi_aclk (clk),
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.m_src_axi_aresetn(resetn),
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.m_axi_arvalid(arvalid),
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.m_axi_arready(arready),
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.m_axi_araddr(araddr),
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.m_axi_arlen(arlen),
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.m_axi_arsize(arsize),
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.m_axi_arburst(arburst),
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.m_axi_arprot(arprot),
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.m_axi_arcache(arcache),
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.m_axi_rready(rready),
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.m_axi_rvalid(rvalid),
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.m_axi_rdata(rdata),
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.m_axi_rlast(rlast),
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.m_axi_rresp(rresp),
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.ctrl_clk(clk),
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.ctrl_resetn(resetn),
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.ctrl_enable(ctrl_enable),
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.ctrl_pause(1'b0),
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.req_eot(),
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.req_valid(1'b1),
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.req_ready(),
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.req_dest_address(TRANSFER_ADDR[31:2]),
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.req_src_address(TRANSFER_ADDR[31:2]),
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.req_x_length(TRANSFER_LEN),
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.req_y_length(24'h00),
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.req_dest_stride(24'h00),
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.req_src_stride(24'h00),
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.req_sync_transfer_start(1'b0),
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.req_last(1'b0),
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.fifo_rd_clk(fifo_clk),
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.fifo_rd_en(1'b1),
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.fifo_rd_valid(),
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.fifo_rd_underflow(),
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.fifo_rd_dout(),
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.dbg_status(dbg_status)
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);
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endmodule
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