Archived
302 lines
7.9 KiB
Verilog
302 lines
7.9 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: Chengdu Tiger
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// Engineer: Tangxy
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//
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// Create Date: 14:14:49 09/06/2021
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// Design Name:
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// Module Name: top
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module Sisyif(
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input clk_40m ,
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input clk_20m ,
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input rst_n ,
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//调零至信处接口
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input SPI_CLK_F ,//SPI控制，时钟暂定50MHz，用来发送跳频频点、发射MGC值、接收MGC值
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input SPI_SYN_F ,//片选
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input SPI_MOSI_F ,
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output SPI_MISO_F ,
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input TP_EN_F ,//跳频使能控制(上升沿更新)
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input TR_MGC_F ,//接收发射MGC使能控制(上升沿更新)
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input CAL_F ,//校准MGC使能(上升沿更新)
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input PRF ,//高发低收，默认接收
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//信处至射频接口
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output standby ,//高开低待机，默认待机
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output SW_PLL ,//乒乓频率源选择0：频率源A —— 1：频率源B
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output T ,//发射电源控制
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output R ,//接收电源控制
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output SW_BPF ,//开关滤波器选择
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output SCLK1 ,//锁相环A控制
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output SDIO1 ,//
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output CS1 ,//
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input LD1 ,//
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output SCLK2 ,//锁相环B控制
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output SDIO2 ,//
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output CS2 ,//
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input LD2 ,//
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output SCLK3 ,//点频源控制
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output SDIO3 ,//
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output CS3 ,//
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input LD3 ,//
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output TMGC_16db ,//发射通道MGC控制,高电平衰减
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output TMGC_8db ,//
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output TMGC_4db ,//
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output TMGC_2db ,//
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output TMGC_1db ,//
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output RMGC_16db ,//四个接收通道MGC控制，同时控制，高电平衰减
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output RMGC_8db ,//
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output RMGC_4db ,//
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output RMGC_2db ,//
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output RMGC_1db ,//
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output ENABLE ,//SPI控制四个接收通道增益校准
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output SC ,//
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output SD ,//
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output END_SYN ,//
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input SDOUT ,//
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inout DQ_WD ,//温度传感器
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output SW_RX //接收监测控制
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);
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wire vio_rstn ;
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wire [9:0] SYNC_OUT ;
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wire [35:0] CONTROL0 ;
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wire [35:0] CONTROL1 ;
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wire [150:0] TRIG0 ;
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wire[15:0] temp_data ;//LSB =0.625 C
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wire[7:0] temp ;//LSB =1°C
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wire[11:0] hop_fre_code;
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wire adf4371_hop1 ;
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wire adf4371_hop2 ;
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wire [15:0] fre_code ;
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wire [7:0] tx_mgc ;
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wire [7:0] rx1_mgc ;
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wire [7:0] rx2_mgc ;
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wire [7:0] rx3_mgc ;
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wire [7:0] rx4_mgc ;
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wire [3:0] cal1_mgc ;
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wire [3:0] cal2_mgc ;
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wire [3:0] cal3_mgc ;
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wire [3:0] cal4_mgc ;
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wire [7:0] tx_cal_mgc ;
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wire [3:0] model ;
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wire [3:0] rf_en ;
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wire [31:0] frame_count;
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wire [3:0] ceshi_model;
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wire [15:0] current_fre_code ;
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wire [15:0] cal_fre_code ;
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wire [7:0] R_MGC_1 ;
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wire SW_C1;
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wire SW;
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wire SW2;
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wire SW3;
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wire [3:0] R_CAL1;
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wire [3:0] R_CAL2;
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wire [3:0] R_CAL3;
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wire [3:0] R_CAL4;
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wire [4:0] T_CAL ;
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assign temp = temp_data[11:4] ;
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assign RMGC_16db = R_MGC_1[4] ;
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assign RMGC_8db = R_MGC_1[3] ;
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assign RMGC_4db = R_MGC_1[2] ;
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assign RMGC_2db = R_MGC_1[1] ;
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assign RMGC_1db = R_MGC_1[0] ;
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assign standby = rf_en == 4'b0 ;
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assign T = PRF ;
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assign R = ~PRF ;
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assign SW_BPF = SW_C1 ;
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assign SW_PLL = SW ;
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assign SW_RX = rx2_mgc == 8'b0 ? 1'b0 :1'b1 ;
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spi_slave u_spi_slave (
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.i_sys_clk(clk_40m),
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.i_sys_rst_n(rst_n),
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.i_spi_sck(SPI_CLK_F),
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.i_spi_cs(SPI_SYN_F),
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.i_spi_sdi(SPI_MOSI_F),
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.o_frame_count(frame_count),
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.o_fre_code(fre_code),
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.o_tx_mgc(tx_mgc),
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.o_model(model),
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.o_rf_en(rf_en),
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.o_cal1_mgc(cal1_mgc),
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.o_cal2_mgc(cal2_mgc),
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.o_cal3_mgc(cal3_mgc),
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.o_cal4_mgc(cal4_mgc),
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.o_tx_cal_mgc(tx_cal_mgc),
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.o_rx1_mgc(rx1_mgc),
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.o_rx2_mgc(rx2_mgc),
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.o_rx3_mgc(rx3_mgc),
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.o_rx4_mgc(rx4_mgc),
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.o_ceshi_model(ceshi_model)
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);
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spi_master u_spi_master (
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.i_sys_rst_n (rst_n) ,
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.i_clk (clk_40m) ,
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//.debug_clk (clk_80m) ,
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.i_spi_sck (SPI_CLK_F) ,
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.i_spi_cs (SPI_SYN_F) ,
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.o_spi_sdo (SPI_MISO_F) ,
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.i_spi_sdi (SPI_MOSI_F) ,
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.i_LD_LO3 (LD3) ,
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.i_LD1 (LD1) ,
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.i_LD2 (LD2) ,
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.i_cal1_mgc (R_CAL4) ,
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.i_cal2_mgc (R_CAL3) ,
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.i_cal3_mgc (R_CAL2) ,
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.i_cal4_mgc (R_CAL1) ,
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.i_temp (temp ) ,
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.i_frame_count (frame_count)
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);
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mgc_ctrl u_mgc_ctrl(
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.i_sys_clk (clk_40m ),
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.i_rst_n (rst_n ),
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.i_TR_SW_F (PRF ),
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.i_TP_EN_F (TP_EN_F ),
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.i_T_MGC_EN_F (TR_MGC_F ),
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.i_R_MGC_EN_F (TR_MGC_F ),
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.i_CAL_F (CAL_F ),
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.i_fre_code (fre_code ),
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.i_tx_mgc (tx_mgc ),
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.i_rx1_mgc (rx1_mgc ),
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.i_rx2_mgc (rx2_mgc ),
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.i_rx3_mgc (rx3_mgc ),
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.i_rx4_mgc (rx4_mgc ),
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.i_ceshi_module (ceshi_model ),
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.o_current_fre_code (current_fre_code ),
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.o_cal_fre_code (cal_fre_code ),
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.o_hop_fre_code (hop_fre_code ), //0(20.375GHz)~3500(23.875GHz)
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.o_adf4371_hop1 (adf4371_hop1 ), //high active
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.o_adf4371_hop2 (adf4371_hop2 ),
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.o_SW (SW ),
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.o_SW2 (SW2 ),
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.o_SW3 (SW3 ),
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.o_SW_C1 (SW_C1 ),
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.o_T_MGC_1dB (TMGC_1db ),
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.o_T_MGC_2dB (TMGC_2db ),
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.o_T_MGC_4dB (TMGC_4db ),
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.o_T_MGC_8dB (TMGC_8db ),
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.o_T_MGC_16dB (TMGC_16db ),
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.o_R_MGC_1 (R_MGC_1 )
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//.o_R_MGC_2 (R_MGC_2 ),
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//.o_R_MGC_3 (R_MGC_3 ),
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//.o_R_MGC_4 (R_MGC_4 )
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);
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wire cfgover;
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adf4371_a u_adf4371_a (
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.sysclk (clk_40m ),
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.arstn (rst_n&vio_rstn ),
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.cs (CS1 ),
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.mux_out (LD1 ),
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.sclk (SCLK1 ),
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.sdio (SDIO1 ),
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.rf_en (rf_en ),
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.SW_PLL (SW_PLL ),
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.CAL_F (CAL_F ),
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.o_cfgover (cfgover ),
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.ceshi_model(ceshi_model ),
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.adf4371_hop(adf4371_hop1),
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.fre_code (hop_fre_code)
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);
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adf4371_b u_adf4371_b (
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.sysclk (clk_40m ),
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.arstn (rst_n&vio_rstn),
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.cs (CS2 ),
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.mux_out (LD2 ),
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.sclk (SCLK2 ),
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.sdio (SDIO2 ),
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.rf_en (rf_en ),
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.SW_PLL (SW_PLL ),
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.CAL_F (CAL_F ),
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.i_cfgover (cfgover ),
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.ceshi_model(ceshi_model ),
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.adf4371_hop(adf4371_hop2),
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.fre_code (hop_fre_code)
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);
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fre_caliatt u_fre_caliatt (
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.i_clk (clk_40m ),
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.i_rstn (rst_n ),
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.ENABLE (ENABLE ),
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.SC (SC ),
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.SD (SD ),
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.END_SYN (END_SYN ),
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.SDOUT (SDOUT ),
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.CAL_F (CAL_F ),
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.i_temp (temp ),
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.i_fre_mode (current_fre_code ),
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.i_cal_fre_code (cal_fre_code ),
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// .SYNC_OUT (SYNC_OUT ),
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.SW (SW ),
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.cal1_mgc (cal1_mgc ),
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.cal2_mgc (cal2_mgc ),
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.cal3_mgc (cal3_mgc ),
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.cal4_mgc (cal4_mgc ),
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.tx_cal_mgc (tx_cal_mgc ),
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.tx_mgc (tx_mgc ),
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.i_ceshi_module (ceshi_model ),
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.R_CAL1 (R_CAL1 ),
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.R_CAL2 (R_CAL2 ),
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.R_CAL3 (R_CAL3 ),
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.R_CAL4 (R_CAL4 ),
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.T_CAL (T_CAL )
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);
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adf4351_2 u_adf4351 (
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.i_sysclk(clk_20m),
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.i_arstn(rst_n),
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.o_ADF4351_SCK(SCLK3),
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.o_ADF4351_DATA(SDIO3),
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.o_ADF4351_LE(CS3),
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.i_ADF4351_locked(LD3)
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);
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ds18b20_temp u_temp (
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.clk(clk_40m),
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.rstn(rst_n),
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.dq(DQ_WD),
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.temp_data(temp_data)
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);
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assign vio_rstn = 1'b1;
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endmodule
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