Archived
510 lines
15 KiB
Verilog
510 lines
15 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2022/07/13 14:20:24
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// Design Name:
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// Module Name: ant_rf_ctrl
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ant_rf_ctrl
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(
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input clk_48m ,
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input clk_96m ,
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input clk_32m ,
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input clk_19p2m ,
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input sys_rst ,
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output ant_clk ,
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output ant_en ,
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output ant_data ,
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output ant_tr ,
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output ant_dary ,
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input ant_dout ,
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output rf_standby ,
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output rf_sw_pll ,
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output rf_t ,
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output rf_r ,
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output rf_sw_bpf ,
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output rf_sclk1 ,
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output rf_sdio1 ,
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output rf_cs1 ,
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input rf_ld1 ,
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output rf_sclk2 ,
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output rf_sdio2 ,
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output rf_cs2 ,
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input rf_ld2 ,
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output rf_sclk3 ,
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output rf_sdio3 ,
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output rf_cs3 ,
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input rf_ld3 ,
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output rf_tmgc_16 ,
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output rf_tmgc_8 ,
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output rf_tmgc_4 ,
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output rf_tmgc_2 ,
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output rf_tmgc_1 ,
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output rf_rmgc_16 ,
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output rf_rmgc_8 ,
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output rf_rmgc_4 ,
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output rf_rmgc_2 ,
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output rf_rmgc_1 ,
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output rf_enable ,
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output rf_sc ,
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output rf_sd ,
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output rf_endsyn ,
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input rf_sdout ,
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inout rf_dq_wd ,
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output rf_sw_rx
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);
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(*dont_touch = "true"*) wire vio_switch ; // 键控开关，沿有效
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(*dont_touch = "true"*) wire vio_trdirection ; // 收发方向
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(*dont_touch = "true"*) wire [15:0] vio_frequency ; // 收发频率
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(*dont_touch = "true"*) wire [ 7:0] vio_emitMGC ; // 发送MGC
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(*dont_touch = "true"*) wire [ 3:0] vio_ch01MGC ; // 1通道校准MGC
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(*dont_touch = "true"*) wire [ 3:0] vio_ch02MGC ; // 2通道校准MGC
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(*dont_touch = "true"*) wire [ 3:0] vio_ch03MGC ; // 3通道校准MGC
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(*dont_touch = "true"*) wire [ 3:0] vio_ch04MGC ; // 4通道校准MGC
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(*dont_touch = "true"*) wire [ 7:0] vio_recvMGC ; // 接收MGC
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(*dont_touch = "true"*) wire [ 7:0] vio_AntMod ; // 天线工作模式
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(*dont_touch = "true"*) wire [15:0] vio_AntOffAxis ; // 天线离轴角
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(*dont_touch = "true"*) wire [15:0] vio_AntYaw ; // 天线偏航角
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(*dont_touch = "true"*) wire [15:0] vio_PrecessTime ; // 处理时间，从EN拉低到DARY拉低
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(*dont_touch = "true"*)wire vio_mode_ant ; // 0定频手动，1扫频模式
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(*dont_touch = "true"*)wire vio_hop_start ; // 0跳频终止，1重新跳频
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(*dont_touch = "true"*)wire vio_standby ; // 0待机模式，1工作模式
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(*dont_touch = "true"*)wire [15:0] vio_hoptime ; // 单跳时间计数器
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reg Ant_switch_D1 = 0;
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reg data_valid = 0;
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reg switch_valid = 0;
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reg [95:0] RF_CtrlWord = 0;
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reg [127:0] Ant_CtrlWord = 0;
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reg [15:0] data_valid_countdown = 0;
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reg [15:0] rst_countdown = 100;
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reg [95:0] RF_CtrlWord_running = 0;
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reg [127:0] Ant_CtrlWord_running = 0;
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reg rst_n = 0;
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reg SPI_SYN_F = 1;
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reg SPI_MOSI_F = 1;
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reg TP_EN_F = 0;
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reg TR_MGC_F = 0;
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reg CAL_F = 0;
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reg PRF = 0;
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wire SPI_MISO_F;
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reg Ant_DATA = 0;
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reg Ant_EN = 0;
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reg Ant_DARY = 0;
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reg Ant_TR = 0;
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//相控阵测试程序
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reg [15:0] cnt_freq_change = 16'd0;
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reg Ant_switch ; // 键控开关，沿有效
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reg [15:0] Ant_frequency; // 收发频率
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reg [ 7:0] Ant_mode ; // 相控阵模式
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reg [ 7:0] RF_mode ; // 射频模式
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always @ (posedge clk_48m) begin
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if(sys_rst) begin
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Ant_switch <= 1'b0;
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cnt_freq_change[15:0] <= 16'd0;
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Ant_frequency[15:0] <= 16'd0;
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RF_mode[7:0] <= 8'h10;
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Ant_mode[7:0] <= 8'h0f;
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end
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else begin
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if(vio_mode_ant) begin
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if(vio_hop_start) begin
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if(cnt_freq_change[15:0] == (vio_hoptime[15:0] - 16'd1)) begin
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Ant_switch <= ~Ant_switch;
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if(Ant_frequency[15:0] == 16'd3500) begin
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Ant_frequency[15:0] <= 16'd0;
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end
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else begin
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Ant_frequency[15:0] <= Ant_frequency[15:0] + 16'd1;
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end
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cnt_freq_change[15:0] <= 16'd0;
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end
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else begin
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Ant_switch <= Ant_switch;
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Ant_frequency[15:0] <= Ant_frequency[15:0];
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cnt_freq_change[15:0] <= cnt_freq_change[15:0] + 16'd1;
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end
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end
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else begin
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Ant_switch <= Ant_switch;
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Ant_frequency[15:0] <= 16'd0;
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cnt_freq_change[15:0] <= 16'd0;
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end
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end
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else begin
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Ant_switch <= vio_switch;
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Ant_frequency[15:0] <= vio_frequency[15:0];
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cnt_freq_change[15:0] <= 16'd0;
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end
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if(vio_standby) begin
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RF_mode[7:0] <= 8'h10;
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Ant_mode[7:0] <= 8'h0f;
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end
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else begin
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RF_mode[7:0] <= 8'h00;
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Ant_mode[7:0] <= vio_AntMod[7:0];
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end
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end
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end
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always @(posedge clk_48m)
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begin
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Ant_switch_D1 <= Ant_switch;
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if(Ant_switch_D1 != Ant_switch)
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switch_valid <= 1'b1;
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else
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switch_valid <= 1'b0;
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if(switch_valid)
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begin
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RF_CtrlWord[95:88] <= 8'hAA;
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RF_CtrlWord[87:80] <= RF_mode[7:0];
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RF_CtrlWord[79:64] <= Ant_frequency[15:0];
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RF_CtrlWord[63:56] <= vio_emitMGC[7:0];
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RF_CtrlWord[55:52] <= vio_ch01MGC[3:0];
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RF_CtrlWord[51:48] <= vio_ch02MGC[3:0];
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RF_CtrlWord[47:44] <= vio_ch03MGC[3:0];
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RF_CtrlWord[43:40] <= vio_ch04MGC[3:0];
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RF_CtrlWord[39:32] <= vio_recvMGC[7:0];
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RF_CtrlWord[31:8] <= 24'h00_0000;
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RF_CtrlWord[7:0] <= 8'hCC;
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Ant_CtrlWord[127:120] <= 8'hAA;
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Ant_CtrlWord[119:112] <= 8'h00;
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Ant_CtrlWord[111:104] <= Ant_mode[7:0];
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Ant_CtrlWord[103: 88] <= vio_AntOffAxis[15:0];
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Ant_CtrlWord[ 87: 72] <= vio_AntYaw[15:0];
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Ant_CtrlWord[ 71: 56] <= Ant_frequency[15:0];
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Ant_CtrlWord[ 55: 8] <= 48'h00_00_00_00_00_00;
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Ant_CtrlWord[ 7: 0] <= 8'hCC;
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end
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else
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begin
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RF_CtrlWord[95:0] <= RF_CtrlWord[95:0];
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Ant_CtrlWord[127:0] <= Ant_CtrlWord[127:0];
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end
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if(switch_valid)
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data_valid_countdown[15:0] <= vio_PrecessTime[15:0];
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else if(data_valid_countdown[15:0] != 16'd0)
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data_valid_countdown[15:0] <= data_valid_countdown[15:0] - 16'd1;
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// RF控制
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if(data_valid_countdown[15:0] == vio_PrecessTime[15:0])
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RF_CtrlWord_running[95:0] <= RF_CtrlWord[95:0];
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else
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RF_CtrlWord_running[95:0] <= {RF_CtrlWord_running[94:0],1'b0};
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if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd96 && data_valid_countdown[15:0] < vio_PrecessTime[15:0])
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begin
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SPI_SYN_F <= 1'b0;
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SPI_MOSI_F <= RF_CtrlWord_running[95];
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end
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else
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begin
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SPI_SYN_F <= 1'b1;
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SPI_MOSI_F <= 1'b0;
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end
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if(data_valid_countdown[15:0] <= 16'd128 && data_valid_countdown[15:0] > 16'd80)
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CAL_F <= 1'b1;
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else
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CAL_F <= 1'b0;
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if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0)
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begin
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TP_EN_F <= 1'b1;
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TR_MGC_F <= 1'b1;
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end
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else
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begin
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TP_EN_F <= 1'b0;
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TR_MGC_F <= 1'b0;
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end
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if(data_valid_countdown[15:0] == 16'd48)
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PRF <= vio_trdirection;
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else
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PRF <= PRF;
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if(sys_rst)
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rst_countdown[15:0] <= 16'd100;
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else if(rst_countdown[15:0] != 0)
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begin
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rst_countdown[15:0] <= rst_countdown[15:0] - 16'd1;
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rst_n <= 1'b0;
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end
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else
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begin
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rst_countdown[15:0] <= rst_countdown[15:0];
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rst_n <= 1'b1;
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end
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// 天线控制
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if(data_valid_countdown[15:0] == vio_PrecessTime[15:0])
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Ant_CtrlWord_running[127:0] <= Ant_CtrlWord[127:0];
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else
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Ant_CtrlWord_running[127:0] <= {Ant_CtrlWord_running[126:0],1'b0};
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if(data_valid_countdown[15:0] >= vio_PrecessTime[15:0]-16'd128 && data_valid_countdown[15:0] < vio_PrecessTime[15:0])
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begin
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Ant_EN <= 1'b0;
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Ant_DATA <= Ant_CtrlWord_running[127];
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end
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else
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begin
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Ant_EN <= 1'b1;
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Ant_DATA <= 1'b0;
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end
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if(data_valid_countdown[15:0] <= 16'd48 && data_valid_countdown[15:0] > 16'd0)
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Ant_DARY <= 1'b0;
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else
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Ant_DARY <= 1'b1;
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if(data_valid_countdown[15:0] == 16'd48)
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Ant_TR <= vio_trdirection;
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else
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Ant_TR <= Ant_TR;
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end
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//RF recv_data
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reg [1:0] state_rfdata;
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reg SPI_SYN_F_d1 = 1'b0;
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reg [15:0] cnt_rfdata = 16'd0;
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reg [95:0] RF_RecvWord = 96'd0;
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reg [95:0] RF_RecvWord_last = 96'd0;
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reg [7:0] RF_temperature = 8'd0 ;
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reg [7:0] RF_IFlocked = 8'd0 ;
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reg [7:0] RF_RFAlocked = 8'd0 ;
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reg [7:0] RF_RFBlocked = 8'd0 ;
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reg [3:0] RF_ch1mgc = 4'd0 ;
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reg [3:0] RF_ch2mgc = 4'd0 ;
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reg [3:0] RF_ch3mgc = 4'd0 ;
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reg [3:0] RF_ch4mgc = 4'd0 ;
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reg [31:0] RF_Framecount = 32'd0 ;
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always @ (posedge clk_48m) begin
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if(sys_rst) begin
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state_rfdata[1:0] <= 2'd0;
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SPI_SYN_F_d1 <= 1'b0;
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RF_RecvWord[95:0] <= 96'd0;
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cnt_rfdata[15:0] <= 16'd0;
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RF_temperature[7:0] <= 8'd0 ;
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RF_IFlocked[7:0] <= 8'd0 ;
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RF_RFAlocked[7:0] <= 8'd0 ;
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RF_RFBlocked[7:0] <= 8'd0 ;
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RF_ch1mgc[3:0] <= 4'd0 ;
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RF_ch2mgc[3:0] <= 4'd0 ;
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RF_ch3mgc[3:0] <= 4'd0 ;
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RF_ch4mgc[3:0] <= 4'd0 ;
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RF_Framecount[31:0] <= 32'd0;
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end
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else begin
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RF_RecvWord[95:0] <= {RF_RecvWord[94:0],SPI_MISO_F};
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if (RF_RecvWord[95:88] == 8'hAA && RF_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾
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RF_temperature[7:0] <= RF_RecvWord[87:80];
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RF_IFlocked[7:0] <= RF_RecvWord[79:72];
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RF_RFAlocked[7:0] <= RF_RecvWord[71:64];
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RF_RFBlocked[7:0] <= RF_RecvWord[63:56];
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RF_ch1mgc[3:0] <= RF_RecvWord[55:52];
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RF_ch2mgc[3:0] <= RF_RecvWord[51:48];
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RF_ch3mgc[3:0] <= RF_RecvWord[47:44];
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RF_ch4mgc[3:0] <= RF_RecvWord[43:40];
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RF_Framecount[31:0] <= RF_RecvWord[39:8];
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RF_RecvWord_last <= RF_RecvWord;
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end
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else begin // hold otherwise
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RF_temperature[7:0] <= RF_temperature[7:0];
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RF_IFlocked[7:0] <= RF_IFlocked[7:0] ;
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RF_RFAlocked[7:0] <= RF_RFAlocked[7:0] ;
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RF_RFBlocked[7:0] <= RF_RFBlocked[7:0] ;
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RF_ch1mgc[3:0] <= RF_ch1mgc[3:0] ;
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RF_ch2mgc[3:0] <= RF_ch2mgc[3:0] ;
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RF_ch3mgc[3:0] <= RF_ch3mgc[3:0] ;
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RF_ch4mgc[3:0] <= RF_ch4mgc[3:0] ;
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RF_Framecount[31:0] <= RF_Framecount[31:0];
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RF_RecvWord_last <= RF_RecvWord_last;
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end
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end
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end
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// 天线的输出时钟转换
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reg Ant_dclk_96m = 1;
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wire [3:0] fifo_wr_din, fifo_rd_dout;
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wire fifo_full, fifo_empty;
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reg Ant_EN_96m = 0;
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reg Ant_DATA_96m = 0;
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reg Ant_DARY_96m = 1;
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reg Ant_TR_96m = 0;
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assign fifo_wr_din[3] = Ant_EN;
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assign fifo_wr_din[2] = Ant_DATA;
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assign fifo_wr_din[1] = Ant_DARY;
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assign fifo_wr_din[0] = Ant_TR;
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reg fifo_rd_en = 0;
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reg fifo_rst = 0;
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reg [8:0] Ant_clk_countdown = 0;
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always @(posedge clk_96m)
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begin
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fifo_rst <= sys_rst;
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fifo_rd_en <= (fifo_rst == 1'b1)? 1'b0:!fifo_rd_en;
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if(fifo_rd_en)
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{Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= fifo_rd_dout[3:0];
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else
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{Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m} <= {Ant_EN_96m,Ant_DATA_96m,Ant_DARY_96m,Ant_TR_96m};
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if(fifo_rd_en && Ant_EN_96m && !fifo_rd_dout[3])
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Ant_clk_countdown[8:0] <= 9'd276;
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else if(Ant_clk_countdown[8:0] != 9'd0)
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Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0] - 9'd1;
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else
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Ant_clk_countdown[8:0] <= Ant_clk_countdown[8:0];
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end
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assign ant_clk = !Ant_clk_countdown[0];
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assign ant_en = Ant_EN_96m;
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assign ant_data = Ant_DATA_96m;
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assign ant_tr = Ant_TR_96m;
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assign ant_dary = Ant_DARY_96m;
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fifo_AntCtrl fifo_AntCtrl
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(
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.rst (fifo_rst ), // input wire rst
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.wr_clk (clk_48m ), // input wire wr_clk
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.rd_clk (clk_96m ), // input wire rd_clk
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.din (fifo_wr_din[3:0] ), // input wire [3 : 0] din
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.wr_en (!fifo_rst ), // input wire wr_en
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.rd_en (fifo_rd_en ), // input wire rd_en
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.dout (fifo_rd_dout[3:0] ), // output wire [3 : 0] dout
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.full (fifo_full ), // output wire full
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.empty (fifo_empty ) // output wire empty
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);
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//Ant recv_data
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reg [1:0] state_antdata;
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reg Ant_EN_96m_d1 = 1'b0;
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reg [15:0] cnt_antdata = 16'd0;
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reg [95:0] Ant_RecvWord = 'b0;
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reg [95:0] Ant_RecvWord_last = 'b0;
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reg [7:0] Ant_Ant_Volt = 8'd0 ;
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reg [7:0] Ant_RF_Volt = 8'd0 ;
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reg [7:0] Ant_IF_Volt = 8'd0 ;
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reg [7:0] Ant_state = 8'd0 ;
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reg [31:0] Ant_Framecount = 32'd0 ;
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always @ (posedge clk_96m) begin
|
|
if(sys_rst) begin
|
|
state_antdata[1:0] <= 2'd0;
|
|
Ant_EN_96m_d1 <= 1'b0;
|
|
Ant_RecvWord[95:0] <= 'd0;
|
|
cnt_antdata[15:0] <= 16'd0;
|
|
Ant_Ant_Volt[7:0] <= 8'd0 ;
|
|
Ant_RF_Volt[7:0] <= 8'd0 ;
|
|
Ant_IF_Volt[7:0] <= 8'd0 ;
|
|
Ant_state[7:0] <= 8'd0 ;
|
|
Ant_Framecount[31:0] <= 32'd0;
|
|
end
|
|
else begin
|
|
Ant_RecvWord[95:0] <= {Ant_RecvWord[94:0],ant_dout};
|
|
|
|
if(Ant_RecvWord[95:88] == 8'hAA && Ant_RecvWord[7:0] == 8'hCC) begin//校验帧头帧尾
|
|
Ant_Ant_Volt[7:0] <= Ant_RecvWord[87:80];
|
|
Ant_RF_Volt[7:0] <= Ant_RecvWord[79:72];
|
|
Ant_IF_Volt[7:0] <= Ant_RecvWord[71:64];
|
|
Ant_state[7:0] <= Ant_RecvWord[47:40];
|
|
Ant_Framecount[31:0] <= Ant_RecvWord[39:8] ;
|
|
Ant_RecvWord_last <= Ant_RecvWord ;
|
|
end
|
|
else begin // hold otherwise
|
|
Ant_Ant_Volt[7:0] <= Ant_Ant_Volt[7:0] ;
|
|
Ant_RF_Volt[7:0] <= Ant_RF_Volt[7:0] ;
|
|
Ant_IF_Volt[7:0] <= Ant_IF_Volt[7:0] ;
|
|
Ant_state[7:0] <= Ant_state[7:0] ;
|
|
Ant_Framecount[31:0] <= Ant_Framecount[31:0] ;
|
|
Ant_RecvWord_last <= Ant_RecvWord_last ;
|
|
end
|
|
end
|
|
|
|
end
|
|
Sisyif uut(
|
|
.clk_40m(clk_32m),
|
|
.clk_20m(clk_19p2m),
|
|
.SPI_CLK_F(clk_48m),
|
|
.rst_n(rst_n),
|
|
.SPI_SYN_F(SPI_SYN_F),
|
|
.SPI_MOSI_F(SPI_MOSI_F),
|
|
.SPI_MISO_F(SPI_MISO_F),
|
|
.TP_EN_F(TP_EN_F),
|
|
.TR_MGC_F(TR_MGC_F),
|
|
.CAL_F(CAL_F),
|
|
.PRF(PRF),
|
|
.standby(rf_standby),
|
|
.SW_PLL(rf_sw_pll),
|
|
.T(rf_t),
|
|
.R(rf_r),
|
|
.SW_BPF(rf_sw_bpf),
|
|
.SCLK1(rf_sclk1),
|
|
.SDIO1(rf_sdio1),
|
|
.CS1(rf_cs1),
|
|
.LD1(rf_ld1),
|
|
.SCLK2(rf_sclk2),
|
|
.SDIO2(rf_sdio2),
|
|
.CS2(rf_cs2),
|
|
.LD2(rf_ld2),
|
|
.SCLK3(rf_sclk3),
|
|
.SDIO3(rf_sdio3),
|
|
.CS3(rf_cs3),
|
|
.LD3(rf_ld3),
|
|
.TMGC_16db(rf_tmgc_16),
|
|
.TMGC_8db(rf_tmgc_8),
|
|
.TMGC_4db(rf_tmgc_4),
|
|
.TMGC_2db(rf_tmgc_2),
|
|
.TMGC_1db(rf_tmgc_1),
|
|
.RMGC_16db(rf_rmgc_16),
|
|
.RMGC_8db(rf_rmgc_8),
|
|
.RMGC_4db(rf_rmgc_4),
|
|
.RMGC_2db(rf_rmgc_2),
|
|
.RMGC_1db(rf_rmgc_1),
|
|
.ENABLE(rf_enable),
|
|
.SC(rf_sc),
|
|
.SD(rf_sd),
|
|
.END_SYN(rf_endsyn),
|
|
.SDOUT(rf_sdout),
|
|
.DQ_WD(rf_dq_wd),
|
|
.SW_RX(rf_sw_rx)
|
|
);
|
|
|
|
endmodule
|